Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1639212

1

T1

136

T2

9067

T3

16212

full_word

1805665

1

T1

65

T2

3276

T3

17036

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3444507	1			T1	201		T2	12343		T3	33248
auto[TlIntgErrCmd]	117	1			T31	4		T35	6		T108	7
auto[TlIntgErrData]	128	1			T31	4		T35	5		T108	15
auto[TlIntgErrBoth]	125	1			T31	2		T35	9		T108	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2733179

1

T1

144

T2

9171

T3

32344

auto[1]

711698

1

T1

57

T2

3172

T3

904

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1551980	1			T1	119		T2	8238		T3	16203
auto[TlIntgErrNone]	partial	auto[1]	86889	1			T1	17		T2	829		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	1181026	1			T1	25		T2	933		T3	16141
auto[TlIntgErrNone]	full_word	auto[1]	624612	1			T1	40		T2	2343		T3	895
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T31	3		T35	3		T108	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T35	3		T108	3		T117	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T367	1		T368	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T31	1		T369	1		T370	2
auto[TlIntgErrData]	partial	auto[0]	59	1			T31	2		T35	2		T108	6
auto[TlIntgErrData]	partial	auto[1]	60	1			T31	2		T35	3		T108	7
auto[TlIntgErrData]	full_word	auto[0]	7	1			T108	2		T117	1		T369	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T114	1		T371	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T35	5		T108	3		T117	3
auto[TlIntgErrBoth]	partial	auto[1]	66	1			T31	2		T35	4		T108	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T369	1		T366	2		T372	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T369	1		T114	1		T373	1