Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	98.94	91.20		91.67	95.48	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.36	85.00	45.45			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.01	94.03	70.69			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38176901	4945439	0	0
DepthKnown_A	38176901	25582414	0	0
RvalidKnown_A	38176901	25582414	0	0
WreadyKnown_A	38176901	25582414	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38176901	4945439	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	4945439	0	0
T4	186	112	0	0
T5	43888	10940	0	0
T6	121628	48058	0	0
T7	4496	0	0	0
T8	100176	3860	0	0
T9	15136	10080	0	0
T11	0	41678	0	0
T12	0	30581	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0
T78	0	33211	0	0
T79	0	16394	0	0
T80	0	3402	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	4945439	0	0
T4	186	112	0	0
T5	43888	10940	0	0
T6	121628	48058	0	0
T7	4496	0	0	0
T8	100176	3860	0	0
T9	15136	10080	0	0
T11	0	41678	0	0
T12	0	30581	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0
T78	0	33211	0	0
T79	0	16394	0	0
T80	0	3402	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38176901	5217665	0	0
DepthKnown_A	38176901	25582414	0	0
RvalidKnown_A	38176901	25582414	0	0
WreadyKnown_A	38176901	25582414	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38176901	5217665	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	5217665	0	0
T4	186	122	0	0
T5	43888	12406	0	0
T6	121628	50148	0	0
T7	4496	0	0	0
T8	100176	4112	0	0
T9	15136	10744	0	0
T11	0	44434	0	0
T12	0	33296	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0
T78	0	34606	0	0
T79	0	17251	0	0
T80	0	3624	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	5217665	0	0
T4	186	122	0	0
T5	43888	12406	0	0
T6	121628	50148	0	0
T7	4496	0	0	0
T8	100176	4112	0	0
T9	15136	10744	0	0
T11	0	44434	0	0
T12	0	33296	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0
T78	0	34606	0	0
T79	0	17251	0	0
T80	0	3624	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38176901	0	0	0
DepthKnown_A	38176901	25582414	0	0
RvalidKnown_A	38176901	25582414	0	0
WreadyKnown_A	38176901	25582414	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38176901	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	25582414	0	0
T3	100119	99632	0	0
T4	186	186	0	0
T5	43888	43584	0	0
T6	121628	121268	0	0
T7	4496	4496	0	0
T8	100176	100176	0	0
T9	0	15136	0	0
T10	0	47692	0	0
T11	0	139776	0	0
T12	0	56936	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	2432	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T13

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Not Covered
1	1	Covered	T1,T2,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T16
1	0	1	Covered	T1,T2,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T13
0	0	Covered	T1,T2,T13

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38176901	2143122	0	0
DepthKnown_A	38176901	12035720	0	0
RvalidKnown_A	38176901	12035720	0	0
WreadyKnown_A	38176901	12035720	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38176901	2143122	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	2143122	0	0
T1	2168	912	0	0
T2	102926	40615	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	0	339	0	0
T19	0	60811	0	0
T20	0	41334	0	0
T46	0	1494	0	0
T52	0	408	0	0
T54	0	7632	0	0
T55	0	70080	0	0
T57	0	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	12035720	0	0
T1	2168	2168	0	0
T2	102926	98840	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	145592	0	0
T14	158493	150312	0	0
T15	165268	157832	0	0
T16	0	2432	0	0
T19	0	155704	0	0
T20	0	121216	0	0
T52	0	1184	0	0
T53	0	360	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	12035720	0	0
T1	2168	2168	0	0
T2	102926	98840	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	145592	0	0
T14	158493	150312	0	0
T15	165268	157832	0	0
T16	0	2432	0	0
T19	0	155704	0	0
T20	0	121216	0	0
T52	0	1184	0	0
T53	0	360	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	12035720	0	0
T1	2168	2168	0	0
T2	102926	98840	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	145592	0	0
T14	158493	150312	0	0
T15	165268	157832	0	0
T16	0	2432	0	0
T19	0	155704	0	0
T20	0	121216	0	0
T52	0	1184	0	0
T53	0	360	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	2143122	0	0
T1	2168	912	0	0
T2	102926	40615	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	0	339	0	0
T19	0	60811	0	0
T20	0	41334	0	0
T46	0	1494	0	0
T52	0	408	0	0
T54	0	7632	0	0
T55	0	70080	0	0
T57	0	15	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T13

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Not Covered
1	1	Covered	T1,T2,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T13
0	0	Covered	T1,T2,T13

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38176901	68890	0	0
DepthKnown_A	38176901	12035720	0	0
RvalidKnown_A	38176901	12035720	0	0
WreadyKnown_A	38176901	12035720	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38176901	68890	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	68890	0	0
T1	2168	30	0	0
T2	102926	1310	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	0	11	0	0
T19	0	1951	0	0
T20	0	1329	0	0
T46	0	48	0	0
T52	0	13	0	0
T54	0	245	0	0
T55	0	2257	0	0
T57	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	12035720	0	0
T1	2168	2168	0	0
T2	102926	98840	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	145592	0	0
T14	158493	150312	0	0
T15	165268	157832	0	0
T16	0	2432	0	0
T19	0	155704	0	0
T20	0	121216	0	0
T52	0	1184	0	0
T53	0	360	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	12035720	0	0
T1	2168	2168	0	0
T2	102926	98840	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	145592	0	0
T14	158493	150312	0	0
T15	165268	157832	0	0
T16	0	2432	0	0
T19	0	155704	0	0
T20	0	121216	0	0
T52	0	1184	0	0
T53	0	360	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	12035720	0	0
T1	2168	2168	0	0
T2	102926	98840	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	145592	0	0
T14	158493	150312	0	0
T15	165268	157832	0	0
T16	0	2432	0	0
T19	0	155704	0	0
T20	0	121216	0	0
T52	0	1184	0	0
T53	0	360	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38176901	68890	0	0
T1	2168	30	0	0
T2	102926	1310	0	0
T3	100119	0	0	0
T4	186	0	0	0
T5	43888	0	0	0
T6	121628	0	0	0
T7	4496	0	0	0
T13	152496	0	0	0
T14	158493	0	0	0
T15	165268	0	0	0
T16	0	11	0	0
T19	0	1951	0	0
T20	0	1329	0	0
T46	0	48	0	0
T52	0	13	0	0
T54	0	245	0	0
T55	0	2257	0	0
T57	0	1	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T7
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	135451329	500184	0	0
DepthKnown_A	135451329	135390026	0	0
RvalidKnown_A	135451329	135390026	0	0
WreadyKnown_A	135451329	135390026	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	135451329	500184	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	500184	0	0
T3	705678	832	0	0
T4	11871	3754	0	0
T5	268945	832	0	0
T6	125444	2880	0	0
T7	4174	836	0	0
T8	0	833	0	0
T9	0	832	0	0
T10	0	832	0	0
T11	0	2493	0	0
T12	0	3136	0	0
T13	117061	0	0	0
T14	123421	0	0	0
T15	662501	0	0	0
T16	4389	0	0	0
T17	1515	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	500184	0	0
T3	705678	832	0	0
T4	11871	3754	0	0
T5	268945	832	0	0
T6	125444	2880	0	0
T7	4174	836	0	0
T8	0	833	0	0
T9	0	832	0	0
T10	0	832	0	0
T11	0	2493	0	0
T12	0	3136	0	0
T13	117061	0	0	0
T14	123421	0	0	0
T15	662501	0	0	0
T16	4389	0	0	0
T17	1515	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	135451329	0	0	0
DepthKnown_A	135451329	135390026	0	0
RvalidKnown_A	135451329	135390026	0	0
WreadyKnown_A	135451329	135390026	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	135451329	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	135451329	0	0	0
DepthKnown_A	135451329	135390026	0	0
RvalidKnown_A	135451329	135390026	0	0
WreadyKnown_A	135451329	135390026	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	135451329	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T16,T19,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	135451329	71844	0	0
DepthKnown_A	135451329	135390026	0	0
RvalidKnown_A	135451329	135390026	0	0
WreadyKnown_A	135451329	135390026	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	135451329	71844	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	71844	0	0
T1	1343	18	0	0
T2	707339	777	0	0
T3	705678	0	0	0
T4	11871	0	0	0
T5	268945	0	0	0
T6	125444	0	0	0
T13	117061	0	0	0
T14	123421	0	0	0
T15	662501	0	0	0
T16	0	220	0	0
T17	1515	0	0	0
T19	0	3197	0	0
T20	0	975	0	0
T46	0	1	0	0
T52	0	16	0	0
T54	0	200	0	0
T55	0	1301	0	0
T56	0	306	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	135390026	0	0
T1	1343	1263	0	0
T2	707339	707271	0	0
T3	705678	705628	0	0
T4	11871	11818	0	0
T5	268945	268882	0	0
T6	125444	125361	0	0
T13	117061	117005	0	0
T14	123421	123412	0	0
T15	662501	662443	0	0
T17	1515	1462	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	135451329	71844	0	0
T1	1343	18	0	0
T2	707339	777	0	0
T3	705678	0	0	0
T4	11871	0	0	0
T5	268945	0	0	0
T6	125444	0	0	0
T13	117061	0	0	0
T14	123421	0	0	0
T15	662501	0	0	0
T16	0	220	0	0
T17	1515	0	0	0
T19	0	3197	0	0
T20	0	975	0	0
T46	0	1	0	0
T52	0	16	0	0
T54	0	200	0	0
T55	0	1301	0	0
T56	0	306	0	0