Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4063 |
0 |
0 |
T31 |
34394 |
1 |
0 |
0 |
T32 |
15207 |
221 |
0 |
0 |
T33 |
4828 |
246 |
0 |
0 |
T35 |
19190 |
6 |
0 |
0 |
T104 |
12137 |
244 |
0 |
0 |
T108 |
29325 |
6 |
0 |
0 |
T110 |
4979 |
213 |
0 |
0 |
T113 |
4016 |
6 |
0 |
0 |
T117 |
20118 |
1 |
0 |
0 |
T118 |
3471 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1566 |
0 |
0 |
T31 |
34394 |
37 |
0 |
0 |
T119 |
15933 |
17 |
0 |
0 |
T120 |
5764 |
4 |
0 |
0 |
T136 |
18861 |
58 |
0 |
0 |
T138 |
3867 |
4 |
0 |
0 |
T140 |
20009 |
128 |
0 |
0 |
T145 |
36636 |
20 |
0 |
0 |
T146 |
32804 |
17 |
0 |
0 |
T147 |
10372 |
18 |
0 |
0 |
T148 |
20962 |
104 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1574 |
0 |
0 |
T31 |
34394 |
29 |
0 |
0 |
T119 |
15933 |
21 |
0 |
0 |
T120 |
5764 |
2 |
0 |
0 |
T136 |
18861 |
104 |
0 |
0 |
T138 |
3867 |
3 |
0 |
0 |
T140 |
20009 |
63 |
0 |
0 |
T145 |
36636 |
37 |
0 |
0 |
T146 |
32804 |
29 |
0 |
0 |
T147 |
10372 |
21 |
0 |
0 |
T148 |
20962 |
68 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1713 |
0 |
0 |
T31 |
34394 |
65 |
0 |
0 |
T119 |
15933 |
41 |
0 |
0 |
T120 |
5764 |
13 |
0 |
0 |
T136 |
18861 |
41 |
0 |
0 |
T138 |
3867 |
11 |
0 |
0 |
T140 |
20009 |
58 |
0 |
0 |
T145 |
36636 |
74 |
0 |
0 |
T146 |
32804 |
42 |
0 |
0 |
T147 |
10372 |
27 |
0 |
0 |
T148 |
20962 |
26 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
8574 |
0 |
0 |
T31 |
34394 |
218 |
0 |
0 |
T119 |
15933 |
128 |
0 |
0 |
T120 |
5764 |
8 |
0 |
0 |
T136 |
18861 |
37 |
0 |
0 |
T138 |
3867 |
114 |
0 |
0 |
T140 |
20009 |
103 |
0 |
0 |
T145 |
36636 |
607 |
0 |
0 |
T146 |
32804 |
560 |
0 |
0 |
T147 |
10372 |
8 |
0 |
0 |
T148 |
20962 |
85 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
8137 |
0 |
0 |
T31 |
34394 |
378 |
0 |
0 |
T119 |
15933 |
315 |
0 |
0 |
T120 |
5764 |
7 |
0 |
0 |
T136 |
18861 |
55 |
0 |
0 |
T138 |
3867 |
124 |
0 |
0 |
T140 |
20009 |
91 |
0 |
0 |
T145 |
36636 |
820 |
0 |
0 |
T146 |
32804 |
445 |
0 |
0 |
T147 |
10372 |
286 |
0 |
0 |
T148 |
20962 |
53 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
8078 |
0 |
0 |
T31 |
34394 |
277 |
0 |
0 |
T119 |
15933 |
409 |
0 |
0 |
T120 |
5764 |
93 |
0 |
0 |
T136 |
18861 |
126 |
0 |
0 |
T138 |
3867 |
7 |
0 |
0 |
T140 |
20009 |
67 |
0 |
0 |
T145 |
36636 |
584 |
0 |
0 |
T146 |
32804 |
489 |
0 |
0 |
T147 |
10372 |
257 |
0 |
0 |
T148 |
20962 |
127 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
8866 |
0 |
0 |
T31 |
34394 |
694 |
0 |
0 |
T119 |
15933 |
260 |
0 |
0 |
T120 |
5764 |
98 |
0 |
0 |
T136 |
18861 |
52 |
0 |
0 |
T138 |
3867 |
9 |
0 |
0 |
T140 |
20009 |
77 |
0 |
0 |
T145 |
36636 |
728 |
0 |
0 |
T146 |
32804 |
467 |
0 |
0 |
T147 |
10372 |
236 |
0 |
0 |
T148 |
20962 |
49 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
8068 |
0 |
0 |
T31 |
34394 |
643 |
0 |
0 |
T119 |
15933 |
272 |
0 |
0 |
T120 |
5764 |
99 |
0 |
0 |
T136 |
18861 |
70 |
0 |
0 |
T138 |
3867 |
126 |
0 |
0 |
T140 |
20009 |
78 |
0 |
0 |
T145 |
36636 |
598 |
0 |
0 |
T146 |
32804 |
412 |
0 |
0 |
T147 |
10372 |
161 |
0 |
0 |
T148 |
20962 |
66 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
7245 |
0 |
0 |
T31 |
34394 |
766 |
0 |
0 |
T119 |
15933 |
127 |
0 |
0 |
T120 |
5764 |
10 |
0 |
0 |
T136 |
18861 |
74 |
0 |
0 |
T138 |
3867 |
6 |
0 |
0 |
T140 |
20009 |
34 |
0 |
0 |
T145 |
36636 |
553 |
0 |
0 |
T146 |
32804 |
429 |
0 |
0 |
T147 |
10372 |
13 |
0 |
0 |
T148 |
20962 |
56 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
8692 |
0 |
0 |
T31 |
34394 |
921 |
0 |
0 |
T119 |
15933 |
441 |
0 |
0 |
T120 |
5764 |
14 |
0 |
0 |
T136 |
18861 |
47 |
0 |
0 |
T138 |
3867 |
2 |
0 |
0 |
T140 |
20009 |
67 |
0 |
0 |
T145 |
36636 |
667 |
0 |
0 |
T146 |
32804 |
419 |
0 |
0 |
T147 |
10372 |
123 |
0 |
0 |
T148 |
20962 |
66 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
8951 |
0 |
0 |
T31 |
34394 |
775 |
0 |
0 |
T119 |
15933 |
269 |
0 |
0 |
T120 |
5764 |
9 |
0 |
0 |
T136 |
18861 |
69 |
0 |
0 |
T138 |
3867 |
10 |
0 |
0 |
T140 |
20009 |
42 |
0 |
0 |
T145 |
36636 |
811 |
0 |
0 |
T146 |
32804 |
390 |
0 |
0 |
T147 |
10372 |
233 |
0 |
0 |
T148 |
20962 |
32 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4392 |
0 |
0 |
T31 |
34394 |
304 |
0 |
0 |
T119 |
15933 |
18 |
0 |
0 |
T120 |
5764 |
9 |
0 |
0 |
T136 |
18861 |
58 |
0 |
0 |
T138 |
3867 |
55 |
0 |
0 |
T140 |
20009 |
59 |
0 |
0 |
T145 |
36636 |
288 |
0 |
0 |
T146 |
32804 |
170 |
0 |
0 |
T147 |
10372 |
75 |
0 |
0 |
T148 |
20962 |
119 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4295 |
0 |
0 |
T31 |
34394 |
319 |
0 |
0 |
T119 |
15933 |
69 |
0 |
0 |
T120 |
5764 |
67 |
0 |
0 |
T136 |
18861 |
51 |
0 |
0 |
T138 |
3867 |
3 |
0 |
0 |
T140 |
20009 |
36 |
0 |
0 |
T145 |
36636 |
330 |
0 |
0 |
T146 |
32804 |
107 |
0 |
0 |
T147 |
10372 |
4 |
0 |
0 |
T148 |
20962 |
86 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3480 |
0 |
0 |
T31 |
34394 |
181 |
0 |
0 |
T112 |
13390 |
4 |
0 |
0 |
T119 |
15933 |
129 |
0 |
0 |
T120 |
5764 |
51 |
0 |
0 |
T136 |
18861 |
9 |
0 |
0 |
T138 |
3867 |
8 |
0 |
0 |
T140 |
20009 |
34 |
0 |
0 |
T145 |
36636 |
241 |
0 |
0 |
T146 |
32804 |
132 |
0 |
0 |
T147 |
10372 |
5 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3969 |
0 |
0 |
T31 |
34394 |
133 |
0 |
0 |
T119 |
15933 |
83 |
0 |
0 |
T120 |
5764 |
43 |
0 |
0 |
T136 |
18861 |
66 |
0 |
0 |
T140 |
20009 |
76 |
0 |
0 |
T145 |
36636 |
355 |
0 |
0 |
T146 |
32804 |
196 |
0 |
0 |
T147 |
10372 |
77 |
0 |
0 |
T148 |
20962 |
65 |
0 |
0 |
T149 |
15586 |
128 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3721 |
0 |
0 |
T31 |
34394 |
126 |
0 |
0 |
T119 |
15933 |
91 |
0 |
0 |
T120 |
5764 |
2 |
0 |
0 |
T136 |
18861 |
52 |
0 |
0 |
T138 |
3867 |
50 |
0 |
0 |
T140 |
20009 |
68 |
0 |
0 |
T145 |
36636 |
274 |
0 |
0 |
T146 |
32804 |
107 |
0 |
0 |
T147 |
10372 |
9 |
0 |
0 |
T148 |
20962 |
54 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3647 |
0 |
0 |
T31 |
34394 |
253 |
0 |
0 |
T119 |
15933 |
61 |
0 |
0 |
T120 |
5764 |
3 |
0 |
0 |
T136 |
18861 |
73 |
0 |
0 |
T138 |
3867 |
3 |
0 |
0 |
T140 |
20009 |
47 |
0 |
0 |
T145 |
36636 |
233 |
0 |
0 |
T146 |
32804 |
129 |
0 |
0 |
T147 |
10372 |
6 |
0 |
0 |
T148 |
20962 |
58 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3783 |
0 |
0 |
T31 |
34394 |
136 |
0 |
0 |
T119 |
15933 |
149 |
0 |
0 |
T120 |
5764 |
15 |
0 |
0 |
T136 |
18861 |
44 |
0 |
0 |
T138 |
3867 |
30 |
0 |
0 |
T140 |
20009 |
72 |
0 |
0 |
T145 |
36636 |
250 |
0 |
0 |
T146 |
32804 |
129 |
0 |
0 |
T147 |
10372 |
37 |
0 |
0 |
T148 |
20962 |
99 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4181 |
0 |
0 |
T31 |
34394 |
240 |
0 |
0 |
T119 |
15933 |
106 |
0 |
0 |
T120 |
5764 |
52 |
0 |
0 |
T136 |
18861 |
45 |
0 |
0 |
T138 |
3867 |
1 |
0 |
0 |
T140 |
20009 |
57 |
0 |
0 |
T145 |
36636 |
264 |
0 |
0 |
T146 |
32804 |
123 |
0 |
0 |
T147 |
10372 |
76 |
0 |
0 |
T148 |
20962 |
70 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3779 |
0 |
0 |
T31 |
34394 |
289 |
0 |
0 |
T119 |
15933 |
136 |
0 |
0 |
T120 |
5764 |
47 |
0 |
0 |
T136 |
18861 |
74 |
0 |
0 |
T138 |
3867 |
2 |
0 |
0 |
T140 |
20009 |
107 |
0 |
0 |
T145 |
36636 |
321 |
0 |
0 |
T146 |
32804 |
95 |
0 |
0 |
T147 |
10372 |
93 |
0 |
0 |
T148 |
20962 |
44 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4018 |
0 |
0 |
T31 |
34394 |
349 |
0 |
0 |
T119 |
15933 |
104 |
0 |
0 |
T120 |
5764 |
63 |
0 |
0 |
T136 |
18861 |
95 |
0 |
0 |
T138 |
3867 |
24 |
0 |
0 |
T140 |
20009 |
71 |
0 |
0 |
T145 |
36636 |
238 |
0 |
0 |
T146 |
32804 |
114 |
0 |
0 |
T147 |
10372 |
20 |
0 |
0 |
T148 |
20962 |
64 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3994 |
0 |
0 |
T31 |
34394 |
327 |
0 |
0 |
T119 |
15933 |
129 |
0 |
0 |
T120 |
5764 |
57 |
0 |
0 |
T136 |
18861 |
27 |
0 |
0 |
T140 |
20009 |
59 |
0 |
0 |
T145 |
36636 |
416 |
0 |
0 |
T146 |
32804 |
128 |
0 |
0 |
T147 |
10372 |
72 |
0 |
0 |
T148 |
20962 |
56 |
0 |
0 |
T149 |
15586 |
20 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3951 |
0 |
0 |
T31 |
34394 |
316 |
0 |
0 |
T119 |
15933 |
167 |
0 |
0 |
T120 |
5764 |
6 |
0 |
0 |
T136 |
18861 |
72 |
0 |
0 |
T138 |
3867 |
7 |
0 |
0 |
T140 |
20009 |
79 |
0 |
0 |
T145 |
36636 |
161 |
0 |
0 |
T146 |
32804 |
108 |
0 |
0 |
T147 |
10372 |
22 |
0 |
0 |
T148 |
20962 |
10 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3315 |
0 |
0 |
T31 |
34394 |
245 |
0 |
0 |
T119 |
15933 |
28 |
0 |
0 |
T120 |
5764 |
1 |
0 |
0 |
T136 |
18861 |
89 |
0 |
0 |
T138 |
3867 |
6 |
0 |
0 |
T140 |
20009 |
27 |
0 |
0 |
T145 |
36636 |
275 |
0 |
0 |
T146 |
32804 |
176 |
0 |
0 |
T147 |
10372 |
9 |
0 |
0 |
T148 |
20962 |
38 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4191 |
0 |
0 |
T31 |
34394 |
308 |
0 |
0 |
T119 |
15933 |
109 |
0 |
0 |
T120 |
5764 |
31 |
0 |
0 |
T136 |
18861 |
44 |
0 |
0 |
T138 |
3867 |
4 |
0 |
0 |
T140 |
20009 |
44 |
0 |
0 |
T145 |
36636 |
224 |
0 |
0 |
T146 |
32804 |
192 |
0 |
0 |
T147 |
10372 |
68 |
0 |
0 |
T148 |
20962 |
55 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3871 |
0 |
0 |
T31 |
34394 |
119 |
0 |
0 |
T119 |
15933 |
124 |
0 |
0 |
T120 |
5764 |
30 |
0 |
0 |
T136 |
18861 |
29 |
0 |
0 |
T138 |
3867 |
28 |
0 |
0 |
T140 |
20009 |
71 |
0 |
0 |
T145 |
36636 |
257 |
0 |
0 |
T146 |
32804 |
112 |
0 |
0 |
T147 |
10372 |
88 |
0 |
0 |
T148 |
20962 |
58 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4356 |
0 |
0 |
T31 |
34394 |
350 |
0 |
0 |
T119 |
15933 |
31 |
0 |
0 |
T120 |
5764 |
8 |
0 |
0 |
T136 |
18861 |
77 |
0 |
0 |
T138 |
3867 |
53 |
0 |
0 |
T140 |
20009 |
69 |
0 |
0 |
T145 |
36636 |
286 |
0 |
0 |
T146 |
32804 |
177 |
0 |
0 |
T147 |
10372 |
90 |
0 |
0 |
T148 |
20962 |
54 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3780 |
0 |
0 |
T31 |
34394 |
268 |
0 |
0 |
T119 |
15933 |
61 |
0 |
0 |
T120 |
5764 |
66 |
0 |
0 |
T136 |
18861 |
56 |
0 |
0 |
T138 |
3867 |
4 |
0 |
0 |
T140 |
20009 |
38 |
0 |
0 |
T145 |
36636 |
160 |
0 |
0 |
T146 |
32804 |
83 |
0 |
0 |
T147 |
10372 |
9 |
0 |
0 |
T148 |
20962 |
85 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4045 |
0 |
0 |
T31 |
34394 |
286 |
0 |
0 |
T119 |
15933 |
65 |
0 |
0 |
T120 |
5764 |
38 |
0 |
0 |
T136 |
18861 |
32 |
0 |
0 |
T138 |
3867 |
49 |
0 |
0 |
T140 |
20009 |
69 |
0 |
0 |
T145 |
36636 |
286 |
0 |
0 |
T146 |
32804 |
85 |
0 |
0 |
T147 |
10372 |
12 |
0 |
0 |
T148 |
20962 |
50 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4247 |
0 |
0 |
T31 |
34394 |
278 |
0 |
0 |
T119 |
15933 |
162 |
0 |
0 |
T120 |
5764 |
49 |
0 |
0 |
T136 |
18861 |
22 |
0 |
0 |
T138 |
3867 |
37 |
0 |
0 |
T140 |
20009 |
38 |
0 |
0 |
T145 |
36636 |
326 |
0 |
0 |
T146 |
32804 |
121 |
0 |
0 |
T147 |
10372 |
81 |
0 |
0 |
T148 |
20962 |
57 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4389 |
0 |
0 |
T31 |
34394 |
255 |
0 |
0 |
T119 |
15933 |
87 |
0 |
0 |
T120 |
5764 |
49 |
0 |
0 |
T136 |
18861 |
75 |
0 |
0 |
T138 |
3867 |
8 |
0 |
0 |
T140 |
20009 |
73 |
0 |
0 |
T145 |
36636 |
258 |
0 |
0 |
T146 |
32804 |
223 |
0 |
0 |
T147 |
10372 |
112 |
0 |
0 |
T148 |
20962 |
63 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3968 |
0 |
0 |
T31 |
34394 |
448 |
0 |
0 |
T119 |
15933 |
134 |
0 |
0 |
T120 |
5764 |
4 |
0 |
0 |
T136 |
18861 |
61 |
0 |
0 |
T138 |
3867 |
9 |
0 |
0 |
T140 |
20009 |
56 |
0 |
0 |
T145 |
36636 |
222 |
0 |
0 |
T146 |
32804 |
120 |
0 |
0 |
T147 |
10372 |
82 |
0 |
0 |
T148 |
20962 |
33 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3864 |
0 |
0 |
T31 |
34394 |
302 |
0 |
0 |
T119 |
15933 |
177 |
0 |
0 |
T120 |
5764 |
11 |
0 |
0 |
T136 |
18861 |
60 |
0 |
0 |
T138 |
3867 |
64 |
0 |
0 |
T140 |
20009 |
45 |
0 |
0 |
T145 |
36636 |
191 |
0 |
0 |
T146 |
32804 |
79 |
0 |
0 |
T147 |
10372 |
21 |
0 |
0 |
T148 |
20962 |
57 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
3653 |
0 |
0 |
T31 |
34394 |
264 |
0 |
0 |
T119 |
15933 |
60 |
0 |
0 |
T120 |
5764 |
56 |
0 |
0 |
T136 |
18861 |
63 |
0 |
0 |
T138 |
3867 |
3 |
0 |
0 |
T140 |
20009 |
6 |
0 |
0 |
T145 |
36636 |
221 |
0 |
0 |
T146 |
32804 |
165 |
0 |
0 |
T147 |
10372 |
95 |
0 |
0 |
T148 |
20962 |
70 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
4061 |
0 |
0 |
T31 |
34394 |
258 |
0 |
0 |
T119 |
15933 |
95 |
0 |
0 |
T120 |
5764 |
4 |
0 |
0 |
T136 |
18861 |
72 |
0 |
0 |
T140 |
20009 |
72 |
0 |
0 |
T145 |
36636 |
204 |
0 |
0 |
T146 |
32804 |
62 |
0 |
0 |
T147 |
10372 |
52 |
0 |
0 |
T148 |
20962 |
90 |
0 |
0 |
T149 |
15586 |
65 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1684 |
0 |
0 |
T31 |
34394 |
61 |
0 |
0 |
T119 |
15933 |
28 |
0 |
0 |
T120 |
5764 |
6 |
0 |
0 |
T136 |
18861 |
88 |
0 |
0 |
T138 |
3867 |
5 |
0 |
0 |
T140 |
20009 |
59 |
0 |
0 |
T145 |
36636 |
54 |
0 |
0 |
T146 |
32804 |
44 |
0 |
0 |
T147 |
10372 |
10 |
0 |
0 |
T148 |
20962 |
51 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1699 |
0 |
0 |
T31 |
34394 |
45 |
0 |
0 |
T119 |
15933 |
20 |
0 |
0 |
T120 |
5764 |
11 |
0 |
0 |
T136 |
18861 |
63 |
0 |
0 |
T138 |
3867 |
1 |
0 |
0 |
T140 |
20009 |
63 |
0 |
0 |
T145 |
36636 |
76 |
0 |
0 |
T146 |
32804 |
41 |
0 |
0 |
T147 |
10372 |
17 |
0 |
0 |
T148 |
20962 |
23 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1683 |
0 |
0 |
T31 |
34394 |
46 |
0 |
0 |
T119 |
15933 |
31 |
0 |
0 |
T120 |
5764 |
8 |
0 |
0 |
T136 |
18861 |
45 |
0 |
0 |
T140 |
20009 |
66 |
0 |
0 |
T145 |
36636 |
65 |
0 |
0 |
T146 |
32804 |
22 |
0 |
0 |
T147 |
10372 |
10 |
0 |
0 |
T148 |
20962 |
77 |
0 |
0 |
T149 |
15586 |
38 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1687 |
0 |
0 |
T31 |
34394 |
44 |
0 |
0 |
T119 |
15933 |
13 |
0 |
0 |
T120 |
5764 |
17 |
0 |
0 |
T136 |
18861 |
86 |
0 |
0 |
T138 |
3867 |
2 |
0 |
0 |
T140 |
20009 |
112 |
0 |
0 |
T145 |
36636 |
55 |
0 |
0 |
T146 |
32804 |
30 |
0 |
0 |
T147 |
10372 |
7 |
0 |
0 |
T148 |
20962 |
66 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
2243 |
0 |
0 |
T31 |
34394 |
79 |
0 |
0 |
T119 |
15933 |
51 |
0 |
0 |
T120 |
5764 |
6 |
0 |
0 |
T136 |
18861 |
68 |
0 |
0 |
T138 |
3867 |
2 |
0 |
0 |
T140 |
20009 |
38 |
0 |
0 |
T145 |
36636 |
102 |
0 |
0 |
T146 |
32804 |
75 |
0 |
0 |
T147 |
10372 |
43 |
0 |
0 |
T148 |
20962 |
97 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
2991 |
0 |
0 |
T31 |
0 |
98 |
0 |
0 |
T36 |
6768 |
47 |
0 |
0 |
T86 |
104731 |
0 |
0 |
0 |
T96 |
2525 |
0 |
0 |
0 |
T97 |
264804 |
0 |
0 |
0 |
T98 |
234744 |
0 |
0 |
0 |
T119 |
0 |
14 |
0 |
0 |
T120 |
0 |
13 |
0 |
0 |
T141 |
174311 |
0 |
0 |
0 |
T142 |
11943 |
0 |
0 |
0 |
T145 |
0 |
98 |
0 |
0 |
T150 |
0 |
41 |
0 |
0 |
T151 |
0 |
8 |
0 |
0 |
T152 |
0 |
40 |
0 |
0 |
T153 |
0 |
5 |
0 |
0 |
T154 |
0 |
24 |
0 |
0 |
T155 |
1455 |
0 |
0 |
0 |
T156 |
219348 |
0 |
0 |
0 |
T157 |
12852 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1667 |
0 |
0 |
T31 |
34394 |
82 |
0 |
0 |
T119 |
15933 |
35 |
0 |
0 |
T120 |
5764 |
6 |
0 |
0 |
T136 |
18861 |
19 |
0 |
0 |
T138 |
3867 |
2 |
0 |
0 |
T140 |
20009 |
5 |
0 |
0 |
T145 |
36636 |
51 |
0 |
0 |
T146 |
32804 |
33 |
0 |
0 |
T147 |
10372 |
24 |
0 |
0 |
T148 |
20962 |
31 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1586 |
0 |
0 |
T31 |
34394 |
47 |
0 |
0 |
T119 |
15933 |
32 |
0 |
0 |
T120 |
5764 |
1 |
0 |
0 |
T136 |
18861 |
23 |
0 |
0 |
T138 |
3867 |
2 |
0 |
0 |
T140 |
20009 |
25 |
0 |
0 |
T145 |
36636 |
74 |
0 |
0 |
T146 |
32804 |
31 |
0 |
0 |
T147 |
10372 |
21 |
0 |
0 |
T148 |
20962 |
64 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1686 |
0 |
0 |
T31 |
34394 |
24 |
0 |
0 |
T119 |
15933 |
32 |
0 |
0 |
T120 |
5764 |
1 |
0 |
0 |
T136 |
18861 |
107 |
0 |
0 |
T138 |
3867 |
7 |
0 |
0 |
T140 |
20009 |
70 |
0 |
0 |
T145 |
36636 |
45 |
0 |
0 |
T146 |
32804 |
23 |
0 |
0 |
T147 |
10372 |
6 |
0 |
0 |
T148 |
20962 |
138 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1443 |
0 |
0 |
T31 |
34394 |
37 |
0 |
0 |
T119 |
15933 |
32 |
0 |
0 |
T120 |
5764 |
3 |
0 |
0 |
T136 |
18861 |
93 |
0 |
0 |
T138 |
3867 |
2 |
0 |
0 |
T140 |
20009 |
25 |
0 |
0 |
T145 |
36636 |
50 |
0 |
0 |
T146 |
32804 |
22 |
0 |
0 |
T147 |
10372 |
21 |
0 |
0 |
T148 |
20962 |
48 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1593 |
0 |
0 |
T31 |
34394 |
34 |
0 |
0 |
T119 |
15933 |
27 |
0 |
0 |
T120 |
5764 |
8 |
0 |
0 |
T136 |
18861 |
64 |
0 |
0 |
T140 |
20009 |
104 |
0 |
0 |
T145 |
36636 |
45 |
0 |
0 |
T146 |
32804 |
23 |
0 |
0 |
T147 |
10372 |
16 |
0 |
0 |
T148 |
20962 |
88 |
0 |
0 |
T149 |
15586 |
19 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1568 |
0 |
0 |
T31 |
34394 |
50 |
0 |
0 |
T119 |
15933 |
33 |
0 |
0 |
T120 |
5764 |
5 |
0 |
0 |
T136 |
18861 |
50 |
0 |
0 |
T140 |
20009 |
71 |
0 |
0 |
T145 |
36636 |
19 |
0 |
0 |
T146 |
32804 |
29 |
0 |
0 |
T147 |
10372 |
15 |
0 |
0 |
T148 |
20962 |
53 |
0 |
0 |
T149 |
15586 |
26 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
2204 |
0 |
0 |
T31 |
34394 |
104 |
0 |
0 |
T119 |
15933 |
50 |
0 |
0 |
T120 |
5764 |
13 |
0 |
0 |
T136 |
18861 |
88 |
0 |
0 |
T138 |
3867 |
6 |
0 |
0 |
T140 |
20009 |
44 |
0 |
0 |
T145 |
36636 |
74 |
0 |
0 |
T146 |
32804 |
56 |
0 |
0 |
T147 |
10372 |
20 |
0 |
0 |
T148 |
20962 |
50 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1538 |
0 |
0 |
T31 |
34394 |
32 |
0 |
0 |
T119 |
15933 |
37 |
0 |
0 |
T136 |
18861 |
62 |
0 |
0 |
T138 |
3867 |
4 |
0 |
0 |
T140 |
20009 |
54 |
0 |
0 |
T145 |
36636 |
36 |
0 |
0 |
T146 |
32804 |
26 |
0 |
0 |
T147 |
10372 |
19 |
0 |
0 |
T148 |
20962 |
84 |
0 |
0 |
T149 |
15586 |
17 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
2235 |
0 |
0 |
T31 |
34394 |
89 |
0 |
0 |
T119 |
15933 |
59 |
0 |
0 |
T120 |
5764 |
17 |
0 |
0 |
T136 |
18861 |
76 |
0 |
0 |
T138 |
3867 |
5 |
0 |
0 |
T140 |
20009 |
81 |
0 |
0 |
T145 |
36636 |
135 |
0 |
0 |
T146 |
32804 |
69 |
0 |
0 |
T147 |
10372 |
13 |
0 |
0 |
T148 |
20962 |
49 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1753 |
0 |
0 |
T31 |
34394 |
76 |
0 |
0 |
T119 |
15933 |
26 |
0 |
0 |
T120 |
5764 |
12 |
0 |
0 |
T136 |
18861 |
92 |
0 |
0 |
T138 |
3867 |
3 |
0 |
0 |
T140 |
20009 |
28 |
0 |
0 |
T145 |
36636 |
69 |
0 |
0 |
T146 |
32804 |
37 |
0 |
0 |
T147 |
10372 |
7 |
0 |
0 |
T148 |
20962 |
82 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1540 |
0 |
0 |
T31 |
34394 |
39 |
0 |
0 |
T119 |
15933 |
17 |
0 |
0 |
T120 |
5764 |
13 |
0 |
0 |
T136 |
18861 |
53 |
0 |
0 |
T138 |
3867 |
9 |
0 |
0 |
T140 |
20009 |
64 |
0 |
0 |
T145 |
36636 |
36 |
0 |
0 |
T146 |
32804 |
26 |
0 |
0 |
T147 |
10372 |
15 |
0 |
0 |
T148 |
20962 |
90 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1575 |
0 |
0 |
T31 |
34394 |
42 |
0 |
0 |
T119 |
15933 |
11 |
0 |
0 |
T120 |
5764 |
6 |
0 |
0 |
T136 |
18861 |
76 |
0 |
0 |
T138 |
3867 |
5 |
0 |
0 |
T140 |
20009 |
82 |
0 |
0 |
T145 |
36636 |
50 |
0 |
0 |
T146 |
32804 |
22 |
0 |
0 |
T147 |
10372 |
23 |
0 |
0 |
T148 |
20962 |
67 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1499 |
0 |
0 |
T31 |
34394 |
42 |
0 |
0 |
T119 |
15933 |
25 |
0 |
0 |
T120 |
5764 |
9 |
0 |
0 |
T136 |
18861 |
96 |
0 |
0 |
T140 |
20009 |
44 |
0 |
0 |
T145 |
36636 |
23 |
0 |
0 |
T146 |
32804 |
21 |
0 |
0 |
T147 |
10372 |
21 |
0 |
0 |
T148 |
20962 |
125 |
0 |
0 |
T149 |
15586 |
18 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1485 |
0 |
0 |
T31 |
34394 |
43 |
0 |
0 |
T112 |
13390 |
5 |
0 |
0 |
T119 |
15933 |
18 |
0 |
0 |
T120 |
5764 |
3 |
0 |
0 |
T136 |
18861 |
82 |
0 |
0 |
T138 |
3867 |
6 |
0 |
0 |
T140 |
20009 |
38 |
0 |
0 |
T145 |
36636 |
51 |
0 |
0 |
T146 |
32804 |
7 |
0 |
0 |
T147 |
10372 |
19 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1366 |
0 |
0 |
T31 |
34394 |
53 |
0 |
0 |
T119 |
15933 |
31 |
0 |
0 |
T120 |
5764 |
5 |
0 |
0 |
T136 |
18861 |
42 |
0 |
0 |
T138 |
3867 |
1 |
0 |
0 |
T140 |
20009 |
57 |
0 |
0 |
T145 |
36636 |
36 |
0 |
0 |
T146 |
32804 |
18 |
0 |
0 |
T147 |
10372 |
23 |
0 |
0 |
T148 |
20962 |
91 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
138037816 |
1562 |
0 |
0 |
T31 |
34394 |
26 |
0 |
0 |
T119 |
15933 |
19 |
0 |
0 |
T120 |
5764 |
3 |
0 |
0 |
T136 |
18861 |
77 |
0 |
0 |
T138 |
3867 |
5 |
0 |
0 |
T140 |
20009 |
59 |
0 |
0 |
T145 |
36636 |
30 |
0 |
0 |
T146 |
32804 |
5 |
0 |
0 |
T147 |
10372 |
29 |
0 |
0 |
T148 |
20962 |
60 |
0 |
0 |