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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.15 97.51 92.84 98.61 80.85 95.88 90.96 88.38


Total test records in report: 834
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T761 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1523503045 Apr 16 12:51:24 PM PDT 24 Apr 16 12:51:26 PM PDT 24 36682772 ps
T93 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3362451997 Apr 16 12:50:59 PM PDT 24 Apr 16 12:51:02 PM PDT 24 125477667 ps
T762 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1918785880 Apr 16 12:51:26 PM PDT 24 Apr 16 12:51:29 PM PDT 24 46335511 ps
T371 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.719634890 Apr 16 12:50:58 PM PDT 24 Apr 16 12:51:08 PM PDT 24 1136330277 ps
T763 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1009960020 Apr 16 12:51:23 PM PDT 24 Apr 16 12:51:25 PM PDT 24 15369024 ps
T764 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.479898804 Apr 16 12:51:04 PM PDT 24 Apr 16 12:51:10 PM PDT 24 61135716 ps
T765 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.304121415 Apr 16 12:51:04 PM PDT 24 Apr 16 12:51:11 PM PDT 24 2232293653 ps
T766 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3904350607 Apr 16 12:51:03 PM PDT 24 Apr 16 12:51:06 PM PDT 24 13473919 ps
T767 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.670184188 Apr 16 12:51:29 PM PDT 24 Apr 16 12:51:32 PM PDT 24 41143117 ps
T768 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2626660363 Apr 16 12:51:21 PM PDT 24 Apr 16 12:51:23 PM PDT 24 12983162 ps
T769 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.927828112 Apr 16 12:51:13 PM PDT 24 Apr 16 12:51:17 PM PDT 24 170395071 ps
T770 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4035153459 Apr 16 12:51:02 PM PDT 24 Apr 16 12:51:08 PM PDT 24 417585773 ps
T771 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1831124140 Apr 16 12:51:10 PM PDT 24 Apr 16 12:51:13 PM PDT 24 243346797 ps
T135 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.707841477 Apr 16 12:51:00 PM PDT 24 Apr 16 12:51:18 PM PDT 24 1044583736 ps
T772 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1154198915 Apr 16 12:51:21 PM PDT 24 Apr 16 12:51:30 PM PDT 24 355645187 ps
T363 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2981260096 Apr 16 12:51:10 PM PDT 24 Apr 16 12:51:15 PM PDT 24 477088186 ps
T773 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2623840610 Apr 16 12:51:02 PM PDT 24 Apr 16 12:51:26 PM PDT 24 1040643124 ps
T774 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1065085848 Apr 16 12:51:05 PM PDT 24 Apr 16 12:51:08 PM PDT 24 18122204 ps
T775 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.47323828 Apr 16 12:51:04 PM PDT 24 Apr 16 12:51:08 PM PDT 24 230973476 ps
T776 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3433659516 Apr 16 12:51:03 PM PDT 24 Apr 16 12:51:07 PM PDT 24 65323323 ps
T365 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.507306797 Apr 16 12:51:00 PM PDT 24 Apr 16 12:51:15 PM PDT 24 207568187 ps
T94 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1487983348 Apr 16 12:51:06 PM PDT 24 Apr 16 12:51:10 PM PDT 24 84072470 ps
T777 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2768978785 Apr 16 12:51:10 PM PDT 24 Apr 16 12:51:14 PM PDT 24 99434582 ps
T778 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3214873936 Apr 16 12:51:17 PM PDT 24 Apr 16 12:51:19 PM PDT 24 35144721 ps
T779 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.753246036 Apr 16 12:51:15 PM PDT 24 Apr 16 12:51:17 PM PDT 24 28457686 ps
T780 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.678172453 Apr 16 12:50:56 PM PDT 24 Apr 16 12:51:03 PM PDT 24 572467738 ps
T781 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3223575990 Apr 16 12:51:23 PM PDT 24 Apr 16 12:51:25 PM PDT 24 57826534 ps
T782 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1191217566 Apr 16 12:51:26 PM PDT 24 Apr 16 12:51:29 PM PDT 24 40621635 ps
T783 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.511620922 Apr 16 12:51:11 PM PDT 24 Apr 16 12:51:13 PM PDT 24 53744610 ps
T784 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2336432369 Apr 16 12:51:11 PM PDT 24 Apr 16 12:51:14 PM PDT 24 101591335 ps
T785 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2342591303 Apr 16 12:51:03 PM PDT 24 Apr 16 12:51:30 PM PDT 24 1233664638 ps
T786 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.564538927 Apr 16 12:50:59 PM PDT 24 Apr 16 12:51:02 PM PDT 24 65550580 ps
T787 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1736617252 Apr 16 12:51:35 PM PDT 24 Apr 16 12:51:39 PM PDT 24 562651586 ps
T788 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1790108627 Apr 16 12:51:29 PM PDT 24 Apr 16 12:51:32 PM PDT 24 18912714 ps
T789 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.311148169 Apr 16 12:51:13 PM PDT 24 Apr 16 12:51:15 PM PDT 24 28416518 ps
T790 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.454340919 Apr 16 12:51:03 PM PDT 24 Apr 16 12:51:36 PM PDT 24 537657541 ps
T791 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.803913172 Apr 16 12:51:19 PM PDT 24 Apr 16 12:51:23 PM PDT 24 45861168 ps
T792 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2482158096 Apr 16 12:50:58 PM PDT 24 Apr 16 12:51:01 PM PDT 24 66592907 ps
T793 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1966510413 Apr 16 12:51:05 PM PDT 24 Apr 16 12:51:10 PM PDT 24 86333495 ps
T794 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.939411420 Apr 16 12:51:01 PM PDT 24 Apr 16 12:51:04 PM PDT 24 37505459 ps
T795 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3465613654 Apr 16 12:50:57 PM PDT 24 Apr 16 12:51:02 PM PDT 24 64768044 ps
T796 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.992951314 Apr 16 12:51:07 PM PDT 24 Apr 16 12:51:12 PM PDT 24 107248055 ps
T797 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.53536975 Apr 16 12:51:07 PM PDT 24 Apr 16 12:51:09 PM PDT 24 18253387 ps
T798 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1011991857 Apr 16 12:51:02 PM PDT 24 Apr 16 12:51:06 PM PDT 24 1664717089 ps
T799 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3770969129 Apr 16 12:50:53 PM PDT 24 Apr 16 12:50:59 PM PDT 24 110356413 ps
T800 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2992460615 Apr 16 12:51:30 PM PDT 24 Apr 16 12:51:33 PM PDT 24 18637819 ps
T801 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.380477439 Apr 16 12:51:11 PM PDT 24 Apr 16 12:51:13 PM PDT 24 10706800 ps
T802 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3809100364 Apr 16 12:51:13 PM PDT 24 Apr 16 12:51:18 PM PDT 24 135368017 ps
T803 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4015008781 Apr 16 12:51:27 PM PDT 24 Apr 16 12:51:30 PM PDT 24 15295384 ps
T368 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2120584644 Apr 16 12:51:08 PM PDT 24 Apr 16 12:51:32 PM PDT 24 1592627633 ps
T804 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1558081219 Apr 16 12:51:25 PM PDT 24 Apr 16 12:51:27 PM PDT 24 29568607 ps
T805 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1772926439 Apr 16 12:51:31 PM PDT 24 Apr 16 12:51:33 PM PDT 24 144852358 ps
T806 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2702402321 Apr 16 12:51:16 PM PDT 24 Apr 16 12:51:17 PM PDT 24 42300792 ps
T807 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2383044280 Apr 16 12:51:22 PM PDT 24 Apr 16 12:51:25 PM PDT 24 274127454 ps
T808 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2321088379 Apr 16 12:51:03 PM PDT 24 Apr 16 12:51:07 PM PDT 24 35997212 ps
T809 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.621281723 Apr 16 12:51:00 PM PDT 24 Apr 16 12:51:19 PM PDT 24 2532834603 ps
T372 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1884583378 Apr 16 12:51:07 PM PDT 24 Apr 16 12:51:22 PM PDT 24 2262271889 ps
T810 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3670690436 Apr 16 12:51:05 PM PDT 24 Apr 16 12:51:10 PM PDT 24 595023376 ps
T811 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3643024679 Apr 16 12:51:19 PM PDT 24 Apr 16 12:51:20 PM PDT 24 16412912 ps
T812 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.818378956 Apr 16 12:51:04 PM PDT 24 Apr 16 12:51:08 PM PDT 24 167079768 ps
T813 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.559360182 Apr 16 12:51:17 PM PDT 24 Apr 16 12:51:19 PM PDT 24 20474826 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1686925100 Apr 16 12:50:59 PM PDT 24 Apr 16 12:51:02 PM PDT 24 25384404 ps
T814 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.179565653 Apr 16 12:50:59 PM PDT 24 Apr 16 12:51:03 PM PDT 24 152629258 ps
T815 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3938819518 Apr 16 12:51:02 PM PDT 24 Apr 16 12:51:06 PM PDT 24 186558239 ps
T816 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.935650583 Apr 16 12:51:07 PM PDT 24 Apr 16 12:51:11 PM PDT 24 224257902 ps
T817 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3440329164 Apr 16 12:51:19 PM PDT 24 Apr 16 12:51:21 PM PDT 24 57589106 ps
T818 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1574308690 Apr 16 12:51:06 PM PDT 24 Apr 16 12:51:12 PM PDT 24 544183887 ps
T819 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2398775329 Apr 16 12:50:54 PM PDT 24 Apr 16 12:50:57 PM PDT 24 289055735 ps
T820 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1883882211 Apr 16 12:51:12 PM PDT 24 Apr 16 12:51:15 PM PDT 24 107843281 ps
T821 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2082661411 Apr 16 12:51:02 PM PDT 24 Apr 16 12:51:07 PM PDT 24 109807562 ps
T822 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3621931154 Apr 16 12:51:17 PM PDT 24 Apr 16 12:51:22 PM PDT 24 278404369 ps
T823 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2983422049 Apr 16 12:51:13 PM PDT 24 Apr 16 12:51:16 PM PDT 24 872948307 ps
T824 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3039142917 Apr 16 12:51:28 PM PDT 24 Apr 16 12:51:30 PM PDT 24 13848819 ps
T825 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4113265038 Apr 16 12:51:03 PM PDT 24 Apr 16 12:51:09 PM PDT 24 46387383 ps
T826 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3751659377 Apr 16 12:51:10 PM PDT 24 Apr 16 12:51:12 PM PDT 24 18309237 ps
T827 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1104167718 Apr 16 12:51:31 PM PDT 24 Apr 16 12:51:34 PM PDT 24 69202870 ps
T828 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.494761598 Apr 16 12:51:22 PM PDT 24 Apr 16 12:51:26 PM PDT 24 106754192 ps
T829 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.763283699 Apr 16 12:51:12 PM PDT 24 Apr 16 12:51:18 PM PDT 24 151040898 ps
T830 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3070510861 Apr 16 12:51:00 PM PDT 24 Apr 16 12:51:04 PM PDT 24 122396033 ps
T831 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1056524166 Apr 16 12:51:05 PM PDT 24 Apr 16 12:51:08 PM PDT 24 10610177 ps
T832 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1683090649 Apr 16 12:51:13 PM PDT 24 Apr 16 12:51:17 PM PDT 24 67510860 ps
T833 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3523995160 Apr 16 12:51:11 PM PDT 24 Apr 16 12:51:15 PM PDT 24 150680112 ps
T373 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2630299211 Apr 16 12:51:05 PM PDT 24 Apr 16 12:51:22 PM PDT 24 1102105017 ps
T834 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3818171413 Apr 16 12:51:10 PM PDT 24 Apr 16 12:51:13 PM PDT 24 95325074 ps

Test location /workspace/coverage/default/9.spi_device_flash_mode.4086654684
Short name T6
Test name
Test status
Simulation time 5702138322 ps
CPU time 28.88 seconds
Started Apr 16 12:47:35 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 240856 kb
Host smart-6e59b904-529e-44fb-9209-275ca6020e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086654684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4086654684
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1379862965
Short name T20
Test name
Test status
Simulation time 7762880608 ps
CPU time 42.04 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:50:26 PM PDT 24
Peak memory 215840 kb
Host smart-a80878e7-06b1-4cca-96db-0081243158eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379862965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1379862965
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_upload.3155625479
Short name T5
Test name
Test status
Simulation time 2689477587 ps
CPU time 11.18 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 223780 kb
Host smart-d62f5761-987f-4061-acca-1ce3ffb66a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155625479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3155625479
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1708705944
Short name T81
Test name
Test status
Simulation time 6834356561 ps
CPU time 49.43 seconds
Started Apr 16 12:47:16 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 224516 kb
Host smart-365a6960-e187-4695-9f28-ddfce28ade75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708705944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1708705944
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4260071813
Short name T31
Test name
Test status
Simulation time 1910849050 ps
CPU time 8.29 seconds
Started Apr 16 12:51:06 PM PDT 24
Finished Apr 16 12:51:16 PM PDT 24
Peak memory 215128 kb
Host smart-9e122ea0-1bc2-4f2c-861d-33999b386df2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260071813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4260071813
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3056877146
Short name T37
Test name
Test status
Simulation time 104088877 ps
CPU time 0.96 seconds
Started Apr 16 12:47:41 PM PDT 24
Finished Apr 16 12:47:43 PM PDT 24
Peak memory 207060 kb
Host smart-938055df-1270-4cec-ae5b-93613470a4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056877146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3056877146
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2471016384
Short name T40
Test name
Test status
Simulation time 20324819257 ps
CPU time 50.33 seconds
Started Apr 16 12:47:13 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 220116 kb
Host smart-827eb3f8-7bd1-46d9-bdb0-e499c57ad077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471016384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2471016384
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_upload.3534747768
Short name T67
Test name
Test status
Simulation time 1256257052 ps
CPU time 12.63 seconds
Started Apr 16 12:48:55 PM PDT 24
Finished Apr 16 12:49:09 PM PDT 24
Peak memory 218844 kb
Host smart-e67f89c2-7f4c-467c-9c90-e3cfd6d583e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534747768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3534747768
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2324896715
Short name T99
Test name
Test status
Simulation time 5937626600 ps
CPU time 41.94 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:40 PM PDT 24
Peak memory 216140 kb
Host smart-3a6cf688-1479-45c5-9b96-8e0a87140088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324896715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2324896715
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3120467419
Short name T38
Test name
Test status
Simulation time 42771084 ps
CPU time 0.73 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:47:13 PM PDT 24
Peak memory 216100 kb
Host smart-79fe4df1-7bcd-4360-b478-5394dd0bcbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120467419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3120467419
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3236065746
Short name T380
Test name
Test status
Simulation time 33144947587 ps
CPU time 51.39 seconds
Started Apr 16 12:47:38 PM PDT 24
Finished Apr 16 12:48:31 PM PDT 24
Peak memory 216284 kb
Host smart-0d9f857e-8221-452f-9208-d3c307434bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236065746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3236065746
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2317590184
Short name T33
Test name
Test status
Simulation time 439044503 ps
CPU time 3.78 seconds
Started Apr 16 12:51:18 PM PDT 24
Finished Apr 16 12:51:23 PM PDT 24
Peak memory 216392 kb
Host smart-0cc5bf85-8703-4acb-9b45-5d5efa65d9d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317590184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2317590184
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.687476124
Short name T63
Test name
Test status
Simulation time 11079547529 ps
CPU time 13.2 seconds
Started Apr 16 12:48:04 PM PDT 24
Finished Apr 16 12:48:20 PM PDT 24
Peak memory 221068 kb
Host smart-2b73c1df-8398-47dc-bf25-3309650dd6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687476124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.687476124
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3629981734
Short name T29
Test name
Test status
Simulation time 1051640453 ps
CPU time 1.15 seconds
Started Apr 16 12:46:57 PM PDT 24
Finished Apr 16 12:47:02 PM PDT 24
Peak memory 234860 kb
Host smart-b07f2fc6-9b6f-405c-bfe6-89e10d30eae9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629981734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3629981734
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.717465815
Short name T237
Test name
Test status
Simulation time 4635458689 ps
CPU time 8.65 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:49:03 PM PDT 24
Peak memory 223316 kb
Host smart-e8f0e97e-0172-4164-bb79-d1e9de0733bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717465815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.717465815
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3938173484
Short name T178
Test name
Test status
Simulation time 10397145054 ps
CPU time 111.61 seconds
Started Apr 16 12:47:11 PM PDT 24
Finished Apr 16 12:49:05 PM PDT 24
Peak memory 233392 kb
Host smart-1a4e8dac-9aa3-49db-a61a-cc67a495258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938173484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3938173484
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1356196141
Short name T85
Test name
Test status
Simulation time 20891084236 ps
CPU time 41.11 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 232620 kb
Host smart-7d411474-a984-43f3-b33b-9ba4e5c08d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356196141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1356196141
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_upload.110596918
Short name T266
Test name
Test status
Simulation time 654288511 ps
CPU time 5.68 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 216144 kb
Host smart-823288d3-c06b-4afc-9084-16d9640db1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110596918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.110596918
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3716468157
Short name T384
Test name
Test status
Simulation time 22689477936 ps
CPU time 58.09 seconds
Started Apr 16 12:48:39 PM PDT 24
Finished Apr 16 12:49:40 PM PDT 24
Peak memory 216276 kb
Host smart-65f4b9c1-68b9-47a1-ab62-f39b484d72a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716468157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3716468157
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1994922353
Short name T123
Test name
Test status
Simulation time 38385581 ps
CPU time 2.68 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 215044 kb
Host smart-6ffdab85-8efb-4c49-b24c-8297fd3f86de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994922353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1994922353
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1272718011
Short name T171
Test name
Test status
Simulation time 4585656744 ps
CPU time 8.51 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:27 PM PDT 24
Peak memory 223032 kb
Host smart-af12c479-d1f2-4608-92a1-710fb09107b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272718011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1272718011
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3990538877
Short name T61
Test name
Test status
Simulation time 2172694752 ps
CPU time 6.17 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 218528 kb
Host smart-288fef39-7a71-49f3-a9f4-543db8bc6da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990538877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3990538877
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_upload.4119347129
Short name T291
Test name
Test status
Simulation time 7955964358 ps
CPU time 11.14 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:14 PM PDT 24
Peak memory 223024 kb
Host smart-38856f9b-d24a-4828-bfcc-a138c12d9da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119347129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.4119347129
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.820983475
Short name T59
Test name
Test status
Simulation time 2971149022 ps
CPU time 12.64 seconds
Started Apr 16 12:48:36 PM PDT 24
Finished Apr 16 12:48:50 PM PDT 24
Peak memory 221424 kb
Host smart-83bcc272-b559-4687-9ace-dd7425a56f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820983475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.820983475
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.667227646
Short name T55
Test name
Test status
Simulation time 13921137501 ps
CPU time 35.61 seconds
Started Apr 16 12:48:47 PM PDT 24
Finished Apr 16 12:49:25 PM PDT 24
Peak memory 216236 kb
Host smart-d07b5002-3732-4c81-8142-feed9cee78f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667227646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.667227646
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3383237595
Short name T265
Test name
Test status
Simulation time 3548292273 ps
CPU time 6.4 seconds
Started Apr 16 12:48:37 PM PDT 24
Finished Apr 16 12:48:45 PM PDT 24
Peak memory 221828 kb
Host smart-8517128a-f93d-4fba-8792-e541bad2a0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383237595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3383237595
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2757424032
Short name T323
Test name
Test status
Simulation time 3231974207 ps
CPU time 8.26 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:28 PM PDT 24
Peak memory 219284 kb
Host smart-f8a36aba-b50e-44b0-8f4a-ce286070f97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757424032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2757424032
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.387660652
Short name T62
Test name
Test status
Simulation time 16003008227 ps
CPU time 45.39 seconds
Started Apr 16 12:49:07 PM PDT 24
Finished Apr 16 12:49:54 PM PDT 24
Peak memory 238524 kb
Host smart-4085f7f1-fa81-4d45-819d-702ac8f34a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387660652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.387660652
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.611801207
Short name T275
Test name
Test status
Simulation time 26848102164 ps
CPU time 21.97 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:49:17 PM PDT 24
Peak memory 233820 kb
Host smart-f3a5136d-c1a6-47f6-8ffe-448dc0656266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611801207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.611801207
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3996372138
Short name T333
Test name
Test status
Simulation time 17830111232 ps
CPU time 51.11 seconds
Started Apr 16 12:47:19 PM PDT 24
Finished Apr 16 12:48:12 PM PDT 24
Peak memory 240832 kb
Host smart-2129c707-3343-4766-9654-395b034e2285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996372138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3996372138
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.65409704
Short name T10
Test name
Test status
Simulation time 2028074622 ps
CPU time 8.85 seconds
Started Apr 16 12:47:06 PM PDT 24
Finished Apr 16 12:47:18 PM PDT 24
Peak memory 235272 kb
Host smart-558de6f8-d89c-43d1-b01c-85da6656cb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65409704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.65409704
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4008743479
Short name T269
Test name
Test status
Simulation time 20973460203 ps
CPU time 59.79 seconds
Started Apr 16 12:48:35 PM PDT 24
Finished Apr 16 12:49:36 PM PDT 24
Peak memory 232056 kb
Host smart-bca0512e-4a02-4e53-b811-3307d71de72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008743479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4008743479
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.648712397
Short name T161
Test name
Test status
Simulation time 478718681 ps
CPU time 7.09 seconds
Started Apr 16 12:48:06 PM PDT 24
Finished Apr 16 12:48:17 PM PDT 24
Peak memory 237220 kb
Host smart-7bab03e2-ade3-4228-a68e-dede3223b4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648712397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.648712397
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3680015962
Short name T310
Test name
Test status
Simulation time 1106923754 ps
CPU time 8.9 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:12 PM PDT 24
Peak memory 216652 kb
Host smart-e326cc8c-1835-4113-803c-c3e4b50144b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680015962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3680015962
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1113167806
Short name T253
Test name
Test status
Simulation time 162991905 ps
CPU time 5.21 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 232736 kb
Host smart-1eae52a5-15c5-403d-adb1-6e0b828b415b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113167806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1113167806
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1923906716
Short name T109
Test name
Test status
Simulation time 18168691941 ps
CPU time 77.42 seconds
Started Apr 16 12:48:35 PM PDT 24
Finished Apr 16 12:49:54 PM PDT 24
Peak memory 233560 kb
Host smart-a2fd591c-6bdd-4711-b9c8-2a659ca6343d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923906716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1923906716
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_intercept.794511474
Short name T352
Test name
Test status
Simulation time 278289735 ps
CPU time 6.51 seconds
Started Apr 16 12:47:08 PM PDT 24
Finished Apr 16 12:47:17 PM PDT 24
Peak memory 218940 kb
Host smart-95a3dda4-babf-415c-a8c8-67a8d4c70423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794511474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.794511474
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.579044530
Short name T7
Test name
Test status
Simulation time 379441040 ps
CPU time 2.55 seconds
Started Apr 16 12:47:54 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 222536 kb
Host smart-d03d28e6-e186-4817-ac00-1320fc161bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579044530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.579044530
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_intercept.524167235
Short name T211
Test name
Test status
Simulation time 3599868564 ps
CPU time 12.15 seconds
Started Apr 16 12:46:56 PM PDT 24
Finished Apr 16 12:47:11 PM PDT 24
Peak memory 232596 kb
Host smart-a0730149-4027-49ee-bce9-3e3e77d38213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524167235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.524167235
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_upload.1302197582
Short name T8
Test name
Test status
Simulation time 10293807822 ps
CPU time 19.46 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:22 PM PDT 24
Peak memory 224096 kb
Host smart-d7899f60-6422-45f5-a2b6-06fdf60f8ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302197582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1302197582
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2588627176
Short name T77
Test name
Test status
Simulation time 2726413441 ps
CPU time 5.12 seconds
Started Apr 16 12:47:20 PM PDT 24
Finished Apr 16 12:47:27 PM PDT 24
Peak memory 218484 kb
Host smart-47a35ccf-f169-441e-a023-21bed6f8e096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588627176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2588627176
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2581634888
Short name T369
Test name
Test status
Simulation time 1525079452 ps
CPU time 22.68 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:35 PM PDT 24
Peak memory 215060 kb
Host smart-51b451be-e512-4bb5-adad-339a7727ba91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581634888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2581634888
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.767999346
Short name T250
Test name
Test status
Simulation time 14105107963 ps
CPU time 10.56 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:48:09 PM PDT 24
Peak memory 219644 kb
Host smart-8c86d9bd-cb11-4c73-adf1-55a3ee760199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767999346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.767999346
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2186349717
Short name T267
Test name
Test status
Simulation time 3136698820 ps
CPU time 10.38 seconds
Started Apr 16 12:48:19 PM PDT 24
Finished Apr 16 12:48:31 PM PDT 24
Peak memory 232640 kb
Host smart-4e34d87a-6d32-45e5-8c53-51a69ca226c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186349717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2186349717
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3686538287
Short name T354
Test name
Test status
Simulation time 5084375975 ps
CPU time 37.67 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:49:23 PM PDT 24
Peak memory 224348 kb
Host smart-5682fa4f-e731-477d-a15b-d3890c05efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686538287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3686538287
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2384541774
Short name T404
Test name
Test status
Simulation time 14558242 ps
CPU time 0.74 seconds
Started Apr 16 12:46:59 PM PDT 24
Finished Apr 16 12:47:03 PM PDT 24
Peak memory 205400 kb
Host smart-fd954fa3-fcdc-4157-9cb3-f78aa5eaf185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384541774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
384541774
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2761169951
Short name T314
Test name
Test status
Simulation time 32469347384 ps
CPU time 22.37 seconds
Started Apr 16 12:47:25 PM PDT 24
Finished Apr 16 12:47:51 PM PDT 24
Peak memory 221460 kb
Host smart-5da629f7-39f8-4509-8800-dd4c9f9bf843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761169951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2761169951
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.738853799
Short name T2
Test name
Test status
Simulation time 39297054282 ps
CPU time 40.92 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:51 PM PDT 24
Peak memory 216288 kb
Host smart-ec45b42e-cd79-4270-91eb-da69c17be0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738853799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.738853799
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.101405819
Short name T180
Test name
Test status
Simulation time 12935308367 ps
CPU time 103.6 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:49:45 PM PDT 24
Peak memory 222140 kb
Host smart-573e5dc7-b9a5-412d-bbb1-6a612ac4b962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101405819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.101405819
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_upload.480774960
Short name T213
Test name
Test status
Simulation time 33770901678 ps
CPU time 44.25 seconds
Started Apr 16 12:48:34 PM PDT 24
Finished Apr 16 12:49:19 PM PDT 24
Peak memory 219888 kb
Host smart-d29c7dc8-2db1-4c2e-8148-fd980801fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480774960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.480774960
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3794245760
Short name T255
Test name
Test status
Simulation time 3453158073 ps
CPU time 13.56 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 218636 kb
Host smart-146111f4-2a04-4ce3-aa61-2cdec753344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794245760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3794245760
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3120141296
Short name T281
Test name
Test status
Simulation time 1133844023 ps
CPU time 9.33 seconds
Started Apr 16 12:47:21 PM PDT 24
Finished Apr 16 12:47:42 PM PDT 24
Peak memory 234960 kb
Host smart-0d3c5d26-daf1-44a2-a75b-8741356d66f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120141296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3120141296
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3616482455
Short name T186
Test name
Test status
Simulation time 5968373510 ps
CPU time 16.24 seconds
Started Apr 16 12:47:42 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 221768 kb
Host smart-811eae9d-e330-4350-b4d1-022c16cd37af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616482455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3616482455
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1484813247
Short name T198
Test name
Test status
Simulation time 673322656 ps
CPU time 5.8 seconds
Started Apr 16 12:48:10 PM PDT 24
Finished Apr 16 12:48:18 PM PDT 24
Peak memory 232200 kb
Host smart-12e3f95a-6292-45fe-ae29-07acf76a784a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484813247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1484813247
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1883999556
Short name T336
Test name
Test status
Simulation time 5980698327 ps
CPU time 50.16 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:55 PM PDT 24
Peak memory 232572 kb
Host smart-b311cb4c-57f2-4ed8-8140-0ba30bf30b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883999556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1883999556
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3525272093
Short name T270
Test name
Test status
Simulation time 17488891242 ps
CPU time 46.04 seconds
Started Apr 16 12:48:06 PM PDT 24
Finished Apr 16 12:48:56 PM PDT 24
Peak memory 219304 kb
Host smart-42d63909-0838-4b57-b9b3-9a7dd9662480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525272093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3525272093
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3816146278
Short name T72
Test name
Test status
Simulation time 1260590449 ps
CPU time 9.14 seconds
Started Apr 16 12:48:38 PM PDT 24
Finished Apr 16 12:48:48 PM PDT 24
Peak memory 224000 kb
Host smart-800d4c03-1e2a-40f3-a25c-cbde2702c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816146278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3816146278
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.799835170
Short name T74
Test name
Test status
Simulation time 3382973054 ps
CPU time 10.82 seconds
Started Apr 16 12:49:33 PM PDT 24
Finished Apr 16 12:49:46 PM PDT 24
Peak memory 222384 kb
Host smart-456e3919-5f25-4f47-824b-4de4312220b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799835170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.799835170
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2906392697
Short name T193
Test name
Test status
Simulation time 2567661947 ps
CPU time 19.64 seconds
Started Apr 16 12:48:48 PM PDT 24
Finished Apr 16 12:49:10 PM PDT 24
Peak memory 223960 kb
Host smart-60a10109-72f6-4bf7-92c8-684638823f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906392697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2906392697
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1574308690
Short name T818
Test name
Test status
Simulation time 544183887 ps
CPU time 3.5 seconds
Started Apr 16 12:51:06 PM PDT 24
Finished Apr 16 12:51:12 PM PDT 24
Peak memory 214892 kb
Host smart-49897e06-a131-4c71-9b17-17450f4068ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574308690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1574308690
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2563797536
Short name T280
Test name
Test status
Simulation time 6641980612 ps
CPU time 5.19 seconds
Started Apr 16 12:46:56 PM PDT 24
Finished Apr 16 12:47:04 PM PDT 24
Peak memory 222396 kb
Host smart-510512cb-29b8-4ff0-91c2-fd9e5510e607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563797536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2563797536
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.147337101
Short name T295
Test name
Test status
Simulation time 664619678 ps
CPU time 5.12 seconds
Started Apr 16 12:47:46 PM PDT 24
Finished Apr 16 12:47:55 PM PDT 24
Peak memory 218632 kb
Host smart-52dfe62d-8a05-48c0-a64a-e55369380793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147337101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.147337101
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4163116639
Short name T176
Test name
Test status
Simulation time 7896896652 ps
CPU time 16.05 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:17 PM PDT 24
Peak memory 223796 kb
Host smart-cac1b6a7-0466-42c7-ba5a-7104fa90a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163116639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4163116639
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1856879845
Short name T220
Test name
Test status
Simulation time 7996201937 ps
CPU time 10.08 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 237468 kb
Host smart-166ae976-72e2-4f16-bd08-2f82c7c063e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856879845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1856879845
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_upload.4183535662
Short name T191
Test name
Test status
Simulation time 351623953 ps
CPU time 2.84 seconds
Started Apr 16 12:48:08 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 216116 kb
Host smart-38132c49-c2ed-4a08-a960-734e047571da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183535662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4183535662
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1605651835
Short name T70
Test name
Test status
Simulation time 56238528753 ps
CPU time 34.9 seconds
Started Apr 16 12:48:47 PM PDT 24
Finished Apr 16 12:49:24 PM PDT 24
Peak memory 233472 kb
Host smart-cb5340b8-5aed-4366-be57-565af6195659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605651835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1605651835
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3777305637
Short name T73
Test name
Test status
Simulation time 3555261980 ps
CPU time 6.12 seconds
Started Apr 16 12:49:02 PM PDT 24
Finished Apr 16 12:49:10 PM PDT 24
Peak memory 232104 kb
Host smart-af613b2e-838c-4ab2-8207-22f3b9a304f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777305637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3777305637
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1621982690
Short name T283
Test name
Test status
Simulation time 3418264260 ps
CPU time 9.09 seconds
Started Apr 16 12:47:12 PM PDT 24
Finished Apr 16 12:47:23 PM PDT 24
Peak memory 224400 kb
Host smart-cc1f2126-d1ad-4064-8069-a7ff435dc7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621982690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1621982690
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4107470295
Short name T28
Test name
Test status
Simulation time 42880040 ps
CPU time 0.96 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:48 PM PDT 24
Peak memory 207144 kb
Host smart-505839dc-2c9e-49a5-8c45-aed478b997ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107470295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4107470295
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1312368606
Short name T227
Test name
Test status
Simulation time 1936559187 ps
CPU time 6.79 seconds
Started Apr 16 12:48:03 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 223504 kb
Host smart-cc1ac556-0588-4ae2-84c2-184a99616922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312368606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1312368606
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1498578941
Short name T364
Test name
Test status
Simulation time 2254488776 ps
CPU time 13.61 seconds
Started Apr 16 12:51:07 PM PDT 24
Finished Apr 16 12:51:22 PM PDT 24
Peak memory 216184 kb
Host smart-498fed79-c455-429f-9d24-cf34e05120e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498578941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1498578941
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3099926478
Short name T41
Test name
Test status
Simulation time 1168717469 ps
CPU time 17.37 seconds
Started Apr 16 12:47:16 PM PDT 24
Finished Apr 16 12:47:35 PM PDT 24
Peak memory 222068 kb
Host smart-3a003431-52fc-4830-97c3-19768cfa6bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099926478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3099926478
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_upload.1068015451
Short name T175
Test name
Test status
Simulation time 15003803480 ps
CPU time 8.87 seconds
Started Apr 16 12:47:30 PM PDT 24
Finished Apr 16 12:47:42 PM PDT 24
Peak memory 232688 kb
Host smart-0cfa41d1-7373-48e1-8fcb-1bde65b2df52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068015451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1068015451
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_upload.3905929655
Short name T624
Test name
Test status
Simulation time 12401865113 ps
CPU time 17.79 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:36 PM PDT 24
Peak memory 218832 kb
Host smart-8d49ffc7-03ff-4d85-8b86-466ef2ed3107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905929655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3905929655
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1204587546
Short name T14
Test name
Test status
Simulation time 51425912872 ps
CPU time 33.08 seconds
Started Apr 16 12:47:39 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 216204 kb
Host smart-976f3f8f-b9ad-4255-9e8c-46c2df94ea07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204587546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1204587546
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1903050804
Short name T209
Test name
Test status
Simulation time 17177472659 ps
CPU time 10.03 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 238452 kb
Host smart-15d35f85-4028-42a3-aa2c-8df07b1e96be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903050804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1903050804
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_upload.2978704277
Short name T166
Test name
Test status
Simulation time 114669756 ps
CPU time 2.47 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 219908 kb
Host smart-4204f3a8-8e64-4bc4-85de-569e8f0e4e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978704277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2978704277
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3636325967
Short name T260
Test name
Test status
Simulation time 19196845685 ps
CPU time 19.4 seconds
Started Apr 16 12:47:23 PM PDT 24
Finished Apr 16 12:47:44 PM PDT 24
Peak memory 223924 kb
Host smart-37963a5d-a537-40d7-ba20-e1a21cc160e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636325967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3636325967
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.894119801
Short name T396
Test name
Test status
Simulation time 26638712498 ps
CPU time 63.75 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:48:50 PM PDT 24
Peak memory 216192 kb
Host smart-6c788eca-1a74-418e-98f6-9dffd069c77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894119801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.894119801
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3527604706
Short name T672
Test name
Test status
Simulation time 6851201562 ps
CPU time 64.74 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:49:06 PM PDT 24
Peak memory 237764 kb
Host smart-4b40c17c-660c-43d3-94af-5361b79e0714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527604706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3527604706
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3398606440
Short name T222
Test name
Test status
Simulation time 9284691812 ps
CPU time 84.88 seconds
Started Apr 16 12:48:02 PM PDT 24
Finished Apr 16 12:49:30 PM PDT 24
Peak memory 218652 kb
Host smart-33b604a8-5f95-419c-8adf-68f00c0dc7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398606440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3398606440
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1860820468
Short name T318
Test name
Test status
Simulation time 11193594156 ps
CPU time 10.89 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 223920 kb
Host smart-d322f832-914f-465b-902e-5106b9ad6090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860820468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1860820468
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_upload.3671947723
Short name T292
Test name
Test status
Simulation time 455524723 ps
CPU time 3.94 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 223000 kb
Host smart-a9a86952-a0b6-48e9-9da8-bb6796ee1986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671947723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3671947723
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2223082739
Short name T248
Test name
Test status
Simulation time 6204686570 ps
CPU time 6.35 seconds
Started Apr 16 12:48:05 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 223116 kb
Host smart-1eaa2d11-fe26-4405-8f98-b782f71550dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223082739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2223082739
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3293894373
Short name T382
Test name
Test status
Simulation time 8234720810 ps
CPU time 42.96 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:45 PM PDT 24
Peak memory 216268 kb
Host smart-3ce015ff-ddc5-4978-96bb-977ffa94795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293894373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3293894373
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3459912122
Short name T11
Test name
Test status
Simulation time 49029944381 ps
CPU time 32.59 seconds
Started Apr 16 12:48:02 PM PDT 24
Finished Apr 16 12:48:38 PM PDT 24
Peak memory 220756 kb
Host smart-cfddec3e-5a06-4d50-bace-d43e1ba996fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459912122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3459912122
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_intercept.620403267
Short name T350
Test name
Test status
Simulation time 4365047430 ps
CPU time 36.3 seconds
Started Apr 16 12:48:06 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 232664 kb
Host smart-e5e17636-71b4-49f4-9d70-9c480736468e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620403267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.620403267
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.501664998
Short name T340
Test name
Test status
Simulation time 10102203042 ps
CPU time 141.77 seconds
Started Apr 16 12:48:24 PM PDT 24
Finished Apr 16 12:50:48 PM PDT 24
Peak memory 240756 kb
Host smart-d86b9f07-a184-4360-a565-0fabb19a2bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501664998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.501664998
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_upload.3894905852
Short name T230
Test name
Test status
Simulation time 5297837234 ps
CPU time 16.89 seconds
Started Apr 16 12:48:21 PM PDT 24
Finished Apr 16 12:48:40 PM PDT 24
Peak memory 224432 kb
Host smart-85f5189a-19e6-4282-88ae-acd3585caa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894905852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3894905852
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2590670130
Short name T200
Test name
Test status
Simulation time 2485165012 ps
CPU time 25.84 seconds
Started Apr 16 12:48:26 PM PDT 24
Finished Apr 16 12:48:53 PM PDT 24
Peak memory 232088 kb
Host smart-58eb7207-f62a-4584-b35a-4af68e9feb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590670130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2590670130
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3663525456
Short name T170
Test name
Test status
Simulation time 3006610908 ps
CPU time 10.17 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:52 PM PDT 24
Peak memory 224336 kb
Host smart-d55ff0bd-d00d-4818-a338-d00c162ff7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663525456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3663525456
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.258555820
Short name T282
Test name
Test status
Simulation time 6848462040 ps
CPU time 23.92 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:42 PM PDT 24
Peak memory 232632 kb
Host smart-c0ddbc69-8397-4355-8a40-675cbac2106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258555820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
258555820
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1538617791
Short name T179
Test name
Test status
Simulation time 132133884 ps
CPU time 3.63 seconds
Started Apr 16 12:48:46 PM PDT 24
Finished Apr 16 12:48:52 PM PDT 24
Peak memory 223144 kb
Host smart-49829360-5a65-4aef-a8a3-768a5bafbac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538617791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1538617791
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.483662634
Short name T284
Test name
Test status
Simulation time 9228216910 ps
CPU time 14.8 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:49:02 PM PDT 24
Peak memory 235596 kb
Host smart-025a30ed-2eea-43cc-a5e1-961f3de3492c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483662634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.483662634
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1950075429
Short name T347
Test name
Test status
Simulation time 1572621269 ps
CPU time 10.78 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:49:08 PM PDT 24
Peak memory 218400 kb
Host smart-7446de58-195e-431f-8326-b7958523caeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950075429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1950075429
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1947767354
Short name T207
Test name
Test status
Simulation time 8002653880 ps
CPU time 7.48 seconds
Started Apr 16 12:47:26 PM PDT 24
Finished Apr 16 12:47:36 PM PDT 24
Peak memory 219104 kb
Host smart-178f9646-796e-4c65-ac0d-3a281b97d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947767354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1947767354
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.23542655
Short name T234
Test name
Test status
Simulation time 4394046926 ps
CPU time 12.61 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:22 PM PDT 24
Peak memory 224436 kb
Host smart-de0283b2-82f8-41cb-96bd-6b6c7a520efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23542655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.23542655
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1453098650
Short name T114
Test name
Test status
Simulation time 2154870601 ps
CPU time 13.62 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:26 PM PDT 24
Peak memory 215444 kb
Host smart-fa2b6c8a-d5d8-4eb0-ae0c-a4aae01415bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453098650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1453098650
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2120584644
Short name T368
Test name
Test status
Simulation time 1592627633 ps
CPU time 23.05 seconds
Started Apr 16 12:51:08 PM PDT 24
Finished Apr 16 12:51:32 PM PDT 24
Peak memory 215360 kb
Host smart-be42b24b-8027-4e96-9daa-0eae589bbc73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120584644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2120584644
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1752662264
Short name T256
Test name
Test status
Simulation time 401694445 ps
CPU time 7.54 seconds
Started Apr 16 12:47:33 PM PDT 24
Finished Apr 16 12:47:42 PM PDT 24
Peak memory 235752 kb
Host smart-74c59c6b-5c14-4f15-aa90-4e4b016a8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752662264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1752662264
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.734255219
Short name T185
Test name
Test status
Simulation time 3075706629 ps
CPU time 10.09 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 233468 kb
Host smart-92c26d9b-2790-486b-a7fa-ba0bc6d0b666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734255219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.734255219
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.7994701
Short name T39
Test name
Test status
Simulation time 77836057619 ps
CPU time 134.99 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:50:01 PM PDT 24
Peak memory 220796 kb
Host smart-1eaf313d-b96f-4fe6-9ef6-c89d92e04ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7994701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.7994701
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2980849114
Short name T316
Test name
Test status
Simulation time 16176115305 ps
CPU time 13.32 seconds
Started Apr 16 12:47:42 PM PDT 24
Finished Apr 16 12:47:57 PM PDT 24
Peak memory 220632 kb
Host smart-6dacf507-e6c6-45dc-9874-8a92ad8ad934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980849114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2980849114
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_upload.473890611
Short name T216
Test name
Test status
Simulation time 49237943 ps
CPU time 2.12 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:47:55 PM PDT 24
Peak memory 217744 kb
Host smart-28bfbc9f-f9c7-4db7-9b1f-61006d5c1927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473890611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.473890611
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2404926047
Short name T219
Test name
Test status
Simulation time 8388991062 ps
CPU time 9.07 seconds
Started Apr 16 12:47:54 PM PDT 24
Finished Apr 16 12:48:09 PM PDT 24
Peak memory 239244 kb
Host smart-a560581d-31fd-4d50-bf3c-1c5158afd102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404926047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2404926047
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_upload.1869321747
Short name T298
Test name
Test status
Simulation time 1863920393 ps
CPU time 3.65 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 223012 kb
Host smart-b4302a69-cd7e-44f1-beb9-234679261511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869321747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1869321747
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.23195285
Short name T66
Test name
Test status
Simulation time 1226975525 ps
CPU time 6.5 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 224332 kb
Host smart-6cb1f2f8-2152-4f04-a939-caf5347c356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23195285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.23195285
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3255970180
Short name T204
Test name
Test status
Simulation time 10657647151 ps
CPU time 9.82 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 216596 kb
Host smart-2cd67915-e4d7-4fda-a2e3-bb0a46627773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255970180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3255970180
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2304592826
Short name T96
Test name
Test status
Simulation time 101045681 ps
CPU time 2.1 seconds
Started Apr 16 12:47:16 PM PDT 24
Finished Apr 16 12:47:19 PM PDT 24
Peak memory 218508 kb
Host smart-e9fb75da-588e-4673-ac43-4139382238d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304592826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2304592826
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.455416494
Short name T167
Test name
Test status
Simulation time 13780832601 ps
CPU time 9.97 seconds
Started Apr 16 12:47:13 PM PDT 24
Finished Apr 16 12:47:25 PM PDT 24
Peak memory 224324 kb
Host smart-72198da1-4b79-4506-8c57-279f3a3ec331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455416494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
455416494
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_upload.2488207449
Short name T183
Test name
Test status
Simulation time 6746913973 ps
CPU time 13.71 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 223428 kb
Host smart-1332edab-26d7-44ca-9764-770d90e8f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488207449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2488207449
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3677628365
Short name T69
Test name
Test status
Simulation time 851875614 ps
CPU time 6.46 seconds
Started Apr 16 12:48:05 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 218568 kb
Host smart-701416a9-c6fd-48df-b714-aae82a900b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677628365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3677628365
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.813630054
Short name T583
Test name
Test status
Simulation time 10077919065 ps
CPU time 26.93 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 216204 kb
Host smart-f32ce457-556d-4e5c-b502-3627ff57adcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813630054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.813630054
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3492780617
Short name T319
Test name
Test status
Simulation time 27634252991 ps
CPU time 23.97 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 223224 kb
Host smart-21bd5c7f-7231-4904-bf97-7da65a9e1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492780617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3492780617
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2813992997
Short name T322
Test name
Test status
Simulation time 369966564 ps
CPU time 2.62 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 218700 kb
Host smart-d743fb89-1b0c-47d4-b1db-82b65d6b5788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813992997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2813992997
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2095342464
Short name T103
Test name
Test status
Simulation time 66644171319 ps
CPU time 82.54 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:49:27 PM PDT 24
Peak memory 232584 kb
Host smart-87830a67-5beb-4764-9cc3-f5d8ebd5c402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095342464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2095342464
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.144564192
Short name T243
Test name
Test status
Simulation time 546317992 ps
CPU time 4.71 seconds
Started Apr 16 12:48:06 PM PDT 24
Finished Apr 16 12:48:14 PM PDT 24
Peak memory 224176 kb
Host smart-5ff512d0-bff9-434a-95e3-245105864778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144564192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.144564192
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1046911511
Short name T562
Test name
Test status
Simulation time 1047257777 ps
CPU time 6.9 seconds
Started Apr 16 12:48:17 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 220968 kb
Host smart-16872ef1-a2a4-43f4-af5c-8c62e0d9f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046911511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1046911511
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2086866494
Short name T82
Test name
Test status
Simulation time 192333761 ps
CPU time 3.3 seconds
Started Apr 16 12:48:02 PM PDT 24
Finished Apr 16 12:48:09 PM PDT 24
Peak memory 218872 kb
Host smart-65bc3688-72fa-4fb2-a954-6d1e225c0b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086866494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2086866494
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3022918759
Short name T326
Test name
Test status
Simulation time 1836427729 ps
CPU time 5.43 seconds
Started Apr 16 12:48:03 PM PDT 24
Finished Apr 16 12:48:12 PM PDT 24
Peak memory 218300 kb
Host smart-0c84a7a7-e769-40a9-8e80-898a0520f099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022918759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3022918759
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1487987623
Short name T343
Test name
Test status
Simulation time 4577241918 ps
CPU time 10.13 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 240740 kb
Host smart-914c94ba-7b1f-481e-90e7-83f4ba7db486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487987623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1487987623
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.641425497
Short name T51
Test name
Test status
Simulation time 7218076485 ps
CPU time 10.12 seconds
Started Apr 16 12:47:22 PM PDT 24
Finished Apr 16 12:47:34 PM PDT 24
Peak memory 216860 kb
Host smart-b5f39dd2-f047-448e-a79d-24923a1bf0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641425497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
641425497
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_upload.2113416555
Short name T242
Test name
Test status
Simulation time 831250256 ps
CPU time 5.18 seconds
Started Apr 16 12:47:10 PM PDT 24
Finished Apr 16 12:47:18 PM PDT 24
Peak memory 218880 kb
Host smart-41dae995-d879-4a29-8ebf-33dbb397635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113416555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2113416555
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.155750896
Short name T341
Test name
Test status
Simulation time 1173194060 ps
CPU time 25.88 seconds
Started Apr 16 12:48:12 PM PDT 24
Finished Apr 16 12:48:40 PM PDT 24
Peak memory 255016 kb
Host smart-2974eec1-14a6-4101-b5a5-d3d77b47810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155750896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.155750896
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2341951778
Short name T205
Test name
Test status
Simulation time 1498612605 ps
CPU time 8.41 seconds
Started Apr 16 12:48:08 PM PDT 24
Finished Apr 16 12:48:19 PM PDT 24
Peak memory 216692 kb
Host smart-0dbc738b-4b69-4f66-804e-188d2d261ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341951778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2341951778
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3265632886
Short name T223
Test name
Test status
Simulation time 15270661363 ps
CPU time 21.44 seconds
Started Apr 16 12:48:03 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 221224 kb
Host smart-c4d4e7b6-47bf-49ad-8d3f-c2eb3d5a7c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265632886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3265632886
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2511363421
Short name T279
Test name
Test status
Simulation time 2983169837 ps
CPU time 11.83 seconds
Started Apr 16 12:48:18 PM PDT 24
Finished Apr 16 12:48:32 PM PDT 24
Peak memory 234940 kb
Host smart-90f25fea-fdad-4773-8231-c5ce61e597ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511363421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2511363421
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2501577106
Short name T277
Test name
Test status
Simulation time 3107471210 ps
CPU time 33.49 seconds
Started Apr 16 12:48:36 PM PDT 24
Finished Apr 16 12:49:11 PM PDT 24
Peak memory 239212 kb
Host smart-24807dc0-c5d4-4650-9bd2-ddbc6636a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501577106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2501577106
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1927627940
Short name T239
Test name
Test status
Simulation time 14513794773 ps
CPU time 39.5 seconds
Started Apr 16 12:48:34 PM PDT 24
Finished Apr 16 12:49:15 PM PDT 24
Peak memory 232632 kb
Host smart-4966067a-a5b2-4525-8cf5-a1959c6a6ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927627940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1927627940
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3148638224
Short name T332
Test name
Test status
Simulation time 8475731964 ps
CPU time 70.01 seconds
Started Apr 16 12:48:37 PM PDT 24
Finished Apr 16 12:49:49 PM PDT 24
Peak memory 224444 kb
Host smart-81e265a5-b9f6-43c4-9605-0e285fe35d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148638224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3148638224
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1021803911
Short name T306
Test name
Test status
Simulation time 22125836938 ps
CPU time 168.89 seconds
Started Apr 16 12:47:00 PM PDT 24
Finished Apr 16 12:49:52 PM PDT 24
Peak memory 236644 kb
Host smart-31d115da-9895-42e3-8527-409ac5e832f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021803911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1021803911
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3986700123
Short name T296
Test name
Test status
Simulation time 1599555686 ps
CPU time 6.43 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:53 PM PDT 24
Peak memory 232388 kb
Host smart-99b79f1b-b059-447a-8980-9a8abe6446f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986700123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3986700123
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.368150460
Short name T247
Test name
Test status
Simulation time 9576122492 ps
CPU time 44.85 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:49:28 PM PDT 24
Peak memory 220820 kb
Host smart-97dcb736-cf49-4ec2-b007-77678deb0b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368150460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.368150460
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3624428601
Short name T71
Test name
Test status
Simulation time 915507463 ps
CPU time 7.25 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:53 PM PDT 24
Peak memory 223452 kb
Host smart-186047fa-49a4-47c2-9688-25e9e5c28603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624428601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3624428601
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.187085201
Short name T261
Test name
Test status
Simulation time 2232349184 ps
CPU time 2.81 seconds
Started Apr 16 12:48:45 PM PDT 24
Finished Apr 16 12:48:51 PM PDT 24
Peak memory 218864 kb
Host smart-718eef06-955d-4ecc-8642-c63b8c409067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187085201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.187085201
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2002282291
Short name T290
Test name
Test status
Simulation time 262077676 ps
CPU time 3.43 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 218808 kb
Host smart-fa585c79-8b0e-4f0c-96de-eb5dd780cc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002282291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2002282291
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3548748803
Short name T84
Test name
Test status
Simulation time 4329805259 ps
CPU time 39.58 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:38 PM PDT 24
Peak memory 232496 kb
Host smart-de2ebf43-1be6-4190-8246-89298a0a0c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548748803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3548748803
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_upload.1312026848
Short name T9
Test name
Test status
Simulation time 107073989 ps
CPU time 3.6 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 223064 kb
Host smart-0981a483-37e3-4410-b0fe-e2318b023881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312026848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1312026848
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3962696189
Short name T160
Test name
Test status
Simulation time 426876590 ps
CPU time 2.25 seconds
Started Apr 16 12:48:55 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 216212 kb
Host smart-5e10f3cd-d646-4d75-a6c6-470cc6067b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962696189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3962696189
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.590718229
Short name T259
Test name
Test status
Simulation time 684612229 ps
CPU time 5.5 seconds
Started Apr 16 12:49:01 PM PDT 24
Finished Apr 16 12:49:08 PM PDT 24
Peak memory 217796 kb
Host smart-bcf4d084-f785-4669-b202-6890347a27fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590718229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.590718229
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1261066177
Short name T313
Test name
Test status
Simulation time 675619066 ps
CPU time 5.93 seconds
Started Apr 16 12:48:59 PM PDT 24
Finished Apr 16 12:49:06 PM PDT 24
Peak memory 218924 kb
Host smart-0a6f26f7-0b5d-4e96-adf5-d3d1555b71a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261066177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1261066177
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1883021978
Short name T315
Test name
Test status
Simulation time 837077360 ps
CPU time 7.51 seconds
Started Apr 16 12:49:01 PM PDT 24
Finished Apr 16 12:49:10 PM PDT 24
Peak memory 224312 kb
Host smart-8c1f9856-b297-49ce-a9fe-d3130f34994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883021978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1883021978
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1686925100
Short name T95
Test name
Test status
Simulation time 25384404 ps
CPU time 1.32 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 206828 kb
Host smart-ce6fa23d-e94b-424f-b54f-ffd26434c7eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686925100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1686925100
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.678172453
Short name T780
Test name
Test status
Simulation time 572467738 ps
CPU time 4.4 seconds
Started Apr 16 12:50:56 PM PDT 24
Finished Apr 16 12:51:03 PM PDT 24
Peak memory 215204 kb
Host smart-192eb4df-b721-484c-af86-a6cf4e30ed8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678172453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.678172453
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.440373987
Short name T126
Test name
Test status
Simulation time 626518359 ps
CPU time 15.38 seconds
Started Apr 16 12:50:57 PM PDT 24
Finished Apr 16 12:51:14 PM PDT 24
Peak memory 207056 kb
Host smart-a2789c41-f432-49bc-b301-daaa82ce686e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440373987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.440373987
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2342591303
Short name T785
Test name
Test status
Simulation time 1233664638 ps
CPU time 24.23 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 206904 kb
Host smart-8a534c62-fec0-48a0-b9b2-dda8e897ff95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342591303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2342591303
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3362451997
Short name T93
Test name
Test status
Simulation time 125477667 ps
CPU time 1.1 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 206836 kb
Host smart-a3d9e3b5-9e42-4471-bad5-4ea034affe9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362451997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3362451997
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3770969129
Short name T799
Test name
Test status
Simulation time 110356413 ps
CPU time 3.87 seconds
Started Apr 16 12:50:53 PM PDT 24
Finished Apr 16 12:50:59 PM PDT 24
Peak memory 216560 kb
Host smart-4f6d4fdf-b35a-4ed3-b2d9-117ad58180f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770969129 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3770969129
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2398775329
Short name T819
Test name
Test status
Simulation time 289055735 ps
CPU time 1.22 seconds
Started Apr 16 12:50:54 PM PDT 24
Finished Apr 16 12:50:57 PM PDT 24
Peak memory 214948 kb
Host smart-3cf36c26-eb3c-4fe9-bb7d-61fe9ea7b8d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398775329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
398775329
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.173744121
Short name T153
Test name
Test status
Simulation time 35476412 ps
CPU time 0.7 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 203444 kb
Host smart-048b55e1-65d7-40d0-9fef-b71433d9a742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173744121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.173744121
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.564538927
Short name T786
Test name
Test status
Simulation time 65550580 ps
CPU time 1.29 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 215036 kb
Host smart-e3c916de-8921-40d6-a0c0-c358fcfacce4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564538927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.564538927
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2482158096
Short name T792
Test name
Test status
Simulation time 66592907 ps
CPU time 0.65 seconds
Started Apr 16 12:50:58 PM PDT 24
Finished Apr 16 12:51:01 PM PDT 24
Peak memory 203208 kb
Host smart-c706ada6-e58c-4fd2-ae0c-75071b521f75
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482158096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2482158096
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3465613654
Short name T795
Test name
Test status
Simulation time 64768044 ps
CPU time 3.68 seconds
Started Apr 16 12:50:57 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 215056 kb
Host smart-7a13a46c-b6c4-473c-a504-0b7bb99a8fb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465613654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3465613654
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.179565653
Short name T814
Test name
Test status
Simulation time 152629258 ps
CPU time 2.26 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:03 PM PDT 24
Peak memory 216248 kb
Host smart-db70f72f-2423-4e4f-9fc5-bc623b393af3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179565653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.179565653
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.507306797
Short name T365
Test name
Test status
Simulation time 207568187 ps
CPU time 12.72 seconds
Started Apr 16 12:51:00 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 215100 kb
Host smart-b52f8266-0f79-4e2f-88c5-f4ca4ae18b27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507306797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.507306797
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1847023725
Short name T130
Test name
Test status
Simulation time 625973122 ps
CPU time 15.87 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 206844 kb
Host smart-8d83b60f-25e6-487b-ae05-c45b9ae095dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847023725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1847023725
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.85932345
Short name T755
Test name
Test status
Simulation time 1066276062 ps
CPU time 30.21 seconds
Started Apr 16 12:51:08 PM PDT 24
Finished Apr 16 12:51:39 PM PDT 24
Peak memory 206844 kb
Host smart-444e6a8c-538f-400a-b0c5-a504a661e066
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85932345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.85932345
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.423023189
Short name T91
Test name
Test status
Simulation time 196110023 ps
CPU time 0.98 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 206608 kb
Host smart-5222921a-ee6d-4797-b2fe-413c4d076b92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423023189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.423023189
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4056409414
Short name T120
Test name
Test status
Simulation time 57668974 ps
CPU time 1.72 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 215136 kb
Host smart-22a9b44c-41bd-4480-8087-ace93c136e9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056409414 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4056409414
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1011991857
Short name T798
Test name
Test status
Simulation time 1664717089 ps
CPU time 2.23 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:06 PM PDT 24
Peak memory 206852 kb
Host smart-6af4e7d4-c73c-4f27-8de5-28e70c00e0fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011991857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
011991857
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2987678001
Short name T741
Test name
Test status
Simulation time 48360918 ps
CPU time 0.73 seconds
Started Apr 16 12:51:01 PM PDT 24
Finished Apr 16 12:51:04 PM PDT 24
Peak memory 203648 kb
Host smart-42216782-9948-4158-9fda-3138f74fab9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987678001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
987678001
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2934385301
Short name T131
Test name
Test status
Simulation time 76084386 ps
CPU time 2.39 seconds
Started Apr 16 12:50:57 PM PDT 24
Finished Apr 16 12:51:01 PM PDT 24
Peak memory 215180 kb
Host smart-50ea2dba-3440-4862-9f0f-73bae8da1f06
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934385301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2934385301
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2822890011
Short name T756
Test name
Test status
Simulation time 13917833 ps
CPU time 0.66 seconds
Started Apr 16 12:51:00 PM PDT 24
Finished Apr 16 12:51:02 PM PDT 24
Peak memory 203600 kb
Host smart-2748a022-0dcf-41a9-8e50-75c838eeef8f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822890011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2822890011
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2024601584
Short name T754
Test name
Test status
Simulation time 54054309 ps
CPU time 1.79 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 215008 kb
Host smart-e4d61874-878e-4a3b-8a9e-64af9815d116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024601584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2024601584
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.314097206
Short name T117
Test name
Test status
Simulation time 838332705 ps
CPU time 12.34 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:14 PM PDT 24
Peak memory 215436 kb
Host smart-6cc274da-1729-40e3-9cba-5ef5a3eb444d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314097206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.314097206
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4127684494
Short name T113
Test name
Test status
Simulation time 40185923 ps
CPU time 2.58 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 216144 kb
Host smart-2dc6b39e-dd76-485e-92e7-6c93089e2aa3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127684494 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4127684494
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.511620922
Short name T783
Test name
Test status
Simulation time 53744610 ps
CPU time 0.69 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 203840 kb
Host smart-fe76ea9e-4993-4967-bc62-e96bc25a0706
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511620922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.511620922
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1966510413
Short name T793
Test name
Test status
Simulation time 86333495 ps
CPU time 2.73 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 215092 kb
Host smart-d8cbd1c7-abff-43d4-b7e4-7bc494a22a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966510413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1966510413
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.949353110
Short name T116
Test name
Test status
Simulation time 160618582 ps
CPU time 2.2 seconds
Started Apr 16 12:51:08 PM PDT 24
Finished Apr 16 12:51:11 PM PDT 24
Peak memory 215272 kb
Host smart-57bbd512-3a97-4545-8c30-9e6a87db6ef0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949353110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.949353110
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3373605564
Short name T748
Test name
Test status
Simulation time 52807285 ps
CPU time 1.59 seconds
Started Apr 16 12:51:09 PM PDT 24
Finished Apr 16 12:51:12 PM PDT 24
Peak memory 215176 kb
Host smart-453eed0e-689d-4b7e-b07d-10fd682b1014
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373605564 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3373605564
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3818171413
Short name T834
Test name
Test status
Simulation time 95325074 ps
CPU time 2.58 seconds
Started Apr 16 12:51:10 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 206956 kb
Host smart-e2f0eb30-51b0-434d-89d3-e65ebac012ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818171413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3818171413
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4279649926
Short name T752
Test name
Test status
Simulation time 26855799 ps
CPU time 0.69 seconds
Started Apr 16 12:51:08 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 203480 kb
Host smart-7fb93a4b-a1e8-4d09-92e8-7b6d0eaef64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279649926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4279649926
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2954388057
Short name T140
Test name
Test status
Simulation time 416874260 ps
CPU time 4.18 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:19 PM PDT 24
Peak memory 214900 kb
Host smart-a17275cd-61f8-4dec-bbf1-4622c28192b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954388057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2954388057
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3523995160
Short name T833
Test name
Test status
Simulation time 150680112 ps
CPU time 3.58 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 216760 kb
Host smart-dc59a5a1-2a77-4d8c-ba8c-dc364d24eb38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523995160 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3523995160
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2983422049
Short name T823
Test name
Test status
Simulation time 872948307 ps
CPU time 1.96 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:16 PM PDT 24
Peak memory 215120 kb
Host smart-f6b61569-7728-4684-bbdb-d2a7ec4efa7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983422049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2983422049
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.380477439
Short name T801
Test name
Test status
Simulation time 10706800 ps
CPU time 0.77 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 203664 kb
Host smart-31507bae-dae2-416e-b846-6479a5230464
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380477439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.380477439
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2103841605
Short name T137
Test name
Test status
Simulation time 487141953 ps
CPU time 3.05 seconds
Started Apr 16 12:51:12 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 215108 kb
Host smart-0ff8137a-47ae-4254-b004-0da3f0d93256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103841605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2103841605
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.304121415
Short name T765
Test name
Test status
Simulation time 2232293653 ps
CPU time 4.4 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:11 PM PDT 24
Peak memory 215264 kb
Host smart-e61ee2fd-f4d0-49df-9a6e-9ff5061d2a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304121415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.304121415
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2188435463
Short name T370
Test name
Test status
Simulation time 2263312189 ps
CPU time 15.16 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:28 PM PDT 24
Peak memory 215540 kb
Host smart-1d48339d-e61b-4586-8440-c6fe0a8bca95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188435463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2188435463
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.125897796
Short name T149
Test name
Test status
Simulation time 649511684 ps
CPU time 3.74 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 216680 kb
Host smart-cc542ba1-8c61-4fee-89c8-84d5a97aca5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125897796 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.125897796
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1883882211
Short name T820
Test name
Test status
Simulation time 107843281 ps
CPU time 1.85 seconds
Started Apr 16 12:51:12 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 215048 kb
Host smart-60ad34c4-3d84-4c07-b4ff-dc4df368d2af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883882211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1883882211
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1994495088
Short name T154
Test name
Test status
Simulation time 15858957 ps
CPU time 0.72 seconds
Started Apr 16 12:51:09 PM PDT 24
Finished Apr 16 12:51:11 PM PDT 24
Peak memory 203820 kb
Host smart-41a78dfb-0c5d-4304-94a4-388669dfd898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994495088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1994495088
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.479898804
Short name T764
Test name
Test status
Simulation time 61135716 ps
CPU time 3.6 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 215116 kb
Host smart-e729b9f0-8476-44cf-bbc3-3da97ad8fade
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479898804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.479898804
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1292013672
Short name T112
Test name
Test status
Simulation time 535673426 ps
CPU time 3.45 seconds
Started Apr 16 12:51:08 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 215116 kb
Host smart-c6b57ba5-25cf-4f37-9b32-27700c695e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292013672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1292013672
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2032309614
Short name T737
Test name
Test status
Simulation time 254356024 ps
CPU time 2.97 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 217428 kb
Host smart-7ae0ae2c-193a-4b96-a747-5ac23b9d7a83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032309614 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2032309614
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1683090649
Short name T832
Test name
Test status
Simulation time 67510860 ps
CPU time 2.27 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 214992 kb
Host smart-79f2dba0-7351-42fe-8e1b-5f865aed9e49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683090649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1683090649
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.311148169
Short name T789
Test name
Test status
Simulation time 28416518 ps
CPU time 0.76 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 203544 kb
Host smart-ec9723f4-e365-4a4c-ba31-abe20cd06329
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311148169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.311148169
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4185946811
Short name T735
Test name
Test status
Simulation time 209600261 ps
CPU time 3.02 seconds
Started Apr 16 12:51:15 PM PDT 24
Finished Apr 16 12:51:18 PM PDT 24
Peak memory 215004 kb
Host smart-0c1f79e9-3cd0-433c-b6e0-866335b2f4d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185946811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4185946811
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.763283699
Short name T829
Test name
Test status
Simulation time 151040898 ps
CPU time 4.44 seconds
Started Apr 16 12:51:12 PM PDT 24
Finished Apr 16 12:51:18 PM PDT 24
Peak memory 216376 kb
Host smart-b554b5e5-4f19-4862-93b6-57d8b0ad5380
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763283699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.763283699
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.284123305
Short name T728
Test name
Test status
Simulation time 207201983 ps
CPU time 3.55 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:18 PM PDT 24
Peak memory 216924 kb
Host smart-1692d98b-8b58-4318-984c-88d57c9866f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284123305 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.284123305
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3765777915
Short name T122
Test name
Test status
Simulation time 140029919 ps
CPU time 2.41 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:16 PM PDT 24
Peak memory 215080 kb
Host smart-9232a073-d521-464f-82ae-6c95cc15f006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765777915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3765777915
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3643024679
Short name T811
Test name
Test status
Simulation time 16412912 ps
CPU time 0.74 seconds
Started Apr 16 12:51:19 PM PDT 24
Finished Apr 16 12:51:20 PM PDT 24
Peak memory 203840 kb
Host smart-9d889551-e36f-4d96-be74-0b5b2d4a97a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643024679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3643024679
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.832973254
Short name T736
Test name
Test status
Simulation time 133424710 ps
CPU time 2.89 seconds
Started Apr 16 12:51:12 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 215092 kb
Host smart-1bf46d56-05c9-400b-bad1-fc51188659d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832973254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.832973254
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3621931154
Short name T822
Test name
Test status
Simulation time 278404369 ps
CPU time 3.36 seconds
Started Apr 16 12:51:17 PM PDT 24
Finished Apr 16 12:51:22 PM PDT 24
Peak memory 215264 kb
Host smart-c9d04d4f-fbdf-4a13-8589-8529db0b3e44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621931154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3621931154
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3340204079
Short name T145
Test name
Test status
Simulation time 1077629177 ps
CPU time 8.3 seconds
Started Apr 16 12:51:16 PM PDT 24
Finished Apr 16 12:51:25 PM PDT 24
Peak memory 215040 kb
Host smart-8563c3ac-6aaa-4458-a47e-d75640178b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340204079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3340204079
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3809100364
Short name T802
Test name
Test status
Simulation time 135368017 ps
CPU time 3.81 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:18 PM PDT 24
Peak memory 216152 kb
Host smart-0f300965-b02e-47be-89bf-6d87570e4f36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809100364 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3809100364
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3967209181
Short name T738
Test name
Test status
Simulation time 44809385 ps
CPU time 1.39 seconds
Started Apr 16 12:51:18 PM PDT 24
Finished Apr 16 12:51:20 PM PDT 24
Peak memory 215028 kb
Host smart-2a65d5de-c95f-44b3-ae9f-c1c78a4fdf3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967209181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3967209181
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3061128960
Short name T759
Test name
Test status
Simulation time 48638366 ps
CPU time 0.74 seconds
Started Apr 16 12:51:25 PM PDT 24
Finished Apr 16 12:51:28 PM PDT 24
Peak memory 203836 kb
Host smart-15160c26-effb-4596-83f8-915955e0aac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061128960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3061128960
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4127153729
Short name T746
Test name
Test status
Simulation time 83632362 ps
CPU time 2.01 seconds
Started Apr 16 12:51:12 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 215096 kb
Host smart-bd12784d-34cb-4dea-94d5-33404493f6c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127153729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4127153729
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.494761598
Short name T828
Test name
Test status
Simulation time 106754192 ps
CPU time 3.02 seconds
Started Apr 16 12:51:22 PM PDT 24
Finished Apr 16 12:51:26 PM PDT 24
Peak memory 215256 kb
Host smart-44ae1a3b-c819-4548-8254-e39c55d9bcb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494761598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.494761598
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2767545064
Short name T35
Test name
Test status
Simulation time 872396028 ps
CPU time 12.88 seconds
Started Apr 16 12:51:18 PM PDT 24
Finished Apr 16 12:51:32 PM PDT 24
Peak memory 215024 kb
Host smart-d91590ff-542c-40c3-9fae-c44552042282
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767545064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2767545064
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.927828112
Short name T769
Test name
Test status
Simulation time 170395071 ps
CPU time 2.56 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 217268 kb
Host smart-826c935a-9aab-46a6-b53c-b2e457350897
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927828112 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.927828112
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.623144259
Short name T753
Test name
Test status
Simulation time 549750906 ps
CPU time 1.22 seconds
Started Apr 16 12:51:15 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 206912 kb
Host smart-1c8e8326-69dc-4cb8-b4cc-0ceddb49990d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623144259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.623144259
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3751659377
Short name T826
Test name
Test status
Simulation time 18309237 ps
CPU time 0.74 seconds
Started Apr 16 12:51:10 PM PDT 24
Finished Apr 16 12:51:12 PM PDT 24
Peak memory 203520 kb
Host smart-4067c845-14b3-4341-a494-2f7ac81544f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751659377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3751659377
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3771410296
Short name T734
Test name
Test status
Simulation time 284965146 ps
CPU time 3.98 seconds
Started Apr 16 12:51:12 PM PDT 24
Finished Apr 16 12:51:18 PM PDT 24
Peak memory 215004 kb
Host smart-55007783-4913-4d49-9ad0-f69d133d5c04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771410296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3771410296
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2981260096
Short name T363
Test name
Test status
Simulation time 477088186 ps
CPU time 3.82 seconds
Started Apr 16 12:51:10 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 215204 kb
Host smart-94573472-6205-4b20-9d45-cbea720f5fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981260096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2981260096
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1154198915
Short name T772
Test name
Test status
Simulation time 355645187 ps
CPU time 8.14 seconds
Started Apr 16 12:51:21 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 215048 kb
Host smart-c445e896-d3ec-47a5-bacb-392f67889965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154198915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1154198915
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2134443101
Short name T739
Test name
Test status
Simulation time 109973324 ps
CPU time 2.87 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 216176 kb
Host smart-b35cd8f2-8ab2-4b39-a190-74c3875e7b71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134443101 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2134443101
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4112267532
Short name T128
Test name
Test status
Simulation time 77571964 ps
CPU time 2.1 seconds
Started Apr 16 12:51:16 PM PDT 24
Finished Apr 16 12:51:20 PM PDT 24
Peak memory 214940 kb
Host smart-487e2299-74d3-40af-a163-c08ef50cbbb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112267532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4112267532
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2025433544
Short name T720
Test name
Test status
Simulation time 13462252 ps
CPU time 0.73 seconds
Started Apr 16 12:51:20 PM PDT 24
Finished Apr 16 12:51:22 PM PDT 24
Peak memory 203820 kb
Host smart-c806aa7d-dd55-4702-96b6-34f153038e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025433544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2025433544
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2336432369
Short name T784
Test name
Test status
Simulation time 101591335 ps
CPU time 1.64 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:14 PM PDT 24
Peak memory 215088 kb
Host smart-c044c3a4-e623-4e5d-9896-e3320d252f6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336432369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2336432369
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.271531265
Short name T108
Test name
Test status
Simulation time 293279628 ps
CPU time 17.71 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:32 PM PDT 24
Peak memory 215332 kb
Host smart-50218b27-83f1-4355-96bf-6fcc86ae9648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271531265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.271531265
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1736617252
Short name T787
Test name
Test status
Simulation time 562651586 ps
CPU time 3.44 seconds
Started Apr 16 12:51:35 PM PDT 24
Finished Apr 16 12:51:39 PM PDT 24
Peak memory 216804 kb
Host smart-f4721a0b-df96-4f45-a9f2-b7ab0cc0897b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736617252 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1736617252
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1104167718
Short name T827
Test name
Test status
Simulation time 69202870 ps
CPU time 1.15 seconds
Started Apr 16 12:51:31 PM PDT 24
Finished Apr 16 12:51:34 PM PDT 24
Peak memory 215036 kb
Host smart-10190608-d4fb-4712-aaf1-b5a9ec5aa4a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104167718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1104167718
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3214873936
Short name T778
Test name
Test status
Simulation time 35144721 ps
CPU time 0.7 seconds
Started Apr 16 12:51:17 PM PDT 24
Finished Apr 16 12:51:19 PM PDT 24
Peak memory 203512 kb
Host smart-4213c738-1330-443b-912a-746eba4ec14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214873936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3214873936
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1150407924
Short name T136
Test name
Test status
Simulation time 785966001 ps
CPU time 4.06 seconds
Started Apr 16 12:51:20 PM PDT 24
Finished Apr 16 12:51:25 PM PDT 24
Peak memory 214948 kb
Host smart-4e4c5b94-0aef-4819-aec0-438dd7e74f4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150407924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1150407924
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.803913172
Short name T791
Test name
Test status
Simulation time 45861168 ps
CPU time 2.97 seconds
Started Apr 16 12:51:19 PM PDT 24
Finished Apr 16 12:51:23 PM PDT 24
Peak memory 215300 kb
Host smart-c3a898bc-c0de-40e2-a329-61506f62f4f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803913172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.803913172
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2035539031
Short name T146
Test name
Test status
Simulation time 656127017 ps
CPU time 7.74 seconds
Started Apr 16 12:51:14 PM PDT 24
Finished Apr 16 12:51:22 PM PDT 24
Peak memory 215076 kb
Host smart-7c9bda87-56c3-462e-992a-44adfd7517e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035539031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2035539031
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.707841477
Short name T135
Test name
Test status
Simulation time 1044583736 ps
CPU time 16.11 seconds
Started Apr 16 12:51:00 PM PDT 24
Finished Apr 16 12:51:18 PM PDT 24
Peak memory 215008 kb
Host smart-ed4033ef-5ce4-403f-8323-20155a92f38b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707841477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.707841477
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2182682578
Short name T132
Test name
Test status
Simulation time 5385034257 ps
CPU time 39.39 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:44 PM PDT 24
Peak memory 206908 kb
Host smart-3d79ecd3-f46a-4660-b01c-8d29a50acf9e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182682578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2182682578
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1487983348
Short name T94
Test name
Test status
Simulation time 84072470 ps
CPU time 1.26 seconds
Started Apr 16 12:51:06 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 206816 kb
Host smart-e191d58a-c383-4828-8378-9904f7946675
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487983348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1487983348
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2082661411
Short name T821
Test name
Test status
Simulation time 109807562 ps
CPU time 2.53 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:07 PM PDT 24
Peak memory 215400 kb
Host smart-db6bd57c-7db9-4871-9bff-6843012a71ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082661411 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2082661411
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.682339035
Short name T133
Test name
Test status
Simulation time 37068101 ps
CPU time 1.92 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 215044 kb
Host smart-c5e0b84e-bef3-4bfc-aadb-f49886ddfdb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682339035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.682339035
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2294071149
Short name T749
Test name
Test status
Simulation time 57913207 ps
CPU time 0.74 seconds
Started Apr 16 12:51:01 PM PDT 24
Finished Apr 16 12:51:04 PM PDT 24
Peak memory 203816 kb
Host smart-ec99d063-d778-4c32-9ee1-abfa0aeb2be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294071149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
294071149
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3476323910
Short name T134
Test name
Test status
Simulation time 67838404 ps
CPU time 1.31 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:07 PM PDT 24
Peak memory 215096 kb
Host smart-968643b3-092a-415e-8c22-1584e5c86cd0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476323910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3476323910
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1056524166
Short name T831
Test name
Test status
Simulation time 10610177 ps
CPU time 0.67 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 203360 kb
Host smart-5d374794-9dff-48d8-a871-07586b988a1c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056524166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1056524166
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.992951314
Short name T796
Test name
Test status
Simulation time 107248055 ps
CPU time 3.66 seconds
Started Apr 16 12:51:07 PM PDT 24
Finished Apr 16 12:51:12 PM PDT 24
Peak memory 215144 kb
Host smart-111d9d54-2e1c-498c-9c38-c00a037bbeb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992951314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.992951314
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3074148426
Short name T115
Test name
Test status
Simulation time 81467056 ps
CPU time 2.99 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 216120 kb
Host smart-8e821e08-c099-43ef-91f9-5d32fe25e53c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074148426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
074148426
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1798845712
Short name T366
Test name
Test status
Simulation time 2756123470 ps
CPU time 14.87 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:22 PM PDT 24
Peak memory 215380 kb
Host smart-6df5ed7d-319d-4835-b5b7-fd1cb79bfefc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798845712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1798845712
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2622461008
Short name T747
Test name
Test status
Simulation time 33576120 ps
CPU time 0.72 seconds
Started Apr 16 12:51:27 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 203496 kb
Host smart-7531c0a5-d7b8-486a-9e59-908975ef3260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622461008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2622461008
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1617295019
Short name T729
Test name
Test status
Simulation time 17857202 ps
CPU time 0.73 seconds
Started Apr 16 12:51:24 PM PDT 24
Finished Apr 16 12:51:26 PM PDT 24
Peak memory 203468 kb
Host smart-e0a138ea-153e-47bb-a936-1c70a5ec2b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617295019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1617295019
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1916482072
Short name T750
Test name
Test status
Simulation time 11902604 ps
CPU time 0.7 seconds
Started Apr 16 12:51:28 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 203520 kb
Host smart-45c8bc53-ae63-4a1b-8c5f-598654a8c712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916482072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1916482072
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3223575990
Short name T781
Test name
Test status
Simulation time 57826534 ps
CPU time 0.75 seconds
Started Apr 16 12:51:23 PM PDT 24
Finished Apr 16 12:51:25 PM PDT 24
Peak memory 203444 kb
Host smart-066f2bc3-ce14-4151-ab5e-262c84c004bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223575990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3223575990
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2363180689
Short name T731
Test name
Test status
Simulation time 14529582 ps
CPU time 0.73 seconds
Started Apr 16 12:51:34 PM PDT 24
Finished Apr 16 12:51:36 PM PDT 24
Peak memory 203540 kb
Host smart-223d78d6-e5d5-4306-aabf-ec8661c4f0fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363180689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2363180689
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3317415790
Short name T742
Test name
Test status
Simulation time 14410745 ps
CPU time 0.73 seconds
Started Apr 16 12:51:24 PM PDT 24
Finished Apr 16 12:51:27 PM PDT 24
Peak memory 203500 kb
Host smart-030aab8b-1d1e-4bc2-af57-92cc4ff02ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317415790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3317415790
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1772926439
Short name T805
Test name
Test status
Simulation time 144852358 ps
CPU time 0.71 seconds
Started Apr 16 12:51:31 PM PDT 24
Finished Apr 16 12:51:33 PM PDT 24
Peak memory 203812 kb
Host smart-68448697-2095-4d18-b4cb-21075aacc977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772926439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1772926439
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4015008781
Short name T803
Test name
Test status
Simulation time 15295384 ps
CPU time 0.75 seconds
Started Apr 16 12:51:27 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 203536 kb
Host smart-4760a67e-d0a6-4e72-a5c4-d97cd15e396f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015008781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4015008781
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2702402321
Short name T806
Test name
Test status
Simulation time 42300792 ps
CPU time 0.75 seconds
Started Apr 16 12:51:16 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 203780 kb
Host smart-6fa9f6e1-39f8-4b31-8ecd-7ec19d36e4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702402321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2702402321
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1558081219
Short name T804
Test name
Test status
Simulation time 29568607 ps
CPU time 0.69 seconds
Started Apr 16 12:51:25 PM PDT 24
Finished Apr 16 12:51:27 PM PDT 24
Peak memory 203488 kb
Host smart-c2114a2d-cff5-4992-ba76-0f2b9873135a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558081219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1558081219
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.621281723
Short name T809
Test name
Test status
Simulation time 2532834603 ps
CPU time 16.04 seconds
Started Apr 16 12:51:00 PM PDT 24
Finished Apr 16 12:51:19 PM PDT 24
Peak memory 206920 kb
Host smart-377030de-ec0d-4991-9768-c26fb6b6278c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621281723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.621281723
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.454340919
Short name T790
Test name
Test status
Simulation time 537657541 ps
CPU time 30.8 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:36 PM PDT 24
Peak memory 206832 kb
Host smart-c92acc63-026f-4e35-a53a-f561e7c0adfb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454340919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.454340919
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.818378956
Short name T812
Test name
Test status
Simulation time 167079768 ps
CPU time 1.6 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 215080 kb
Host smart-b1e21405-f9e4-4c17-b625-9cf7ddeb82f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818378956 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.818378956
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2304078901
Short name T124
Test name
Test status
Simulation time 332467241 ps
CPU time 2.3 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 215036 kb
Host smart-91061733-27a5-4905-b34e-54ebc155e3eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304078901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
304078901
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1065085848
Short name T774
Test name
Test status
Simulation time 18122204 ps
CPU time 0.69 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 203456 kb
Host smart-b7462607-eac9-4aa6-af8b-0aa67041fc5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065085848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
065085848
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2321088379
Short name T808
Test name
Test status
Simulation time 35997212 ps
CPU time 1.37 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:07 PM PDT 24
Peak memory 215116 kb
Host smart-8aca0205-b833-49fe-8822-4139b1fecc8f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321088379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2321088379
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.939411420
Short name T794
Test name
Test status
Simulation time 37505459 ps
CPU time 0.68 seconds
Started Apr 16 12:51:01 PM PDT 24
Finished Apr 16 12:51:04 PM PDT 24
Peak memory 203368 kb
Host smart-961307b7-69da-45dd-8489-46b5387b2818
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939411420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.939411420
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1697939694
Short name T34
Test name
Test status
Simulation time 153540382 ps
CPU time 2.54 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:07 PM PDT 24
Peak memory 215068 kb
Host smart-4d65fad3-1a71-4f2a-bfc9-9fd1da74a56d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697939694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1697939694
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.47323828
Short name T775
Test name
Test status
Simulation time 230973476 ps
CPU time 1.8 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 215196 kb
Host smart-8b041aad-7a74-4bbf-af88-32407530bbe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47323828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.47323828
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1523503045
Short name T761
Test name
Test status
Simulation time 36682772 ps
CPU time 0.77 seconds
Started Apr 16 12:51:24 PM PDT 24
Finished Apr 16 12:51:26 PM PDT 24
Peak memory 203504 kb
Host smart-37950578-95bb-4867-8939-2cb8f645e85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523503045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1523503045
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1588258845
Short name T722
Test name
Test status
Simulation time 25149503 ps
CPU time 0.7 seconds
Started Apr 16 12:51:27 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 203536 kb
Host smart-155cba00-c5e0-4b8c-ba99-b78bdfe0aab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588258845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1588258845
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2626660363
Short name T768
Test name
Test status
Simulation time 12983162 ps
CPU time 0.73 seconds
Started Apr 16 12:51:21 PM PDT 24
Finished Apr 16 12:51:23 PM PDT 24
Peak memory 203808 kb
Host smart-45c85899-c9ae-4049-84fc-49cab2ab5346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626660363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2626660363
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1790108627
Short name T788
Test name
Test status
Simulation time 18912714 ps
CPU time 0.7 seconds
Started Apr 16 12:51:29 PM PDT 24
Finished Apr 16 12:51:32 PM PDT 24
Peak memory 203524 kb
Host smart-31d4489c-5161-4f03-bdb2-b29874212757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790108627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1790108627
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.753246036
Short name T779
Test name
Test status
Simulation time 28457686 ps
CPU time 0.76 seconds
Started Apr 16 12:51:15 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 203528 kb
Host smart-480bacf2-a671-434e-807b-acce56887da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753246036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.753246036
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1198661017
Short name T723
Test name
Test status
Simulation time 37154666 ps
CPU time 0.73 seconds
Started Apr 16 12:51:24 PM PDT 24
Finished Apr 16 12:51:25 PM PDT 24
Peak memory 203808 kb
Host smart-4e03dc03-bbeb-4f0b-b86d-e93c1e515c33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198661017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1198661017
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1224566841
Short name T726
Test name
Test status
Simulation time 16555553 ps
CPU time 0.78 seconds
Started Apr 16 12:51:15 PM PDT 24
Finished Apr 16 12:51:17 PM PDT 24
Peak memory 203488 kb
Host smart-331dbcb4-1bd4-4997-b905-74d8ac286ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224566841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1224566841
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2436490430
Short name T760
Test name
Test status
Simulation time 14108590 ps
CPU time 0.72 seconds
Started Apr 16 12:51:20 PM PDT 24
Finished Apr 16 12:51:21 PM PDT 24
Peak memory 203716 kb
Host smart-e2e212ea-98b4-4d7e-ad5f-227e767cab7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436490430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2436490430
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1191217566
Short name T782
Test name
Test status
Simulation time 40621635 ps
CPU time 0.67 seconds
Started Apr 16 12:51:26 PM PDT 24
Finished Apr 16 12:51:29 PM PDT 24
Peak memory 203820 kb
Host smart-616b44cf-62a6-454b-8964-117eb500039a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191217566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1191217566
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1009960020
Short name T763
Test name
Test status
Simulation time 15369024 ps
CPU time 0.7 seconds
Started Apr 16 12:51:23 PM PDT 24
Finished Apr 16 12:51:25 PM PDT 24
Peak memory 203324 kb
Host smart-0afbff4d-86f4-4bed-a42d-48143925053a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009960020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1009960020
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3953898781
Short name T725
Test name
Test status
Simulation time 212724498 ps
CPU time 7.07 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:11 PM PDT 24
Peak memory 206876 kb
Host smart-afa0c67c-70b5-41a6-882d-f4438c77ac7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953898781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3953898781
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.438129519
Short name T730
Test name
Test status
Simulation time 1842739498 ps
CPU time 34.91 seconds
Started Apr 16 12:51:06 PM PDT 24
Finished Apr 16 12:51:42 PM PDT 24
Peak memory 206776 kb
Host smart-7c9e2dc9-8f71-420d-a0bd-dc37af433d96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438129519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.438129519
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2782900819
Short name T92
Test name
Test status
Simulation time 41463761 ps
CPU time 1.43 seconds
Started Apr 16 12:51:17 PM PDT 24
Finished Apr 16 12:51:19 PM PDT 24
Peak memory 216088 kb
Host smart-6aeeb6e2-28ae-4c48-b982-53960f46bffa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782900819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2782900819
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1050736116
Short name T119
Test name
Test status
Simulation time 159362821 ps
CPU time 3.75 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 218088 kb
Host smart-80431188-a4eb-40bc-bf20-7a0d74c81b23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050736116 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1050736116
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1516072798
Short name T127
Test name
Test status
Simulation time 90559927 ps
CPU time 2.66 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 215084 kb
Host smart-792f8b25-cadc-4e92-8d51-360b023e157a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516072798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
516072798
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3944065034
Short name T743
Test name
Test status
Simulation time 30601872 ps
CPU time 0.73 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:07 PM PDT 24
Peak memory 203508 kb
Host smart-bc1f87e6-b5e4-4fa7-8074-fe3b8cd1aa7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944065034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
944065034
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1307655195
Short name T125
Test name
Test status
Simulation time 23771992 ps
CPU time 1.67 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 215140 kb
Host smart-5bb489ba-afcd-45fd-89cc-022523503221
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307655195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1307655195
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2369913269
Short name T744
Test name
Test status
Simulation time 12254032 ps
CPU time 0.65 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:06 PM PDT 24
Peak memory 203632 kb
Host smart-6dff94e0-af7c-42ed-8ec9-b9a8d42e6afc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369913269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2369913269
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1508857839
Short name T148
Test name
Test status
Simulation time 2620459148 ps
CPU time 4.25 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 215152 kb
Host smart-b2e25c00-fff8-4cfe-9003-93e1a57d2743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508857839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1508857839
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3854906413
Short name T32
Test name
Test status
Simulation time 156791395 ps
CPU time 4.57 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:06 PM PDT 24
Peak memory 216220 kb
Host smart-9c19f915-0f66-470b-a316-86a032312a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854906413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
854906413
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2623840610
Short name T773
Test name
Test status
Simulation time 1040643124 ps
CPU time 22.44 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:26 PM PDT 24
Peak memory 215096 kb
Host smart-b3dc34d6-23f1-4515-a44f-b9407c655781
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623840610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2623840610
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1918785880
Short name T762
Test name
Test status
Simulation time 46335511 ps
CPU time 0.76 seconds
Started Apr 16 12:51:26 PM PDT 24
Finished Apr 16 12:51:29 PM PDT 24
Peak memory 203536 kb
Host smart-6ca20836-a4ee-4a9a-be80-b47e64837188
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918785880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1918785880
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3465436190
Short name T745
Test name
Test status
Simulation time 25077835 ps
CPU time 0.77 seconds
Started Apr 16 12:51:29 PM PDT 24
Finished Apr 16 12:51:32 PM PDT 24
Peak memory 203500 kb
Host smart-1dfdf9bd-470b-442f-872c-531e5816e01c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465436190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3465436190
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.670184188
Short name T767
Test name
Test status
Simulation time 41143117 ps
CPU time 0.69 seconds
Started Apr 16 12:51:29 PM PDT 24
Finished Apr 16 12:51:32 PM PDT 24
Peak memory 203436 kb
Host smart-d73810a2-01aa-4c15-aeb3-31d92f87106a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670184188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.670184188
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2992460615
Short name T800
Test name
Test status
Simulation time 18637819 ps
CPU time 0.77 seconds
Started Apr 16 12:51:30 PM PDT 24
Finished Apr 16 12:51:33 PM PDT 24
Peak memory 203500 kb
Host smart-c528929a-ad33-4c90-9ee5-c03178c4e334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992460615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2992460615
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1187417287
Short name T733
Test name
Test status
Simulation time 16685260 ps
CPU time 0.77 seconds
Started Apr 16 12:51:31 PM PDT 24
Finished Apr 16 12:51:33 PM PDT 24
Peak memory 203836 kb
Host smart-df5c7273-c34e-4661-94c2-a3720e125291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187417287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1187417287
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2180472010
Short name T740
Test name
Test status
Simulation time 27867277 ps
CPU time 0.72 seconds
Started Apr 16 12:51:28 PM PDT 24
Finished Apr 16 12:51:31 PM PDT 24
Peak memory 203520 kb
Host smart-423492f8-4d75-4bda-a708-44d46cc5f61e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180472010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2180472010
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3440329164
Short name T817
Test name
Test status
Simulation time 57589106 ps
CPU time 0.76 seconds
Started Apr 16 12:51:19 PM PDT 24
Finished Apr 16 12:51:21 PM PDT 24
Peak memory 203512 kb
Host smart-9613e622-660f-4dc4-9102-a4d82dff5b93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440329164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3440329164
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3468481331
Short name T724
Test name
Test status
Simulation time 13544063 ps
CPU time 0.7 seconds
Started Apr 16 12:51:29 PM PDT 24
Finished Apr 16 12:51:36 PM PDT 24
Peak memory 203836 kb
Host smart-1769b068-d8f0-423e-9cda-b40c002ea7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468481331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3468481331
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3039142917
Short name T824
Test name
Test status
Simulation time 13848819 ps
CPU time 0.7 seconds
Started Apr 16 12:51:28 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 203484 kb
Host smart-47f086c6-1d9a-438e-b7c7-e904dc4c6fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039142917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3039142917
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2708397031
Short name T721
Test name
Test status
Simulation time 23252124 ps
CPU time 0.69 seconds
Started Apr 16 12:51:28 PM PDT 24
Finished Apr 16 12:51:30 PM PDT 24
Peak memory 203512 kb
Host smart-7d69b45a-9f79-4b3c-b48f-b0d5a6c0e10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708397031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2708397031
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3938819518
Short name T815
Test name
Test status
Simulation time 186558239 ps
CPU time 2.49 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:06 PM PDT 24
Peak memory 216524 kb
Host smart-6756a8c8-5d11-421d-b578-f65932f19c06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938819518 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3938819518
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3070510861
Short name T830
Test name
Test status
Simulation time 122396033 ps
CPU time 1.87 seconds
Started Apr 16 12:51:00 PM PDT 24
Finished Apr 16 12:51:04 PM PDT 24
Peak memory 215036 kb
Host smart-35068c42-43cb-4f7c-8ed5-124a5754176a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070510861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
070510861
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3904350607
Short name T766
Test name
Test status
Simulation time 13473919 ps
CPU time 0.71 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:06 PM PDT 24
Peak memory 203504 kb
Host smart-6b976b34-68e6-4b8a-983d-e311f16917e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904350607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
904350607
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4113265038
Short name T825
Test name
Test status
Simulation time 46387383 ps
CPU time 2.84 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 215072 kb
Host smart-cacc13ea-f231-489e-a9d4-31c67f80c2a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113265038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4113265038
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3433659516
Short name T776
Test name
Test status
Simulation time 65323323 ps
CPU time 1.97 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:07 PM PDT 24
Peak memory 215240 kb
Host smart-a5b53a82-ebba-4cc8-981c-b2732d391819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433659516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
433659516
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.719634890
Short name T371
Test name
Test status
Simulation time 1136330277 ps
CPU time 7.72 seconds
Started Apr 16 12:50:58 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 223092 kb
Host smart-6077da12-09cf-4d84-87f9-b2cd7cab793c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719634890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.719634890
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2018505054
Short name T147
Test name
Test status
Simulation time 450969202 ps
CPU time 2.64 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:07 PM PDT 24
Peak memory 216948 kb
Host smart-c7a99399-b7e0-4987-ae0f-1cd0a38e5292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018505054 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2018505054
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3024560725
Short name T751
Test name
Test status
Simulation time 170005550 ps
CPU time 1.3 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 215028 kb
Host smart-a30fc7a2-329c-4939-8782-195bebc14642
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024560725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
024560725
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3357734769
Short name T727
Test name
Test status
Simulation time 39426112 ps
CPU time 0.74 seconds
Started Apr 16 12:51:00 PM PDT 24
Finished Apr 16 12:51:03 PM PDT 24
Peak memory 203468 kb
Host smart-9bae559b-af2b-4599-89d9-88dd49096ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357734769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
357734769
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4035153459
Short name T770
Test name
Test status
Simulation time 417585773 ps
CPU time 4.18 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 214996 kb
Host smart-9fbdda09-f08b-40d0-ae07-df965af3d9f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035153459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4035153459
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2117645404
Short name T104
Test name
Test status
Simulation time 258270692 ps
CPU time 3.82 seconds
Started Apr 16 12:51:02 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 215280 kb
Host smart-1f7efec2-6f52-4803-bea6-e1333a839a01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117645404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
117645404
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1555451603
Short name T367
Test name
Test status
Simulation time 416179540 ps
CPU time 6.47 seconds
Started Apr 16 12:50:59 PM PDT 24
Finished Apr 16 12:51:08 PM PDT 24
Peak memory 215124 kb
Host smart-90df8e9e-85ec-4647-a39a-57fe61cb2f14
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555451603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1555451603
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1954096207
Short name T118
Test name
Test status
Simulation time 496066080 ps
CPU time 2.68 seconds
Started Apr 16 12:51:08 PM PDT 24
Finished Apr 16 12:51:12 PM PDT 24
Peak memory 216228 kb
Host smart-ddd0375b-ad1c-42b0-b108-6545c7b76f0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954096207 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1954096207
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.935650583
Short name T816
Test name
Test status
Simulation time 224257902 ps
CPU time 2.54 seconds
Started Apr 16 12:51:07 PM PDT 24
Finished Apr 16 12:51:11 PM PDT 24
Peak memory 215056 kb
Host smart-6fe4417b-7646-474f-8746-9747bd89ae18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935650583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.935650583
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.387897041
Short name T757
Test name
Test status
Simulation time 35800912 ps
CPU time 0.68 seconds
Started Apr 16 12:51:13 PM PDT 24
Finished Apr 16 12:51:15 PM PDT 24
Peak memory 203844 kb
Host smart-22b48a99-c47f-450d-8d93-27c774cd238e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387897041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.387897041
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.712855035
Short name T139
Test name
Test status
Simulation time 340986963 ps
CPU time 4.48 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:11 PM PDT 24
Peak memory 215072 kb
Host smart-963e27fa-0ae3-4a3d-b801-49ffcdb45d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712855035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.712855035
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3653122930
Short name T110
Test name
Test status
Simulation time 95787359 ps
CPU time 3.97 seconds
Started Apr 16 12:51:04 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 216180 kb
Host smart-2850db5f-b383-48e7-be9c-d97c4a31ad3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653122930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
653122930
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2630299211
Short name T373
Test name
Test status
Simulation time 1102105017 ps
CPU time 14.8 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:22 PM PDT 24
Peak memory 215092 kb
Host smart-c503e0cc-3587-492e-acd2-500ca184014b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630299211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2630299211
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2072080312
Short name T758
Test name
Test status
Simulation time 80395812 ps
CPU time 1.62 seconds
Started Apr 16 12:51:06 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 215156 kb
Host smart-60f4b7ab-ed01-4ba7-90bc-35f18a93ef7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072080312 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2072080312
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1342061801
Short name T138
Test name
Test status
Simulation time 161242105 ps
CPU time 1.41 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 206872 kb
Host smart-ca7864fd-8f55-4162-9052-f4fc8e258e44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342061801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
342061801
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.559360182
Short name T813
Test name
Test status
Simulation time 20474826 ps
CPU time 0.74 seconds
Started Apr 16 12:51:17 PM PDT 24
Finished Apr 16 12:51:19 PM PDT 24
Peak memory 203476 kb
Host smart-8d679f40-10d9-43a8-9a0b-7917fc38975c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559360182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.559360182
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2383044280
Short name T807
Test name
Test status
Simulation time 274127454 ps
CPU time 1.62 seconds
Started Apr 16 12:51:22 PM PDT 24
Finished Apr 16 12:51:25 PM PDT 24
Peak memory 215032 kb
Host smart-6aedc928-913d-4c9d-8cf6-2effac2cc58b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383044280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2383044280
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1444042024
Short name T111
Test name
Test status
Simulation time 173179884 ps
CPU time 4.49 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 215264 kb
Host smart-6f1c8e90-becd-445f-b349-cbe34b297eaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444042024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
444042024
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1788080689
Short name T732
Test name
Test status
Simulation time 279487057 ps
CPU time 7.24 seconds
Started Apr 16 12:51:03 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 216420 kb
Host smart-82aa26ca-5ae6-4546-85d8-3d986e8472d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788080689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1788080689
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2768978785
Short name T777
Test name
Test status
Simulation time 99434582 ps
CPU time 2.51 seconds
Started Apr 16 12:51:10 PM PDT 24
Finished Apr 16 12:51:14 PM PDT 24
Peak memory 216556 kb
Host smart-fcbfee58-b59d-4fbd-a010-464ef240c5bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768978785 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2768978785
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2365115328
Short name T129
Test name
Test status
Simulation time 103914769 ps
CPU time 1.12 seconds
Started Apr 16 12:51:11 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 206860 kb
Host smart-d163c885-32e9-458d-aaf8-7d013b074746
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365115328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
365115328
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.53536975
Short name T797
Test name
Test status
Simulation time 18253387 ps
CPU time 0.74 seconds
Started Apr 16 12:51:07 PM PDT 24
Finished Apr 16 12:51:09 PM PDT 24
Peak memory 203448 kb
Host smart-368d0625-9335-41a2-9638-4f5f775f5f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53536975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.53536975
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1831124140
Short name T771
Test name
Test status
Simulation time 243346797 ps
CPU time 2 seconds
Started Apr 16 12:51:10 PM PDT 24
Finished Apr 16 12:51:13 PM PDT 24
Peak memory 215080 kb
Host smart-ce6ae025-8c1e-4bd2-8914-52ff451e4ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831124140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1831124140
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3670690436
Short name T810
Test name
Test status
Simulation time 595023376 ps
CPU time 2.44 seconds
Started Apr 16 12:51:05 PM PDT 24
Finished Apr 16 12:51:10 PM PDT 24
Peak memory 215324 kb
Host smart-69cfa8ac-ba47-4bca-ab95-1293a8bcc2e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670690436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
670690436
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1884583378
Short name T372
Test name
Test status
Simulation time 2262271889 ps
CPU time 13.89 seconds
Started Apr 16 12:51:07 PM PDT 24
Finished Apr 16 12:51:22 PM PDT 24
Peak memory 215328 kb
Host smart-c7750304-ab3c-4607-944a-19dfbbbff7ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884583378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1884583378
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3802429660
Short name T646
Test name
Test status
Simulation time 28287822 ps
CPU time 0.69 seconds
Started Apr 16 12:46:53 PM PDT 24
Finished Apr 16 12:46:57 PM PDT 24
Peak memory 205268 kb
Host smart-92a9ab44-5a85-4075-8d0c-5059f7ed458c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802429660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
802429660
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2593502973
Short name T17
Test name
Test status
Simulation time 31572027 ps
CPU time 0.78 seconds
Started Apr 16 12:46:54 PM PDT 24
Finished Apr 16 12:46:57 PM PDT 24
Peak memory 206492 kb
Host smart-a30b316e-8fd7-4753-b423-41b86ccae36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593502973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2593502973
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1560365510
Short name T543
Test name
Test status
Simulation time 44538606118 ps
CPU time 84.82 seconds
Started Apr 16 12:46:57 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 238580 kb
Host smart-cd54ab23-5a8d-4e3a-b585-8a5eb1880c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560365510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1560365510
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3036882894
Short name T177
Test name
Test status
Simulation time 7426041026 ps
CPU time 9.7 seconds
Started Apr 16 12:47:00 PM PDT 24
Finished Apr 16 12:47:13 PM PDT 24
Peak memory 238236 kb
Host smart-1d447671-e889-465f-b19e-eb769c016729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036882894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3036882894
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.563485630
Short name T102
Test name
Test status
Simulation time 197026930 ps
CPU time 3.05 seconds
Started Apr 16 12:47:04 PM PDT 24
Finished Apr 16 12:47:09 PM PDT 24
Peak memory 218984 kb
Host smart-2bcccb75-64c6-4f97-959a-53b87f9c3ffe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=563485630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.563485630
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2363560008
Short name T44
Test name
Test status
Simulation time 61426598 ps
CPU time 1.06 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:11 PM PDT 24
Peak memory 234892 kb
Host smart-8980d279-3513-4279-96c8-7c188caf8321
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363560008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2363560008
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1423871977
Short name T56
Test name
Test status
Simulation time 1228308961 ps
CPU time 10.11 seconds
Started Apr 16 12:47:05 PM PDT 24
Finished Apr 16 12:47:17 PM PDT 24
Peak memory 216020 kb
Host smart-8db182c8-fbb0-4b6f-9636-01f38047c279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423871977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1423871977
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1751047578
Short name T472
Test name
Test status
Simulation time 6206963495 ps
CPU time 9.38 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:47:21 PM PDT 24
Peak memory 216172 kb
Host smart-06d24177-b008-45ff-9e51-508290fe5bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751047578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1751047578
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.470309727
Short name T699
Test name
Test status
Simulation time 357716242 ps
CPU time 1.66 seconds
Started Apr 16 12:47:04 PM PDT 24
Finished Apr 16 12:47:08 PM PDT 24
Peak memory 208056 kb
Host smart-dbe7c5f0-b477-455c-9a87-91ef09cb4cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470309727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.470309727
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2180469142
Short name T486
Test name
Test status
Simulation time 46551791 ps
CPU time 0.79 seconds
Started Apr 16 12:47:11 PM PDT 24
Finished Apr 16 12:47:14 PM PDT 24
Peak memory 205612 kb
Host smart-d4c5fb09-de72-42f7-b717-8a0fa1c15126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180469142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2180469142
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4101684080
Short name T251
Test name
Test status
Simulation time 60179235245 ps
CPU time 12.88 seconds
Started Apr 16 12:47:04 PM PDT 24
Finished Apr 16 12:47:19 PM PDT 24
Peak memory 232576 kb
Host smart-6ae97712-8e64-45df-9ad6-4e879e10a3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101684080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4101684080
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2187175319
Short name T443
Test name
Test status
Simulation time 16606785 ps
CPU time 0.77 seconds
Started Apr 16 12:46:59 PM PDT 24
Finished Apr 16 12:47:03 PM PDT 24
Peak memory 205440 kb
Host smart-aeaa6465-d3c5-4ec9-b217-f08035b56a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187175319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2187175319
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.682877460
Short name T355
Test name
Test status
Simulation time 2996039000 ps
CPU time 22.02 seconds
Started Apr 16 12:46:58 PM PDT 24
Finished Apr 16 12:47:24 PM PDT 24
Peak memory 238804 kb
Host smart-fd27b940-8fc2-4ee4-b94f-59124c4e313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682877460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.682877460
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.949345082
Short name T300
Test name
Test status
Simulation time 161837630 ps
CPU time 4.1 seconds
Started Apr 16 12:47:13 PM PDT 24
Finished Apr 16 12:47:19 PM PDT 24
Peak memory 218540 kb
Host smart-bfbf7fed-afcc-4ca8-adf3-9d960f2f0072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949345082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.949345082
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1028834846
Short name T325
Test name
Test status
Simulation time 4401969977 ps
CPU time 7.76 seconds
Started Apr 16 12:47:33 PM PDT 24
Finished Apr 16 12:47:43 PM PDT 24
Peak memory 219624 kb
Host smart-91adf70e-f5b3-4f0b-879a-1133b8230719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028834846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1028834846
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4257780010
Short name T527
Test name
Test status
Simulation time 2998258014 ps
CPU time 4.73 seconds
Started Apr 16 12:47:14 PM PDT 24
Finished Apr 16 12:47:20 PM PDT 24
Peak memory 220616 kb
Host smart-3be0bcbe-c32c-41d8-a244-6c4ed99ccc54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4257780010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4257780010
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.51555363
Short name T45
Test name
Test status
Simulation time 327155983 ps
CPU time 1.18 seconds
Started Apr 16 12:47:06 PM PDT 24
Finished Apr 16 12:47:09 PM PDT 24
Peak memory 235608 kb
Host smart-c19205b5-d0eb-4e14-aa38-1de7d65a9cc8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51555363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.51555363
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4103758363
Short name T378
Test name
Test status
Simulation time 5528235602 ps
CPU time 24.16 seconds
Started Apr 16 12:47:01 PM PDT 24
Finished Apr 16 12:47:28 PM PDT 24
Peak memory 216200 kb
Host smart-d1c31281-ab69-4452-b8b8-0801be3f88e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103758363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4103758363
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2403654733
Short name T439
Test name
Test status
Simulation time 1721758320 ps
CPU time 4.63 seconds
Started Apr 16 12:47:08 PM PDT 24
Finished Apr 16 12:47:20 PM PDT 24
Peak memory 216096 kb
Host smart-df4cc3f6-585f-463d-b64c-36aaf8072f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403654733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2403654733
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3547681638
Short name T16
Test name
Test status
Simulation time 199633127 ps
CPU time 1.37 seconds
Started Apr 16 12:46:57 PM PDT 24
Finished Apr 16 12:47:02 PM PDT 24
Peak memory 216148 kb
Host smart-adad6190-c78f-4651-8d59-d8d9295b7b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547681638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3547681638
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.207309017
Short name T537
Test name
Test status
Simulation time 109050774 ps
CPU time 1.04 seconds
Started Apr 16 12:46:56 PM PDT 24
Finished Apr 16 12:47:01 PM PDT 24
Peak memory 206680 kb
Host smart-7118ce2e-6c03-4de0-9b0e-eff5f68d9950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207309017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.207309017
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.104871180
Short name T196
Test name
Test status
Simulation time 117296319 ps
CPU time 2.2 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:47:14 PM PDT 24
Peak memory 218348 kb
Host smart-23a69a40-acce-4bf3-82d1-4801e388593f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104871180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.104871180
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.206994997
Short name T523
Test name
Test status
Simulation time 35905175 ps
CPU time 0.68 seconds
Started Apr 16 12:47:24 PM PDT 24
Finished Apr 16 12:47:27 PM PDT 24
Peak memory 205700 kb
Host smart-8aff1da9-78af-4792-af20-76d78afa71c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206994997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.206994997
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.639099134
Short name T189
Test name
Test status
Simulation time 576814365 ps
CPU time 6.29 seconds
Started Apr 16 12:47:41 PM PDT 24
Finished Apr 16 12:47:49 PM PDT 24
Peak memory 218232 kb
Host smart-d8208bf7-8ccb-4160-8423-8b53d3c5199f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639099134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.639099134
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1178819576
Short name T402
Test name
Test status
Simulation time 19400648 ps
CPU time 0.74 seconds
Started Apr 16 12:47:26 PM PDT 24
Finished Apr 16 12:47:30 PM PDT 24
Peak memory 205436 kb
Host smart-115ae894-1685-488f-8add-2df390705d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178819576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1178819576
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1049138106
Short name T570
Test name
Test status
Simulation time 1170210460 ps
CPU time 19.79 seconds
Started Apr 16 12:47:26 PM PDT 24
Finished Apr 16 12:47:49 PM PDT 24
Peak memory 224428 kb
Host smart-c04f77f6-57bb-4023-a54a-377ba65f2271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049138106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1049138106
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1112527218
Short name T174
Test name
Test status
Simulation time 3726501030 ps
CPU time 34.64 seconds
Started Apr 16 12:47:24 PM PDT 24
Finished Apr 16 12:48:00 PM PDT 24
Peak memory 232276 kb
Host smart-57f14d4c-3d08-422b-aed3-0da63787a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112527218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1112527218
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1910609791
Short name T320
Test name
Test status
Simulation time 201026194 ps
CPU time 3.95 seconds
Started Apr 16 12:47:35 PM PDT 24
Finished Apr 16 12:47:41 PM PDT 24
Peak memory 223176 kb
Host smart-1b856b35-8bd2-4e88-bf08-98dfd8e3b3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910609791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1910609791
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3142456472
Short name T312
Test name
Test status
Simulation time 2309570849 ps
CPU time 7.38 seconds
Started Apr 16 12:47:32 PM PDT 24
Finished Apr 16 12:47:41 PM PDT 24
Peak memory 218296 kb
Host smart-2524bb09-1333-4994-8ec8-74e316ec82ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142456472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3142456472
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3482276895
Short name T144
Test name
Test status
Simulation time 120244075 ps
CPU time 4.49 seconds
Started Apr 16 12:47:28 PM PDT 24
Finished Apr 16 12:47:35 PM PDT 24
Peak memory 223184 kb
Host smart-a36d3791-fd98-480e-b87d-1b71b5ced987
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482276895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3482276895
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3475502428
Short name T636
Test name
Test status
Simulation time 4399623351 ps
CPU time 19.56 seconds
Started Apr 16 12:47:32 PM PDT 24
Finished Apr 16 12:47:54 PM PDT 24
Peak memory 216284 kb
Host smart-d7071f3e-fc1f-482f-9606-99adfa75a159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475502428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3475502428
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2881139807
Short name T550
Test name
Test status
Simulation time 713549528 ps
CPU time 3.17 seconds
Started Apr 16 12:47:22 PM PDT 24
Finished Apr 16 12:47:27 PM PDT 24
Peak memory 216152 kb
Host smart-a83474a8-2f75-43bd-8883-39c2140149bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881139807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2881139807
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1455417853
Short name T391
Test name
Test status
Simulation time 146441933 ps
CPU time 1.79 seconds
Started Apr 16 12:47:25 PM PDT 24
Finished Apr 16 12:47:29 PM PDT 24
Peak memory 216140 kb
Host smart-d411a5ad-e018-40ce-94ce-aaac2ab5bd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455417853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1455417853
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.463236539
Short name T551
Test name
Test status
Simulation time 113902249 ps
CPU time 1.09 seconds
Started Apr 16 12:47:34 PM PDT 24
Finished Apr 16 12:47:37 PM PDT 24
Peak memory 206616 kb
Host smart-15d9faa5-3452-427a-aaf0-94de08e13c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463236539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.463236539
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2884399930
Short name T469
Test name
Test status
Simulation time 23275900 ps
CPU time 0.72 seconds
Started Apr 16 12:47:29 PM PDT 24
Finished Apr 16 12:47:33 PM PDT 24
Peak memory 204728 kb
Host smart-17e00357-a8f4-4784-9a29-736449d60746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884399930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2884399930
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4077467372
Short name T21
Test name
Test status
Simulation time 13533827 ps
CPU time 0.81 seconds
Started Apr 16 12:47:22 PM PDT 24
Finished Apr 16 12:47:24 PM PDT 24
Peak memory 206476 kb
Host smart-510c0871-ea8e-4643-853c-79ad2f6c9f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077467372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4077467372
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.961154488
Short name T121
Test name
Test status
Simulation time 952061844 ps
CPU time 22.53 seconds
Started Apr 16 12:47:40 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 250524 kb
Host smart-e92b6fb6-1bd4-4374-a8e3-b330f366eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961154488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.961154488
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.99031858
Short name T285
Test name
Test status
Simulation time 137777077 ps
CPU time 3.06 seconds
Started Apr 16 12:47:22 PM PDT 24
Finished Apr 16 12:47:26 PM PDT 24
Peak memory 222588 kb
Host smart-2ac544f2-a71d-41b0-9cff-f226c0140db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99031858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.99031858
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2000955765
Short name T235
Test name
Test status
Simulation time 9939019445 ps
CPU time 78.5 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:49:04 PM PDT 24
Peak memory 232420 kb
Host smart-d36dfe55-50a1-41f5-a9e6-7a66bb11d490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000955765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2000955765
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3924140502
Short name T324
Test name
Test status
Simulation time 8983609585 ps
CPU time 18.92 seconds
Started Apr 16 12:47:34 PM PDT 24
Finished Apr 16 12:47:55 PM PDT 24
Peak memory 228992 kb
Host smart-8c3f42cd-c16a-4f82-9913-030173722d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924140502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3924140502
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3371073527
Short name T79
Test name
Test status
Simulation time 3353478274 ps
CPU time 9.35 seconds
Started Apr 16 12:47:20 PM PDT 24
Finished Apr 16 12:47:31 PM PDT 24
Peak memory 222240 kb
Host smart-3aba402c-7089-4977-94ef-7083aacf4206
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371073527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3371073527
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.399595739
Short name T393
Test name
Test status
Simulation time 3429900654 ps
CPU time 20.03 seconds
Started Apr 16 12:47:32 PM PDT 24
Finished Apr 16 12:47:55 PM PDT 24
Peak memory 216356 kb
Host smart-ce5bcb88-59b1-4421-b610-4f0fd07947b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399595739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.399595739
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.590498334
Short name T669
Test name
Test status
Simulation time 1777013272 ps
CPU time 6.44 seconds
Started Apr 16 12:47:38 PM PDT 24
Finished Apr 16 12:47:46 PM PDT 24
Peak memory 216164 kb
Host smart-ec3123ee-adc6-46e5-adc2-10c36a1c6dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590498334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.590498334
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.932715763
Short name T696
Test name
Test status
Simulation time 50224937 ps
CPU time 1.09 seconds
Started Apr 16 12:47:35 PM PDT 24
Finished Apr 16 12:47:38 PM PDT 24
Peak memory 207768 kb
Host smart-fbd56f78-e759-431a-8dc0-b084ae00ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932715763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.932715763
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3195088363
Short name T431
Test name
Test status
Simulation time 17440286 ps
CPU time 0.76 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:47:46 PM PDT 24
Peak memory 205700 kb
Host smart-f77cefa5-5ea4-415a-92ee-45a79c111377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195088363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3195088363
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2071823789
Short name T678
Test name
Test status
Simulation time 38640697 ps
CPU time 0.71 seconds
Started Apr 16 12:47:31 PM PDT 24
Finished Apr 16 12:47:34 PM PDT 24
Peak memory 205332 kb
Host smart-7f3e6b4a-909e-4d97-93fa-2367ccc7b90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071823789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2071823789
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1524520111
Short name T661
Test name
Test status
Simulation time 1972134671 ps
CPU time 9.51 seconds
Started Apr 16 12:47:31 PM PDT 24
Finished Apr 16 12:47:43 PM PDT 24
Peak memory 223608 kb
Host smart-5ab59b8a-b02d-4601-a63c-5b0fc05a8c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524520111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1524520111
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2932330416
Short name T572
Test name
Test status
Simulation time 41019758 ps
CPU time 0.85 seconds
Started Apr 16 12:47:42 PM PDT 24
Finished Apr 16 12:47:45 PM PDT 24
Peak memory 206468 kb
Host smart-20baf31b-d835-4a87-bcb8-52849a576db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932330416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2932330416
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2697577460
Short name T556
Test name
Test status
Simulation time 19553616416 ps
CPU time 78.13 seconds
Started Apr 16 12:47:42 PM PDT 24
Finished Apr 16 12:49:03 PM PDT 24
Peak memory 257208 kb
Host smart-6ecb0e26-dd1b-4bcd-84cd-f4ef2b61db5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697577460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2697577460
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.305515703
Short name T229
Test name
Test status
Simulation time 150760270 ps
CPU time 3.24 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:47:49 PM PDT 24
Peak memory 218560 kb
Host smart-c01f8eda-8b14-4443-92b8-1a724f75e995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305515703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.305515703
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.876973784
Short name T238
Test name
Test status
Simulation time 4016247556 ps
CPU time 11.25 seconds
Started Apr 16 12:47:22 PM PDT 24
Finished Apr 16 12:47:35 PM PDT 24
Peak memory 218700 kb
Host smart-bfef0b12-6030-4ccd-87f7-8b77709e026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876973784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.876973784
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.107103430
Short name T458
Test name
Test status
Simulation time 6640584467 ps
CPU time 7.4 seconds
Started Apr 16 12:47:37 PM PDT 24
Finished Apr 16 12:47:45 PM PDT 24
Peak memory 218972 kb
Host smart-05f5ccf0-b8bd-4f1e-bd62-abb56088f0e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=107103430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.107103430
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1686848468
Short name T379
Test name
Test status
Simulation time 9157668025 ps
CPU time 24.51 seconds
Started Apr 16 12:47:27 PM PDT 24
Finished Apr 16 12:47:54 PM PDT 24
Peak memory 216272 kb
Host smart-df67017a-edae-4486-965b-369343bd5a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686848468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1686848468
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.776544448
Short name T557
Test name
Test status
Simulation time 804726047 ps
CPU time 4.62 seconds
Started Apr 16 12:47:30 PM PDT 24
Finished Apr 16 12:47:37 PM PDT 24
Peak memory 216208 kb
Host smart-816041ad-c2fe-4d18-99a9-6104e00ec88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776544448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.776544448
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1763613725
Short name T496
Test name
Test status
Simulation time 458623214 ps
CPU time 5.09 seconds
Started Apr 16 12:47:16 PM PDT 24
Finished Apr 16 12:47:23 PM PDT 24
Peak memory 216136 kb
Host smart-666fb525-4994-4932-a144-fd6a3e489242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763613725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1763613725
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2626645601
Short name T465
Test name
Test status
Simulation time 89283765 ps
CPU time 0.73 seconds
Started Apr 16 12:47:25 PM PDT 24
Finished Apr 16 12:47:28 PM PDT 24
Peak memory 205716 kb
Host smart-417b77dd-dbd7-44cd-8568-b7f3df00cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626645601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2626645601
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.17716533
Short name T417
Test name
Test status
Simulation time 45546318 ps
CPU time 0.74 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:47:48 PM PDT 24
Peak memory 205356 kb
Host smart-33a4d79f-a05a-4a24-8d3b-1aafa47237e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17716533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.17716533
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2129197045
Short name T609
Test name
Test status
Simulation time 39714597 ps
CPU time 0.78 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:47:47 PM PDT 24
Peak memory 206484 kb
Host smart-7f6001ea-ebb3-4c52-980c-d340034d5135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129197045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2129197045
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2449920383
Short name T653
Test name
Test status
Simulation time 8547944181 ps
CPU time 61.98 seconds
Started Apr 16 12:47:34 PM PDT 24
Finished Apr 16 12:48:38 PM PDT 24
Peak memory 249008 kb
Host smart-0ac027f5-504a-4fa4-a100-87741c3b2ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449920383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2449920383
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.847907724
Short name T361
Test name
Test status
Simulation time 2100164853 ps
CPU time 14.58 seconds
Started Apr 16 12:47:31 PM PDT 24
Finished Apr 16 12:47:48 PM PDT 24
Peak memory 222156 kb
Host smart-da9b4a94-08e4-45ed-844e-42d5d024b6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847907724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.847907724
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3249050225
Short name T210
Test name
Test status
Simulation time 9493191564 ps
CPU time 79.13 seconds
Started Apr 16 12:47:38 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 222912 kb
Host smart-516c0367-0345-49f6-9dd0-df5066f9d623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249050225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3249050225
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3268563826
Short name T574
Test name
Test status
Simulation time 1453010082 ps
CPU time 4.96 seconds
Started Apr 16 12:47:40 PM PDT 24
Finished Apr 16 12:47:46 PM PDT 24
Peak memory 220096 kb
Host smart-eed94565-f917-47d9-ae11-6d1bd36ff4cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3268563826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3268563826
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1874479582
Short name T535
Test name
Test status
Simulation time 1155312900 ps
CPU time 3.63 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:47:51 PM PDT 24
Peak memory 216284 kb
Host smart-fb00310b-6421-474d-9fc8-23fedb0ca6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874479582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1874479582
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1805808594
Short name T400
Test name
Test status
Simulation time 44054001 ps
CPU time 2.37 seconds
Started Apr 16 12:47:54 PM PDT 24
Finished Apr 16 12:48:02 PM PDT 24
Peak memory 208000 kb
Host smart-291ed37a-a91b-4f5d-a94f-6442e99e6d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805808594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1805808594
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.683740380
Short name T680
Test name
Test status
Simulation time 83157984 ps
CPU time 0.96 seconds
Started Apr 16 12:47:40 PM PDT 24
Finished Apr 16 12:47:42 PM PDT 24
Peak memory 206720 kb
Host smart-89397907-eedf-4231-be33-05267e813be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683740380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.683740380
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3713125566
Short name T289
Test name
Test status
Simulation time 79217909615 ps
CPU time 17.47 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 233316 kb
Host smart-00f86fd5-4231-4be0-ba03-38c35ccdd180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713125566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3713125566
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1848749119
Short name T506
Test name
Test status
Simulation time 22722007 ps
CPU time 0.72 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:47:55 PM PDT 24
Peak memory 205636 kb
Host smart-eaa80a47-bedc-4ac8-b9e8-6f1f18722d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848749119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1848749119
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.107234086
Short name T418
Test name
Test status
Simulation time 38654327 ps
CPU time 0.79 seconds
Started Apr 16 12:47:33 PM PDT 24
Finished Apr 16 12:47:36 PM PDT 24
Peak memory 206848 kb
Host smart-1ce457ea-2051-4179-a354-507986f69201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107234086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.107234086
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2571634634
Short name T335
Test name
Test status
Simulation time 3114976456 ps
CPU time 46.05 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:48:39 PM PDT 24
Peak memory 234700 kb
Host smart-b075a3b5-807a-4cfa-8055-426443ae0195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571634634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2571634634
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2129969927
Short name T89
Test name
Test status
Simulation time 14096748116 ps
CPU time 18.51 seconds
Started Apr 16 12:47:36 PM PDT 24
Finished Apr 16 12:47:56 PM PDT 24
Peak memory 219016 kb
Host smart-464f8155-719e-4d58-b77f-ede3cec4888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129969927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2129969927
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.777196819
Short name T162
Test name
Test status
Simulation time 113136144 ps
CPU time 2.85 seconds
Started Apr 16 12:47:39 PM PDT 24
Finished Apr 16 12:47:44 PM PDT 24
Peak memory 216688 kb
Host smart-e6c00034-e8a9-4481-8522-fdb6efe987ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777196819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.777196819
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1667652697
Short name T638
Test name
Test status
Simulation time 3436471131 ps
CPU time 8.43 seconds
Started Apr 16 12:47:46 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 218944 kb
Host smart-ad98d102-9075-43c8-8f53-8c4f297cadc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1667652697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1667652697
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.346824182
Short name T599
Test name
Test status
Simulation time 2210629483 ps
CPU time 13.7 seconds
Started Apr 16 12:47:32 PM PDT 24
Finished Apr 16 12:47:48 PM PDT 24
Peak memory 216256 kb
Host smart-c8015ade-7cf3-46ca-81ff-653275506b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346824182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.346824182
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2301244573
Short name T595
Test name
Test status
Simulation time 8729387272 ps
CPU time 9.24 seconds
Started Apr 16 12:47:45 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 216108 kb
Host smart-5d6f8b25-b53c-4531-8a22-714546c6bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301244573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2301244573
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3962859908
Short name T389
Test name
Test status
Simulation time 912774466 ps
CPU time 2.77 seconds
Started Apr 16 12:47:45 PM PDT 24
Finished Apr 16 12:47:51 PM PDT 24
Peak memory 216188 kb
Host smart-3c39a25b-87bc-4768-9405-be5fe402f6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962859908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3962859908
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3960371349
Short name T533
Test name
Test status
Simulation time 137527937 ps
CPU time 0.9 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:47:59 PM PDT 24
Peak memory 206624 kb
Host smart-5728400a-62e8-4064-a979-6874074b2913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960371349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3960371349
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3913441776
Short name T687
Test name
Test status
Simulation time 38590493 ps
CPU time 0.74 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:47:56 PM PDT 24
Peak memory 204792 kb
Host smart-01b237cd-2e75-4cb8-ae93-1981fc12e598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913441776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3913441776
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1096199524
Short name T689
Test name
Test status
Simulation time 58036524 ps
CPU time 0.81 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:47:46 PM PDT 24
Peak memory 205476 kb
Host smart-9c534320-e2bf-45a6-8648-62dba529cac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096199524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1096199524
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.489878738
Short name T12
Test name
Test status
Simulation time 208965229 ps
CPU time 11.82 seconds
Started Apr 16 12:47:41 PM PDT 24
Finished Apr 16 12:47:55 PM PDT 24
Peak memory 232620 kb
Host smart-b06c79fb-dc8e-47f9-8d44-e0984efb1071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489878738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.489878738
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2628096391
Short name T228
Test name
Test status
Simulation time 28049136277 ps
CPU time 17.36 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:48:03 PM PDT 24
Peak memory 232500 kb
Host smart-f09512df-2e68-4eca-bd7f-38594fb2e2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628096391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2628096391
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3638292941
Short name T712
Test name
Test status
Simulation time 409024915 ps
CPU time 5.38 seconds
Started Apr 16 12:47:39 PM PDT 24
Finished Apr 16 12:47:46 PM PDT 24
Peak memory 221400 kb
Host smart-d48a20e3-f04d-4684-b601-896aa181e73d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3638292941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3638292941
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1896303722
Short name T15
Test name
Test status
Simulation time 27604470768 ps
CPU time 22.92 seconds
Started Apr 16 12:47:32 PM PDT 24
Finished Apr 16 12:47:57 PM PDT 24
Peak memory 216444 kb
Host smart-66e72ed3-a18c-4b51-afce-0722a8f7aa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896303722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1896303722
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.556024326
Short name T58
Test name
Test status
Simulation time 183564717 ps
CPU time 3.18 seconds
Started Apr 16 12:47:34 PM PDT 24
Finished Apr 16 12:47:39 PM PDT 24
Peak memory 216208 kb
Host smart-eaa4e670-8ee8-4e46-9225-f5f5f1eda22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556024326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.556024326
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3646802351
Short name T437
Test name
Test status
Simulation time 269432351 ps
CPU time 0.94 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:47:48 PM PDT 24
Peak memory 206632 kb
Host smart-5ad5e408-16e6-4f86-954f-bf842d476373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646802351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3646802351
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3593187111
Short name T512
Test name
Test status
Simulation time 26752653 ps
CPU time 0.75 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:47:46 PM PDT 24
Peak memory 205288 kb
Host smart-c226cd04-4e45-494b-a41a-ea62712b3060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593187111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3593187111
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.4160693142
Short name T23
Test name
Test status
Simulation time 193124216 ps
CPU time 2.21 seconds
Started Apr 16 12:47:46 PM PDT 24
Finished Apr 16 12:47:53 PM PDT 24
Peak memory 218976 kb
Host smart-6f400589-3981-496c-b650-dbb7279347d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160693142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.4160693142
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.561595510
Short name T558
Test name
Test status
Simulation time 17910314 ps
CPU time 0.81 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:47:57 PM PDT 24
Peak memory 206500 kb
Host smart-13907abf-0aeb-4fa3-991d-d62a78aea4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561595510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.561595510
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1009918771
Short name T304
Test name
Test status
Simulation time 882347630 ps
CPU time 8.69 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:48:02 PM PDT 24
Peak memory 232052 kb
Host smart-18fbb586-4bd7-494e-b7c0-66d50663aa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009918771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1009918771
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2066468472
Short name T208
Test name
Test status
Simulation time 18035137667 ps
CPU time 41.97 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:44 PM PDT 24
Peak memory 218584 kb
Host smart-de735a25-d87f-4ab0-bf1f-a22cee632eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066468472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2066468472
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3781321949
Short name T329
Test name
Test status
Simulation time 4260642296 ps
CPU time 12.02 seconds
Started Apr 16 12:47:45 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 234688 kb
Host smart-62dfb9e4-6d22-4da3-b945-69169f860133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781321949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3781321949
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.560553808
Short name T593
Test name
Test status
Simulation time 893326253 ps
CPU time 7.15 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 222416 kb
Host smart-42da4116-fa57-4e79-9501-168b11c87829
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=560553808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.560553808
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2584495900
Short name T651
Test name
Test status
Simulation time 40906242402 ps
CPU time 26.86 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:30 PM PDT 24
Peak memory 216212 kb
Host smart-2e8867cd-3ece-4ec3-b0ea-d2393bd07105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584495900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2584495900
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2618826513
Short name T716
Test name
Test status
Simulation time 41522099 ps
CPU time 1.11 seconds
Started Apr 16 12:47:45 PM PDT 24
Finished Apr 16 12:47:50 PM PDT 24
Peak memory 207192 kb
Host smart-904a6d19-db3d-40e9-9381-39b230b46840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618826513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2618826513
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1498066061
Short name T577
Test name
Test status
Simulation time 193187918 ps
CPU time 0.89 seconds
Started Apr 16 12:47:45 PM PDT 24
Finished Apr 16 12:47:50 PM PDT 24
Peak memory 205672 kb
Host smart-fcad949f-b04f-4c33-979c-90b41d90bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498066061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1498066061
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3133411277
Short name T691
Test name
Test status
Simulation time 1747676169 ps
CPU time 4.92 seconds
Started Apr 16 12:47:41 PM PDT 24
Finished Apr 16 12:47:48 PM PDT 24
Peak memory 231932 kb
Host smart-2d7c913d-bcc4-4e41-a0c7-4ba7a29bfe23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133411277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3133411277
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3343055764
Short name T416
Test name
Test status
Simulation time 24555721 ps
CPU time 0.7 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:47:57 PM PDT 24
Peak memory 205348 kb
Host smart-9567aafd-4efc-418d-bedd-1d142f679fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343055764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3343055764
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2745115730
Short name T309
Test name
Test status
Simulation time 328269096 ps
CPU time 3.95 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:02 PM PDT 24
Peak memory 222904 kb
Host smart-ab8dc2f6-e507-44b0-a286-3b6d89bf74c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745115730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2745115730
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4137575865
Short name T455
Test name
Test status
Simulation time 44614578 ps
CPU time 0.74 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 206488 kb
Host smart-26e725b1-c170-4cda-a3da-cd6a8efc67ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137575865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4137575865
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3529590483
Short name T710
Test name
Test status
Simulation time 7865726857 ps
CPU time 70.76 seconds
Started Apr 16 12:47:53 PM PDT 24
Finished Apr 16 12:49:10 PM PDT 24
Peak memory 240348 kb
Host smart-cb123a2a-3694-4ce7-ab93-b6d39a036f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529590483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3529590483
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.366266197
Short name T257
Test name
Test status
Simulation time 1456269863 ps
CPU time 17.9 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:48:09 PM PDT 24
Peak memory 219000 kb
Host smart-4672d7a7-9c01-413b-aacc-56ee7f932d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366266197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.366266197
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3522227020
Short name T606
Test name
Test status
Simulation time 111237024 ps
CPU time 2.58 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:47:49 PM PDT 24
Peak memory 222952 kb
Host smart-085aa308-e2ae-4bf5-abf1-5c697a2ab5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522227020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3522227020
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.837744516
Short name T202
Test name
Test status
Simulation time 1389979641 ps
CPU time 4.73 seconds
Started Apr 16 12:47:45 PM PDT 24
Finished Apr 16 12:47:53 PM PDT 24
Peak memory 223084 kb
Host smart-9ccdfa65-94df-4c57-84e0-3fa3ef5f07b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837744516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.837744516
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.826615766
Short name T241
Test name
Test status
Simulation time 35777488819 ps
CPU time 48.09 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 238844 kb
Host smart-e462c0cd-44bf-4c7a-ad56-f50e26307e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826615766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.826615766
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1620917887
Short name T517
Test name
Test status
Simulation time 579452579 ps
CPU time 8.4 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:48:02 PM PDT 24
Peak memory 221796 kb
Host smart-9ee9760c-608e-480e-9f30-bfa4777545fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1620917887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1620917887
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.49859185
Short name T655
Test name
Test status
Simulation time 112985413 ps
CPU time 1.13 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 207068 kb
Host smart-f0480c7b-4bd1-46a6-909a-472383a01979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49859185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress
_all.49859185
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3046873954
Short name T617
Test name
Test status
Simulation time 3294087360 ps
CPU time 31.44 seconds
Started Apr 16 12:47:43 PM PDT 24
Finished Apr 16 12:48:17 PM PDT 24
Peak memory 216280 kb
Host smart-6359403e-eb34-44e6-9dac-f9f76592846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046873954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3046873954
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3214114640
Short name T659
Test name
Test status
Simulation time 31228761981 ps
CPU time 22.76 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:48:18 PM PDT 24
Peak memory 216244 kb
Host smart-57eb5832-bfec-4d6b-b5d3-317c71c574fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214114640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3214114640
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.769815776
Short name T664
Test name
Test status
Simulation time 103881631 ps
CPU time 2.2 seconds
Started Apr 16 12:47:44 PM PDT 24
Finished Apr 16 12:47:49 PM PDT 24
Peak memory 216072 kb
Host smart-8e0a7bf5-0fc1-43d5-8523-a6bda746bce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769815776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.769815776
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2529866455
Short name T581
Test name
Test status
Simulation time 41071180 ps
CPU time 0.85 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 205680 kb
Host smart-aae5733c-f6c8-471d-bb9f-38f1f1424001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529866455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2529866455
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1214982641
Short name T642
Test name
Test status
Simulation time 13695479 ps
CPU time 0.71 seconds
Started Apr 16 12:47:53 PM PDT 24
Finished Apr 16 12:48:00 PM PDT 24
Peak memory 205260 kb
Host smart-09971d0f-ea4a-49e7-acad-1c76abe1591f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214982641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1214982641
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.36031831
Short name T641
Test name
Test status
Simulation time 25450391 ps
CPU time 0.77 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:47:53 PM PDT 24
Peak memory 206500 kb
Host smart-fee8c8af-126e-435f-bb32-e2df7d1d5f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36031831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.36031831
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3887537079
Short name T339
Test name
Test status
Simulation time 3792108787 ps
CPU time 53.2 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:48:48 PM PDT 24
Peak memory 249036 kb
Host smart-efdb385a-8030-4d5a-b1aa-38a98cdcdca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887537079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3887537079
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.969789203
Short name T500
Test name
Test status
Simulation time 130495732 ps
CPU time 3.54 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:48:00 PM PDT 24
Peak memory 219964 kb
Host smart-957760ec-b3be-4250-8a04-aa78ade9641f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=969789203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.969789203
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2014803739
Short name T665
Test name
Test status
Simulation time 879730190 ps
CPU time 3.27 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:48:00 PM PDT 24
Peak memory 216232 kb
Host smart-6d0d8f4b-cf37-4656-8edf-392f9d692520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014803739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2014803739
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3335281765
Short name T464
Test name
Test status
Simulation time 1786897933 ps
CPU time 8.97 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 216120 kb
Host smart-be707556-8211-4152-aa86-40e08c78a5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335281765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3335281765
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2954897929
Short name T698
Test name
Test status
Simulation time 14932647 ps
CPU time 0.76 seconds
Started Apr 16 12:48:10 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 205656 kb
Host smart-dfc82b82-e698-40ad-9a36-1f771b8f0fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954897929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2954897929
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3029381080
Short name T693
Test name
Test status
Simulation time 16644203 ps
CPU time 0.73 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:48:00 PM PDT 24
Peak memory 205712 kb
Host smart-377429f3-dd3a-4863-8e5d-49e38e28e6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029381080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3029381080
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.476236317
Short name T491
Test name
Test status
Simulation time 11563595 ps
CPU time 0.69 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 205376 kb
Host smart-83ea1d72-0c78-4229-b0c8-124f9983fbf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476236317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.476236317
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3427930970
Short name T453
Test name
Test status
Simulation time 20677461 ps
CPU time 0.77 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:47:52 PM PDT 24
Peak memory 206792 kb
Host smart-8cb28c4c-70d2-47bf-9226-a673a7b0ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427930970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3427930970
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3271152694
Short name T50
Test name
Test status
Simulation time 538863396 ps
CPU time 9.93 seconds
Started Apr 16 12:47:40 PM PDT 24
Finished Apr 16 12:47:52 PM PDT 24
Peak memory 253084 kb
Host smart-0117ee6a-d0ef-4dcb-b9cf-af08fbd95bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271152694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3271152694
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3390077162
Short name T159
Test name
Test status
Simulation time 2770573629 ps
CPU time 19.78 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:48:12 PM PDT 24
Peak memory 216648 kb
Host smart-8ebf5edf-3057-4bd3-a9ae-a582c686d654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390077162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3390077162
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2585102987
Short name T477
Test name
Test status
Simulation time 443289561 ps
CPU time 7.42 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 222844 kb
Host smart-969d48f1-d97e-40eb-ba1c-cedea5563b92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2585102987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2585102987
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1767930421
Short name T386
Test name
Test status
Simulation time 18725938188 ps
CPU time 27.63 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:48:20 PM PDT 24
Peak memory 216428 kb
Host smart-516fffff-cacc-4430-a174-8c7a48e09532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767930421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1767930421
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3633699587
Short name T671
Test name
Test status
Simulation time 43114584975 ps
CPU time 28.8 seconds
Started Apr 16 12:47:55 PM PDT 24
Finished Apr 16 12:48:29 PM PDT 24
Peak memory 216148 kb
Host smart-c901c474-5a59-4400-8731-c6b20c1d03bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633699587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3633699587
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.35919591
Short name T498
Test name
Test status
Simulation time 54527231 ps
CPU time 0.88 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 206256 kb
Host smart-550556c5-6c3f-474e-a68e-206814de2489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35919591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.35919591
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2428817633
Short name T571
Test name
Test status
Simulation time 127975800 ps
CPU time 1.09 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 206576 kb
Host smart-f0396198-7924-44ef-ad5c-dd7b37d6d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428817633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2428817633
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3080229228
Short name T608
Test name
Test status
Simulation time 24609924 ps
CPU time 0.75 seconds
Started Apr 16 12:46:58 PM PDT 24
Finished Apr 16 12:47:02 PM PDT 24
Peak memory 204820 kb
Host smart-a34d97a2-6c51-47a0-88ab-95cd82577eeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080229228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
080229228
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2521658441
Short name T584
Test name
Test status
Simulation time 19887779 ps
CPU time 0.84 seconds
Started Apr 16 12:46:58 PM PDT 24
Finished Apr 16 12:47:02 PM PDT 24
Peak memory 206548 kb
Host smart-35ec7aa6-9f52-4bf9-859c-5f45124ddc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521658441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2521658441
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1456642652
Short name T338
Test name
Test status
Simulation time 2636183649 ps
CPU time 16.36 seconds
Started Apr 16 12:46:56 PM PDT 24
Finished Apr 16 12:47:17 PM PDT 24
Peak memory 249000 kb
Host smart-6dab1bcf-b698-4e42-8f22-22585704ba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456642652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1456642652
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2318264787
Short name T360
Test name
Test status
Simulation time 444088568 ps
CPU time 5.24 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:24 PM PDT 24
Peak memory 216324 kb
Host smart-b3cd69b7-2fde-4547-b7da-a774a56d5af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318264787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2318264787
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1276233866
Short name T184
Test name
Test status
Simulation time 18523111574 ps
CPU time 29.89 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:49 PM PDT 24
Peak memory 228536 kb
Host smart-6239d1ea-e2af-4d5b-b2b5-21e2cce1bc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276233866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1276233866
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1909651087
Short name T627
Test name
Test status
Simulation time 2116505504 ps
CPU time 4.49 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:14 PM PDT 24
Peak memory 218740 kb
Host smart-2f759050-c6db-416b-9543-9bede5c57262
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1909651087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1909651087
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1682323726
Short name T442
Test name
Test status
Simulation time 25250373695 ps
CPU time 17.49 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:27 PM PDT 24
Peak memory 216272 kb
Host smart-ba11cadf-c0a2-4fcc-9b2c-9dc04f5de25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682323726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1682323726
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2713196977
Short name T398
Test name
Test status
Simulation time 892287551 ps
CPU time 4.12 seconds
Started Apr 16 12:47:06 PM PDT 24
Finished Apr 16 12:47:13 PM PDT 24
Peak memory 216248 kb
Host smart-b3198ca4-0bf3-4696-a756-0bcc660658fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713196977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2713196977
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3152585166
Short name T495
Test name
Test status
Simulation time 42411980 ps
CPU time 0.97 seconds
Started Apr 16 12:46:59 PM PDT 24
Finished Apr 16 12:47:03 PM PDT 24
Peak memory 206708 kb
Host smart-807a8860-9aa5-4396-a56d-c3f785452921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152585166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3152585166
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.648168994
Short name T657
Test name
Test status
Simulation time 12893594 ps
CPU time 0.68 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 204760 kb
Host smart-e037cfc9-80f5-46c2-92b8-4c8cc4090190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648168994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.648168994
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3432154118
Short name T591
Test name
Test status
Simulation time 430195732 ps
CPU time 2.82 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:07 PM PDT 24
Peak memory 218524 kb
Host smart-6bacec08-5842-48fe-a2e4-bbf7828c9506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432154118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3432154118
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2499859094
Short name T618
Test name
Test status
Simulation time 75346834 ps
CPU time 0.77 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:02 PM PDT 24
Peak memory 206492 kb
Host smart-6d0fb6de-1183-4b78-b37a-acf5599f0c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499859094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2499859094
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.328871443
Short name T337
Test name
Test status
Simulation time 14919653137 ps
CPU time 189.06 seconds
Started Apr 16 12:47:45 PM PDT 24
Finished Apr 16 12:50:58 PM PDT 24
Peak memory 250436 kb
Host smart-b5f57534-b82a-4aeb-b776-346064ee4ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328871443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.328871443
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1830929540
Short name T249
Test name
Test status
Simulation time 110796943 ps
CPU time 2.74 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 218968 kb
Host smart-7c6c1c4e-aad1-4d78-b377-434fe347c45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830929540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1830929540
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1455959241
Short name T225
Test name
Test status
Simulation time 3472064341 ps
CPU time 21.65 seconds
Started Apr 16 12:47:55 PM PDT 24
Finished Apr 16 12:48:22 PM PDT 24
Peak memory 233668 kb
Host smart-28bea280-1b74-48aa-bd66-b134b6730cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455959241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1455959241
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1450787301
Short name T65
Test name
Test status
Simulation time 16252740557 ps
CPU time 14.49 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:12 PM PDT 24
Peak memory 233208 kb
Host smart-076c1d29-7aca-4a90-9dc8-55a05bdebe30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450787301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1450787301
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3833441375
Short name T565
Test name
Test status
Simulation time 360186640 ps
CPU time 6.54 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:48:02 PM PDT 24
Peak memory 222844 kb
Host smart-a8218923-51d3-4940-b2bb-95fb00fb9b24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3833441375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3833441375
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4042986571
Short name T98
Test name
Test status
Simulation time 15649747235 ps
CPU time 24.83 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:48:20 PM PDT 24
Peak memory 216256 kb
Host smart-bda27418-4f6f-4191-ab46-dab927fa469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042986571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4042986571
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4074899578
Short name T531
Test name
Test status
Simulation time 27239693970 ps
CPU time 18.6 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:22 PM PDT 24
Peak memory 216128 kb
Host smart-814b70bd-c08f-4d0e-a1df-8eedf6a9deb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074899578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4074899578
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1603010433
Short name T576
Test name
Test status
Simulation time 175449482 ps
CPU time 0.91 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:03 PM PDT 24
Peak memory 206716 kb
Host smart-a7bf56df-c616-44b5-ba37-5e06386aa276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603010433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1603010433
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2405545666
Short name T684
Test name
Test status
Simulation time 149457922 ps
CPU time 0.87 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 206728 kb
Host smart-ca298372-5e5f-4a2f-96d5-a16757bcee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405545666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2405545666
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2467830723
Short name T568
Test name
Test status
Simulation time 127631306 ps
CPU time 0.68 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 205296 kb
Host smart-85a074f8-5daf-4d30-aef0-26c891386732
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467830723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2467830723
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3153029468
Short name T601
Test name
Test status
Simulation time 904412873 ps
CPU time 3.36 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:47:59 PM PDT 24
Peak memory 221972 kb
Host smart-67c3e197-62f8-4521-8dfb-1165440ee2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153029468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3153029468
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.395685811
Short name T519
Test name
Test status
Simulation time 21727482 ps
CPU time 0.82 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 206372 kb
Host smart-6daf0bcb-46ce-47bd-a69a-75e0cd6e7a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395685811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.395685811
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1268000506
Short name T358
Test name
Test status
Simulation time 2102252801 ps
CPU time 15.8 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 237940 kb
Host smart-4a93e824-3fbc-419f-b9fd-6ac16bb4ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268000506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1268000506
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3427536239
Short name T299
Test name
Test status
Simulation time 2947251517 ps
CPU time 9.79 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:07 PM PDT 24
Peak memory 218964 kb
Host smart-26583f6d-ee47-44ef-a1aa-46ad04008a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427536239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3427536239
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1057300486
Short name T301
Test name
Test status
Simulation time 29359314981 ps
CPU time 118.86 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:49:53 PM PDT 24
Peak memory 240668 kb
Host smart-01d5f293-36d0-4cff-bf5e-4c5efcd78c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057300486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1057300486
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2239880871
Short name T64
Test name
Test status
Simulation time 46829186620 ps
CPU time 21.68 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:48:17 PM PDT 24
Peak memory 223000 kb
Host smart-83cc515d-2458-44d5-8bbb-54019106e47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239880871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2239880871
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.91700371
Short name T428
Test name
Test status
Simulation time 177853504 ps
CPU time 3.82 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 218932 kb
Host smart-9711a02f-3005-4694-af6c-679683c07810
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=91700371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direc
t.91700371
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.847785104
Short name T563
Test name
Test status
Simulation time 7461810259 ps
CPU time 25.68 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 216144 kb
Host smart-dc9f2a63-d21a-4130-b792-d9b5d7facfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847785104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.847785104
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2231858459
Short name T524
Test name
Test status
Simulation time 1354424229 ps
CPU time 6.32 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 216132 kb
Host smart-d50957a0-e0e8-4f73-89ad-0490c4575dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231858459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2231858459
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3167699195
Short name T607
Test name
Test status
Simulation time 102416857 ps
CPU time 2.25 seconds
Started Apr 16 12:48:11 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 216020 kb
Host smart-43ae585d-e182-4edc-9f7c-cf6899013d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167699195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3167699195
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2060290826
Short name T682
Test name
Test status
Simulation time 1255332976 ps
CPU time 1.05 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 206736 kb
Host smart-85f8cf46-948b-41e8-ab54-28b9391a3d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060290826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2060290826
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3972596421
Short name T597
Test name
Test status
Simulation time 39540168 ps
CPU time 0.7 seconds
Started Apr 16 12:47:49 PM PDT 24
Finished Apr 16 12:47:56 PM PDT 24
Peak memory 205384 kb
Host smart-36d5216b-a054-44d0-b790-7d349a084cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972596421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3972596421
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2020859505
Short name T419
Test name
Test status
Simulation time 30189913 ps
CPU time 0.75 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:48:01 PM PDT 24
Peak memory 206736 kb
Host smart-b41efb9d-34a0-41b0-ae86-7376e6964c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020859505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2020859505
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2647361632
Short name T78
Test name
Test status
Simulation time 5101745510 ps
CPU time 31.4 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:37 PM PDT 24
Peak memory 232672 kb
Host smart-bf5efcb3-6a51-4ec0-b415-5dbc91cb53b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647361632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2647361632
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3718908676
Short name T106
Test name
Test status
Simulation time 112497856657 ps
CPU time 224.32 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:51:41 PM PDT 24
Peak memory 221624 kb
Host smart-fbc9d402-8573-40f0-a181-57e4ceecf039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718908676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3718908676
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3080729408
Short name T675
Test name
Test status
Simulation time 5555434206 ps
CPU time 10.94 seconds
Started Apr 16 12:47:51 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 219540 kb
Host smart-be86f893-3ace-4f0b-8ace-dbae012a4234
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3080729408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3080729408
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1925421631
Short name T612
Test name
Test status
Simulation time 5329308514 ps
CPU time 4.04 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:07 PM PDT 24
Peak memory 216060 kb
Host smart-366a2fd6-8e1f-45c4-a3ca-dddcb2904181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925421631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1925421631
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2946473252
Short name T548
Test name
Test status
Simulation time 25220025 ps
CPU time 1.1 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:03 PM PDT 24
Peak memory 207764 kb
Host smart-7f68f731-fcc5-4aac-b1b8-03283086bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946473252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2946473252
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2590427208
Short name T707
Test name
Test status
Simulation time 63579511 ps
CPU time 0.77 seconds
Started Apr 16 12:48:06 PM PDT 24
Finished Apr 16 12:48:10 PM PDT 24
Peak memory 205608 kb
Host smart-190e9ddb-00d7-47ac-b5ba-bd6c91f0f64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590427208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2590427208
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3109734373
Short name T233
Test name
Test status
Simulation time 1803618392 ps
CPU time 6.83 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 217508 kb
Host smart-7a09c681-bd3b-41a0-b129-2f4e349f2759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109734373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3109734373
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4099897544
Short name T620
Test name
Test status
Simulation time 46617203 ps
CPU time 0.69 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:47:59 PM PDT 24
Peak memory 205660 kb
Host smart-20a68f92-9921-4ae9-8ab9-50b5409c36d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099897544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4099897544
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3940503571
Short name T272
Test name
Test status
Simulation time 636635984 ps
CPU time 3.33 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 232476 kb
Host smart-1c5d140c-4794-41bd-b231-64d4b455720a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940503571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3940503571
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1946644124
Short name T667
Test name
Test status
Simulation time 53338621 ps
CPU time 0.74 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:02 PM PDT 24
Peak memory 205452 kb
Host smart-bf5879e5-e6b2-4569-82ee-7c2efed5ddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946644124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1946644124
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2627086353
Short name T287
Test name
Test status
Simulation time 588016599 ps
CPU time 4.74 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 222888 kb
Host smart-926033b9-d17b-474a-8889-e9395dacd786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627086353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2627086353
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2568857751
Short name T668
Test name
Test status
Simulation time 7337300821 ps
CPU time 16.85 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:18 PM PDT 24
Peak memory 239376 kb
Host smart-4ce2e4b4-66f0-4f1c-8b3f-1391d7eeeb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568857751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2568857751
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.401253520
Short name T168
Test name
Test status
Simulation time 20068218755 ps
CPU time 12.09 seconds
Started Apr 16 12:47:52 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 234716 kb
Host smart-b801b857-fc24-4222-8f40-23e926236bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401253520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.401253520
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.18268896
Short name T549
Test name
Test status
Simulation time 1042127396 ps
CPU time 3.68 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 219980 kb
Host smart-d99fff06-590d-46f1-a2d4-223fbe412027
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=18268896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.18268896
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1040881500
Short name T101
Test name
Test status
Simulation time 1146675345 ps
CPU time 3.28 seconds
Started Apr 16 12:47:48 PM PDT 24
Finished Apr 16 12:47:57 PM PDT 24
Peak memory 216064 kb
Host smart-72e6b7c3-ca78-4a2f-a0a5-a16f8fc0fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040881500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1040881500
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.82712037
Short name T604
Test name
Test status
Simulation time 43505578 ps
CPU time 1.32 seconds
Started Apr 16 12:47:47 PM PDT 24
Finished Apr 16 12:47:53 PM PDT 24
Peak memory 216228 kb
Host smart-d9b550ae-55e8-496a-a878-7a197a8cd98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82712037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.82712037
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3176373315
Short name T717
Test name
Test status
Simulation time 31788009 ps
CPU time 0.71 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 205680 kb
Host smart-313fe53d-3cea-4ac8-9081-0bf5412415e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176373315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3176373315
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3412638864
Short name T644
Test name
Test status
Simulation time 54249570 ps
CPU time 0.66 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 204780 kb
Host smart-f6a37211-7ff6-4248-8629-d339ea899207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412638864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3412638864
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3300682450
Short name T422
Test name
Test status
Simulation time 31118348 ps
CPU time 0.77 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 206472 kb
Host smart-24d925c6-2291-4cf1-96a0-5cc77eed97c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300682450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3300682450
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1048544208
Short name T60
Test name
Test status
Simulation time 154669689 ps
CPU time 2.97 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:07 PM PDT 24
Peak memory 223148 kb
Host smart-a8f2942d-33a0-4521-a54a-a24c4013c9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048544208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1048544208
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3088733461
Short name T559
Test name
Test status
Simulation time 7612993604 ps
CPU time 14.55 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:20 PM PDT 24
Peak memory 220756 kb
Host smart-3a964023-ed99-4be1-9427-80478738d193
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3088733461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3088733461
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1476449191
Short name T504
Test name
Test status
Simulation time 2699480161 ps
CPU time 9.64 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 219900 kb
Host smart-8af171f0-2fad-4144-b78a-426aa2d0c488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476449191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1476449191
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1242435281
Short name T685
Test name
Test status
Simulation time 7375266962 ps
CPU time 7.38 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 216056 kb
Host smart-689cbcab-ff09-4cbf-a237-e4325279b995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242435281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1242435281
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2552307340
Short name T52
Test name
Test status
Simulation time 197573718 ps
CPU time 1.88 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 216168 kb
Host smart-50790e09-24bf-4434-9037-d5cb0183a631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552307340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2552307340
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1661324738
Short name T683
Test name
Test status
Simulation time 374191102 ps
CPU time 1.01 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 206700 kb
Host smart-a8d0bfc1-9c5f-4e0f-aad6-39db141b8bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661324738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1661324738
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1189071865
Short name T351
Test name
Test status
Simulation time 2507860926 ps
CPU time 6.67 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 222816 kb
Host smart-0a583195-6544-4955-ab66-8bdd34115c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189071865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1189071865
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3362469045
Short name T485
Test name
Test status
Simulation time 27649921 ps
CPU time 0.71 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 205356 kb
Host smart-4499ef9d-e6d1-49f4-b8a8-6c6ce6f847d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362469045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3362469045
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1590843879
Short name T410
Test name
Test status
Simulation time 36189198 ps
CPU time 0.83 seconds
Started Apr 16 12:48:03 PM PDT 24
Finished Apr 16 12:48:07 PM PDT 24
Peak memory 206472 kb
Host smart-88076851-0ffc-42be-9573-207da3d73d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590843879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1590843879
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2411640790
Short name T346
Test name
Test status
Simulation time 25145407278 ps
CPU time 98.33 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:49:42 PM PDT 24
Peak memory 249048 kb
Host smart-5d7a9002-f9a3-48eb-b40a-e3ceed198d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411640790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2411640790
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.426714623
Short name T87
Test name
Test status
Simulation time 6677761094 ps
CPU time 15.93 seconds
Started Apr 16 12:47:56 PM PDT 24
Finished Apr 16 12:48:17 PM PDT 24
Peak memory 232760 kb
Host smart-72c185b0-2f49-437c-9683-e42dfddb0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426714623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.426714623
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1475213357
Short name T42
Test name
Test status
Simulation time 15486151793 ps
CPU time 28.27 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:32 PM PDT 24
Peak memory 238976 kb
Host smart-0ade5825-3a84-4307-9c08-189923e01fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475213357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1475213357
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1630508231
Short name T4
Test name
Test status
Simulation time 242276279 ps
CPU time 2.27 seconds
Started Apr 16 12:47:55 PM PDT 24
Finished Apr 16 12:48:03 PM PDT 24
Peak memory 218404 kb
Host smart-c55503c7-f339-46f3-83d8-6a8075473b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630508231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1630508231
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.582316298
Short name T547
Test name
Test status
Simulation time 252150560 ps
CPU time 3.41 seconds
Started Apr 16 12:48:18 PM PDT 24
Finished Apr 16 12:48:23 PM PDT 24
Peak memory 219412 kb
Host smart-b4275ea9-797c-41f3-a5ef-0f24b4391198
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=582316298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.582316298
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2096994871
Short name T634
Test name
Test status
Simulation time 2021119792 ps
CPU time 11.22 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 216220 kb
Host smart-53a2ef9f-17bb-4df0-9be5-eb80131b8954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096994871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2096994871
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3896476066
Short name T541
Test name
Test status
Simulation time 2779744539 ps
CPU time 8.61 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:12 PM PDT 24
Peak memory 216220 kb
Host smart-af38892c-5493-49ab-933f-226899a71d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896476066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3896476066
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2800435382
Short name T643
Test name
Test status
Simulation time 74541850 ps
CPU time 0.96 seconds
Started Apr 16 12:48:09 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 207056 kb
Host smart-363943ee-7578-4e82-9776-b8d7696c96ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800435382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2800435382
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2626881445
Short name T532
Test name
Test status
Simulation time 137532518 ps
CPU time 0.84 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:03 PM PDT 24
Peak memory 205664 kb
Host smart-7089f280-4a30-49b0-98f8-2b9c8efb6934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626881445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2626881445
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.797408527
Short name T218
Test name
Test status
Simulation time 1529518764 ps
CPU time 4.63 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 232588 kb
Host smart-2f58e4e2-4726-4e97-abb4-7db54d3a511e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797408527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.797408527
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.460092518
Short name T471
Test name
Test status
Simulation time 16570764 ps
CPU time 0.74 seconds
Started Apr 16 12:47:50 PM PDT 24
Finished Apr 16 12:48:00 PM PDT 24
Peak memory 205772 kb
Host smart-fd315d90-6b94-4c3e-975e-095316828ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460092518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.460092518
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2206465100
Short name T483
Test name
Test status
Simulation time 55375382 ps
CPU time 0.77 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 206816 kb
Host smart-29f37bd1-524f-4870-9759-2ab63c821a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206465100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2206465100
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3757500332
Short name T164
Test name
Test status
Simulation time 6023551533 ps
CPU time 17.65 seconds
Started Apr 16 12:48:11 PM PDT 24
Finished Apr 16 12:48:30 PM PDT 24
Peak memory 232268 kb
Host smart-4399577b-feb4-483d-9018-ef4b82ebe764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757500332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3757500332
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.824411979
Short name T470
Test name
Test status
Simulation time 317776235 ps
CPU time 5.04 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:10 PM PDT 24
Peak memory 220344 kb
Host smart-67f4889c-a0b3-46ed-9c82-a8129e28e317
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=824411979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.824411979
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.921563354
Short name T487
Test name
Test status
Simulation time 6184129105 ps
CPU time 4.38 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 216312 kb
Host smart-1bffecdd-01ff-495c-a240-ca1897586bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921563354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.921563354
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2279368956
Short name T407
Test name
Test status
Simulation time 2300931509 ps
CPU time 10.94 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:21 PM PDT 24
Peak memory 216072 kb
Host smart-df2512bf-8821-480e-9098-d7763049ae13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279368956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2279368956
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1531293999
Short name T631
Test name
Test status
Simulation time 82029845 ps
CPU time 1.36 seconds
Started Apr 16 12:47:57 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 216148 kb
Host smart-4d778ce0-f1e2-4c85-869e-eac000dc1979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531293999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1531293999
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2414101308
Short name T590
Test name
Test status
Simulation time 121114860 ps
CPU time 0.95 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:21 PM PDT 24
Peak memory 206732 kb
Host smart-4f13e381-44e4-482e-8769-47b37800fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414101308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2414101308
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2972908092
Short name T441
Test name
Test status
Simulation time 14731170 ps
CPU time 0.75 seconds
Started Apr 16 12:48:03 PM PDT 24
Finished Apr 16 12:48:07 PM PDT 24
Peak memory 205376 kb
Host smart-13a7598b-4c4e-466c-9e6f-ac8e268125df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972908092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2972908092
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2702349741
Short name T637
Test name
Test status
Simulation time 40588674 ps
CPU time 0.74 seconds
Started Apr 16 12:48:18 PM PDT 24
Finished Apr 16 12:48:21 PM PDT 24
Peak memory 206460 kb
Host smart-190bc056-6077-4899-83e2-3313bcf6d064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702349741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2702349741
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2503465799
Short name T258
Test name
Test status
Simulation time 4802561891 ps
CPU time 50.38 seconds
Started Apr 16 12:47:59 PM PDT 24
Finished Apr 16 12:48:54 PM PDT 24
Peak memory 217244 kb
Host smart-7dd385c3-2539-4534-b41d-efe53c21b393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503465799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2503465799
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3708953818
Short name T362
Test name
Test status
Simulation time 7427353030 ps
CPU time 13.54 seconds
Started Apr 16 12:48:09 PM PDT 24
Finished Apr 16 12:48:25 PM PDT 24
Peak memory 216776 kb
Host smart-07c3d51c-f4ad-4048-8116-486f063ad16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708953818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3708953818
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2181719973
Short name T501
Test name
Test status
Simulation time 3024535088 ps
CPU time 8.55 seconds
Started Apr 16 12:47:54 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 222968 kb
Host smart-230b9901-e1ea-491e-9f0e-d2af22e6932a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2181719973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2181719973
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2108007487
Short name T390
Test name
Test status
Simulation time 7436285148 ps
CPU time 34.15 seconds
Started Apr 16 12:48:03 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 216404 kb
Host smart-34c0ead9-42b8-4fa9-9411-b82d206ee7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108007487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2108007487
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1574952602
Short name T403
Test name
Test status
Simulation time 1540674963 ps
CPU time 4.28 seconds
Started Apr 16 12:47:55 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 216188 kb
Host smart-dea8d4c5-5e4a-4558-9998-e838b42b766d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574952602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1574952602
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.7123068
Short name T592
Test name
Test status
Simulation time 48742373 ps
CPU time 1.4 seconds
Started Apr 16 12:48:10 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 216164 kb
Host smart-7ce3f4f0-85e8-4cc6-95f0-e37b4f7658a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7123068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.7123068
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2149427771
Short name T598
Test name
Test status
Simulation time 48930500 ps
CPU time 0.91 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 206732 kb
Host smart-be13646b-9607-4181-9c3a-ed91958b1c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149427771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2149427771
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2752111366
Short name T615
Test name
Test status
Simulation time 13211311 ps
CPU time 0.7 seconds
Started Apr 16 12:48:25 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 205344 kb
Host smart-e70b7294-dad3-4ecc-a4ca-23ad15d43625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752111366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2752111366
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2765870764
Short name T293
Test name
Test status
Simulation time 2213692625 ps
CPU time 5.45 seconds
Started Apr 16 12:48:14 PM PDT 24
Finished Apr 16 12:48:20 PM PDT 24
Peak memory 232636 kb
Host smart-8e3c28be-4fa2-43af-88af-96fe156827cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765870764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2765870764
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2972773993
Short name T662
Test name
Test status
Simulation time 82789254 ps
CPU time 0.74 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:06 PM PDT 24
Peak memory 205340 kb
Host smart-aab71ff5-68ef-47a2-8245-3562b9aef782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972773993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2972773993
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3514641154
Short name T331
Test name
Test status
Simulation time 2612413039 ps
CPU time 35.95 seconds
Started Apr 16 12:48:08 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 232624 kb
Host smart-88665f20-edd4-4386-a711-a76be46a3da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514641154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3514641154
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.900951446
Short name T254
Test name
Test status
Simulation time 1711779750 ps
CPU time 6.59 seconds
Started Apr 16 12:48:09 PM PDT 24
Finished Apr 16 12:48:18 PM PDT 24
Peak memory 220112 kb
Host smart-9ffed917-eac6-4f02-ae11-1e567e7bd2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900951446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.900951446
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.718384414
Short name T80
Test name
Test status
Simulation time 7280075694 ps
CPU time 31.04 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 234148 kb
Host smart-29007b41-cdff-4ba4-b4b9-b60ac56d6a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718384414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.718384414
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2206280312
Short name T294
Test name
Test status
Simulation time 1149270570 ps
CPU time 4.49 seconds
Started Apr 16 12:48:03 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 218608 kb
Host smart-77c731b4-1f89-4baa-a6d5-0f06c26d53df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206280312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2206280312
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3573896455
Short name T466
Test name
Test status
Simulation time 334436331 ps
CPU time 3.82 seconds
Started Apr 16 12:48:08 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 222348 kb
Host smart-bf15f22e-106e-4285-8e43-d535b673c261
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3573896455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3573896455
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2036671715
Short name T376
Test name
Test status
Simulation time 1734181249 ps
CPU time 16.31 seconds
Started Apr 16 12:48:09 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 216148 kb
Host smart-b3ba212c-4c56-41dd-917f-f7f46818609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036671715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2036671715
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.990085614
Short name T450
Test name
Test status
Simulation time 5852657041 ps
CPU time 5.62 seconds
Started Apr 16 12:48:15 PM PDT 24
Finished Apr 16 12:48:22 PM PDT 24
Peak memory 216188 kb
Host smart-ea3e60ed-c981-4b46-9931-1fdff34a9839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990085614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.990085614
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2937242586
Short name T542
Test name
Test status
Simulation time 107997818 ps
CPU time 1.68 seconds
Started Apr 16 12:47:58 PM PDT 24
Finished Apr 16 12:48:04 PM PDT 24
Peak memory 216196 kb
Host smart-365350e1-90ea-4304-97e7-e7f520dc54fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937242586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2937242586
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4062789372
Short name T157
Test name
Test status
Simulation time 257078596 ps
CPU time 1.14 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:16 PM PDT 24
Peak memory 206708 kb
Host smart-4962eab5-cc74-453a-96be-273fa9399ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062789372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4062789372
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1069433967
Short name T460
Test name
Test status
Simulation time 18073553 ps
CPU time 0.73 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 205372 kb
Host smart-82c8c62d-1313-4f84-8f35-d86e609de5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069433967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1069433967
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1108285300
Short name T473
Test name
Test status
Simulation time 2389997353 ps
CPU time 6.38 seconds
Started Apr 16 12:48:04 PM PDT 24
Finished Apr 16 12:48:14 PM PDT 24
Peak memory 232236 kb
Host smart-ed400845-32a0-4b36-ba90-f55c1bee2ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108285300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1108285300
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3181399757
Short name T674
Test name
Test status
Simulation time 58198464 ps
CPU time 0.71 seconds
Started Apr 16 12:48:23 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 205412 kb
Host smart-9142c6b1-8a41-4aa0-8257-a7e685385570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181399757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3181399757
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2468704405
Short name T268
Test name
Test status
Simulation time 6892064368 ps
CPU time 48.35 seconds
Started Apr 16 12:48:00 PM PDT 24
Finished Apr 16 12:48:53 PM PDT 24
Peak memory 236848 kb
Host smart-2fdc03b5-538a-45cf-ac82-6a351f757950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468704405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2468704405
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2869578848
Short name T206
Test name
Test status
Simulation time 25839912093 ps
CPU time 12.48 seconds
Started Apr 16 12:48:02 PM PDT 24
Finished Apr 16 12:48:18 PM PDT 24
Peak memory 238720 kb
Host smart-24fcb0f8-aeab-408c-9134-9d14a0b9100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869578848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2869578848
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1854615690
Short name T484
Test name
Test status
Simulation time 2725096183 ps
CPU time 8.41 seconds
Started Apr 16 12:48:04 PM PDT 24
Finished Apr 16 12:48:16 PM PDT 24
Peak memory 222672 kb
Host smart-1dcbf7d8-789f-47cd-a986-76828be335eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1854615690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1854615690
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1642071639
Short name T681
Test name
Test status
Simulation time 3088276978 ps
CPU time 5.1 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:19 PM PDT 24
Peak memory 216272 kb
Host smart-358dc39a-d917-4f56-86f5-afaad536e137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642071639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1642071639
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3427632170
Short name T589
Test name
Test status
Simulation time 4447831691 ps
CPU time 6.44 seconds
Started Apr 16 12:48:09 PM PDT 24
Finished Apr 16 12:48:18 PM PDT 24
Peak memory 216216 kb
Host smart-b1224f7f-789d-4ab3-b637-651080b50445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427632170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3427632170
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.386871176
Short name T688
Test name
Test status
Simulation time 1963808164 ps
CPU time 4.07 seconds
Started Apr 16 12:48:01 PM PDT 24
Finished Apr 16 12:48:10 PM PDT 24
Peak memory 217600 kb
Host smart-188d7af8-a3e2-456b-8de8-7b682dc35efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386871176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.386871176
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.384506375
Short name T690
Test name
Test status
Simulation time 26924714 ps
CPU time 0.78 seconds
Started Apr 16 12:48:23 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 205516 kb
Host smart-761e3f34-65e3-422f-92f0-73414ba87291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384506375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.384506375
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1353385118
Short name T245
Test name
Test status
Simulation time 410144019 ps
CPU time 5.15 seconds
Started Apr 16 12:48:08 PM PDT 24
Finished Apr 16 12:48:16 PM PDT 24
Peak memory 227744 kb
Host smart-9a5db139-f0ef-4b29-8ad7-c10a83578b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353385118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1353385118
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4276390896
Short name T405
Test name
Test status
Simulation time 13434531 ps
CPU time 0.66 seconds
Started Apr 16 12:47:06 PM PDT 24
Finished Apr 16 12:47:09 PM PDT 24
Peak memory 204780 kb
Host smart-0b6188e2-0b21-4233-b87e-f1abab3e9ea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276390896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
276390896
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3455058868
Short name T645
Test name
Test status
Simulation time 18012991 ps
CPU time 0.77 seconds
Started Apr 16 12:46:55 PM PDT 24
Finished Apr 16 12:46:59 PM PDT 24
Peak memory 205492 kb
Host smart-e4aae926-5f91-45a1-a59d-bd312853e46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455058868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3455058868
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.51436674
Short name T357
Test name
Test status
Simulation time 3319151602 ps
CPU time 40.58 seconds
Started Apr 16 12:47:04 PM PDT 24
Finished Apr 16 12:47:47 PM PDT 24
Peak memory 232524 kb
Host smart-053024c0-64e8-450e-bdfa-24a204d22b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51436674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.51436674
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3189403793
Short name T302
Test name
Test status
Simulation time 8334206799 ps
CPU time 81.85 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:48:33 PM PDT 24
Peak memory 231624 kb
Host smart-5b3e7d4e-bf4b-43dd-90aa-7bce39f963c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189403793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3189403793
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3690867628
Short name T462
Test name
Test status
Simulation time 2292455615 ps
CPU time 10.74 seconds
Started Apr 16 12:47:01 PM PDT 24
Finished Apr 16 12:47:15 PM PDT 24
Peak memory 222808 kb
Host smart-19dffb06-2059-4de2-a38c-5dca126454a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3690867628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3690867628
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1447620386
Short name T43
Test name
Test status
Simulation time 152805436 ps
CPU time 1.16 seconds
Started Apr 16 12:47:05 PM PDT 24
Finished Apr 16 12:47:08 PM PDT 24
Peak memory 234876 kb
Host smart-e662d10f-3311-4c0d-a682-89bce9d13017
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447620386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1447620386
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1917307150
Short name T534
Test name
Test status
Simulation time 4088517157 ps
CPU time 20.08 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:30 PM PDT 24
Peak memory 216500 kb
Host smart-e2636c5a-7503-4108-ab02-3e7ea3459655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917307150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1917307150
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.588309777
Short name T573
Test name
Test status
Simulation time 4848191690 ps
CPU time 7.09 seconds
Started Apr 16 12:47:08 PM PDT 24
Finished Apr 16 12:47:17 PM PDT 24
Peak memory 216264 kb
Host smart-5619d5ed-4017-450f-8296-b1182a5e27f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588309777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.588309777
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2254678499
Short name T560
Test name
Test status
Simulation time 86047725 ps
CPU time 0.78 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:11 PM PDT 24
Peak memory 205672 kb
Host smart-e3fda780-1f62-4245-89e4-b765501939a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254678499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2254678499
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2038157581
Short name T521
Test name
Test status
Simulation time 139639843 ps
CPU time 0.75 seconds
Started Apr 16 12:46:59 PM PDT 24
Finished Apr 16 12:47:04 PM PDT 24
Peak memory 205732 kb
Host smart-abaaf935-c66d-4df6-a61a-6f4e79aff256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038157581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2038157581
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1245445865
Short name T564
Test name
Test status
Simulation time 36601876 ps
CPU time 0.71 seconds
Started Apr 16 12:48:12 PM PDT 24
Finished Apr 16 12:48:14 PM PDT 24
Peak memory 205412 kb
Host smart-58f86bfc-4f09-4833-ac52-15136490458f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245445865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1245445865
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2567281487
Short name T452
Test name
Test status
Simulation time 61601825 ps
CPU time 0.78 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:15 PM PDT 24
Peak memory 206472 kb
Host smart-9715319a-920b-48a9-86d0-2f3dec2590e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567281487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2567281487
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2390060154
Short name T76
Test name
Test status
Simulation time 7892687491 ps
CPU time 31.64 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 218116 kb
Host smart-a50b5ba4-680d-4f4f-b480-41e97f13137c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390060154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2390060154
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2621878853
Short name T321
Test name
Test status
Simulation time 20697765053 ps
CPU time 25.67 seconds
Started Apr 16 12:48:10 PM PDT 24
Finished Apr 16 12:48:38 PM PDT 24
Peak memory 219272 kb
Host smart-3b76e0c4-a010-4b3f-af3f-60188be6c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621878853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2621878853
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4176516063
Short name T421
Test name
Test status
Simulation time 886743609 ps
CPU time 11.71 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:22 PM PDT 24
Peak memory 218856 kb
Host smart-86ba411b-0d29-4f49-b6bf-2d4d039935e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176516063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4176516063
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.460047618
Short name T377
Test name
Test status
Simulation time 12632392386 ps
CPU time 57.56 seconds
Started Apr 16 12:48:16 PM PDT 24
Finished Apr 16 12:49:15 PM PDT 24
Peak memory 216252 kb
Host smart-616a5cad-b3d0-4f50-9b16-4928de39dbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460047618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.460047618
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2833060489
Short name T502
Test name
Test status
Simulation time 7510384640 ps
CPU time 13.66 seconds
Started Apr 16 12:48:13 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 216184 kb
Host smart-e531ac46-632e-49cf-a3a3-4e6f76ea37df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833060489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2833060489
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.702005921
Short name T520
Test name
Test status
Simulation time 163905011 ps
CPU time 2.19 seconds
Started Apr 16 12:48:04 PM PDT 24
Finished Apr 16 12:48:14 PM PDT 24
Peak memory 216216 kb
Host smart-971af372-c94b-429c-8171-0080788aee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702005921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.702005921
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1326604198
Short name T493
Test name
Test status
Simulation time 303586412 ps
CPU time 1 seconds
Started Apr 16 12:48:19 PM PDT 24
Finished Apr 16 12:48:22 PM PDT 24
Peak memory 206688 kb
Host smart-283374b7-4f11-4b06-b8c4-da325c60a9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326604198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1326604198
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.149061944
Short name T252
Test name
Test status
Simulation time 5973440862 ps
CPU time 20.01 seconds
Started Apr 16 12:48:24 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 233232 kb
Host smart-2b4cf4a8-10da-4b9e-9883-ee1d9ad32060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149061944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.149061944
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1880743376
Short name T457
Test name
Test status
Simulation time 12850232 ps
CPU time 0.68 seconds
Started Apr 16 12:48:09 PM PDT 24
Finished Apr 16 12:48:12 PM PDT 24
Peak memory 205340 kb
Host smart-e10c378b-5174-421a-b617-d8d655603f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880743376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1880743376
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.412955402
Short name T22
Test name
Test status
Simulation time 10002752583 ps
CPU time 13.46 seconds
Started Apr 16 12:48:26 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 218328 kb
Host smart-7aa86d89-36a1-4ffd-8c61-4b5051ce66da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412955402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.412955402
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1650893977
Short name T18
Test name
Test status
Simulation time 24071954 ps
CPU time 0.74 seconds
Started Apr 16 12:48:05 PM PDT 24
Finished Apr 16 12:48:09 PM PDT 24
Peak memory 206492 kb
Host smart-e46c3e29-8b08-4c50-8879-02864096afaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650893977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1650893977
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3580500354
Short name T704
Test name
Test status
Simulation time 19154546013 ps
CPU time 68.46 seconds
Started Apr 16 12:48:26 PM PDT 24
Finished Apr 16 12:49:36 PM PDT 24
Peak memory 249112 kb
Host smart-865ab948-5a5e-4bec-a4ba-6d137eb6174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580500354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3580500354
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.245319937
Short name T212
Test name
Test status
Simulation time 7443636737 ps
CPU time 5.79 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:16 PM PDT 24
Peak memory 216888 kb
Host smart-ce4b5354-ba38-44af-84e2-30aa40892d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245319937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.245319937
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.332465692
Short name T587
Test name
Test status
Simulation time 646497561 ps
CPU time 8.13 seconds
Started Apr 16 12:48:32 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 218756 kb
Host smart-73d713a0-5b9c-4160-81a0-c89d11e4f89e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332465692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.332465692
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3025314769
Short name T19
Test name
Test status
Simulation time 8496092160 ps
CPU time 47.25 seconds
Started Apr 16 12:48:05 PM PDT 24
Finished Apr 16 12:48:56 PM PDT 24
Peak memory 216076 kb
Host smart-615a256e-97b7-4258-bbce-e9d39210b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025314769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3025314769
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1295035780
Short name T575
Test name
Test status
Simulation time 1403987041 ps
CPU time 7.54 seconds
Started Apr 16 12:48:12 PM PDT 24
Finished Apr 16 12:48:21 PM PDT 24
Peak memory 216140 kb
Host smart-33b009aa-7485-45af-b9b3-6781420b7352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295035780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1295035780
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1029955478
Short name T679
Test name
Test status
Simulation time 702126572 ps
CPU time 1.73 seconds
Started Apr 16 12:48:19 PM PDT 24
Finished Apr 16 12:48:23 PM PDT 24
Peak memory 216016 kb
Host smart-ae1b1569-0701-4e26-8055-8fe3dd8d0202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029955478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1029955478
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2490431073
Short name T100
Test name
Test status
Simulation time 140769102 ps
CPU time 1.05 seconds
Started Apr 16 12:48:15 PM PDT 24
Finished Apr 16 12:48:17 PM PDT 24
Peak memory 205704 kb
Host smart-ecce832b-e950-4a39-ac6a-adf73150bea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490431073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2490431073
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4213078304
Short name T201
Test name
Test status
Simulation time 56971784 ps
CPU time 2.21 seconds
Started Apr 16 12:48:19 PM PDT 24
Finished Apr 16 12:48:23 PM PDT 24
Peak memory 218904 kb
Host smart-6bbc3d2d-b190-4c1c-8f11-27a1f8814fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213078304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4213078304
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1028353837
Short name T409
Test name
Test status
Simulation time 15869540 ps
CPU time 0.75 seconds
Started Apr 16 12:48:30 PM PDT 24
Finished Apr 16 12:48:32 PM PDT 24
Peak memory 204824 kb
Host smart-35337850-5e31-46bf-b6ce-6fa1480879f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028353837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1028353837
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1523120695
Short name T567
Test name
Test status
Simulation time 29678093 ps
CPU time 0.75 seconds
Started Apr 16 12:48:07 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 206496 kb
Host smart-af01a0e3-c285-47be-9fea-2763f7ababfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523120695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1523120695
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1784653936
Short name T334
Test name
Test status
Simulation time 7669186695 ps
CPU time 96.25 seconds
Started Apr 16 12:48:19 PM PDT 24
Finished Apr 16 12:49:57 PM PDT 24
Peak memory 249344 kb
Host smart-726d5386-be91-4d56-9789-21becec9ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784653936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1784653936
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1941063717
Short name T226
Test name
Test status
Simulation time 7117678465 ps
CPU time 40.03 seconds
Started Apr 16 12:48:19 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 232912 kb
Host smart-8edaedd9-e4a9-4051-950a-c78763254807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941063717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1941063717
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.202345817
Short name T68
Test name
Test status
Simulation time 55470958104 ps
CPU time 22.61 seconds
Started Apr 16 12:48:20 PM PDT 24
Finished Apr 16 12:48:45 PM PDT 24
Peak memory 232544 kb
Host smart-795b4222-8ddd-4ca7-a3c5-a9e1ef81f053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202345817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.202345817
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3727414327
Short name T647
Test name
Test status
Simulation time 8004395787 ps
CPU time 6.42 seconds
Started Apr 16 12:48:36 PM PDT 24
Finished Apr 16 12:48:43 PM PDT 24
Peak memory 219104 kb
Host smart-abff471a-7cf1-464b-8bad-d1ac24f0cd3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3727414327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3727414327
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4170477668
Short name T602
Test name
Test status
Simulation time 41413359 ps
CPU time 0.88 seconds
Started Apr 16 12:48:20 PM PDT 24
Finished Apr 16 12:48:23 PM PDT 24
Peak memory 206812 kb
Host smart-9fae45a5-8b4b-415c-af8f-3c88d5b259fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170477668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4170477668
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2124253387
Short name T97
Test name
Test status
Simulation time 4996355639 ps
CPU time 20.73 seconds
Started Apr 16 12:48:20 PM PDT 24
Finished Apr 16 12:48:42 PM PDT 24
Peak memory 216296 kb
Host smart-8b896027-96a9-4e7b-a783-6b8c798cc8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124253387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2124253387
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1091231168
Short name T677
Test name
Test status
Simulation time 9265320526 ps
CPU time 26.73 seconds
Started Apr 16 12:48:18 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 216208 kb
Host smart-7efc4e86-a379-4843-b433-cf7fb7bb5b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091231168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1091231168
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1516000444
Short name T392
Test name
Test status
Simulation time 331085197 ps
CPU time 1.36 seconds
Started Apr 16 12:48:24 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 216244 kb
Host smart-601c54aa-e709-4d9e-90cb-0537fa3cce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516000444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1516000444
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2995981637
Short name T522
Test name
Test status
Simulation time 73542286 ps
CPU time 0.78 seconds
Started Apr 16 12:48:26 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 205664 kb
Host smart-250da7bf-c6df-4792-8ec4-037356395c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995981637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2995981637
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3190161956
Short name T192
Test name
Test status
Simulation time 5762637090 ps
CPU time 11.75 seconds
Started Apr 16 12:48:16 PM PDT 24
Finished Apr 16 12:48:29 PM PDT 24
Peak memory 216788 kb
Host smart-a3df7a76-2ef7-4e51-bb39-4d66b460cab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190161956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3190161956
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3699802330
Short name T507
Test name
Test status
Simulation time 13310443 ps
CPU time 0.72 seconds
Started Apr 16 12:48:22 PM PDT 24
Finished Apr 16 12:48:25 PM PDT 24
Peak memory 205348 kb
Host smart-e567bef4-bf34-4354-9468-da34ccb687f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699802330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3699802330
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1602118378
Short name T475
Test name
Test status
Simulation time 26151982 ps
CPU time 0.78 seconds
Started Apr 16 12:48:17 PM PDT 24
Finished Apr 16 12:48:19 PM PDT 24
Peak memory 206788 kb
Host smart-8c330140-43d3-4315-b42a-6b76dbf32fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602118378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1602118378
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1587042448
Short name T158
Test name
Test status
Simulation time 137476301 ps
CPU time 5.12 seconds
Started Apr 16 12:48:37 PM PDT 24
Finished Apr 16 12:48:44 PM PDT 24
Peak memory 223488 kb
Host smart-5d1d07ed-856c-4c16-b298-1a308c9fc196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587042448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1587042448
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.409528283
Short name T701
Test name
Test status
Simulation time 1224566662 ps
CPU time 5.52 seconds
Started Apr 16 12:48:27 PM PDT 24
Finished Apr 16 12:48:34 PM PDT 24
Peak memory 218460 kb
Host smart-8942a9d6-e9b7-4594-8c0b-71284936efc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409528283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.409528283
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1161437007
Short name T451
Test name
Test status
Simulation time 2695269700 ps
CPU time 12.67 seconds
Started Apr 16 12:48:17 PM PDT 24
Finished Apr 16 12:48:31 PM PDT 24
Peak memory 221416 kb
Host smart-b49dd612-3e08-4eb7-bcee-b581fd46d695
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1161437007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1161437007
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2196196200
Short name T397
Test name
Test status
Simulation time 18645333133 ps
CPU time 28.09 seconds
Started Apr 16 12:48:17 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 216204 kb
Host smart-d9b87f27-18f8-4676-a822-93e16090aba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196196200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2196196200
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1575923805
Short name T482
Test name
Test status
Simulation time 3871034768 ps
CPU time 11.64 seconds
Started Apr 16 12:48:21 PM PDT 24
Finished Apr 16 12:48:35 PM PDT 24
Peak memory 216180 kb
Host smart-26d5b26f-8731-4029-b8fd-e3ad7f3c7de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575923805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1575923805
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.402972866
Short name T540
Test name
Test status
Simulation time 35977874 ps
CPU time 0.92 seconds
Started Apr 16 12:48:33 PM PDT 24
Finished Apr 16 12:48:35 PM PDT 24
Peak memory 206744 kb
Host smart-8c207284-47eb-405e-8998-ad28bd9bf632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402972866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.402972866
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.209239315
Short name T505
Test name
Test status
Simulation time 34857019 ps
CPU time 0.84 seconds
Started Apr 16 12:48:26 PM PDT 24
Finished Apr 16 12:48:28 PM PDT 24
Peak memory 205672 kb
Host smart-d000ca19-7f8a-46f2-bd62-b40245195868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209239315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.209239315
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2684019019
Short name T526
Test name
Test status
Simulation time 39453514 ps
CPU time 0.7 seconds
Started Apr 16 12:48:31 PM PDT 24
Finished Apr 16 12:48:33 PM PDT 24
Peak memory 205584 kb
Host smart-1fb75ac0-2371-453f-a0e7-3e7c294ee0d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684019019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2684019019
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.120857326
Short name T706
Test name
Test status
Simulation time 100667053 ps
CPU time 2.66 seconds
Started Apr 16 12:48:28 PM PDT 24
Finished Apr 16 12:48:32 PM PDT 24
Peak memory 223004 kb
Host smart-9fc14148-1646-4ca3-8c84-607400192ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120857326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.120857326
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1075398899
Short name T481
Test name
Test status
Simulation time 55528635 ps
CPU time 0.81 seconds
Started Apr 16 12:48:23 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 206516 kb
Host smart-7ea9d48d-cff6-41cc-b631-85b1a3c2248e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075398899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1075398899
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.545631565
Short name T461
Test name
Test status
Simulation time 9518603352 ps
CPU time 35.27 seconds
Started Apr 16 12:48:39 PM PDT 24
Finished Apr 16 12:49:16 PM PDT 24
Peak memory 232464 kb
Host smart-628a36f6-8c94-4a83-9ee9-078347f98b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545631565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.545631565
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2932656454
Short name T415
Test name
Test status
Simulation time 7245751721 ps
CPU time 16.53 seconds
Started Apr 16 12:48:34 PM PDT 24
Finished Apr 16 12:48:52 PM PDT 24
Peak memory 233964 kb
Host smart-da56cf56-d9a9-42c0-8ac1-fe8b794694b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932656454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2932656454
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.154150000
Short name T217
Test name
Test status
Simulation time 2935938857 ps
CPU time 10.9 seconds
Started Apr 16 12:48:24 PM PDT 24
Finished Apr 16 12:48:38 PM PDT 24
Peak memory 222976 kb
Host smart-2eb4ca51-71cc-4c7c-869f-947af314ae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154150000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.154150000
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.745633215
Short name T142
Test name
Test status
Simulation time 853215142 ps
CPU time 4.27 seconds
Started Apr 16 12:48:34 PM PDT 24
Finished Apr 16 12:48:40 PM PDT 24
Peak memory 222844 kb
Host smart-2642841b-a79e-4362-b080-df15d4be70ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=745633215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.745633215
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.321419804
Short name T151
Test name
Test status
Simulation time 77007757 ps
CPU time 1.19 seconds
Started Apr 16 12:48:23 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 207168 kb
Host smart-dfb874b0-1ac2-46f3-aa79-879cdb534f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321419804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.321419804
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3913083421
Short name T385
Test name
Test status
Simulation time 30579298854 ps
CPU time 48.19 seconds
Started Apr 16 12:48:20 PM PDT 24
Finished Apr 16 12:49:11 PM PDT 24
Peak memory 216200 kb
Host smart-c7098ddc-2e5e-450f-a732-3f5a9ed58222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913083421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3913083421
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2889680246
Short name T622
Test name
Test status
Simulation time 4791071040 ps
CPU time 17.43 seconds
Started Apr 16 12:48:32 PM PDT 24
Finished Apr 16 12:48:51 PM PDT 24
Peak memory 216216 kb
Host smart-e60b79ec-290a-4c51-9e0c-912df8702d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889680246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2889680246
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2622516197
Short name T497
Test name
Test status
Simulation time 74287214 ps
CPU time 1.07 seconds
Started Apr 16 12:48:27 PM PDT 24
Finished Apr 16 12:48:30 PM PDT 24
Peak memory 207812 kb
Host smart-1ce52991-cda6-436d-a9ee-9a22a801fec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622516197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2622516197
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2063824356
Short name T632
Test name
Test status
Simulation time 139614573 ps
CPU time 0.93 seconds
Started Apr 16 12:48:22 PM PDT 24
Finished Apr 16 12:48:26 PM PDT 24
Peak memory 206652 kb
Host smart-e482c501-e7a6-45e4-8581-14589d9d546c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063824356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2063824356
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4272918969
Short name T165
Test name
Test status
Simulation time 725684612 ps
CPU time 7.11 seconds
Started Apr 16 12:48:28 PM PDT 24
Finished Apr 16 12:48:36 PM PDT 24
Peak memory 223776 kb
Host smart-8d549ba1-402d-477f-b3b5-c2c0c678d236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272918969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4272918969
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.764709117
Short name T434
Test name
Test status
Simulation time 28202383 ps
CPU time 0.73 seconds
Started Apr 16 12:48:36 PM PDT 24
Finished Apr 16 12:48:37 PM PDT 24
Peak memory 204720 kb
Host smart-6110b953-1d65-4d0c-b009-60139c345ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764709117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.764709117
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1734486028
Short name T553
Test name
Test status
Simulation time 21185298 ps
CPU time 0.76 seconds
Started Apr 16 12:48:35 PM PDT 24
Finished Apr 16 12:48:37 PM PDT 24
Peak memory 206512 kb
Host smart-9c5ad798-22a3-441c-a70d-52298e824813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734486028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1734486028
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3700552073
Short name T330
Test name
Test status
Simulation time 310885432 ps
CPU time 8.79 seconds
Started Apr 16 12:48:30 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 232564 kb
Host smart-1e187de8-7f7f-4491-b8c2-49b2d5f1899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700552073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3700552073
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3978064333
Short name T199
Test name
Test status
Simulation time 453680808 ps
CPU time 4.91 seconds
Started Apr 16 12:48:28 PM PDT 24
Finished Apr 16 12:48:34 PM PDT 24
Peak memory 218168 kb
Host smart-c0599535-77c8-4b8e-885c-799cc0f5d808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978064333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3978064333
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.588417553
Short name T263
Test name
Test status
Simulation time 2305708095 ps
CPU time 6.87 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:50 PM PDT 24
Peak memory 221464 kb
Host smart-11c32ae8-5c57-4f2d-a2fa-7c56826a7929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588417553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.588417553
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4266573798
Short name T459
Test name
Test status
Simulation time 557354002 ps
CPU time 9.36 seconds
Started Apr 16 12:48:36 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 219196 kb
Host smart-d89b0ccb-dce2-49db-b28e-614b7c0b268c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4266573798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4266573798
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2782072263
Short name T605
Test name
Test status
Simulation time 157721834 ps
CPU time 0.91 seconds
Started Apr 16 12:48:33 PM PDT 24
Finished Apr 16 12:48:35 PM PDT 24
Peak memory 206864 kb
Host smart-cd9af78b-ec52-475a-a4ba-cf13b317392c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782072263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2782072263
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.835089767
Short name T375
Test name
Test status
Simulation time 4845072097 ps
CPU time 15.49 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:49:59 PM PDT 24
Peak memory 218160 kb
Host smart-6a84008f-4fc3-479a-bd94-fe139bd7041b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835089767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.835089767
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2799885357
Short name T408
Test name
Test status
Simulation time 1578701425 ps
CPU time 6.41 seconds
Started Apr 16 12:48:31 PM PDT 24
Finished Apr 16 12:48:39 PM PDT 24
Peak memory 216168 kb
Host smart-ac00b28d-c7df-4e0c-9d50-0f581ff80b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799885357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2799885357
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2796080020
Short name T46
Test name
Test status
Simulation time 187754882 ps
CPU time 1.45 seconds
Started Apr 16 12:48:31 PM PDT 24
Finished Apr 16 12:48:34 PM PDT 24
Peak memory 216140 kb
Host smart-3fb4f1b5-6566-4dd4-88f7-ac2dea26c5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796080020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2796080020
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2725188330
Short name T420
Test name
Test status
Simulation time 63832910 ps
CPU time 0.86 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:43 PM PDT 24
Peak memory 205700 kb
Host smart-a58c397f-2b38-472c-a859-07fec2489caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725188330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2725188330
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3630247145
Short name T231
Test name
Test status
Simulation time 1872727251 ps
CPU time 4.42 seconds
Started Apr 16 12:48:41 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 222888 kb
Host smart-69579744-b5f5-4497-a579-5efa547cb883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630247145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3630247145
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.868213453
Short name T611
Test name
Test status
Simulation time 22529393 ps
CPU time 0.7 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:44 PM PDT 24
Peak memory 204820 kb
Host smart-8d3849ca-0077-4a2f-889b-7ff203e0b431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868213453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.868213453
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3975672108
Short name T715
Test name
Test status
Simulation time 468633772 ps
CPU time 6.81 seconds
Started Apr 16 12:48:24 PM PDT 24
Finished Apr 16 12:48:34 PM PDT 24
Peak memory 218700 kb
Host smart-73e9c591-583d-4626-aaab-055058864fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975672108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3975672108
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.417920709
Short name T426
Test name
Test status
Simulation time 28287472 ps
CPU time 0.74 seconds
Started Apr 16 12:48:35 PM PDT 24
Finished Apr 16 12:48:37 PM PDT 24
Peak memory 205808 kb
Host smart-e22eaa2a-0923-4c54-bcd3-627ef68705c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417920709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.417920709
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1512941139
Short name T232
Test name
Test status
Simulation time 1964834407 ps
CPU time 18.61 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 216580 kb
Host smart-be7dcc54-fa24-435b-9235-0e10288f9755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512941139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1512941139
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2204748147
Short name T240
Test name
Test status
Simulation time 2411705567 ps
CPU time 15.44 seconds
Started Apr 16 12:48:29 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 218368 kb
Host smart-5b291ed1-0ab8-4029-862b-751b01dc7465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204748147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2204748147
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1111403300
Short name T328
Test name
Test status
Simulation time 18897934147 ps
CPU time 18.36 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 224040 kb
Host smart-2ceddaa3-e0c3-4abf-b85a-131ed3209743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111403300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1111403300
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.576392104
Short name T143
Test name
Test status
Simulation time 772891926 ps
CPU time 5.47 seconds
Started Apr 16 12:48:28 PM PDT 24
Finished Apr 16 12:48:35 PM PDT 24
Peak memory 221916 kb
Host smart-5bd31dcf-a5e5-4aa1-85dd-b5df886cdd2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=576392104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.576392104
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.804263371
Short name T413
Test name
Test status
Simulation time 4298635911 ps
CPU time 6.89 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:49:50 PM PDT 24
Peak memory 215784 kb
Host smart-72d39a8a-743a-46e2-8ce5-55dd56b4ae08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804263371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.804263371
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1513244129
Short name T57
Test name
Test status
Simulation time 17942392 ps
CPU time 0.81 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:44 PM PDT 24
Peak memory 205672 kb
Host smart-3d792bbf-8b57-4288-8b6c-d518473c42a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513244129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1513244129
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.97112808
Short name T654
Test name
Test status
Simulation time 114684260 ps
CPU time 0.88 seconds
Started Apr 16 12:48:34 PM PDT 24
Finished Apr 16 12:48:36 PM PDT 24
Peak memory 205688 kb
Host smart-b03b5ca3-8c9b-4ddb-907c-86af9b206ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97112808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.97112808
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2471155038
Short name T440
Test name
Test status
Simulation time 49418091 ps
CPU time 0.73 seconds
Started Apr 16 12:49:42 PM PDT 24
Finished Apr 16 12:49:44 PM PDT 24
Peak memory 204896 kb
Host smart-5d657f15-4653-44fd-acba-af09e83f4d10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471155038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2471155038
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.652709586
Short name T503
Test name
Test status
Simulation time 56703683 ps
CPU time 0.79 seconds
Started Apr 16 12:48:39 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 205492 kb
Host smart-753c07f9-1a20-4b95-aa8a-ef749f921f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652709586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.652709586
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_intercept.782788131
Short name T278
Test name
Test status
Simulation time 228764641 ps
CPU time 5.56 seconds
Started Apr 16 12:48:36 PM PDT 24
Finished Apr 16 12:48:42 PM PDT 24
Peak memory 232548 kb
Host smart-2b5eb399-c2f5-461d-a1c8-759d68bce47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782788131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.782788131
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3010269311
Short name T195
Test name
Test status
Simulation time 13883430837 ps
CPU time 23.14 seconds
Started Apr 16 12:48:39 PM PDT 24
Finished Apr 16 12:49:03 PM PDT 24
Peak memory 218716 kb
Host smart-99303d4f-ae14-4479-9394-4284efaaa377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010269311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3010269311
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.82129765
Short name T194
Test name
Test status
Simulation time 68621035 ps
CPU time 2.72 seconds
Started Apr 16 12:48:34 PM PDT 24
Finished Apr 16 12:48:38 PM PDT 24
Peak memory 220012 kb
Host smart-5bd1bdec-4d52-403d-bf91-5d1ec6e844b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82129765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.82129765
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3571421988
Short name T494
Test name
Test status
Simulation time 770081713 ps
CPU time 3.86 seconds
Started Apr 16 12:48:33 PM PDT 24
Finished Apr 16 12:48:38 PM PDT 24
Peak memory 219960 kb
Host smart-040699cc-d77e-497e-8a25-c3027aef243f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3571421988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3571421988
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2452710232
Short name T387
Test name
Test status
Simulation time 2872489527 ps
CPU time 11.49 seconds
Started Apr 16 12:48:32 PM PDT 24
Finished Apr 16 12:48:44 PM PDT 24
Peak memory 216280 kb
Host smart-007d6a8a-dec4-4976-a4da-0c3aad2b283f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452710232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2452710232
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2850736382
Short name T578
Test name
Test status
Simulation time 18761614832 ps
CPU time 26.93 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:49:12 PM PDT 24
Peak memory 216208 kb
Host smart-507cabd8-237e-4964-b4b2-58fd4df2fa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850736382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2850736382
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3504835666
Short name T401
Test name
Test status
Simulation time 66935001 ps
CPU time 1.06 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:43 PM PDT 24
Peak memory 207604 kb
Host smart-6ef87d43-8099-4b80-9c57-2e7575315558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504835666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3504835666
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.301814612
Short name T640
Test name
Test status
Simulation time 112586774 ps
CPU time 0.98 seconds
Started Apr 16 12:48:33 PM PDT 24
Finished Apr 16 12:48:36 PM PDT 24
Peak memory 206696 kb
Host smart-ab3a4cb2-4cf5-47e4-b226-a82258c79cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301814612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.301814612
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2871962303
Short name T546
Test name
Test status
Simulation time 24347106 ps
CPU time 0.68 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 204780 kb
Host smart-d7b6e2a0-be9d-44f0-a4f8-73520d4806b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871962303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2871962303
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3477978618
Short name T155
Test name
Test status
Simulation time 15023028 ps
CPU time 0.77 seconds
Started Apr 16 12:48:35 PM PDT 24
Finished Apr 16 12:48:37 PM PDT 24
Peak memory 206508 kb
Host smart-e401bc91-1573-45fd-a64f-024c289b2a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477978618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3477978618
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3845350469
Short name T342
Test name
Test status
Simulation time 1395346058 ps
CPU time 14.14 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:57 PM PDT 24
Peak memory 240612 kb
Host smart-c99fccff-0970-4bcb-85ef-b44f90e574cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845350469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3845350469
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2385097522
Short name T271
Test name
Test status
Simulation time 77319468974 ps
CPU time 181.18 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:51:48 PM PDT 24
Peak memory 232068 kb
Host smart-bc891c5d-5b85-47d6-8d39-052155cee952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385097522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2385097522
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3218489310
Short name T182
Test name
Test status
Simulation time 5910154729 ps
CPU time 14.94 seconds
Started Apr 16 12:48:33 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 223616 kb
Host smart-0f07fdc3-cc33-4cf1-acb7-340248b624ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218489310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3218489310
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.274770189
Short name T311
Test name
Test status
Simulation time 1077547220 ps
CPU time 9.67 seconds
Started Apr 16 12:48:37 PM PDT 24
Finished Apr 16 12:48:48 PM PDT 24
Peak memory 230448 kb
Host smart-5b4f73d8-1dd0-4d7f-9ea8-7e35d11b2e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274770189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.274770189
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.832660424
Short name T511
Test name
Test status
Simulation time 1122375860 ps
CPU time 12.89 seconds
Started Apr 16 12:48:35 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 222244 kb
Host smart-d077f1b5-49c1-4aa1-ae22-76de9a72d034
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=832660424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.832660424
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3763094418
Short name T621
Test name
Test status
Simulation time 6174714874 ps
CPU time 8.85 seconds
Started Apr 16 12:48:31 PM PDT 24
Finished Apr 16 12:48:41 PM PDT 24
Peak memory 216188 kb
Host smart-8e5209b6-02a5-46bf-a0f8-6aa78e1b500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763094418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3763094418
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3672444642
Short name T13
Test name
Test status
Simulation time 1170638956 ps
CPU time 8.61 seconds
Started Apr 16 12:48:41 PM PDT 24
Finished Apr 16 12:48:52 PM PDT 24
Peak memory 216188 kb
Host smart-786210bc-c9b0-4804-9fcd-268a9f00e5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672444642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3672444642
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2060478990
Short name T650
Test name
Test status
Simulation time 190074130 ps
CPU time 2.22 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:48 PM PDT 24
Peak memory 216356 kb
Host smart-06ddb94a-326a-410e-80cb-0d27746dbf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060478990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2060478990
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2397503372
Short name T514
Test name
Test status
Simulation time 77406643 ps
CPU time 0.82 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 206728 kb
Host smart-24570968-317b-411e-a7d6-0fa10bee1937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397503372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2397503372
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2056322779
Short name T188
Test name
Test status
Simulation time 21551314277 ps
CPU time 18.63 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:49:06 PM PDT 24
Peak memory 224212 kb
Host smart-0d74f58f-fa9d-422b-ac44-a67eba1e51ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056322779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2056322779
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4275004826
Short name T586
Test name
Test status
Simulation time 13166022 ps
CPU time 0.71 seconds
Started Apr 16 12:48:41 PM PDT 24
Finished Apr 16 12:48:45 PM PDT 24
Peak memory 205348 kb
Host smart-845de431-ed2f-48e3-8da5-a391fc45b207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275004826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4275004826
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1824353824
Short name T676
Test name
Test status
Simulation time 118267221 ps
CPU time 0.74 seconds
Started Apr 16 12:48:37 PM PDT 24
Finished Apr 16 12:48:39 PM PDT 24
Peak memory 206476 kb
Host smart-02c4d806-fdbb-4bf0-8b97-006bb8f8a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824353824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1824353824
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.815883775
Short name T703
Test name
Test status
Simulation time 1169427053 ps
CPU time 8.89 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:56 PM PDT 24
Peak memory 224360 kb
Host smart-9049f05c-096a-4a8d-84fe-e116c3a11d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815883775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.815883775
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1020623717
Short name T107
Test name
Test status
Simulation time 8245290606 ps
CPU time 32.45 seconds
Started Apr 16 12:48:46 PM PDT 24
Finished Apr 16 12:49:21 PM PDT 24
Peak memory 216696 kb
Host smart-710ba8f7-7b2e-4b19-82a2-dc4c84db059e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020623717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1020623717
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3587794362
Short name T3
Test name
Test status
Simulation time 7351078473 ps
CPU time 69.55 seconds
Started Apr 16 12:48:38 PM PDT 24
Finished Apr 16 12:49:49 PM PDT 24
Peak memory 223604 kb
Host smart-4c593895-d0fa-4f1d-8ae8-84dc72d6268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587794362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3587794362
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1888958612
Short name T49
Test name
Test status
Simulation time 792230213 ps
CPU time 12.09 seconds
Started Apr 16 12:48:45 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 218940 kb
Host smart-d571b5cd-1ae4-4796-b5bc-6073928f9daf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1888958612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1888958612
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3898740803
Short name T423
Test name
Test status
Simulation time 3179742741 ps
CPU time 4.4 seconds
Started Apr 16 12:48:46 PM PDT 24
Finished Apr 16 12:48:53 PM PDT 24
Peak memory 216184 kb
Host smart-70fba562-943b-46e8-abdc-8d4cc48e9d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898740803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3898740803
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.298017039
Short name T579
Test name
Test status
Simulation time 409654204 ps
CPU time 1.69 seconds
Started Apr 16 12:48:41 PM PDT 24
Finished Apr 16 12:48:45 PM PDT 24
Peak memory 216148 kb
Host smart-df82a21a-4184-4f8f-903d-2c637f8d34ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298017039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.298017039
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.470036845
Short name T444
Test name
Test status
Simulation time 182244808 ps
CPU time 0.77 seconds
Started Apr 16 12:48:45 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 205712 kb
Host smart-79ffb2a3-1574-41f8-bb7f-5205bf60e038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470036845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.470036845
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1719159206
Short name T187
Test name
Test status
Simulation time 26174785389 ps
CPU time 36.54 seconds
Started Apr 16 12:48:45 PM PDT 24
Finished Apr 16 12:49:25 PM PDT 24
Peak memory 222616 kb
Host smart-e18ce299-9378-48ca-a9cd-3ea6acdf0398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719159206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1719159206
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2665788386
Short name T25
Test name
Test status
Simulation time 52309259 ps
CPU time 0.72 seconds
Started Apr 16 12:47:19 PM PDT 24
Finished Apr 16 12:47:22 PM PDT 24
Peak memory 205652 kb
Host smart-f5ff0030-0f17-4711-9d5a-82c15bf11ebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665788386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
665788386
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4052079430
Short name T648
Test name
Test status
Simulation time 17686003377 ps
CPU time 13.9 seconds
Started Apr 16 12:47:05 PM PDT 24
Finished Apr 16 12:47:21 PM PDT 24
Peak memory 232240 kb
Host smart-24bb597c-dd83-4939-8129-adc1413d5c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052079430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4052079430
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3479283123
Short name T429
Test name
Test status
Simulation time 64134460 ps
CPU time 0.74 seconds
Started Apr 16 12:47:08 PM PDT 24
Finished Apr 16 12:47:11 PM PDT 24
Peak memory 206476 kb
Host smart-9423233f-45c4-42b7-ae83-053ba9a97a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479283123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3479283123
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2589353403
Short name T88
Test name
Test status
Simulation time 224370056 ps
CPU time 3.79 seconds
Started Apr 16 12:47:07 PM PDT 24
Finished Apr 16 12:47:13 PM PDT 24
Peak memory 223036 kb
Host smart-d65ec425-d72e-45f8-8ca7-2591da75b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589353403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2589353403
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2100033441
Short name T197
Test name
Test status
Simulation time 3919061424 ps
CPU time 12.89 seconds
Started Apr 16 12:47:08 PM PDT 24
Finished Apr 16 12:47:24 PM PDT 24
Peak memory 220500 kb
Host smart-7dd2207b-1931-4e51-8a69-597a0c5b2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100033441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2100033441
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1467931456
Short name T719
Test name
Test status
Simulation time 292696535 ps
CPU time 5.19 seconds
Started Apr 16 12:47:02 PM PDT 24
Finished Apr 16 12:47:10 PM PDT 24
Peak memory 221564 kb
Host smart-e6976de6-d5df-4c88-9fe8-94641eadcec3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1467931456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1467931456
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3534521935
Short name T30
Test name
Test status
Simulation time 211249661 ps
CPU time 1.21 seconds
Started Apr 16 12:47:19 PM PDT 24
Finished Apr 16 12:47:22 PM PDT 24
Peak memory 234860 kb
Host smart-edf97fc3-4f83-4067-a4bd-a07e7b65201d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534521935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3534521935
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1287852096
Short name T349
Test name
Test status
Simulation time 37731086 ps
CPU time 0.98 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:47:13 PM PDT 24
Peak memory 206984 kb
Host smart-467e1c79-1e74-4f9a-a87c-28265aeb62bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287852096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1287852096
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2784399322
Short name T588
Test name
Test status
Simulation time 12373038106 ps
CPU time 33.03 seconds
Started Apr 16 12:47:33 PM PDT 24
Finished Apr 16 12:48:08 PM PDT 24
Peak memory 216360 kb
Host smart-09049e7e-eba2-42e0-940a-3fc94b3815f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784399322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2784399322
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2034247192
Short name T596
Test name
Test status
Simulation time 109056864 ps
CPU time 1.28 seconds
Started Apr 16 12:47:06 PM PDT 24
Finished Apr 16 12:47:09 PM PDT 24
Peak memory 207736 kb
Host smart-dd81f6c0-8807-4658-aff1-cf302844ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034247192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2034247192
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.488542897
Short name T399
Test name
Test status
Simulation time 1116108044 ps
CPU time 3.99 seconds
Started Apr 16 12:47:10 PM PDT 24
Finished Apr 16 12:47:21 PM PDT 24
Peak memory 216200 kb
Host smart-46d04c21-bd19-456d-8ecc-b27f5ef4b74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488542897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.488542897
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2989888818
Short name T666
Test name
Test status
Simulation time 40711230 ps
CPU time 0.85 seconds
Started Apr 16 12:47:28 PM PDT 24
Finished Apr 16 12:47:32 PM PDT 24
Peak memory 206664 kb
Host smart-48d60a05-0944-462d-a7ff-c21754f46d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989888818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2989888818
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1788229898
Short name T246
Test name
Test status
Simulation time 13501954562 ps
CPU time 10.76 seconds
Started Apr 16 12:47:14 PM PDT 24
Finished Apr 16 12:47:32 PM PDT 24
Peak memory 234052 kb
Host smart-4cac0f80-e739-405d-8039-b301632f5276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788229898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1788229898
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.253290680
Short name T488
Test name
Test status
Simulation time 34075661 ps
CPU time 0.71 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:48 PM PDT 24
Peak memory 205392 kb
Host smart-735cfed7-2a22-4189-8fc1-60bad308a3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253290680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.253290680
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4022271344
Short name T181
Test name
Test status
Simulation time 841922987 ps
CPU time 3.78 seconds
Started Apr 16 12:48:41 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 223944 kb
Host smart-989e329e-9b9d-4ac9-84a7-15962741546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022271344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4022271344
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1426002628
Short name T652
Test name
Test status
Simulation time 27625541 ps
CPU time 0.74 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 205472 kb
Host smart-61d53926-98d4-4100-8935-c9daf2527352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426002628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1426002628
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3160173713
Short name T344
Test name
Test status
Simulation time 4788152280 ps
CPU time 63.4 seconds
Started Apr 16 12:48:49 PM PDT 24
Finished Apr 16 12:49:54 PM PDT 24
Peak memory 239944 kb
Host smart-b768f241-eb97-4bc1-b1cd-ceba1db0f989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160173713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3160173713
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3247117011
Short name T610
Test name
Test status
Simulation time 866042389 ps
CPU time 10.63 seconds
Started Apr 16 12:48:41 PM PDT 24
Finished Apr 16 12:48:55 PM PDT 24
Peak memory 222852 kb
Host smart-902401ae-2a1c-4a8b-8346-fe60e5511c0c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3247117011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3247117011
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2218873758
Short name T705
Test name
Test status
Simulation time 18096938409 ps
CPU time 35.76 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:49:23 PM PDT 24
Peak memory 216268 kb
Host smart-db7b6085-dce3-47bc-863e-2960766b1715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218873758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2218873758
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3921662464
Short name T438
Test name
Test status
Simulation time 7865048835 ps
CPU time 26.94 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:49:24 PM PDT 24
Peak memory 216148 kb
Host smart-6a50b60c-02d1-4157-9eff-e43de404f862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921662464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3921662464
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2461178029
Short name T445
Test name
Test status
Simulation time 142105439 ps
CPU time 1.45 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 215976 kb
Host smart-89daa30d-eb49-4ac8-b13c-331c830cc274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461178029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2461178029
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2238986173
Short name T561
Test name
Test status
Simulation time 129389962 ps
CPU time 1.06 seconds
Started Apr 16 12:48:38 PM PDT 24
Finished Apr 16 12:48:40 PM PDT 24
Peak memory 205680 kb
Host smart-1a6a66f5-7836-48ac-9425-cbd6602ed312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238986173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2238986173
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3725436417
Short name T273
Test name
Test status
Simulation time 35884534935 ps
CPU time 24.82 seconds
Started Apr 16 12:48:37 PM PDT 24
Finished Apr 16 12:49:03 PM PDT 24
Peak memory 236896 kb
Host smart-f671eceb-abbe-464d-9d5a-d766cb5d5e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725436417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3725436417
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2475430471
Short name T27
Test name
Test status
Simulation time 14807416 ps
CPU time 0.72 seconds
Started Apr 16 12:48:45 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 204796 kb
Host smart-aec9d86f-1974-4394-9502-4f7832b30f18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475430471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2475430471
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3583170809
Short name T163
Test name
Test status
Simulation time 667669357 ps
CPU time 5.84 seconds
Started Apr 16 12:48:47 PM PDT 24
Finished Apr 16 12:48:55 PM PDT 24
Peak memory 222272 kb
Host smart-b052d06c-1c47-4f13-bcf8-b2640686beab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583170809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3583170809
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1034993105
Short name T623
Test name
Test status
Simulation time 62802920 ps
CPU time 0.77 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 205792 kb
Host smart-cff9934a-a052-4a7c-af4e-ce36d7087ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034993105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1034993105
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3914639141
Short name T508
Test name
Test status
Simulation time 100334950 ps
CPU time 4.38 seconds
Started Apr 16 12:48:48 PM PDT 24
Finished Apr 16 12:48:54 PM PDT 24
Peak memory 222324 kb
Host smart-63b69b15-c761-4532-85a0-aa95701c35b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3914639141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3914639141
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3132036050
Short name T348
Test name
Test status
Simulation time 66917446 ps
CPU time 1.11 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:46 PM PDT 24
Peak memory 206972 kb
Host smart-198e46c5-e464-4de3-80c2-b7c5543992ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132036050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3132036050
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2407607422
Short name T463
Test name
Test status
Simulation time 97467738 ps
CPU time 1.59 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 207800 kb
Host smart-8ddb073c-37cf-4370-8102-b5ec06ff88ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407607422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2407607422
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2667479865
Short name T480
Test name
Test status
Simulation time 38639328 ps
CPU time 1.66 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:48 PM PDT 24
Peak memory 216168 kb
Host smart-abe6509c-ba35-4375-a78c-43ef79429501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667479865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2667479865
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1685167237
Short name T513
Test name
Test status
Simulation time 456404952 ps
CPU time 1.04 seconds
Started Apr 16 12:48:44 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 206680 kb
Host smart-40ac6bda-49f5-4e14-933c-549f793b8d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685167237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1685167237
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1000873982
Short name T528
Test name
Test status
Simulation time 15327545 ps
CPU time 0.69 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:48:55 PM PDT 24
Peak memory 205328 kb
Host smart-72582131-f549-4bcc-81d3-f9d1f995fa19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000873982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1000873982
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2759228916
Short name T435
Test name
Test status
Simulation time 49310079 ps
CPU time 0.77 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:48:55 PM PDT 24
Peak memory 206780 kb
Host smart-8d524ada-28d1-4b92-9c9c-844a75c28ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759228916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2759228916
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1252158860
Short name T345
Test name
Test status
Simulation time 7896649507 ps
CPU time 87.6 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 249372 kb
Host smart-6ab2f75e-fddb-49ae-8bd6-df2e6c75506c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252158860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1252158860
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1846426854
Short name T215
Test name
Test status
Simulation time 6230229745 ps
CPU time 13.59 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 223336 kb
Host smart-b0e4cdbd-24a2-4a17-b156-828c6d11d5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846426854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1846426854
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3332498124
Short name T105
Test name
Test status
Simulation time 2368776706 ps
CPU time 12.31 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:49:08 PM PDT 24
Peak memory 216852 kb
Host smart-e2155d10-e92f-4610-96b4-5a7a01178a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332498124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3332498124
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1158687925
Short name T582
Test name
Test status
Simulation time 752688940 ps
CPU time 10.71 seconds
Started Apr 16 12:48:47 PM PDT 24
Finished Apr 16 12:49:00 PM PDT 24
Peak memory 219080 kb
Host smart-81e94a89-05ee-4c80-965a-a3845c15e341
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1158687925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1158687925
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2999880146
Short name T152
Test name
Test status
Simulation time 55186369 ps
CPU time 0.96 seconds
Started Apr 16 12:48:40 PM PDT 24
Finished Apr 16 12:48:43 PM PDT 24
Peak memory 206628 kb
Host smart-b86d9863-a6aa-4ceb-a79c-7a7277694019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999880146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2999880146
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3329314172
Short name T695
Test name
Test status
Simulation time 10757649980 ps
CPU time 54.07 seconds
Started Apr 16 12:48:48 PM PDT 24
Finished Apr 16 12:49:44 PM PDT 24
Peak memory 216296 kb
Host smart-de5ce926-4530-444d-b628-2281df3aa54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329314172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3329314172
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1509637773
Short name T425
Test name
Test status
Simulation time 15312648326 ps
CPU time 21.86 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:49:07 PM PDT 24
Peak memory 216224 kb
Host smart-ebf76770-ab6e-4997-80e9-3c8f58450ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509637773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1509637773
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.334085623
Short name T616
Test name
Test status
Simulation time 218742224 ps
CPU time 6.29 seconds
Started Apr 16 12:48:52 PM PDT 24
Finished Apr 16 12:49:00 PM PDT 24
Peak memory 216224 kb
Host smart-c88ab16c-afd8-41ee-a619-0213454608f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334085623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.334085623
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3163226364
Short name T468
Test name
Test status
Simulation time 218260581 ps
CPU time 1.28 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:47 PM PDT 24
Peak memory 206700 kb
Host smart-cbe66e52-8600-40ea-a3fd-bcf4b79ca2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163226364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3163226364
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3178145428
Short name T173
Test name
Test status
Simulation time 23361259758 ps
CPU time 34.64 seconds
Started Apr 16 12:48:50 PM PDT 24
Finished Apr 16 12:49:26 PM PDT 24
Peak memory 224944 kb
Host smart-71c97d19-6ee1-44b5-abd9-2567771716e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178145428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3178145428
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2310402073
Short name T600
Test name
Test status
Simulation time 38127707 ps
CPU time 0.67 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:48:58 PM PDT 24
Peak memory 205372 kb
Host smart-97fb5d63-2393-4935-964c-d84f0264ed8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310402073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2310402073
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1889872023
Short name T83
Test name
Test status
Simulation time 172314034 ps
CPU time 3.37 seconds
Started Apr 16 12:48:54 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 222668 kb
Host smart-54b96568-9987-4e59-a0e4-3f9efd38e552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889872023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1889872023
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.451499259
Short name T412
Test name
Test status
Simulation time 26610306 ps
CPU time 0.73 seconds
Started Apr 16 12:48:47 PM PDT 24
Finished Apr 16 12:48:50 PM PDT 24
Peak memory 205384 kb
Host smart-1fda6385-717d-484b-8627-6b743b13a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451499259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.451499259
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1014114156
Short name T203
Test name
Test status
Simulation time 8081304587 ps
CPU time 14.18 seconds
Started Apr 16 12:48:43 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 238824 kb
Host smart-1d13e578-8d32-4546-9e4c-d60b67166b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014114156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1014114156
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1644801733
Short name T454
Test name
Test status
Simulation time 996527882 ps
CPU time 6.7 seconds
Started Apr 16 12:48:50 PM PDT 24
Finished Apr 16 12:48:58 PM PDT 24
Peak memory 220212 kb
Host smart-3a5362f2-fff2-4fea-ad77-271340027adc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1644801733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1644801733
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1221891109
Short name T663
Test name
Test status
Simulation time 4560561983 ps
CPU time 11.22 seconds
Started Apr 16 12:48:44 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 216288 kb
Host smart-c4af8bd4-b166-491a-bbbc-b6a3ce1e9d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221891109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1221891109
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2097668256
Short name T633
Test name
Test status
Simulation time 2315239124 ps
CPU time 5.36 seconds
Started Apr 16 12:48:42 PM PDT 24
Finished Apr 16 12:48:51 PM PDT 24
Peak memory 216216 kb
Host smart-de7cb76d-b337-4f4a-9aa3-7e85fd4edef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097668256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2097668256
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1013049289
Short name T515
Test name
Test status
Simulation time 91275549 ps
CPU time 2.78 seconds
Started Apr 16 12:48:45 PM PDT 24
Finished Apr 16 12:48:51 PM PDT 24
Peak memory 216204 kb
Host smart-0e6403c2-9385-4f32-aa92-d7f39f529757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013049289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1013049289
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3815405991
Short name T510
Test name
Test status
Simulation time 309843598 ps
CPU time 0.9 seconds
Started Apr 16 12:48:45 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 206700 kb
Host smart-e690a93f-474b-459a-8ff0-6507210daa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815405991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3815405991
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2484667456
Short name T713
Test name
Test status
Simulation time 184646470 ps
CPU time 0.71 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:48:56 PM PDT 24
Peak memory 205724 kb
Host smart-428b8b51-889a-49aa-9b64-3d7a590a9742
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484667456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2484667456
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.611796498
Short name T594
Test name
Test status
Simulation time 55755217 ps
CPU time 0.76 seconds
Started Apr 16 12:48:52 PM PDT 24
Finished Apr 16 12:48:55 PM PDT 24
Peak memory 206820 kb
Host smart-17167e96-04c8-4812-bcea-8f1a3bb11b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611796498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.611796498
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1597146719
Short name T660
Test name
Test status
Simulation time 13494898699 ps
CPU time 71.7 seconds
Started Apr 16 12:49:00 PM PDT 24
Finished Apr 16 12:50:14 PM PDT 24
Peak memory 238764 kb
Host smart-14a7cef9-633d-4cd3-aab4-4c060290edb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597146719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1597146719
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3872929342
Short name T274
Test name
Test status
Simulation time 29043545218 ps
CPU time 11.36 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:49:06 PM PDT 24
Peak memory 216740 kb
Host smart-34ccfc01-845a-4842-8ac2-8744bf8d22fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872929342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3872929342
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.294443257
Short name T566
Test name
Test status
Simulation time 226282219 ps
CPU time 4.6 seconds
Started Apr 16 12:48:48 PM PDT 24
Finished Apr 16 12:48:54 PM PDT 24
Peak memory 220316 kb
Host smart-51ea5f9c-af72-4fd0-afbc-ae874a5d3c19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=294443257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.294443257
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2335680074
Short name T150
Test name
Test status
Simulation time 61237479 ps
CPU time 1.01 seconds
Started Apr 16 12:48:52 PM PDT 24
Finished Apr 16 12:48:55 PM PDT 24
Peak memory 206828 kb
Host smart-ecd9564e-245d-459d-a80a-ee7de06b36fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335680074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2335680074
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3777857744
Short name T388
Test name
Test status
Simulation time 4302164040 ps
CPU time 32.88 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:49:31 PM PDT 24
Peak memory 216160 kb
Host smart-51bb81fa-69ab-4648-b250-0da7378be42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777857744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3777857744
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3138479149
Short name T411
Test name
Test status
Simulation time 4518091982 ps
CPU time 5.32 seconds
Started Apr 16 12:48:52 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 216272 kb
Host smart-aab333ac-2639-4c3e-addd-30bf03db9620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138479149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3138479149
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3348779677
Short name T649
Test name
Test status
Simulation time 216908807 ps
CPU time 1.97 seconds
Started Apr 16 12:48:54 PM PDT 24
Finished Apr 16 12:48:57 PM PDT 24
Peak memory 216212 kb
Host smart-5210b43f-e377-4725-9887-b71c7d8209fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348779677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3348779677
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2172009186
Short name T700
Test name
Test status
Simulation time 193002882 ps
CPU time 1.08 seconds
Started Apr 16 12:48:50 PM PDT 24
Finished Apr 16 12:48:52 PM PDT 24
Peak memory 206712 kb
Host smart-d698091e-3c73-42f0-a067-6c745b1876f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172009186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2172009186
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1333797304
Short name T625
Test name
Test status
Simulation time 12212954 ps
CPU time 0.73 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:48:56 PM PDT 24
Peak memory 205336 kb
Host smart-8052b949-4b45-4360-bf5a-9652bcfb6e25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333797304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1333797304
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1729645402
Short name T264
Test name
Test status
Simulation time 917526233 ps
CPU time 6.92 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:05 PM PDT 24
Peak memory 223972 kb
Host smart-dd13151c-5fba-4f69-95cd-cc836822520d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729645402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1729645402
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2083504267
Short name T476
Test name
Test status
Simulation time 156717983 ps
CPU time 0.78 seconds
Started Apr 16 12:48:49 PM PDT 24
Finished Apr 16 12:48:52 PM PDT 24
Peak memory 206500 kb
Host smart-89e7ff62-a8fd-4ee9-993a-0c2b487fed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083504267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2083504267
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2450548184
Short name T141
Test name
Test status
Simulation time 7263128611 ps
CPU time 34.49 seconds
Started Apr 16 12:49:00 PM PDT 24
Finished Apr 16 12:49:37 PM PDT 24
Peak memory 224468 kb
Host smart-a9af2e3b-2a1c-40bf-9f68-a373afafc167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450548184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2450548184
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.348498976
Short name T288
Test name
Test status
Simulation time 746188813 ps
CPU time 11.88 seconds
Started Apr 16 12:48:52 PM PDT 24
Finished Apr 16 12:49:06 PM PDT 24
Peak memory 218628 kb
Host smart-8953ecf3-5a72-4d3c-b123-4f11a6cebe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348498976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.348498976
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.142508816
Short name T190
Test name
Test status
Simulation time 48890409740 ps
CPU time 30.57 seconds
Started Apr 16 12:48:50 PM PDT 24
Finished Apr 16 12:49:22 PM PDT 24
Peak memory 232608 kb
Host smart-cfcba230-802c-4455-a229-d73d5679ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142508816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.142508816
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1146835066
Short name T628
Test name
Test status
Simulation time 491368785 ps
CPU time 3.71 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:03 PM PDT 24
Peak memory 222040 kb
Host smart-8544be55-715f-47dc-8703-c62088728392
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1146835066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1146835066
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2345038342
Short name T552
Test name
Test status
Simulation time 17952876263 ps
CPU time 27.91 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:49:25 PM PDT 24
Peak memory 216164 kb
Host smart-d7cfb12b-66fc-4985-b0b0-ca0fa1adc85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345038342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2345038342
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1254411421
Short name T492
Test name
Test status
Simulation time 5553388515 ps
CPU time 12.1 seconds
Started Apr 16 12:48:53 PM PDT 24
Finished Apr 16 12:49:07 PM PDT 24
Peak memory 216168 kb
Host smart-a4139845-03e3-4052-b78f-fd633c156f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254411421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1254411421
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.423225990
Short name T697
Test name
Test status
Simulation time 742131863 ps
CPU time 6.09 seconds
Started Apr 16 12:48:52 PM PDT 24
Finished Apr 16 12:49:00 PM PDT 24
Peak memory 216196 kb
Host smart-e90224b9-3601-4776-a1be-6471237667d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423225990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.423225990
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1189860433
Short name T656
Test name
Test status
Simulation time 38934394 ps
CPU time 0.7 seconds
Started Apr 16 12:48:51 PM PDT 24
Finished Apr 16 12:48:53 PM PDT 24
Peak memory 205664 kb
Host smart-293dc258-412a-4f3c-9865-92b780e3348b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189860433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1189860433
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1700050653
Short name T414
Test name
Test status
Simulation time 34867701 ps
CPU time 0.71 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:00 PM PDT 24
Peak memory 205248 kb
Host smart-cf9f8675-81fd-4a68-9c3b-4155cd529f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700050653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1700050653
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1188259017
Short name T539
Test name
Test status
Simulation time 15640506 ps
CPU time 0.77 seconds
Started Apr 16 12:49:09 PM PDT 24
Finished Apr 16 12:49:11 PM PDT 24
Peak memory 205820 kb
Host smart-23fda6d7-79cb-40a2-b81d-fece1f8dabc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188259017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1188259017
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3512006094
Short name T630
Test name
Test status
Simulation time 30294793148 ps
CPU time 30.06 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:28 PM PDT 24
Peak memory 240716 kb
Host smart-1563bd6e-4206-42ce-b05f-0cf37f02494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512006094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3512006094
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1041170244
Short name T172
Test name
Test status
Simulation time 960421411 ps
CPU time 4.99 seconds
Started Apr 16 12:49:06 PM PDT 24
Finished Apr 16 12:49:13 PM PDT 24
Peak memory 222876 kb
Host smart-f5345b79-9db4-4134-b7cb-571d71df92a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041170244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1041170244
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.716653782
Short name T286
Test name
Test status
Simulation time 24296904923 ps
CPU time 9.64 seconds
Started Apr 16 12:49:03 PM PDT 24
Finished Apr 16 12:49:14 PM PDT 24
Peak memory 232188 kb
Host smart-7e3873b8-47df-4038-b3e0-43c438179f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716653782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.716653782
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2986602472
Short name T447
Test name
Test status
Simulation time 1925113034 ps
CPU time 4.21 seconds
Started Apr 16 12:48:59 PM PDT 24
Finished Apr 16 12:49:05 PM PDT 24
Peak memory 222700 kb
Host smart-0ee86492-100f-4fd5-a2a4-6cf6fc5f446d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2986602472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2986602472
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.235911192
Short name T374
Test name
Test status
Simulation time 3315809640 ps
CPU time 17.54 seconds
Started Apr 16 12:49:59 PM PDT 24
Finished Apr 16 12:50:18 PM PDT 24
Peak memory 216248 kb
Host smart-881a131d-f2ff-408d-bc51-134f06f2a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235911192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.235911192
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3158561642
Short name T614
Test name
Test status
Simulation time 1852822100 ps
CPU time 5.93 seconds
Started Apr 16 12:48:51 PM PDT 24
Finished Apr 16 12:48:58 PM PDT 24
Peak memory 216180 kb
Host smart-686bc306-d733-4ee5-8c3c-d3b04a8e1f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158561642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3158561642
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1943270668
Short name T673
Test name
Test status
Simulation time 513628822 ps
CPU time 5.68 seconds
Started Apr 16 12:48:50 PM PDT 24
Finished Apr 16 12:48:57 PM PDT 24
Peak memory 216136 kb
Host smart-255389e3-8d91-4800-979f-f30b336c0fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943270668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1943270668
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3633214051
Short name T53
Test name
Test status
Simulation time 40951091 ps
CPU time 0.82 seconds
Started Apr 16 12:48:55 PM PDT 24
Finished Apr 16 12:48:57 PM PDT 24
Peak memory 205544 kb
Host smart-3c9f9ac8-0a29-4b0a-9e34-81a562fc916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633214051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3633214051
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.871181833
Short name T702
Test name
Test status
Simulation time 14523823 ps
CPU time 0.72 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 205376 kb
Host smart-3124613e-8cd3-4f91-ae44-aa363e6f3c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871181833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.871181833
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2806792696
Short name T692
Test name
Test status
Simulation time 751502087 ps
CPU time 8.6 seconds
Started Apr 16 12:48:55 PM PDT 24
Finished Apr 16 12:49:05 PM PDT 24
Peak memory 217220 kb
Host smart-ae4d8c49-e365-4c50-9284-2c54bf50e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806792696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2806792696
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3695396083
Short name T569
Test name
Test status
Simulation time 36894935 ps
CPU time 0.73 seconds
Started Apr 16 12:49:00 PM PDT 24
Finished Apr 16 12:49:02 PM PDT 24
Peak memory 206520 kb
Host smart-d6e6a539-0049-4ddb-ab2f-b0d4ec6f3010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695396083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3695396083
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1699416585
Short name T686
Test name
Test status
Simulation time 39509566692 ps
CPU time 88.89 seconds
Started Apr 16 12:49:01 PM PDT 24
Finished Apr 16 12:50:32 PM PDT 24
Peak memory 239284 kb
Host smart-b10df934-9dd3-4858-b845-5883d9f33e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699416585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1699416585
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2672837579
Short name T244
Test name
Test status
Simulation time 2031929564 ps
CPU time 6.47 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:06 PM PDT 24
Peak memory 221352 kb
Host smart-89c830b2-b3ab-4d7e-a56e-c153989fbd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672837579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2672837579
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2867673594
Short name T307
Test name
Test status
Simulation time 28555128044 ps
CPU time 20.44 seconds
Started Apr 16 12:49:03 PM PDT 24
Finished Apr 16 12:49:25 PM PDT 24
Peak memory 218684 kb
Host smart-ed6caaa6-ec26-4171-8147-9fd0ae6aa218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867673594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2867673594
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4063791751
Short name T626
Test name
Test status
Simulation time 297329672 ps
CPU time 2.55 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 218476 kb
Host smart-e16102a2-a7e7-4f8a-ad80-1990facc7ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063791751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4063791751
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3959011718
Short name T516
Test name
Test status
Simulation time 294804401 ps
CPU time 4.53 seconds
Started Apr 16 12:48:55 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 220284 kb
Host smart-7464644e-fa80-4e10-a2f2-158b9eaa227e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3959011718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3959011718
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2187740657
Short name T538
Test name
Test status
Simulation time 1338671352 ps
CPU time 9.34 seconds
Started Apr 16 12:49:01 PM PDT 24
Finished Apr 16 12:49:12 PM PDT 24
Peak memory 216104 kb
Host smart-414c0707-c0f9-41f5-8856-d9be4c1469d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187740657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2187740657
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1273733160
Short name T619
Test name
Test status
Simulation time 156915328 ps
CPU time 1.8 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:49:00 PM PDT 24
Peak memory 216196 kb
Host smart-dacd531b-64f7-4399-8d3f-cc902ee69d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273733160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1273733160
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3102492195
Short name T430
Test name
Test status
Simulation time 49721780 ps
CPU time 0.86 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:48:58 PM PDT 24
Peak memory 205636 kb
Host smart-8eeaf037-f0dd-48c3-91df-bd0f6f8b1cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102492195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3102492195
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.288176091
Short name T433
Test name
Test status
Simulation time 47873265 ps
CPU time 0.78 seconds
Started Apr 16 12:49:05 PM PDT 24
Finished Apr 16 12:49:07 PM PDT 24
Peak memory 205288 kb
Host smart-0236bd5b-afa2-44bc-b4fb-99e32f385960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288176091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.288176091
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3261274224
Short name T670
Test name
Test status
Simulation time 35284247 ps
CPU time 0.79 seconds
Started Apr 16 12:49:01 PM PDT 24
Finished Apr 16 12:49:04 PM PDT 24
Peak memory 206800 kb
Host smart-157d996e-dec4-47f4-9c88-86c3ed080d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261274224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3261274224
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.365104700
Short name T635
Test name
Test status
Simulation time 2105167035 ps
CPU time 6.7 seconds
Started Apr 16 12:49:06 PM PDT 24
Finished Apr 16 12:49:14 PM PDT 24
Peak memory 237744 kb
Host smart-d50faaa5-fbb9-4430-8773-d27ded1cdecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365104700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.365104700
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.341336985
Short name T169
Test name
Test status
Simulation time 5692601128 ps
CPU time 57.38 seconds
Started Apr 16 12:49:01 PM PDT 24
Finished Apr 16 12:50:00 PM PDT 24
Peak memory 232768 kb
Host smart-6e5eb353-3576-43bd-8204-0037dc5bd9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341336985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.341336985
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.859590810
Short name T276
Test name
Test status
Simulation time 2987313111 ps
CPU time 9.74 seconds
Started Apr 16 12:48:59 PM PDT 24
Finished Apr 16 12:49:10 PM PDT 24
Peak memory 224332 kb
Host smart-66f5321e-0530-4559-94d8-c5cbadf000c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859590810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.859590810
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.842905002
Short name T432
Test name
Test status
Simulation time 295367679 ps
CPU time 3.6 seconds
Started Apr 16 12:48:54 PM PDT 24
Finished Apr 16 12:48:59 PM PDT 24
Peak memory 222352 kb
Host smart-880f4cef-cc80-413e-9563-d169051f2917
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=842905002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.842905002
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1591747111
Short name T529
Test name
Test status
Simulation time 2006652826 ps
CPU time 31.9 seconds
Started Apr 16 12:48:55 PM PDT 24
Finished Apr 16 12:49:28 PM PDT 24
Peak memory 216220 kb
Host smart-acf9a154-cdd3-4966-948d-48b185411af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591747111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1591747111
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.256090191
Short name T449
Test name
Test status
Simulation time 4761249549 ps
CPU time 12.61 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:12 PM PDT 24
Peak memory 216312 kb
Host smart-8a802662-ad8a-4639-9120-d30c16af22ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256090191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.256090191
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1822285480
Short name T544
Test name
Test status
Simulation time 38751515 ps
CPU time 0.9 seconds
Started Apr 16 12:48:57 PM PDT 24
Finished Apr 16 12:49:00 PM PDT 24
Peak memory 206708 kb
Host smart-a2dd0dd8-d445-4151-a5d9-5eefdb62e8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822285480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1822285480
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3649224573
Short name T711
Test name
Test status
Simulation time 145352732 ps
CPU time 0.83 seconds
Started Apr 16 12:49:03 PM PDT 24
Finished Apr 16 12:49:05 PM PDT 24
Peak memory 205680 kb
Host smart-42051137-5bc4-402f-8418-b6348a8705be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649224573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3649224573
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1181346575
Short name T714
Test name
Test status
Simulation time 9114133153 ps
CPU time 16.87 seconds
Started Apr 16 12:48:56 PM PDT 24
Finished Apr 16 12:49:14 PM PDT 24
Peak memory 217376 kb
Host smart-f31541c8-ba75-4a72-a9ad-2d914dc2e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181346575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1181346575
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1848368151
Short name T479
Test name
Test status
Simulation time 14684119 ps
CPU time 0.73 seconds
Started Apr 16 12:49:02 PM PDT 24
Finished Apr 16 12:49:05 PM PDT 24
Peak memory 205680 kb
Host smart-b0be03d5-57a3-4bef-8966-2a153a6385d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848368151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1848368151
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4238830978
Short name T24
Test name
Test status
Simulation time 10268440919 ps
CPU time 27.83 seconds
Started Apr 16 12:49:04 PM PDT 24
Finished Apr 16 12:49:33 PM PDT 24
Peak memory 218428 kb
Host smart-4114c33b-bfbf-4084-8e09-d38d65d1b0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238830978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4238830978
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.399149947
Short name T554
Test name
Test status
Simulation time 36154986 ps
CPU time 0.71 seconds
Started Apr 16 12:48:59 PM PDT 24
Finished Apr 16 12:49:01 PM PDT 24
Peak memory 205784 kb
Host smart-ff7b3938-dd37-4869-b213-e4d6fc545466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399149947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.399149947
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3968496232
Short name T308
Test name
Test status
Simulation time 192927564 ps
CPU time 3.45 seconds
Started Apr 16 12:49:00 PM PDT 24
Finished Apr 16 12:49:05 PM PDT 24
Peak memory 223128 kb
Host smart-031f7059-d7c1-4f21-9b99-6109aa6661ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968496232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3968496232
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3608361352
Short name T236
Test name
Test status
Simulation time 1986771875 ps
CPU time 4.77 seconds
Started Apr 16 12:49:03 PM PDT 24
Finished Apr 16 12:49:10 PM PDT 24
Peak memory 216724 kb
Host smart-d7745caf-ba68-4d99-a002-a680ef1724e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608361352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3608361352
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.616651912
Short name T658
Test name
Test status
Simulation time 908324154 ps
CPU time 8.76 seconds
Started Apr 16 12:49:08 PM PDT 24
Finished Apr 16 12:49:18 PM PDT 24
Peak memory 221832 kb
Host smart-911f2aa0-ba8f-401e-b579-00f40907cdb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616651912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.616651912
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2639507178
Short name T54
Test name
Test status
Simulation time 302748219 ps
CPU time 5.05 seconds
Started Apr 16 12:49:07 PM PDT 24
Finished Apr 16 12:49:14 PM PDT 24
Peak memory 216112 kb
Host smart-b020dc74-11d9-41c9-a836-1336ba6acf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639507178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2639507178
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1078339335
Short name T406
Test name
Test status
Simulation time 13584373898 ps
CPU time 10.9 seconds
Started Apr 16 12:49:15 PM PDT 24
Finished Apr 16 12:49:26 PM PDT 24
Peak memory 216216 kb
Host smart-1641f3a1-9e95-4e60-8f57-4d19b55ab4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078339335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1078339335
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.443811807
Short name T530
Test name
Test status
Simulation time 159594908 ps
CPU time 1.91 seconds
Started Apr 16 12:49:04 PM PDT 24
Finished Apr 16 12:49:07 PM PDT 24
Peak memory 216084 kb
Host smart-856970a5-8c2c-4848-a369-8b94b2dda005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443811807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.443811807
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3310550544
Short name T639
Test name
Test status
Simulation time 249063306 ps
CPU time 1.08 seconds
Started Apr 16 12:49:11 PM PDT 24
Finished Apr 16 12:49:14 PM PDT 24
Peak memory 206660 kb
Host smart-d177b01b-ca50-4df2-ab35-d3119597abff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310550544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3310550544
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.644560004
Short name T456
Test name
Test status
Simulation time 129084870 ps
CPU time 0.71 seconds
Started Apr 16 12:47:13 PM PDT 24
Finished Apr 16 12:47:16 PM PDT 24
Peak memory 204776 kb
Host smart-92b67ee8-0965-408b-b3b2-49449267ea0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644560004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.644560004
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4028441252
Short name T613
Test name
Test status
Simulation time 19217753 ps
CPU time 0.75 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:19 PM PDT 24
Peak memory 206512 kb
Host smart-91f2c1bd-9f94-4efa-8711-36691d94fc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028441252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4028441252
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.579431652
Short name T356
Test name
Test status
Simulation time 9217763261 ps
CPU time 129.45 seconds
Started Apr 16 12:47:20 PM PDT 24
Finished Apr 16 12:49:31 PM PDT 24
Peak memory 249076 kb
Host smart-f7791ace-851d-4c6b-8520-2e2c6b07c835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579431652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.579431652
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.76457305
Short name T214
Test name
Test status
Simulation time 9390929092 ps
CPU time 8.64 seconds
Started Apr 16 12:47:15 PM PDT 24
Finished Apr 16 12:47:26 PM PDT 24
Peak memory 220712 kb
Host smart-a07865d2-6d22-4209-8ca1-27f5ca4c7b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76457305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.76457305
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.17125364
Short name T424
Test name
Test status
Simulation time 497284910 ps
CPU time 6.43 seconds
Started Apr 16 12:47:25 PM PDT 24
Finished Apr 16 12:47:34 PM PDT 24
Peak memory 218652 kb
Host smart-39624e85-94b6-4161-9174-aea7e5babfff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=17125364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.17125364
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1912439012
Short name T394
Test name
Test status
Simulation time 2632976490 ps
CPU time 8.26 seconds
Started Apr 16 12:47:32 PM PDT 24
Finished Apr 16 12:47:43 PM PDT 24
Peak memory 216280 kb
Host smart-69302449-7c00-479f-a619-7d6a042fba13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912439012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1912439012
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3328946011
Short name T580
Test name
Test status
Simulation time 509693374 ps
CPU time 1.56 seconds
Started Apr 16 12:47:14 PM PDT 24
Finished Apr 16 12:47:17 PM PDT 24
Peak memory 207736 kb
Host smart-6ccb9ebf-f791-495e-99a2-f9c585c54edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328946011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3328946011
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3422264852
Short name T585
Test name
Test status
Simulation time 374979297 ps
CPU time 1.92 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:47:13 PM PDT 24
Peak memory 216216 kb
Host smart-a5ac73b7-8a0f-4db3-a8c8-ed90379a42d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422264852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3422264852
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2551293401
Short name T467
Test name
Test status
Simulation time 42402324 ps
CPU time 0.82 seconds
Started Apr 16 12:47:08 PM PDT 24
Finished Apr 16 12:47:12 PM PDT 24
Peak memory 205668 kb
Host smart-b3c13d9f-3b84-4ae6-bf7b-5adf0c1f79ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551293401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2551293401
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3480810356
Short name T353
Test name
Test status
Simulation time 11755402093 ps
CPU time 33.95 seconds
Started Apr 16 12:47:38 PM PDT 24
Finished Apr 16 12:48:13 PM PDT 24
Peak memory 222648 kb
Host smart-380f7ed2-3b20-4b6f-a227-9b51e7f6c76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480810356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3480810356
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3885212806
Short name T48
Test name
Test status
Simulation time 13685562 ps
CPU time 0.77 seconds
Started Apr 16 12:47:16 PM PDT 24
Finished Apr 16 12:47:18 PM PDT 24
Peak memory 204828 kb
Host smart-a632281a-7b2b-443f-a2dc-33e693013bad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885212806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
885212806
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.536456997
Short name T525
Test name
Test status
Simulation time 224371531 ps
CPU time 0.78 seconds
Started Apr 16 12:47:23 PM PDT 24
Finished Apr 16 12:47:26 PM PDT 24
Peak memory 206808 kb
Host smart-fd8d5330-d9f6-4e8f-9702-8d78167b90ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536456997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.536456997
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1737646975
Short name T86
Test name
Test status
Simulation time 2276759028 ps
CPU time 10.24 seconds
Started Apr 16 12:47:18 PM PDT 24
Finished Apr 16 12:47:30 PM PDT 24
Peak memory 216688 kb
Host smart-3c12c01e-0bf7-4169-8957-36a29d364674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737646975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1737646975
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.684028568
Short name T156
Test name
Test status
Simulation time 99704909090 ps
CPU time 175.44 seconds
Started Apr 16 12:47:11 PM PDT 24
Finished Apr 16 12:50:09 PM PDT 24
Peak memory 248440 kb
Host smart-91fdff9b-22c5-4bf1-a161-783703047297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684028568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.684028568
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3262686008
Short name T317
Test name
Test status
Simulation time 29105158903 ps
CPU time 13.44 seconds
Started Apr 16 12:47:28 PM PDT 24
Finished Apr 16 12:47:45 PM PDT 24
Peak memory 222720 kb
Host smart-d00d7ed4-9ffd-4e40-ab64-a46a95202b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262686008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3262686008
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.275960178
Short name T47
Test name
Test status
Simulation time 564280030 ps
CPU time 6.89 seconds
Started Apr 16 12:47:29 PM PDT 24
Finished Apr 16 12:47:38 PM PDT 24
Peak memory 219808 kb
Host smart-d6d7ec1d-b684-4365-b77d-2e41249d58b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=275960178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.275960178
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2839333272
Short name T629
Test name
Test status
Simulation time 39857126935 ps
CPU time 55.32 seconds
Started Apr 16 12:47:12 PM PDT 24
Finished Apr 16 12:48:09 PM PDT 24
Peak memory 216456 kb
Host smart-84b48b5f-76ab-48fd-8e89-54a448a7f9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839333272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2839333272
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3433546772
Short name T448
Test name
Test status
Simulation time 111427519615 ps
CPU time 27.17 seconds
Started Apr 16 12:47:42 PM PDT 24
Finished Apr 16 12:48:11 PM PDT 24
Peak memory 216132 kb
Host smart-c625f8f2-15ae-4de4-a625-5408f1406453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433546772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3433546772
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.367656318
Short name T478
Test name
Test status
Simulation time 356517233 ps
CPU time 15.01 seconds
Started Apr 16 12:47:26 PM PDT 24
Finished Apr 16 12:47:44 PM PDT 24
Peak memory 216372 kb
Host smart-191685fa-dc71-4e52-98e1-f25bdc8d1a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367656318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.367656318
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4256988263
Short name T603
Test name
Test status
Simulation time 31272419 ps
CPU time 0.78 seconds
Started Apr 16 12:47:14 PM PDT 24
Finished Apr 16 12:47:16 PM PDT 24
Peak memory 205692 kb
Host smart-d4045580-a2de-4d7e-97e8-5bb5ca61ce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256988263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4256988263
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3487123417
Short name T303
Test name
Test status
Simulation time 76518332936 ps
CPU time 29.15 seconds
Started Apr 16 12:47:26 PM PDT 24
Finished Apr 16 12:47:58 PM PDT 24
Peak memory 223128 kb
Host smart-332f8a44-1ce8-43a7-a6ed-3257960907b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487123417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3487123417
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2093814594
Short name T489
Test name
Test status
Simulation time 220271471 ps
CPU time 0.71 seconds
Started Apr 16 12:47:27 PM PDT 24
Finished Apr 16 12:47:31 PM PDT 24
Peak memory 204796 kb
Host smart-fdc74729-1d6e-4c79-b23d-ef6416d48cd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093814594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
093814594
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3886629895
Short name T536
Test name
Test status
Simulation time 27687779 ps
CPU time 0.76 seconds
Started Apr 16 12:47:12 PM PDT 24
Finished Apr 16 12:47:15 PM PDT 24
Peak memory 206504 kb
Host smart-bde5a03b-86a3-4b1c-898b-bc1abdb3091d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886629895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3886629895
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2779147123
Short name T262
Test name
Test status
Simulation time 11792819695 ps
CPU time 21.42 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:47:34 PM PDT 24
Peak memory 223724 kb
Host smart-aef70cee-5b40-4bec-b686-01da4e6570d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779147123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2779147123
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1580127025
Short name T518
Test name
Test status
Simulation time 529024348 ps
CPU time 6.22 seconds
Started Apr 16 12:47:09 PM PDT 24
Finished Apr 16 12:47:18 PM PDT 24
Peak memory 222912 kb
Host smart-47abdf57-73a5-4d68-80bc-e89e1fd4edef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1580127025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1580127025
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2732693692
Short name T36
Test name
Test status
Simulation time 294312186 ps
CPU time 1.14 seconds
Started Apr 16 12:47:17 PM PDT 24
Finished Apr 16 12:47:20 PM PDT 24
Peak memory 207180 kb
Host smart-2be6bdae-d587-41d5-abf9-100444e03e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732693692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2732693692
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.4084438227
Short name T709
Test name
Test status
Simulation time 165754085 ps
CPU time 3.17 seconds
Started Apr 16 12:47:30 PM PDT 24
Finished Apr 16 12:47:35 PM PDT 24
Peak memory 216368 kb
Host smart-23b0dd83-eace-413e-92d8-19f11391de5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084438227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.4084438227
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3893904020
Short name T694
Test name
Test status
Simulation time 818606530 ps
CPU time 3.36 seconds
Started Apr 16 12:47:18 PM PDT 24
Finished Apr 16 12:47:23 PM PDT 24
Peak memory 216100 kb
Host smart-1aa355eb-c27e-48eb-8c06-eda53c87f590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893904020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3893904020
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3553541165
Short name T555
Test name
Test status
Simulation time 38674232 ps
CPU time 0.9 seconds
Started Apr 16 12:47:15 PM PDT 24
Finished Apr 16 12:47:18 PM PDT 24
Peak memory 206312 kb
Host smart-7bd07497-ced7-41bf-90b7-8f91d45d8949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553541165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3553541165
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2704623779
Short name T490
Test name
Test status
Simulation time 27235973 ps
CPU time 0.77 seconds
Started Apr 16 12:47:15 PM PDT 24
Finished Apr 16 12:47:18 PM PDT 24
Peak memory 205668 kb
Host smart-2611ee5a-4d82-4681-8ba4-e3d43c4811a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704623779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2704623779
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2065736687
Short name T297
Test name
Test status
Simulation time 4875865672 ps
CPU time 14.51 seconds
Started Apr 16 12:47:21 PM PDT 24
Finished Apr 16 12:47:37 PM PDT 24
Peak memory 218968 kb
Host smart-f33e3523-f00a-4673-8114-40e84b5e00d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065736687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2065736687
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.146528237
Short name T436
Test name
Test status
Simulation time 23264545 ps
CPU time 0.71 seconds
Started Apr 16 12:47:10 PM PDT 24
Finished Apr 16 12:47:13 PM PDT 24
Peak memory 204768 kb
Host smart-f2636626-58b1-41fb-94ad-44652ceda12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146528237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.146528237
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3793612099
Short name T499
Test name
Test status
Simulation time 62583386 ps
CPU time 0.79 seconds
Started Apr 16 12:47:22 PM PDT 24
Finished Apr 16 12:47:24 PM PDT 24
Peak memory 206476 kb
Host smart-d2eea3c2-1770-40af-99a3-94a384a90ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793612099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3793612099
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.922384634
Short name T359
Test name
Test status
Simulation time 21015931035 ps
CPU time 150.17 seconds
Started Apr 16 12:47:26 PM PDT 24
Finished Apr 16 12:50:00 PM PDT 24
Peak memory 252648 kb
Host smart-59533374-af13-4e7f-abfd-11029c5f30bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922384634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.922384634
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2940064677
Short name T327
Test name
Test status
Simulation time 115241929 ps
CPU time 2.45 seconds
Started Apr 16 12:47:12 PM PDT 24
Finished Apr 16 12:47:17 PM PDT 24
Peak memory 216584 kb
Host smart-b6d915c8-bb22-494e-8eb1-7d6a12368f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940064677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2940064677
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3084011497
Short name T305
Test name
Test status
Simulation time 701615748 ps
CPU time 2.64 seconds
Started Apr 16 12:47:21 PM PDT 24
Finished Apr 16 12:47:26 PM PDT 24
Peak memory 222708 kb
Host smart-e337390d-a0e9-4804-a035-c4cc05191f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084011497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3084011497
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1764287851
Short name T708
Test name
Test status
Simulation time 5061193344 ps
CPU time 19.2 seconds
Started Apr 16 12:47:22 PM PDT 24
Finished Apr 16 12:47:49 PM PDT 24
Peak memory 220104 kb
Host smart-0315f313-265c-4827-ac69-d8ba99013329
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1764287851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1764287851
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.927446810
Short name T381
Test name
Test status
Simulation time 2323073148 ps
CPU time 28.31 seconds
Started Apr 16 12:47:35 PM PDT 24
Finished Apr 16 12:48:05 PM PDT 24
Peak memory 216216 kb
Host smart-97c4536d-7bdb-4ab2-a3ba-c77828900ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927446810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.927446810
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.993708597
Short name T427
Test name
Test status
Simulation time 6951082123 ps
CPU time 10.67 seconds
Started Apr 16 12:47:28 PM PDT 24
Finished Apr 16 12:47:41 PM PDT 24
Peak memory 216264 kb
Host smart-934ae686-622e-4fec-a439-64ba80ba212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993708597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.993708597
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2991794067
Short name T395
Test name
Test status
Simulation time 105496311 ps
CPU time 2.8 seconds
Started Apr 16 12:47:30 PM PDT 24
Finished Apr 16 12:47:36 PM PDT 24
Peak memory 216392 kb
Host smart-c099f1fe-0f5d-42e5-85ae-26da7393ce02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991794067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2991794067
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3427038700
Short name T545
Test name
Test status
Simulation time 42590802 ps
CPU time 0.72 seconds
Started Apr 16 12:47:21 PM PDT 24
Finished Apr 16 12:47:24 PM PDT 24
Peak memory 205656 kb
Host smart-966facdc-0c62-4c6b-a21d-17cb2bbe4618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427038700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3427038700
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1480106541
Short name T26
Test name
Test status
Simulation time 33706908 ps
CPU time 0.75 seconds
Started Apr 16 12:47:31 PM PDT 24
Finished Apr 16 12:47:34 PM PDT 24
Peak memory 204816 kb
Host smart-41aab078-fc7f-41c9-a2f7-3bfa7c04f4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480106541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
480106541
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1542383578
Short name T509
Test name
Test status
Simulation time 16258851 ps
CPU time 0.75 seconds
Started Apr 16 12:47:23 PM PDT 24
Finished Apr 16 12:47:26 PM PDT 24
Peak memory 205780 kb
Host smart-edbaeaeb-df5e-4d92-a8d2-67d93c2a7dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542383578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1542383578
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3888457351
Short name T75
Test name
Test status
Simulation time 7053822891 ps
CPU time 15.66 seconds
Started Apr 16 12:47:33 PM PDT 24
Finished Apr 16 12:47:51 PM PDT 24
Peak memory 218512 kb
Host smart-75f09cf0-c1b5-4020-9569-04bed854e2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888457351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3888457351
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1696441456
Short name T224
Test name
Test status
Simulation time 2435503888 ps
CPU time 34.38 seconds
Started Apr 16 12:47:42 PM PDT 24
Finished Apr 16 12:48:19 PM PDT 24
Peak memory 238700 kb
Host smart-94d95a61-84dc-4d53-9272-3d6d954b7c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696441456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1696441456
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3911697287
Short name T90
Test name
Test status
Simulation time 340829048 ps
CPU time 4.92 seconds
Started Apr 16 12:47:32 PM PDT 24
Finished Apr 16 12:47:39 PM PDT 24
Peak memory 221064 kb
Host smart-feec108f-4a67-4dcb-9da3-bb99e5f33061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911697287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3911697287
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.8865502
Short name T718
Test name
Test status
Simulation time 4278157878 ps
CPU time 7.5 seconds
Started Apr 16 12:47:19 PM PDT 24
Finished Apr 16 12:47:29 PM PDT 24
Peak memory 222600 kb
Host smart-9dea581a-8cfb-412a-944c-2ef478003cbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=8865502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.8865502
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2075154397
Short name T383
Test name
Test status
Simulation time 58677173300 ps
CPU time 73.11 seconds
Started Apr 16 12:47:34 PM PDT 24
Finished Apr 16 12:48:49 PM PDT 24
Peak memory 216356 kb
Host smart-681d2374-080b-4d13-a1fb-8b77c1eff15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075154397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2075154397
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3057918255
Short name T474
Test name
Test status
Simulation time 258497359 ps
CPU time 1.25 seconds
Started Apr 16 12:47:29 PM PDT 24
Finished Apr 16 12:47:33 PM PDT 24
Peak memory 207584 kb
Host smart-6b9e4d04-423e-4250-83c0-12c1f5e69c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057918255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3057918255
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.463116554
Short name T1
Test name
Test status
Simulation time 122206001 ps
CPU time 1.09 seconds
Started Apr 16 12:47:29 PM PDT 24
Finished Apr 16 12:47:33 PM PDT 24
Peak memory 207800 kb
Host smart-24b271af-b089-477d-93ca-c8a19e8388b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463116554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.463116554
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4249000392
Short name T446
Test name
Test status
Simulation time 37845912 ps
CPU time 0.8 seconds
Started Apr 16 12:47:25 PM PDT 24
Finished Apr 16 12:47:29 PM PDT 24
Peak memory 205688 kb
Host smart-fd51ade4-901d-45c5-837f-dad3ad8e80d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249000392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4249000392
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2345619966
Short name T221
Test name
Test status
Simulation time 423106529 ps
CPU time 2.3 seconds
Started Apr 16 12:47:11 PM PDT 24
Finished Apr 16 12:47:16 PM PDT 24
Peak memory 219544 kb
Host smart-7df8273b-878e-4a10-8f2e-3a8e22fc88a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345619966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2345619966
Directory /workspace/9.spi_device_upload/latest
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