Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1474271	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1641324

1

T1

172

T2

876

T3

1012

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2425451	1			T1	1		T2	4		T3	297
values[0x0]	344175	1			T1	108		T2	444		T3	455
values[0x1]	345969	1			T1	116		T2	435		T3	436

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1119445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1996150

1

T1

185

T2

878

T3

1043

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9093	1			T1	1		T2	4		T4	20
valid_sources[0x01]	22264	1			T3	13		T4	7		T12	85
valid_sources[0x02]	11013	1			T2	13		T4	5		T12	77
valid_sources[0x03]	9582	1			T2	4		T3	3		T4	3
valid_sources[0x04]	10277	1			T2	7		T4	3		T12	78
valid_sources[0x05]	12959	1			T3	16		T4	9		T12	85
valid_sources[0x06]	19979	1			T4	6		T12	72		T5	30
valid_sources[0x07]	13788	1			T1	2		T4	12		T12	86
valid_sources[0x08]	10942	1			T2	21		T3	1		T4	3
valid_sources[0x09]	10692	1			T2	1		T3	2		T4	12
valid_sources[0x0a]	9654	1			T1	1		T2	14		T3	2
valid_sources[0x0b]	17550	1			T2	11		T3	16		T4	10
valid_sources[0x0c]	11361	1			T4	9		T12	91		T5	33
valid_sources[0x0d]	16776	1			T1	2		T3	16		T4	3
valid_sources[0x0e]	10406	1			T4	11		T12	70		T5	43
valid_sources[0x0f]	8981	1			T1	3		T2	13		T4	15
valid_sources[0x10]	9158	1			T2	8		T3	5		T4	7
valid_sources[0x11]	16371	1			T3	4		T4	5		T12	81
valid_sources[0x12]	17216	1			T1	2		T2	5		T4	7
valid_sources[0x13]	10452	1			T1	2		T2	3		T3	13
valid_sources[0x14]	18412	1			T1	3		T2	2		T3	7
valid_sources[0x15]	10675	1			T4	8		T12	104		T5	35
valid_sources[0x16]	9257	1			T2	9		T3	5		T4	1
valid_sources[0x17]	10470	1			T2	29		T3	1		T4	5
valid_sources[0x18]	9077	1			T3	4		T4	5		T12	76
valid_sources[0x19]	10106	1			T1	2		T2	7		T3	4
valid_sources[0x1a]	16185	1			T4	4		T12	83		T5	45
valid_sources[0x1b]	10021	1			T3	8		T4	2		T12	90
valid_sources[0x1c]	9804	1			T3	9		T4	14		T12	69
valid_sources[0x1d]	18427	1			T2	7		T4	5		T12	85
valid_sources[0x1e]	9068	1			T4	3		T12	70		T5	33
valid_sources[0x1f]	44086	1			T2	6		T3	5		T4	9
valid_sources[0x20]	10200	1			T2	40		T3	1		T4	16
valid_sources[0x21]	9473	1			T3	13		T4	5		T12	86
valid_sources[0x22]	9621	1			T2	4		T3	9		T4	5
valid_sources[0x23]	11820	1			T1	1		T3	11		T4	3
valid_sources[0x24]	17757	1			T2	1		T3	14		T4	7
valid_sources[0x25]	9854	1			T1	9		T4	7		T12	71
valid_sources[0x26]	13131	1			T2	5		T3	5		T4	8
valid_sources[0x27]	26577	1			T2	2		T3	1		T4	5
valid_sources[0x28]	12303	1			T3	6		T4	13		T12	83
valid_sources[0x29]	10437	1			T3	5		T4	13		T12	77
valid_sources[0x2a]	12135	1			T1	1		T2	2		T4	8
valid_sources[0x2b]	9052	1			T3	8		T4	8		T12	96
valid_sources[0x2c]	16321	1			T1	1		T4	8		T12	87
valid_sources[0x2d]	9800	1			T3	10		T4	14		T12	77
valid_sources[0x2e]	11276	1			T1	1		T3	6		T4	3
valid_sources[0x2f]	12638	1			T4	5		T12	81		T5	33
valid_sources[0x30]	9205	1			T3	4		T4	2		T12	98
valid_sources[0x31]	10564	1			T2	11		T4	10		T12	102
valid_sources[0x32]	16095	1			T2	9		T3	1		T4	6
valid_sources[0x33]	8781	1			T2	3		T4	16		T12	84
valid_sources[0x34]	9404	1			T4	15		T12	88		T5	49
valid_sources[0x35]	9310	1			T3	6		T4	5		T12	84
valid_sources[0x36]	10672	1			T2	13		T3	7		T4	11
valid_sources[0x37]	30604	1			T1	3		T3	2		T4	8
valid_sources[0x38]	9403	1			T1	6		T2	8		T4	1
valid_sources[0x39]	18272	1			T2	12		T3	1		T4	4
valid_sources[0x3a]	30163	1			T4	6		T12	75		T5	30
valid_sources[0x3b]	19009	1			T3	5		T4	12		T12	78
valid_sources[0x3c]	9799	1			T4	5		T12	72		T5	17
valid_sources[0x3d]	9019	1			T1	3		T3	9		T4	7
valid_sources[0x3e]	9180	1			T4	6		T12	74		T5	30
valid_sources[0x3f]	8629	1			T2	6		T4	10		T12	78
valid_sources[0x40]	11062	1			T2	8		T4	8		T12	94
valid_sources[0x41]	14893	1			T1	1		T4	7		T12	64
valid_sources[0x42]	8839	1			T3	2		T4	7		T12	84
valid_sources[0x43]	22500	1			T4	16		T12	60		T5	23
valid_sources[0x44]	14700	1			T1	1		T2	4		T3	6
valid_sources[0x45]	10701	1			T1	4		T3	1		T4	5
valid_sources[0x46]	9463	1			T1	2		T2	8		T3	7
valid_sources[0x47]	9328	1			T2	4		T3	14		T4	6
valid_sources[0x48]	8925	1			T2	17		T4	9		T12	82
valid_sources[0x49]	18139	1			T1	1		T3	2		T4	9
valid_sources[0x4a]	15645	1			T2	14		T3	18		T4	2
valid_sources[0x4b]	10990	1			T3	6		T4	1		T12	74
valid_sources[0x4c]	9299	1			T2	1		T3	18		T4	12
valid_sources[0x4d]	11449	1			T1	4		T2	3		T3	12
valid_sources[0x4e]	9559	1			T4	4		T12	94		T5	28
valid_sources[0x4f]	9996	1			T1	3		T2	7		T4	5
valid_sources[0x50]	9112	1			T2	2		T3	1		T4	5
valid_sources[0x51]	10627	1			T4	8		T12	80		T5	32
valid_sources[0x52]	12278	1			T2	8		T3	8		T4	9
valid_sources[0x53]	9230	1			T2	11		T3	25		T4	7
valid_sources[0x54]	9158	1			T1	1		T2	8		T4	12
valid_sources[0x55]	12258	1			T2	2		T3	3		T4	4
valid_sources[0x56]	8864	1			T2	14		T4	12		T12	83
valid_sources[0x57]	9572	1			T1	1		T4	17		T12	89
valid_sources[0x58]	8684	1			T3	12		T4	16		T12	77
valid_sources[0x59]	10865	1			T1	3		T3	7		T4	8
valid_sources[0x5a]	9159	1			T2	1		T3	3		T4	5
valid_sources[0x5b]	10577	1			T3	10		T4	6		T12	85
valid_sources[0x5c]	10162	1			T3	4		T4	6		T12	76
valid_sources[0x5d]	13791	1			T1	1		T3	3		T4	20
valid_sources[0x5e]	10097	1			T2	3		T4	3		T12	93
valid_sources[0x5f]	10145	1			T3	4		T4	5		T12	86
valid_sources[0x60]	8566	1			T2	5		T4	10		T12	96
valid_sources[0x61]	11649	1			T1	2		T2	4		T4	6
valid_sources[0x62]	9369	1			T4	7		T12	75		T5	29
valid_sources[0x63]	9733	1			T3	2		T4	9		T12	83
valid_sources[0x64]	11777	1			T4	10		T12	87		T5	28
valid_sources[0x65]	11981	1			T1	3		T3	7		T4	15
valid_sources[0x66]	10940	1			T2	5		T4	4		T12	91
valid_sources[0x67]	9277	1			T1	7		T2	10		T4	6
valid_sources[0x68]	16186	1			T4	4		T12	65		T5	17
valid_sources[0x69]	19633	1			T3	7		T4	8		T12	74
valid_sources[0x6a]	8457	1			T3	11		T4	6		T12	71
valid_sources[0x6b]	15419	1			T3	6		T4	13		T12	85
valid_sources[0x6c]	10471	1			T1	1		T3	6		T4	12
valid_sources[0x6d]	10201	1			T3	8		T4	7		T12	93
valid_sources[0x6e]	8731	1			T1	5		T3	9		T4	6
valid_sources[0x6f]	9074	1			T3	5		T4	7		T12	97
valid_sources[0x70]	10343	1			T3	1		T4	14		T12	73
valid_sources[0x71]	10490	1			T3	9		T4	10		T12	70
valid_sources[0x72]	10021	1			T3	1		T4	8		T12	74
valid_sources[0x73]	9411	1			T1	1		T2	8		T3	2
valid_sources[0x74]	20729	1			T1	11		T3	1		T4	8
valid_sources[0x75]	11642	1			T3	6		T4	12		T12	83
valid_sources[0x76]	9795	1			T1	6		T2	3		T4	7
valid_sources[0x77]	10931	1			T2	17		T3	14		T4	10
valid_sources[0x78]	9157	1			T1	5		T3	7		T4	6
valid_sources[0x79]	13439	1			T3	10		T4	3		T12	83
valid_sources[0x7a]	10158	1			T2	10		T4	3		T12	80
valid_sources[0x7b]	13524	1			T1	9		T4	10		T12	89
valid_sources[0x7c]	9931	1			T3	1		T4	6		T12	94
valid_sources[0x7d]	10458	1			T1	9		T4	7		T12	84
valid_sources[0x7e]	9952	1			T2	2		T3	19		T4	10
valid_sources[0x7f]	9912	1			T1	1		T3	8		T4	4
valid_sources[0x80]	9410	1			T4	2		T12	94		T5	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018738

1

T1

1

T2

1

T3

134

values[0x0]

all_enables

biggest_size

314217

1

T1

78

T2

442

T3

451

values[0x1]

all_enables

biggest_size

308369

1

T1

93

T2

433

T3

427