Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1496146

1

T1

53

T2

7

T3

176

full_word

1642579

1

T1

172

T2

876

T3

1012

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3138305	1			T1	225		T2	883		T3	1188
auto[TlIntgErrCmd]	117	1			T35	7		T108	6		T112	9
auto[TlIntgErrData]	157	1			T35	5		T108	11		T112	5
auto[TlIntgErrBoth]	146	1			T35	8		T108	3		T112	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2429107

1

T1

1

T2

4

T3

297

auto[1]

709618

1

T1

224

T2

879

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1409888	1			T2	3		T3	163		T4	588
auto[TlIntgErrNone]	partial	auto[1]	85879	1			T1	53		T2	4		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	1019027	1			T1	1		T2	1		T3	134
auto[TlIntgErrNone]	full_word	auto[1]	623511	1			T1	171		T2	875		T3	878
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T35	3		T112	6		T345	2
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T35	4		T108	6		T112	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T112	1		T348	1		T350	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T348	1		T351	2		T350	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T35	2		T108	4		T112	3
auto[TlIntgErrData]	partial	auto[1]	71	1			T35	3		T108	5		T112	2
auto[TlIntgErrData]	full_word	auto[0]	13	1			T108	2		T345	1		T347	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T345	2		T347	2		T350	1
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T35	6		T108	1		T112	2
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T35	1		T108	2		T112	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T35	1		T346	1		T352	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T112	1		T345	2		T348	1