Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	98.94	91.20		91.67	95.48	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.36	85.00	45.45			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.01	94.03	70.69			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37924082	5623154	0	0
DepthKnown_A	37924082	24745869	0	0
RvalidKnown_A	37924082	24745869	0	0
WreadyKnown_A	37924082	24745869	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37924082	5623154	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	5623154	0	0
T3	13788	12590	0	0
T4	4998	4654	0	0
T5	129127	44390	0	0
T6	134392	24560	0	0
T7	113694	0	0	0
T8	75095	11848	0	0
T9	146272	11086	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0
T18	0	58684	0	0
T43	0	7945	0	0
T73	0	14223	0	0
T74	0	16104	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	5623154	0	0
T3	13788	12590	0	0
T4	4998	4654	0	0
T5	129127	44390	0	0
T6	134392	24560	0	0
T7	113694	0	0	0
T8	75095	11848	0	0
T9	146272	11086	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0
T18	0	58684	0	0
T43	0	7945	0	0
T73	0	14223	0	0
T74	0	16104	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T3,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T3,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T5

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37924082	5928758	0	0
DepthKnown_A	37924082	24745869	0	0
RvalidKnown_A	37924082	24745869	0	0
WreadyKnown_A	37924082	24745869	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37924082	5928758	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	5928758	0	0
T3	13788	13508	0	0
T4	4998	4870	0	0
T5	129127	48452	0	0
T6	134392	27012	0	0
T7	113694	0	0	0
T8	75095	12350	0	0
T9	146272	11440	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0
T18	0	61808	0	0
T43	0	8198	0	0
T73	0	15059	0	0
T74	0	16888	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	5928758	0	0
T3	13788	13508	0	0
T4	4998	4870	0	0
T5	129127	48452	0	0
T6	134392	27012	0	0
T7	113694	0	0	0
T8	75095	12350	0	0
T9	146272	11440	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0
T18	0	61808	0	0
T43	0	8198	0	0
T73	0	15059	0	0
T74	0	16888	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37924082	0	0	0
DepthKnown_A	37924082	24745869	0	0
RvalidKnown_A	37924082	24745869	0	0
WreadyKnown_A	37924082	24745869	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37924082	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	24745869	0	0
T2	61388	61388	0	0
T3	13788	13788	0	0
T4	4998	4998	0	0
T5	129127	129044	0	0
T6	134392	134056	0	0
T7	113694	5	0	0
T8	75095	74600	0	0
T9	0	146272	0	0
T10	0	22096	0	0
T11	0	58368	0	0
T12	179082	0	0	0
T13	402555	0	0	0
T14	119489	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T12,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Not Covered
1	1	Covered	T12,T13,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T12,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T17
1	0	1	Covered	T12,T13,T17
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T17

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T17

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T17

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T12,T13,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T12,T7
0	0	Covered	T1,T12,T7

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37924082	2242800	0	0
DepthKnown_A	37924082	12635936	0	0
RvalidKnown_A	37924082	12635936	0	0
WreadyKnown_A	37924082	12635936	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37924082	2242800	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	2242800	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	0	0	0
T8	75095	0	0	0
T9	146272	0	0	0
T10	22262	0	0	0
T12	179082	80756	0	0
T13	402555	101428	0	0
T14	119489	0	0	0
T17	3024	1221	0	0
T48	0	38	0	0
T49	0	58084	0	0
T51	0	205	0	0
T52	0	1707	0	0
T53	0	2835	0	0
T54	0	1447	0	0
T55	0	842	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	12635936	0	0
T1	81137	75888	0	0
T2	61388	0	0	0
T3	13788	0	0	0
T4	4998	0	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	107120	0	0
T8	75095	0	0	0
T12	179082	170688	0	0
T13	402555	393480	0	0
T14	0	113608	0	0
T17	0	3024	0	0
T21	0	432	0	0
T48	0	152	0	0
T49	0	154256	0	0
T50	0	20640	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	12635936	0	0
T1	81137	75888	0	0
T2	61388	0	0	0
T3	13788	0	0	0
T4	4998	0	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	107120	0	0
T8	75095	0	0	0
T12	179082	170688	0	0
T13	402555	393480	0	0
T14	0	113608	0	0
T17	0	3024	0	0
T21	0	432	0	0
T48	0	152	0	0
T49	0	154256	0	0
T50	0	20640	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	12635936	0	0
T1	81137	75888	0	0
T2	61388	0	0	0
T3	13788	0	0	0
T4	4998	0	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	107120	0	0
T8	75095	0	0	0
T12	179082	170688	0	0
T13	402555	393480	0	0
T14	0	113608	0	0
T17	0	3024	0	0
T21	0	432	0	0
T48	0	152	0	0
T49	0	154256	0	0
T50	0	20640	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	2242800	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	0	0	0
T8	75095	0	0	0
T9	146272	0	0	0
T10	22262	0	0	0
T12	179082	80756	0	0
T13	402555	101428	0	0
T14	119489	0	0	0
T17	3024	1221	0	0
T48	0	38	0	0
T49	0	58084	0	0
T51	0	205	0	0
T52	0	1707	0	0
T53	0	2835	0	0
T54	0	1447	0	0
T55	0	842	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T12,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T7
1	0	Not Covered
1	1	Covered	T12,T13,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T12,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T12,T13,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T13,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T12,T7
0	0	Covered	T1,T12,T7

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37924082	72101	0	0
DepthKnown_A	37924082	12635936	0	0
RvalidKnown_A	37924082	12635936	0	0
WreadyKnown_A	37924082	12635936	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37924082	72101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	72101	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	0	0	0
T8	75095	0	0	0
T9	146272	0	0	0
T10	22262	0	0	0
T12	179082	2595	0	0
T13	402555	3259	0	0
T14	119489	0	0	0
T17	3024	40	0	0
T48	0	1	0	0
T49	0	1873	0	0
T51	0	6	0	0
T52	0	54	0	0
T53	0	92	0	0
T54	0	46	0	0
T55	0	27	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	12635936	0	0
T1	81137	75888	0	0
T2	61388	0	0	0
T3	13788	0	0	0
T4	4998	0	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	107120	0	0
T8	75095	0	0	0
T12	179082	170688	0	0
T13	402555	393480	0	0
T14	0	113608	0	0
T17	0	3024	0	0
T21	0	432	0	0
T48	0	152	0	0
T49	0	154256	0	0
T50	0	20640	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	12635936	0	0
T1	81137	75888	0	0
T2	61388	0	0	0
T3	13788	0	0	0
T4	4998	0	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	107120	0	0
T8	75095	0	0	0
T12	179082	170688	0	0
T13	402555	393480	0	0
T14	0	113608	0	0
T17	0	3024	0	0
T21	0	432	0	0
T48	0	152	0	0
T49	0	154256	0	0
T50	0	20640	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	12635936	0	0
T1	81137	75888	0	0
T2	61388	0	0	0
T3	13788	0	0	0
T4	4998	0	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	107120	0	0
T8	75095	0	0	0
T12	179082	170688	0	0
T13	402555	393480	0	0
T14	0	113608	0	0
T17	0	3024	0	0
T21	0	432	0	0
T48	0	152	0	0
T49	0	154256	0	0
T50	0	20640	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37924082	72101	0	0
T5	129127	0	0	0
T6	134392	0	0	0
T7	113694	0	0	0
T8	75095	0	0	0
T9	146272	0	0	0
T10	22262	0	0	0
T12	179082	2595	0	0
T13	402555	3259	0	0
T14	119489	0	0	0
T17	3024	40	0	0
T48	0	1	0	0
T49	0	1873	0	0
T51	0	6	0	0
T52	0	54	0	0
T53	0	92	0	0
T54	0	46	0	0
T55	0	27	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T6,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	125316427	454695	0	0
DepthKnown_A	125316427	125257531	0	0
RvalidKnown_A	125316427	125257531	0	0
WreadyKnown_A	125316427	125257531	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	125316427	454695	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	454695	0	0
T2	68634	832	0	0
T3	10632	832	0	0
T4	27705	832	0	0
T5	132487	832	0	0
T6	811794	832	0	0
T7	109188	0	0	0
T8	526536	832	0	0
T9	0	832	0	0
T10	0	2718	0	0
T11	0	832	0	0
T12	107822	0	0	0
T15	1121	0	0	0
T16	5661	0	0	0
T18	0	3697	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	454695	0	0
T2	68634	832	0	0
T3	10632	832	0	0
T4	27705	832	0	0
T5	132487	832	0	0
T6	811794	832	0	0
T7	109188	0	0	0
T8	526536	832	0	0
T9	0	832	0	0
T10	0	2718	0	0
T11	0	832	0	0
T12	107822	0	0	0
T15	1121	0	0	0
T16	5661	0	0	0
T18	0	3697	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	125316427	0	0	0
DepthKnown_A	125316427	125257531	0	0
RvalidKnown_A	125316427	125257531	0	0
WreadyKnown_A	125316427	125257531	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	125316427	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	125316427	0	0	0
DepthKnown_A	125316427	125257531	0	0
RvalidKnown_A	125316427	125257531	0	0
WreadyKnown_A	125316427	125257531	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	125316427	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T13,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T13,T17,T49
1	1	0	Not Covered
1	1	1	Covered	T12,T13,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T12,T13,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T13,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T12,T13,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	125316427	88366	0	0
DepthKnown_A	125316427	125257531	0	0
RvalidKnown_A	125316427	125257531	0	0
WreadyKnown_A	125316427	125257531	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	125316427	88366	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	88366	0	0
T5	132487	0	0	0
T6	811794	0	0	0
T7	109188	0	0	0
T8	526536	0	0	0
T9	589010	0	0	0
T12	107822	1304	0	0
T13	498865	4170	0	0
T14	60015	0	0	0
T16	5661	0	0	0
T17	0	98	0	0
T19	4531	0	0	0
T48	0	1	0	0
T49	0	4206	0	0
T51	0	176	0	0
T52	0	17	0	0
T53	0	21	0	0
T54	0	41	0	0
T55	0	48	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	125257531	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	125316427	88366	0	0
T5	132487	0	0	0
T6	811794	0	0	0
T7	109188	0	0	0
T8	526536	0	0	0
T9	589010	0	0	0
T12	107822	1304	0	0
T13	498865	4170	0	0
T14	60015	0	0	0
T16	5661	0	0	0
T17	0	98	0	0
T19	4531	0	0	0
T48	0	1	0	0
T49	0	4206	0	0
T51	0	176	0	0
T52	0	17	0	0
T53	0	21	0	0
T54	0	41	0	0
T55	0	48	0	0