Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127681774	3007275	0	0
DepthKnown_A	127681774	127576274	0	0
RvalidKnown_A	127681774	127576274	0	0
WreadyKnown_A	127681774	127576274	0	0
gen_passthru_fifo.paramCheckPass	824	824	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	3007275	0	0
T1	37002	225	0	0
T2	68634	51	0	0
T3	10632	356	0	0
T4	27705	1208	0	0
T5	132487	7787	0	0
T6	811794	89	0	0
T7	109188	629	0	0
T12	107822	19747	0	0
T15	1121	16	0	0
T16	5661	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	127576274	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	127576274	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	127576274	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	127681774	5272509	0	0
DepthKnown_A	127681774	127576274	0	0
RvalidKnown_A	127681774	127576274	0	0
WreadyKnown_A	127681774	127576274	0	0
gen_passthru_fifo.paramCheckPass	824	824	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	5272509	0	0
T1	37002	979	0	0
T2	68634	51	0	0
T3	10632	356	0	0
T4	27705	1208	0	0
T5	132487	7787	0	0
T6	811794	89	0	0
T7	109188	1864	0	0
T12	107822	19613	0	0
T15	1121	16	0	0
T16	5661	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	127576274	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	127576274	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127681774	127576274	0	0
T1	37002	36924	0	0
T2	68634	68579	0	0
T3	10632	10532	0	0
T4	27705	27626	0	0
T5	132487	132426	0	0
T6	811794	811712	0	0
T7	109188	109132	0	0
T12	107822	107813	0	0
T15	1121	1047	0	0
T16	5661	4131	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	824	824	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0