Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
3821 |
0 |
0 |
T33 |
13628 |
229 |
0 |
0 |
T34 |
15290 |
16 |
0 |
0 |
T35 |
20432 |
1 |
0 |
0 |
T107 |
9468 |
4 |
0 |
0 |
T108 |
68110 |
2 |
0 |
0 |
T112 |
71864 |
3 |
0 |
0 |
T113 |
12004 |
3 |
0 |
0 |
T114 |
2319 |
108 |
0 |
0 |
T115 |
3534 |
161 |
0 |
0 |
T119 |
5514 |
278 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2593 |
0 |
0 |
T34 |
15290 |
7 |
0 |
0 |
T36 |
12844 |
43 |
0 |
0 |
T108 |
68110 |
58 |
0 |
0 |
T112 |
71864 |
73 |
0 |
0 |
T113 |
12004 |
21 |
0 |
0 |
T125 |
181242 |
454 |
0 |
0 |
T132 |
117629 |
699 |
0 |
0 |
T134 |
11671 |
12 |
0 |
0 |
T136 |
6572 |
15 |
0 |
0 |
T143 |
13033 |
40 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2535 |
0 |
0 |
T34 |
15290 |
7 |
0 |
0 |
T36 |
12844 |
14 |
0 |
0 |
T108 |
68110 |
72 |
0 |
0 |
T112 |
71864 |
78 |
0 |
0 |
T113 |
12004 |
13 |
0 |
0 |
T125 |
181242 |
453 |
0 |
0 |
T132 |
117629 |
705 |
0 |
0 |
T134 |
11671 |
12 |
0 |
0 |
T136 |
6572 |
7 |
0 |
0 |
T143 |
13033 |
42 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
3277 |
0 |
0 |
T34 |
15290 |
20 |
0 |
0 |
T36 |
12844 |
43 |
0 |
0 |
T108 |
68110 |
130 |
0 |
0 |
T112 |
71864 |
169 |
0 |
0 |
T113 |
12004 |
14 |
0 |
0 |
T125 |
181242 |
462 |
0 |
0 |
T132 |
117629 |
755 |
0 |
0 |
T134 |
11671 |
34 |
0 |
0 |
T136 |
6572 |
15 |
0 |
0 |
T143 |
13033 |
36 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
10854 |
0 |
0 |
T34 |
15290 |
118 |
0 |
0 |
T36 |
12844 |
30 |
0 |
0 |
T108 |
68110 |
1277 |
0 |
0 |
T112 |
71864 |
858 |
0 |
0 |
T113 |
12004 |
244 |
0 |
0 |
T125 |
181242 |
427 |
0 |
0 |
T132 |
117629 |
833 |
0 |
0 |
T134 |
11671 |
137 |
0 |
0 |
T136 |
6572 |
3 |
0 |
0 |
T143 |
13033 |
44 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
10339 |
0 |
0 |
T34 |
15290 |
102 |
0 |
0 |
T36 |
12844 |
25 |
0 |
0 |
T108 |
68110 |
1054 |
0 |
0 |
T112 |
71864 |
812 |
0 |
0 |
T113 |
12004 |
269 |
0 |
0 |
T125 |
181242 |
444 |
0 |
0 |
T132 |
117629 |
758 |
0 |
0 |
T134 |
11671 |
231 |
0 |
0 |
T136 |
6572 |
110 |
0 |
0 |
T143 |
13033 |
24 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
13073 |
0 |
0 |
T34 |
15290 |
113 |
0 |
0 |
T36 |
12844 |
11 |
0 |
0 |
T108 |
68110 |
1665 |
0 |
0 |
T112 |
71864 |
1505 |
0 |
0 |
T113 |
12004 |
146 |
0 |
0 |
T125 |
181242 |
484 |
0 |
0 |
T132 |
117629 |
815 |
0 |
0 |
T134 |
11671 |
351 |
0 |
0 |
T136 |
6572 |
210 |
0 |
0 |
T143 |
13033 |
34 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
12711 |
0 |
0 |
T34 |
15290 |
192 |
0 |
0 |
T36 |
12844 |
24 |
0 |
0 |
T108 |
68110 |
1121 |
0 |
0 |
T112 |
71864 |
1636 |
0 |
0 |
T113 |
12004 |
131 |
0 |
0 |
T125 |
181242 |
456 |
0 |
0 |
T132 |
117629 |
696 |
0 |
0 |
T134 |
11671 |
296 |
0 |
0 |
T136 |
6572 |
129 |
0 |
0 |
T143 |
13033 |
20 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
11464 |
0 |
0 |
T34 |
15290 |
189 |
0 |
0 |
T36 |
12844 |
76 |
0 |
0 |
T108 |
68110 |
1168 |
0 |
0 |
T112 |
71864 |
1004 |
0 |
0 |
T113 |
12004 |
228 |
0 |
0 |
T125 |
181242 |
422 |
0 |
0 |
T132 |
117629 |
774 |
0 |
0 |
T134 |
11671 |
252 |
0 |
0 |
T136 |
6572 |
12 |
0 |
0 |
T143 |
13033 |
9 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
11297 |
0 |
0 |
T34 |
15290 |
107 |
0 |
0 |
T36 |
12844 |
22 |
0 |
0 |
T108 |
68110 |
1201 |
0 |
0 |
T112 |
71864 |
1166 |
0 |
0 |
T113 |
12004 |
279 |
0 |
0 |
T125 |
181242 |
478 |
0 |
0 |
T132 |
117629 |
715 |
0 |
0 |
T134 |
11671 |
126 |
0 |
0 |
T136 |
6572 |
14 |
0 |
0 |
T143 |
13033 |
11 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
10828 |
0 |
0 |
T34 |
15290 |
75 |
0 |
0 |
T36 |
12844 |
24 |
0 |
0 |
T108 |
68110 |
944 |
0 |
0 |
T112 |
71864 |
1478 |
0 |
0 |
T113 |
12004 |
135 |
0 |
0 |
T125 |
181242 |
427 |
0 |
0 |
T132 |
117629 |
729 |
0 |
0 |
T134 |
11671 |
274 |
0 |
0 |
T136 |
6572 |
10 |
0 |
0 |
T143 |
13033 |
31 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
11563 |
0 |
0 |
T34 |
15290 |
99 |
0 |
0 |
T36 |
12844 |
54 |
0 |
0 |
T108 |
68110 |
1203 |
0 |
0 |
T112 |
71864 |
1287 |
0 |
0 |
T113 |
12004 |
164 |
0 |
0 |
T125 |
181242 |
453 |
0 |
0 |
T132 |
117629 |
780 |
0 |
0 |
T134 |
11671 |
158 |
0 |
0 |
T136 |
6572 |
148 |
0 |
0 |
T143 |
13033 |
27 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6547 |
0 |
0 |
T34 |
15290 |
36 |
0 |
0 |
T36 |
12844 |
60 |
0 |
0 |
T108 |
68110 |
545 |
0 |
0 |
T112 |
71864 |
685 |
0 |
0 |
T113 |
12004 |
12 |
0 |
0 |
T125 |
181242 |
454 |
0 |
0 |
T132 |
117629 |
725 |
0 |
0 |
T134 |
11671 |
49 |
0 |
0 |
T137 |
104623 |
422 |
0 |
0 |
T143 |
13033 |
26 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6167 |
0 |
0 |
T34 |
15290 |
56 |
0 |
0 |
T36 |
12844 |
50 |
0 |
0 |
T108 |
68110 |
823 |
0 |
0 |
T112 |
71864 |
492 |
0 |
0 |
T113 |
12004 |
17 |
0 |
0 |
T125 |
181242 |
448 |
0 |
0 |
T132 |
117629 |
778 |
0 |
0 |
T134 |
11671 |
147 |
0 |
0 |
T136 |
6572 |
36 |
0 |
0 |
T143 |
13033 |
34 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
5909 |
0 |
0 |
T34 |
15290 |
37 |
0 |
0 |
T36 |
12844 |
21 |
0 |
0 |
T108 |
68110 |
421 |
0 |
0 |
T112 |
71864 |
466 |
0 |
0 |
T113 |
12004 |
12 |
0 |
0 |
T125 |
181242 |
493 |
0 |
0 |
T132 |
117629 |
776 |
0 |
0 |
T134 |
11671 |
109 |
0 |
0 |
T136 |
6572 |
48 |
0 |
0 |
T143 |
13033 |
37 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6562 |
0 |
0 |
T34 |
15290 |
52 |
0 |
0 |
T36 |
12844 |
25 |
0 |
0 |
T108 |
68110 |
569 |
0 |
0 |
T112 |
71864 |
660 |
0 |
0 |
T113 |
12004 |
71 |
0 |
0 |
T125 |
181242 |
461 |
0 |
0 |
T132 |
117629 |
777 |
0 |
0 |
T134 |
11671 |
121 |
0 |
0 |
T136 |
6572 |
52 |
0 |
0 |
T143 |
13033 |
20 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6409 |
0 |
0 |
T34 |
15290 |
47 |
0 |
0 |
T36 |
12844 |
65 |
0 |
0 |
T108 |
68110 |
439 |
0 |
0 |
T112 |
71864 |
595 |
0 |
0 |
T113 |
12004 |
6 |
0 |
0 |
T125 |
181242 |
488 |
0 |
0 |
T132 |
117629 |
723 |
0 |
0 |
T134 |
11671 |
57 |
0 |
0 |
T136 |
6572 |
98 |
0 |
0 |
T143 |
13033 |
25 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6296 |
0 |
0 |
T34 |
15290 |
65 |
0 |
0 |
T36 |
12844 |
66 |
0 |
0 |
T108 |
68110 |
446 |
0 |
0 |
T112 |
71864 |
525 |
0 |
0 |
T113 |
12004 |
59 |
0 |
0 |
T125 |
181242 |
456 |
0 |
0 |
T132 |
117629 |
777 |
0 |
0 |
T134 |
11671 |
102 |
0 |
0 |
T136 |
6572 |
33 |
0 |
0 |
T143 |
13033 |
41 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6463 |
0 |
0 |
T34 |
15290 |
22 |
0 |
0 |
T36 |
12844 |
30 |
0 |
0 |
T108 |
68110 |
576 |
0 |
0 |
T112 |
71864 |
495 |
0 |
0 |
T113 |
12004 |
90 |
0 |
0 |
T125 |
181242 |
398 |
0 |
0 |
T132 |
117629 |
698 |
0 |
0 |
T134 |
11671 |
55 |
0 |
0 |
T136 |
6572 |
36 |
0 |
0 |
T143 |
13033 |
51 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6148 |
0 |
0 |
T34 |
15290 |
81 |
0 |
0 |
T36 |
12844 |
33 |
0 |
0 |
T108 |
68110 |
490 |
0 |
0 |
T112 |
71864 |
459 |
0 |
0 |
T113 |
12004 |
58 |
0 |
0 |
T125 |
181242 |
461 |
0 |
0 |
T132 |
117629 |
691 |
0 |
0 |
T134 |
11671 |
13 |
0 |
0 |
T136 |
6572 |
36 |
0 |
0 |
T143 |
13033 |
17 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6161 |
0 |
0 |
T34 |
15290 |
104 |
0 |
0 |
T36 |
12844 |
43 |
0 |
0 |
T108 |
68110 |
441 |
0 |
0 |
T112 |
71864 |
680 |
0 |
0 |
T113 |
12004 |
94 |
0 |
0 |
T125 |
181242 |
417 |
0 |
0 |
T132 |
117629 |
725 |
0 |
0 |
T134 |
11671 |
131 |
0 |
0 |
T136 |
6572 |
76 |
0 |
0 |
T143 |
13033 |
7 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
5729 |
0 |
0 |
T34 |
15290 |
50 |
0 |
0 |
T36 |
12844 |
32 |
0 |
0 |
T108 |
68110 |
633 |
0 |
0 |
T112 |
71864 |
329 |
0 |
0 |
T113 |
12004 |
18 |
0 |
0 |
T125 |
181242 |
463 |
0 |
0 |
T132 |
117629 |
742 |
0 |
0 |
T134 |
11671 |
89 |
0 |
0 |
T136 |
6572 |
45 |
0 |
0 |
T143 |
13033 |
21 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6236 |
0 |
0 |
T34 |
15290 |
67 |
0 |
0 |
T36 |
12844 |
7 |
0 |
0 |
T108 |
68110 |
591 |
0 |
0 |
T112 |
71864 |
459 |
0 |
0 |
T113 |
12004 |
89 |
0 |
0 |
T125 |
181242 |
446 |
0 |
0 |
T132 |
117629 |
717 |
0 |
0 |
T134 |
11671 |
115 |
0 |
0 |
T136 |
6572 |
121 |
0 |
0 |
T143 |
13033 |
3 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6488 |
0 |
0 |
T34 |
15290 |
72 |
0 |
0 |
T36 |
12844 |
41 |
0 |
0 |
T108 |
68110 |
739 |
0 |
0 |
T112 |
71864 |
537 |
0 |
0 |
T113 |
12004 |
78 |
0 |
0 |
T125 |
181242 |
442 |
0 |
0 |
T132 |
117629 |
680 |
0 |
0 |
T134 |
11671 |
151 |
0 |
0 |
T136 |
6572 |
53 |
0 |
0 |
T143 |
13033 |
30 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
5936 |
0 |
0 |
T34 |
15290 |
53 |
0 |
0 |
T36 |
12844 |
16 |
0 |
0 |
T108 |
68110 |
485 |
0 |
0 |
T112 |
71864 |
638 |
0 |
0 |
T113 |
12004 |
71 |
0 |
0 |
T125 |
181242 |
445 |
0 |
0 |
T132 |
117629 |
710 |
0 |
0 |
T134 |
11671 |
37 |
0 |
0 |
T136 |
6572 |
11 |
0 |
0 |
T143 |
13033 |
12 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6173 |
0 |
0 |
T34 |
15290 |
11 |
0 |
0 |
T36 |
12844 |
82 |
0 |
0 |
T108 |
68110 |
599 |
0 |
0 |
T112 |
71864 |
388 |
0 |
0 |
T113 |
12004 |
113 |
0 |
0 |
T125 |
181242 |
455 |
0 |
0 |
T132 |
117629 |
709 |
0 |
0 |
T134 |
11671 |
37 |
0 |
0 |
T136 |
6572 |
85 |
0 |
0 |
T143 |
13033 |
20 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6022 |
0 |
0 |
T34 |
15290 |
45 |
0 |
0 |
T36 |
12844 |
15 |
0 |
0 |
T108 |
68110 |
563 |
0 |
0 |
T112 |
71864 |
629 |
0 |
0 |
T113 |
12004 |
79 |
0 |
0 |
T125 |
181242 |
460 |
0 |
0 |
T132 |
117629 |
787 |
0 |
0 |
T134 |
11671 |
58 |
0 |
0 |
T136 |
6572 |
10 |
0 |
0 |
T143 |
13033 |
34 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6340 |
0 |
0 |
T34 |
15290 |
16 |
0 |
0 |
T36 |
12844 |
40 |
0 |
0 |
T108 |
68110 |
496 |
0 |
0 |
T112 |
71864 |
710 |
0 |
0 |
T113 |
12004 |
71 |
0 |
0 |
T125 |
181242 |
434 |
0 |
0 |
T132 |
117629 |
717 |
0 |
0 |
T134 |
11671 |
82 |
0 |
0 |
T136 |
6572 |
83 |
0 |
0 |
T143 |
13033 |
29 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6133 |
0 |
0 |
T34 |
15290 |
37 |
0 |
0 |
T36 |
12844 |
79 |
0 |
0 |
T108 |
68110 |
486 |
0 |
0 |
T112 |
71864 |
413 |
0 |
0 |
T113 |
12004 |
89 |
0 |
0 |
T125 |
181242 |
464 |
0 |
0 |
T132 |
117629 |
775 |
0 |
0 |
T134 |
11671 |
94 |
0 |
0 |
T136 |
6572 |
59 |
0 |
0 |
T143 |
13033 |
27 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6014 |
0 |
0 |
T34 |
15290 |
25 |
0 |
0 |
T36 |
12844 |
45 |
0 |
0 |
T108 |
68110 |
481 |
0 |
0 |
T112 |
71864 |
429 |
0 |
0 |
T113 |
12004 |
62 |
0 |
0 |
T125 |
181242 |
430 |
0 |
0 |
T132 |
117629 |
672 |
0 |
0 |
T134 |
11671 |
62 |
0 |
0 |
T136 |
6572 |
93 |
0 |
0 |
T143 |
13033 |
8 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6132 |
0 |
0 |
T34 |
15290 |
78 |
0 |
0 |
T36 |
12844 |
35 |
0 |
0 |
T108 |
68110 |
759 |
0 |
0 |
T112 |
71864 |
575 |
0 |
0 |
T113 |
12004 |
6 |
0 |
0 |
T125 |
181242 |
455 |
0 |
0 |
T132 |
117629 |
715 |
0 |
0 |
T134 |
11671 |
65 |
0 |
0 |
T136 |
6572 |
48 |
0 |
0 |
T143 |
13033 |
36 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6879 |
0 |
0 |
T34 |
15290 |
67 |
0 |
0 |
T36 |
12844 |
35 |
0 |
0 |
T108 |
68110 |
492 |
0 |
0 |
T112 |
71864 |
637 |
0 |
0 |
T113 |
12004 |
81 |
0 |
0 |
T125 |
181242 |
484 |
0 |
0 |
T132 |
117629 |
743 |
0 |
0 |
T134 |
11671 |
121 |
0 |
0 |
T136 |
6572 |
9 |
0 |
0 |
T143 |
13033 |
17 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6679 |
0 |
0 |
T34 |
15290 |
33 |
0 |
0 |
T36 |
12844 |
27 |
0 |
0 |
T108 |
68110 |
593 |
0 |
0 |
T112 |
71864 |
583 |
0 |
0 |
T113 |
12004 |
64 |
0 |
0 |
T125 |
181242 |
460 |
0 |
0 |
T132 |
117629 |
784 |
0 |
0 |
T134 |
11671 |
53 |
0 |
0 |
T136 |
6572 |
35 |
0 |
0 |
T143 |
13033 |
2 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6138 |
0 |
0 |
T34 |
15290 |
64 |
0 |
0 |
T36 |
12844 |
23 |
0 |
0 |
T108 |
68110 |
544 |
0 |
0 |
T112 |
71864 |
665 |
0 |
0 |
T113 |
12004 |
77 |
0 |
0 |
T125 |
181242 |
471 |
0 |
0 |
T132 |
117629 |
700 |
0 |
0 |
T134 |
11671 |
60 |
0 |
0 |
T136 |
6572 |
47 |
0 |
0 |
T143 |
13033 |
28 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
5689 |
0 |
0 |
T34 |
15290 |
88 |
0 |
0 |
T36 |
12844 |
37 |
0 |
0 |
T108 |
68110 |
375 |
0 |
0 |
T112 |
71864 |
417 |
0 |
0 |
T113 |
12004 |
110 |
0 |
0 |
T125 |
181242 |
414 |
0 |
0 |
T132 |
117629 |
792 |
0 |
0 |
T134 |
11671 |
61 |
0 |
0 |
T136 |
6572 |
52 |
0 |
0 |
T143 |
13033 |
37 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
6422 |
0 |
0 |
T34 |
15290 |
85 |
0 |
0 |
T36 |
12844 |
52 |
0 |
0 |
T108 |
68110 |
714 |
0 |
0 |
T112 |
71864 |
618 |
0 |
0 |
T113 |
12004 |
12 |
0 |
0 |
T125 |
181242 |
438 |
0 |
0 |
T132 |
117629 |
764 |
0 |
0 |
T134 |
11671 |
57 |
0 |
0 |
T136 |
6572 |
10 |
0 |
0 |
T137 |
104623 |
427 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2989 |
0 |
0 |
T34 |
15290 |
24 |
0 |
0 |
T36 |
12844 |
80 |
0 |
0 |
T108 |
68110 |
114 |
0 |
0 |
T112 |
71864 |
120 |
0 |
0 |
T113 |
12004 |
13 |
0 |
0 |
T125 |
181242 |
465 |
0 |
0 |
T132 |
117629 |
808 |
0 |
0 |
T134 |
11671 |
15 |
0 |
0 |
T136 |
6572 |
16 |
0 |
0 |
T143 |
13033 |
5 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2907 |
0 |
0 |
T34 |
15290 |
4 |
0 |
0 |
T36 |
12844 |
98 |
0 |
0 |
T108 |
68110 |
108 |
0 |
0 |
T112 |
71864 |
85 |
0 |
0 |
T113 |
12004 |
11 |
0 |
0 |
T125 |
181242 |
454 |
0 |
0 |
T132 |
117629 |
682 |
0 |
0 |
T134 |
11671 |
21 |
0 |
0 |
T136 |
6572 |
19 |
0 |
0 |
T143 |
13033 |
29 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2972 |
0 |
0 |
T34 |
15290 |
24 |
0 |
0 |
T36 |
12844 |
58 |
0 |
0 |
T108 |
68110 |
146 |
0 |
0 |
T112 |
71864 |
118 |
0 |
0 |
T113 |
12004 |
15 |
0 |
0 |
T125 |
181242 |
457 |
0 |
0 |
T132 |
117629 |
748 |
0 |
0 |
T134 |
11671 |
14 |
0 |
0 |
T136 |
6572 |
5 |
0 |
0 |
T143 |
13033 |
35 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2724 |
0 |
0 |
T34 |
15290 |
21 |
0 |
0 |
T36 |
12844 |
30 |
0 |
0 |
T108 |
68110 |
109 |
0 |
0 |
T112 |
71864 |
105 |
0 |
0 |
T113 |
12004 |
10 |
0 |
0 |
T125 |
181242 |
450 |
0 |
0 |
T132 |
117629 |
702 |
0 |
0 |
T134 |
11671 |
14 |
0 |
0 |
T136 |
6572 |
14 |
0 |
0 |
T143 |
13033 |
16 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
3549 |
0 |
0 |
T34 |
15290 |
43 |
0 |
0 |
T36 |
12844 |
15 |
0 |
0 |
T108 |
68110 |
159 |
0 |
0 |
T112 |
71864 |
186 |
0 |
0 |
T113 |
12004 |
41 |
0 |
0 |
T125 |
181242 |
506 |
0 |
0 |
T132 |
117629 |
745 |
0 |
0 |
T134 |
11671 |
22 |
0 |
0 |
T136 |
6572 |
15 |
0 |
0 |
T143 |
13033 |
15 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
4901 |
0 |
0 |
T34 |
0 |
60 |
0 |
0 |
T36 |
0 |
47 |
0 |
0 |
T39 |
6279 |
21 |
0 |
0 |
T41 |
3217 |
0 |
0 |
0 |
T52 |
2033 |
0 |
0 |
0 |
T57 |
20699 |
0 |
0 |
0 |
T104 |
6017 |
0 |
0 |
0 |
T108 |
0 |
473 |
0 |
0 |
T112 |
0 |
298 |
0 |
0 |
T116 |
744256 |
0 |
0 |
0 |
T125 |
0 |
398 |
0 |
0 |
T132 |
0 |
714 |
0 |
0 |
T151 |
84895 |
0 |
0 |
0 |
T152 |
20016 |
0 |
0 |
0 |
T153 |
0 |
8 |
0 |
0 |
T154 |
0 |
2 |
0 |
0 |
T155 |
0 |
33 |
0 |
0 |
T156 |
47627 |
0 |
0 |
0 |
T157 |
256561 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2987 |
0 |
0 |
T34 |
15290 |
6 |
0 |
0 |
T36 |
12844 |
29 |
0 |
0 |
T108 |
68110 |
114 |
0 |
0 |
T112 |
71864 |
93 |
0 |
0 |
T113 |
12004 |
14 |
0 |
0 |
T125 |
181242 |
543 |
0 |
0 |
T132 |
117629 |
797 |
0 |
0 |
T134 |
11671 |
39 |
0 |
0 |
T136 |
6572 |
18 |
0 |
0 |
T143 |
13033 |
3 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2638 |
0 |
0 |
T36 |
12844 |
11 |
0 |
0 |
T108 |
68110 |
138 |
0 |
0 |
T112 |
71864 |
85 |
0 |
0 |
T113 |
12004 |
22 |
0 |
0 |
T125 |
181242 |
449 |
0 |
0 |
T132 |
117629 |
681 |
0 |
0 |
T134 |
11671 |
20 |
0 |
0 |
T136 |
6572 |
5 |
0 |
0 |
T137 |
104623 |
403 |
0 |
0 |
T143 |
13033 |
46 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2569 |
0 |
0 |
T34 |
15290 |
7 |
0 |
0 |
T36 |
12844 |
44 |
0 |
0 |
T108 |
68110 |
91 |
0 |
0 |
T112 |
71864 |
74 |
0 |
0 |
T113 |
12004 |
12 |
0 |
0 |
T125 |
181242 |
484 |
0 |
0 |
T132 |
117629 |
718 |
0 |
0 |
T134 |
11671 |
13 |
0 |
0 |
T136 |
6572 |
9 |
0 |
0 |
T143 |
13033 |
31 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2612 |
0 |
0 |
T34 |
15290 |
35 |
0 |
0 |
T36 |
12844 |
72 |
0 |
0 |
T108 |
68110 |
82 |
0 |
0 |
T112 |
71864 |
75 |
0 |
0 |
T113 |
12004 |
14 |
0 |
0 |
T125 |
181242 |
406 |
0 |
0 |
T132 |
117629 |
733 |
0 |
0 |
T134 |
11671 |
16 |
0 |
0 |
T136 |
6572 |
1 |
0 |
0 |
T143 |
13033 |
34 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2648 |
0 |
0 |
T34 |
15290 |
12 |
0 |
0 |
T36 |
12844 |
48 |
0 |
0 |
T108 |
68110 |
89 |
0 |
0 |
T112 |
71864 |
72 |
0 |
0 |
T113 |
12004 |
20 |
0 |
0 |
T125 |
181242 |
443 |
0 |
0 |
T132 |
117629 |
788 |
0 |
0 |
T134 |
11671 |
12 |
0 |
0 |
T136 |
6572 |
8 |
0 |
0 |
T143 |
13033 |
9 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2482 |
0 |
0 |
T34 |
15290 |
22 |
0 |
0 |
T36 |
12844 |
51 |
0 |
0 |
T108 |
68110 |
90 |
0 |
0 |
T112 |
71864 |
62 |
0 |
0 |
T113 |
12004 |
11 |
0 |
0 |
T125 |
181242 |
477 |
0 |
0 |
T132 |
117629 |
754 |
0 |
0 |
T134 |
11671 |
8 |
0 |
0 |
T136 |
6572 |
2 |
0 |
0 |
T143 |
13033 |
13 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
3595 |
0 |
0 |
T34 |
15290 |
35 |
0 |
0 |
T36 |
12844 |
19 |
0 |
0 |
T108 |
68110 |
209 |
0 |
0 |
T112 |
71864 |
192 |
0 |
0 |
T113 |
12004 |
26 |
0 |
0 |
T125 |
181242 |
487 |
0 |
0 |
T132 |
117629 |
826 |
0 |
0 |
T134 |
11671 |
35 |
0 |
0 |
T136 |
6572 |
12 |
0 |
0 |
T143 |
13033 |
8 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2512 |
0 |
0 |
T34 |
15290 |
22 |
0 |
0 |
T36 |
12844 |
45 |
0 |
0 |
T108 |
68110 |
68 |
0 |
0 |
T112 |
71864 |
60 |
0 |
0 |
T113 |
12004 |
12 |
0 |
0 |
T125 |
181242 |
400 |
0 |
0 |
T132 |
117629 |
703 |
0 |
0 |
T134 |
11671 |
19 |
0 |
0 |
T136 |
6572 |
7 |
0 |
0 |
T143 |
13033 |
15 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
3766 |
0 |
0 |
T34 |
15290 |
30 |
0 |
0 |
T36 |
12844 |
18 |
0 |
0 |
T108 |
68110 |
270 |
0 |
0 |
T112 |
71864 |
237 |
0 |
0 |
T113 |
12004 |
55 |
0 |
0 |
T125 |
181242 |
411 |
0 |
0 |
T132 |
117629 |
738 |
0 |
0 |
T134 |
11671 |
25 |
0 |
0 |
T137 |
104623 |
465 |
0 |
0 |
T143 |
13033 |
28 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2952 |
0 |
0 |
T34 |
15290 |
15 |
0 |
0 |
T36 |
12844 |
28 |
0 |
0 |
T108 |
68110 |
158 |
0 |
0 |
T112 |
71864 |
127 |
0 |
0 |
T113 |
12004 |
19 |
0 |
0 |
T125 |
181242 |
472 |
0 |
0 |
T132 |
117629 |
773 |
0 |
0 |
T134 |
11671 |
7 |
0 |
0 |
T136 |
6572 |
1 |
0 |
0 |
T143 |
13033 |
19 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2478 |
0 |
0 |
T34 |
15290 |
15 |
0 |
0 |
T36 |
12844 |
60 |
0 |
0 |
T108 |
68110 |
60 |
0 |
0 |
T112 |
71864 |
76 |
0 |
0 |
T113 |
12004 |
17 |
0 |
0 |
T125 |
181242 |
411 |
0 |
0 |
T132 |
117629 |
732 |
0 |
0 |
T134 |
11671 |
6 |
0 |
0 |
T137 |
104623 |
442 |
0 |
0 |
T143 |
13033 |
21 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2675 |
0 |
0 |
T34 |
15290 |
25 |
0 |
0 |
T36 |
12844 |
75 |
0 |
0 |
T108 |
68110 |
63 |
0 |
0 |
T112 |
71864 |
100 |
0 |
0 |
T113 |
12004 |
5 |
0 |
0 |
T125 |
181242 |
502 |
0 |
0 |
T132 |
117629 |
722 |
0 |
0 |
T134 |
11671 |
12 |
0 |
0 |
T136 |
6572 |
14 |
0 |
0 |
T143 |
13033 |
13 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2583 |
0 |
0 |
T34 |
15290 |
16 |
0 |
0 |
T36 |
12844 |
25 |
0 |
0 |
T108 |
68110 |
77 |
0 |
0 |
T112 |
71864 |
69 |
0 |
0 |
T113 |
12004 |
9 |
0 |
0 |
T125 |
181242 |
482 |
0 |
0 |
T132 |
117629 |
808 |
0 |
0 |
T134 |
11671 |
13 |
0 |
0 |
T136 |
6572 |
9 |
0 |
0 |
T143 |
13033 |
5 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2512 |
0 |
0 |
T34 |
15290 |
8 |
0 |
0 |
T36 |
12844 |
19 |
0 |
0 |
T108 |
68110 |
76 |
0 |
0 |
T112 |
71864 |
73 |
0 |
0 |
T113 |
12004 |
11 |
0 |
0 |
T125 |
181242 |
455 |
0 |
0 |
T132 |
117629 |
695 |
0 |
0 |
T134 |
11671 |
9 |
0 |
0 |
T136 |
6572 |
4 |
0 |
0 |
T143 |
13033 |
13 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2514 |
0 |
0 |
T34 |
15290 |
12 |
0 |
0 |
T36 |
12844 |
46 |
0 |
0 |
T108 |
68110 |
54 |
0 |
0 |
T112 |
71864 |
92 |
0 |
0 |
T113 |
12004 |
9 |
0 |
0 |
T125 |
181242 |
448 |
0 |
0 |
T132 |
117629 |
714 |
0 |
0 |
T134 |
11671 |
18 |
0 |
0 |
T136 |
6572 |
6 |
0 |
0 |
T143 |
13033 |
29 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127681774 |
2710 |
0 |
0 |
T34 |
15290 |
15 |
0 |
0 |
T36 |
12844 |
21 |
0 |
0 |
T108 |
68110 |
81 |
0 |
0 |
T112 |
71864 |
68 |
0 |
0 |
T113 |
12004 |
25 |
0 |
0 |
T125 |
181242 |
438 |
0 |
0 |
T132 |
117629 |
754 |
0 |
0 |
T134 |
11671 |
7 |
0 |
0 |
T136 |
6572 |
6 |
0 |
0 |
T143 |
13033 |
34 |
0 |
0 |