| T254 |
/workspace/coverage/default/9.spi_device_upload.183626107 |
|
|
Apr 18 12:44:24 PM PDT 24 |
Apr 18 12:44:57 PM PDT 24 |
137735286903 ps |
| T307 |
/workspace/coverage/default/25.spi_device_pass_cmd_filtering.1861815554 |
|
|
Apr 18 12:45:08 PM PDT 24 |
Apr 18 12:45:30 PM PDT 24 |
28488616427 ps |
| T611 |
/workspace/coverage/default/27.spi_device_csb_read.2377464033 |
|
|
Apr 18 12:45:22 PM PDT 24 |
Apr 18 12:45:24 PM PDT 24 |
51158854 ps |
| T326 |
/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2822601989 |
|
|
Apr 18 12:45:58 PM PDT 24 |
Apr 18 12:46:03 PM PDT 24 |
78649626 ps |
| T612 |
/workspace/coverage/default/47.spi_device_alert_test.1550643105 |
|
|
Apr 18 12:46:22 PM PDT 24 |
Apr 18 12:46:24 PM PDT 24 |
19666839 ps |
| T613 |
/workspace/coverage/default/41.spi_device_read_buffer_direct.1840751477 |
|
|
Apr 18 12:45:58 PM PDT 24 |
Apr 18 12:46:12 PM PDT 24 |
3040344533 ps |
| T614 |
/workspace/coverage/default/34.spi_device_tpm_all.2973638044 |
|
|
Apr 18 12:45:36 PM PDT 24 |
Apr 18 12:46:22 PM PDT 24 |
4615289671 ps |
| T615 |
/workspace/coverage/default/26.spi_device_tpm_sts_read.4025243613 |
|
|
Apr 18 12:45:10 PM PDT 24 |
Apr 18 12:45:12 PM PDT 24 |
110744487 ps |
| T166 |
/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2009218739 |
|
|
Apr 18 12:45:50 PM PDT 24 |
Apr 18 12:46:02 PM PDT 24 |
2081354849 ps |
| T42 |
/workspace/coverage/default/0.spi_device_ram_cfg.1647844768 |
|
|
Apr 18 12:44:04 PM PDT 24 |
Apr 18 12:44:06 PM PDT 24 |
17073595 ps |
| T616 |
/workspace/coverage/default/16.spi_device_tpm_sts_read.2734702147 |
|
|
Apr 18 12:44:52 PM PDT 24 |
Apr 18 12:44:54 PM PDT 24 |
54178459 ps |
| T617 |
/workspace/coverage/default/12.spi_device_alert_test.2608848785 |
|
|
Apr 18 12:44:34 PM PDT 24 |
Apr 18 12:44:36 PM PDT 24 |
11512555 ps |
| T618 |
/workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2808156599 |
|
|
Apr 18 12:44:19 PM PDT 24 |
Apr 18 12:44:39 PM PDT 24 |
14697125344 ps |
| T619 |
/workspace/coverage/default/2.spi_device_tpm_sts_read.2161766156 |
|
|
Apr 18 12:44:07 PM PDT 24 |
Apr 18 12:44:09 PM PDT 24 |
586516237 ps |
| T272 |
/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2581824426 |
|
|
Apr 18 12:44:52 PM PDT 24 |
Apr 18 12:45:19 PM PDT 24 |
9024806206 ps |
| T620 |
/workspace/coverage/default/38.spi_device_csb_read.773703345 |
|
|
Apr 18 12:45:58 PM PDT 24 |
Apr 18 12:46:02 PM PDT 24 |
26851872 ps |
| T621 |
/workspace/coverage/default/1.spi_device_tpm_all.1263528617 |
|
|
Apr 18 12:43:58 PM PDT 24 |
Apr 18 12:44:53 PM PDT 24 |
9601615269 ps |
| T622 |
/workspace/coverage/default/1.spi_device_csb_read.2540239577 |
|
|
Apr 18 12:44:01 PM PDT 24 |
Apr 18 12:44:03 PM PDT 24 |
25134543 ps |
| T274 |
/workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2175957909 |
|
|
Apr 18 12:45:16 PM PDT 24 |
Apr 18 12:45:21 PM PDT 24 |
722757232 ps |
| T47 |
/workspace/coverage/default/1.spi_device_sec_cm.2611291224 |
|
|
Apr 18 12:44:13 PM PDT 24 |
Apr 18 12:44:15 PM PDT 24 |
347883260 ps |
| T331 |
/workspace/coverage/default/43.spi_device_pass_cmd_filtering.1037114182 |
|
|
Apr 18 12:46:13 PM PDT 24 |
Apr 18 12:46:23 PM PDT 24 |
5208274307 ps |
| T248 |
/workspace/coverage/default/26.spi_device_pass_cmd_filtering.1422425101 |
|
|
Apr 18 12:45:19 PM PDT 24 |
Apr 18 12:45:38 PM PDT 24 |
20355733749 ps |
| T81 |
/workspace/coverage/default/43.spi_device_cfg_cmd.3625705120 |
|
|
Apr 18 12:46:07 PM PDT 24 |
Apr 18 12:46:10 PM PDT 24 |
101623505 ps |
| T251 |
/workspace/coverage/default/14.spi_device_pass_cmd_filtering.157636396 |
|
|
Apr 18 12:44:33 PM PDT 24 |
Apr 18 12:44:41 PM PDT 24 |
510065243 ps |
| T262 |
/workspace/coverage/default/12.spi_device_pass_addr_payload_swap.271186702 |
|
|
Apr 18 12:44:47 PM PDT 24 |
Apr 18 12:44:54 PM PDT 24 |
245550472 ps |
| T300 |
/workspace/coverage/default/24.spi_device_pass_cmd_filtering.2208991613 |
|
|
Apr 18 12:45:06 PM PDT 24 |
Apr 18 12:45:45 PM PDT 24 |
12123804310 ps |
| T623 |
/workspace/coverage/default/49.spi_device_alert_test.3781828057 |
|
|
Apr 18 12:46:26 PM PDT 24 |
Apr 18 12:46:27 PM PDT 24 |
23453269 ps |
| T624 |
/workspace/coverage/default/12.spi_device_flash_mode.2974812548 |
|
|
Apr 18 12:44:26 PM PDT 24 |
Apr 18 12:46:33 PM PDT 24 |
17954647477 ps |
| T625 |
/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1883511312 |
|
|
Apr 18 12:44:12 PM PDT 24 |
Apr 18 12:44:24 PM PDT 24 |
3161247994 ps |
| T323 |
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.131945566 |
|
|
Apr 18 12:44:19 PM PDT 24 |
Apr 18 12:44:25 PM PDT 24 |
1038212255 ps |
| T626 |
/workspace/coverage/default/5.spi_device_alert_test.2351180954 |
|
|
Apr 18 12:44:16 PM PDT 24 |
Apr 18 12:44:18 PM PDT 24 |
43019461 ps |
| T627 |
/workspace/coverage/default/24.spi_device_tpm_rw.1396402165 |
|
|
Apr 18 12:45:05 PM PDT 24 |
Apr 18 12:45:13 PM PDT 24 |
543013780 ps |
| T628 |
/workspace/coverage/default/5.spi_device_csb_read.424070999 |
|
|
Apr 18 12:44:13 PM PDT 24 |
Apr 18 12:44:14 PM PDT 24 |
17706173 ps |
| T629 |
/workspace/coverage/default/15.spi_device_tpm_sts_read.1806343295 |
|
|
Apr 18 12:44:39 PM PDT 24 |
Apr 18 12:44:41 PM PDT 24 |
34236595 ps |
| T281 |
/workspace/coverage/default/39.spi_device_flash_mode.2072591693 |
|
|
Apr 18 12:45:57 PM PDT 24 |
Apr 18 12:46:37 PM PDT 24 |
2243421083 ps |
| T630 |
/workspace/coverage/default/43.spi_device_csb_read.1504402410 |
|
|
Apr 18 12:46:03 PM PDT 24 |
Apr 18 12:46:05 PM PDT 24 |
40344200 ps |
| T631 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.3645089721 |
|
|
Apr 18 12:45:02 PM PDT 24 |
Apr 18 12:45:04 PM PDT 24 |
101907145 ps |
| T632 |
/workspace/coverage/default/11.spi_device_csb_read.1072897170 |
|
|
Apr 18 12:44:25 PM PDT 24 |
Apr 18 12:44:28 PM PDT 24 |
97772827 ps |
| T633 |
/workspace/coverage/default/28.spi_device_flash_mode.3705243596 |
|
|
Apr 18 12:45:19 PM PDT 24 |
Apr 18 12:48:42 PM PDT 24 |
64372098741 ps |
| T317 |
/workspace/coverage/default/20.spi_device_mailbox.144840255 |
|
|
Apr 18 12:45:00 PM PDT 24 |
Apr 18 12:46:18 PM PDT 24 |
8206769242 ps |
| T255 |
/workspace/coverage/default/14.spi_device_pass_addr_payload_swap.425836444 |
|
|
Apr 18 12:44:50 PM PDT 24 |
Apr 18 12:45:03 PM PDT 24 |
19350325129 ps |
| T289 |
/workspace/coverage/default/27.spi_device_flash_mode.177796249 |
|
|
Apr 18 12:45:18 PM PDT 24 |
Apr 18 12:45:43 PM PDT 24 |
9843013585 ps |
| T298 |
/workspace/coverage/default/46.spi_device_intercept.20601576 |
|
|
Apr 18 12:46:15 PM PDT 24 |
Apr 18 12:46:24 PM PDT 24 |
652412621 ps |
| T310 |
/workspace/coverage/default/47.spi_device_pass_cmd_filtering.1799691002 |
|
|
Apr 18 12:46:23 PM PDT 24 |
Apr 18 12:46:45 PM PDT 24 |
6656756272 ps |
| T316 |
/workspace/coverage/default/10.spi_device_intercept.1569721721 |
|
|
Apr 18 12:44:25 PM PDT 24 |
Apr 18 12:44:35 PM PDT 24 |
5522681649 ps |
| T634 |
/workspace/coverage/default/44.spi_device_mailbox.113401484 |
|
|
Apr 18 12:46:13 PM PDT 24 |
Apr 18 12:46:18 PM PDT 24 |
855501542 ps |
| T635 |
/workspace/coverage/default/14.spi_device_read_buffer_direct.1692752374 |
|
|
Apr 18 12:44:34 PM PDT 24 |
Apr 18 12:44:46 PM PDT 24 |
1676995292 ps |
| T273 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3691904115 |
|
|
Apr 18 12:46:17 PM PDT 24 |
Apr 18 12:46:24 PM PDT 24 |
1015832407 ps |
| T636 |
/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2433400869 |
|
|
Apr 18 12:46:22 PM PDT 24 |
Apr 18 12:46:53 PM PDT 24 |
40891205209 ps |
| T637 |
/workspace/coverage/default/8.spi_device_flash_mode.2737848253 |
|
|
Apr 18 12:44:24 PM PDT 24 |
Apr 18 12:44:40 PM PDT 24 |
1262183600 ps |
| T359 |
/workspace/coverage/default/23.spi_device_tpm_all.3366770401 |
|
|
Apr 18 12:45:12 PM PDT 24 |
Apr 18 12:46:24 PM PDT 24 |
49234565943 ps |
| T638 |
/workspace/coverage/default/38.spi_device_alert_test.1077548841 |
|
|
Apr 18 12:45:54 PM PDT 24 |
Apr 18 12:45:58 PM PDT 24 |
44341687 ps |
| T364 |
/workspace/coverage/default/47.spi_device_tpm_all.2931990257 |
|
|
Apr 18 12:46:18 PM PDT 24 |
Apr 18 12:46:30 PM PDT 24 |
4051522491 ps |
| T639 |
/workspace/coverage/default/24.spi_device_tpm_sts_read.403194355 |
|
|
Apr 18 12:45:11 PM PDT 24 |
Apr 18 12:45:13 PM PDT 24 |
114749660 ps |
| T640 |
/workspace/coverage/default/32.spi_device_read_buffer_direct.2059478996 |
|
|
Apr 18 12:45:30 PM PDT 24 |
Apr 18 12:45:41 PM PDT 24 |
824065601 ps |
| T641 |
/workspace/coverage/default/31.spi_device_alert_test.3075685883 |
|
|
Apr 18 12:45:30 PM PDT 24 |
Apr 18 12:45:32 PM PDT 24 |
43606944 ps |
| T642 |
/workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4026223944 |
|
|
Apr 18 12:46:23 PM PDT 24 |
Apr 18 12:46:32 PM PDT 24 |
4852327991 ps |
| T225 |
/workspace/coverage/default/27.spi_device_intercept.558624540 |
|
|
Apr 18 12:45:12 PM PDT 24 |
Apr 18 12:45:41 PM PDT 24 |
10901929309 ps |
| T643 |
/workspace/coverage/default/25.spi_device_tpm_rw.3615095396 |
|
|
Apr 18 12:45:22 PM PDT 24 |
Apr 18 12:45:27 PM PDT 24 |
349355338 ps |
| T287 |
/workspace/coverage/default/29.spi_device_flash_mode.2179043334 |
|
|
Apr 18 12:45:18 PM PDT 24 |
Apr 18 12:45:46 PM PDT 24 |
2146936518 ps |
| T644 |
/workspace/coverage/default/29.spi_device_csb_read.1854305978 |
|
|
Apr 18 12:45:29 PM PDT 24 |
Apr 18 12:45:31 PM PDT 24 |
49221860 ps |
| T645 |
/workspace/coverage/default/6.spi_device_tpm_sts_read.1138811014 |
|
|
Apr 18 12:44:20 PM PDT 24 |
Apr 18 12:44:22 PM PDT 24 |
114140749 ps |
| T252 |
/workspace/coverage/default/22.spi_device_pass_cmd_filtering.1962789268 |
|
|
Apr 18 12:45:09 PM PDT 24 |
Apr 18 12:45:34 PM PDT 24 |
49743409702 ps |
| T646 |
/workspace/coverage/default/12.spi_device_tpm_rw.1736633498 |
|
|
Apr 18 12:44:55 PM PDT 24 |
Apr 18 12:44:57 PM PDT 24 |
21357668 ps |
| T647 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.334425741 |
|
|
Apr 18 12:45:07 PM PDT 24 |
Apr 18 12:45:12 PM PDT 24 |
4157269758 ps |
| T648 |
/workspace/coverage/default/47.spi_device_tpm_rw.3392220620 |
|
|
Apr 18 12:46:23 PM PDT 24 |
Apr 18 12:46:25 PM PDT 24 |
83605906 ps |
| T649 |
/workspace/coverage/default/28.spi_device_cfg_cmd.114660904 |
|
|
Apr 18 12:45:23 PM PDT 24 |
Apr 18 12:45:37 PM PDT 24 |
3511811562 ps |
| T338 |
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.843258339 |
|
|
Apr 18 12:44:22 PM PDT 24 |
Apr 18 12:44:39 PM PDT 24 |
3959321768 ps |
| T650 |
/workspace/coverage/default/20.spi_device_read_buffer_direct.55830444 |
|
|
Apr 18 12:45:05 PM PDT 24 |
Apr 18 12:45:12 PM PDT 24 |
639923448 ps |
| T651 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.4051510654 |
|
|
Apr 18 12:46:16 PM PDT 24 |
Apr 18 12:46:21 PM PDT 24 |
1053396261 ps |
| T652 |
/workspace/coverage/default/11.spi_device_alert_test.3848284823 |
|
|
Apr 18 12:44:31 PM PDT 24 |
Apr 18 12:44:33 PM PDT 24 |
12516069 ps |
| T232 |
/workspace/coverage/default/40.spi_device_intercept.4105861388 |
|
|
Apr 18 12:45:58 PM PDT 24 |
Apr 18 12:46:16 PM PDT 24 |
5924697081 ps |
| T305 |
/workspace/coverage/default/13.spi_device_pass_cmd_filtering.1017743630 |
|
|
Apr 18 12:44:39 PM PDT 24 |
Apr 18 12:45:13 PM PDT 24 |
44279028276 ps |
| T653 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.479743870 |
|
|
Apr 18 12:43:53 PM PDT 24 |
Apr 18 12:43:54 PM PDT 24 |
49523103 ps |
| T654 |
/workspace/coverage/default/10.spi_device_tpm_rw.773104454 |
|
|
Apr 18 12:44:34 PM PDT 24 |
Apr 18 12:44:36 PM PDT 24 |
29710644 ps |
| T169 |
/workspace/coverage/default/1.spi_device_upload.3945972281 |
|
|
Apr 18 12:43:58 PM PDT 24 |
Apr 18 12:44:02 PM PDT 24 |
1139714802 ps |
| T655 |
/workspace/coverage/default/45.spi_device_read_buffer_direct.3516785594 |
|
|
Apr 18 12:46:15 PM PDT 24 |
Apr 18 12:46:27 PM PDT 24 |
1001009057 ps |
| T249 |
/workspace/coverage/default/41.spi_device_mailbox.2697968310 |
|
|
Apr 18 12:45:59 PM PDT 24 |
Apr 18 12:47:13 PM PDT 24 |
16763558152 ps |
| T270 |
/workspace/coverage/default/39.spi_device_intercept.2619767889 |
|
|
Apr 18 12:45:59 PM PDT 24 |
Apr 18 12:46:14 PM PDT 24 |
1708764166 ps |
| T656 |
/workspace/coverage/default/7.spi_device_tpm_rw.1315355254 |
|
|
Apr 18 12:44:24 PM PDT 24 |
Apr 18 12:44:28 PM PDT 24 |
278836903 ps |
| T657 |
/workspace/coverage/default/26.spi_device_csb_read.2670681156 |
|
|
Apr 18 12:45:06 PM PDT 24 |
Apr 18 12:45:09 PM PDT 24 |
24658063 ps |
| T167 |
/workspace/coverage/default/27.spi_device_pass_cmd_filtering.3467339596 |
|
|
Apr 18 12:45:18 PM PDT 24 |
Apr 18 12:45:24 PM PDT 24 |
4060650274 ps |
| T658 |
/workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1913800876 |
|
|
Apr 18 12:45:48 PM PDT 24 |
Apr 18 12:46:00 PM PDT 24 |
11156081334 ps |
| T297 |
/workspace/coverage/default/11.spi_device_flash_mode.1899482071 |
|
|
Apr 18 12:44:29 PM PDT 24 |
Apr 18 12:45:06 PM PDT 24 |
2333801299 ps |
| T659 |
/workspace/coverage/default/42.spi_device_flash_mode.2710635530 |
|
|
Apr 18 12:46:00 PM PDT 24 |
Apr 18 12:46:45 PM PDT 24 |
11966204303 ps |
| T360 |
/workspace/coverage/default/0.spi_device_tpm_all.707481075 |
|
|
Apr 18 12:43:56 PM PDT 24 |
Apr 18 12:44:36 PM PDT 24 |
29675125288 ps |
| T660 |
/workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3937312452 |
|
|
Apr 18 12:44:24 PM PDT 24 |
Apr 18 12:44:33 PM PDT 24 |
3488256901 ps |
| T661 |
/workspace/coverage/default/28.spi_device_tpm_all.1191386488 |
|
|
Apr 18 12:45:23 PM PDT 24 |
Apr 18 12:45:56 PM PDT 24 |
6009353016 ps |
| T662 |
/workspace/coverage/default/37.spi_device_flash_mode.3471917463 |
|
|
Apr 18 12:45:48 PM PDT 24 |
Apr 18 12:47:20 PM PDT 24 |
6400853527 ps |
| T663 |
/workspace/coverage/default/19.spi_device_tpm_sts_read.3544664850 |
|
|
Apr 18 12:44:54 PM PDT 24 |
Apr 18 12:44:57 PM PDT 24 |
106695211 ps |
| T306 |
/workspace/coverage/default/33.spi_device_intercept.1000043821 |
|
|
Apr 18 12:45:30 PM PDT 24 |
Apr 18 12:45:42 PM PDT 24 |
842551339 ps |
| T330 |
/workspace/coverage/default/17.spi_device_intercept.882383415 |
|
|
Apr 18 12:44:49 PM PDT 24 |
Apr 18 12:45:07 PM PDT 24 |
8175098519 ps |
| T327 |
/workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3976189544 |
|
|
Apr 18 12:46:12 PM PDT 24 |
Apr 18 12:46:22 PM PDT 24 |
1253596452 ps |
| T664 |
/workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1003459927 |
|
|
Apr 18 12:44:14 PM PDT 24 |
Apr 18 12:44:48 PM PDT 24 |
13558391920 ps |
| T665 |
/workspace/coverage/default/6.spi_device_flash_mode.2696406210 |
|
|
Apr 18 12:44:21 PM PDT 24 |
Apr 18 12:46:27 PM PDT 24 |
18047415027 ps |
| T666 |
/workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3314712615 |
|
|
Apr 18 12:44:22 PM PDT 24 |
Apr 18 12:44:33 PM PDT 24 |
2274544401 ps |
| T667 |
/workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2427808230 |
|
|
Apr 18 12:44:32 PM PDT 24 |
Apr 18 12:44:39 PM PDT 24 |
1056045530 ps |
| T668 |
/workspace/coverage/default/25.spi_device_intercept.2235717607 |
|
|
Apr 18 12:45:17 PM PDT 24 |
Apr 18 12:45:34 PM PDT 24 |
1257627324 ps |
| T669 |
/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3315198902 |
|
|
Apr 18 12:45:02 PM PDT 24 |
Apr 18 12:45:11 PM PDT 24 |
22366218300 ps |
| T670 |
/workspace/coverage/default/33.spi_device_csb_read.3195575431 |
|
|
Apr 18 12:45:33 PM PDT 24 |
Apr 18 12:45:35 PM PDT 24 |
23791264 ps |
| T671 |
/workspace/coverage/default/46.spi_device_alert_test.4024810552 |
|
|
Apr 18 12:46:18 PM PDT 24 |
Apr 18 12:46:20 PM PDT 24 |
22782773 ps |
| T672 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3389408006 |
|
|
Apr 18 12:44:54 PM PDT 24 |
Apr 18 12:45:10 PM PDT 24 |
71333842747 ps |
| T673 |
/workspace/coverage/default/14.spi_device_tpm_sts_read.998791305 |
|
|
Apr 18 12:44:34 PM PDT 24 |
Apr 18 12:44:35 PM PDT 24 |
90373204 ps |
| T674 |
/workspace/coverage/default/6.spi_device_csb_read.1241126755 |
|
|
Apr 18 12:44:14 PM PDT 24 |
Apr 18 12:44:16 PM PDT 24 |
163619684 ps |
| T271 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2418275761 |
|
|
Apr 18 12:45:28 PM PDT 24 |
Apr 18 12:46:02 PM PDT 24 |
12844313064 ps |
| T675 |
/workspace/coverage/default/20.spi_device_tpm_all.853096968 |
|
|
Apr 18 12:45:08 PM PDT 24 |
Apr 18 12:45:12 PM PDT 24 |
502473848 ps |
| T219 |
/workspace/coverage/default/30.spi_device_upload.4106863317 |
|
|
Apr 18 12:45:25 PM PDT 24 |
Apr 18 12:45:29 PM PDT 24 |
1613724476 ps |
| T676 |
/workspace/coverage/default/44.spi_device_tpm_rw.2914198206 |
|
|
Apr 18 12:46:05 PM PDT 24 |
Apr 18 12:46:09 PM PDT 24 |
70676815 ps |
| T308 |
/workspace/coverage/default/15.spi_device_intercept.3522010227 |
|
|
Apr 18 12:44:35 PM PDT 24 |
Apr 18 12:45:00 PM PDT 24 |
10378543005 ps |
| T193 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.2265523285 |
|
|
Apr 18 12:44:05 PM PDT 24 |
Apr 18 12:44:10 PM PDT 24 |
681611556 ps |
| T677 |
/workspace/coverage/default/20.spi_device_cfg_cmd.3043122564 |
|
|
Apr 18 12:44:52 PM PDT 24 |
Apr 18 12:44:55 PM PDT 24 |
170885934 ps |
| T322 |
/workspace/coverage/default/3.spi_device_pass_addr_payload_swap.660336644 |
|
|
Apr 18 12:44:05 PM PDT 24 |
Apr 18 12:44:11 PM PDT 24 |
459207499 ps |
| T678 |
/workspace/coverage/default/45.spi_device_tpm_sts_read.543616213 |
|
|
Apr 18 12:46:14 PM PDT 24 |
Apr 18 12:46:16 PM PDT 24 |
256626773 ps |
| T333 |
/workspace/coverage/default/43.spi_device_mailbox.2328806599 |
|
|
Apr 18 12:46:12 PM PDT 24 |
Apr 18 12:47:50 PM PDT 24 |
14838203099 ps |
| T679 |
/workspace/coverage/default/49.spi_device_read_buffer_direct.1879060338 |
|
|
Apr 18 12:46:26 PM PDT 24 |
Apr 18 12:46:30 PM PDT 24 |
308733375 ps |
| T680 |
/workspace/coverage/default/18.spi_device_read_buffer_direct.672065015 |
|
|
Apr 18 12:44:54 PM PDT 24 |
Apr 18 12:44:59 PM PDT 24 |
477427154 ps |
| T681 |
/workspace/coverage/default/38.spi_device_tpm_rw.3390389835 |
|
|
Apr 18 12:45:47 PM PDT 24 |
Apr 18 12:45:49 PM PDT 24 |
186447501 ps |
| T682 |
/workspace/coverage/default/24.spi_device_csb_read.1472883176 |
|
|
Apr 18 12:45:15 PM PDT 24 |
Apr 18 12:45:16 PM PDT 24 |
48655529 ps |
| T683 |
/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.93204134 |
|
|
Apr 18 12:45:17 PM PDT 24 |
Apr 18 12:45:23 PM PDT 24 |
6141321895 ps |
| T240 |
/workspace/coverage/default/24.spi_device_mailbox.2113343607 |
|
|
Apr 18 12:45:16 PM PDT 24 |
Apr 18 12:46:43 PM PDT 24 |
33000427144 ps |
| T684 |
/workspace/coverage/default/36.spi_device_tpm_all.1782006048 |
|
|
Apr 18 12:45:41 PM PDT 24 |
Apr 18 12:45:53 PM PDT 24 |
8740892828 ps |
| T685 |
/workspace/coverage/default/33.spi_device_alert_test.839146555 |
|
|
Apr 18 12:45:40 PM PDT 24 |
Apr 18 12:45:41 PM PDT 24 |
13088789 ps |
| T686 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.1332221314 |
|
|
Apr 18 12:45:54 PM PDT 24 |
Apr 18 12:45:59 PM PDT 24 |
81536702 ps |
| T687 |
/workspace/coverage/default/13.spi_device_tpm_sts_read.910216296 |
|
|
Apr 18 12:44:38 PM PDT 24 |
Apr 18 12:44:40 PM PDT 24 |
92931268 ps |
| T179 |
/workspace/coverage/default/19.spi_device_intercept.2119201329 |
|
|
Apr 18 12:44:47 PM PDT 24 |
Apr 18 12:45:16 PM PDT 24 |
14020331971 ps |
| T312 |
/workspace/coverage/default/5.spi_device_upload.3714824643 |
|
|
Apr 18 12:44:18 PM PDT 24 |
Apr 18 12:45:00 PM PDT 24 |
13222425403 ps |
| T688 |
/workspace/coverage/default/29.spi_device_tpm_all.3671595595 |
|
|
Apr 18 12:45:17 PM PDT 24 |
Apr 18 12:46:01 PM PDT 24 |
3541747838 ps |
| T689 |
/workspace/coverage/default/36.spi_device_tpm_rw.2898591695 |
|
|
Apr 18 12:45:41 PM PDT 24 |
Apr 18 12:45:45 PM PDT 24 |
1022289923 ps |
| T324 |
/workspace/coverage/default/28.spi_device_pass_addr_payload_swap.129358693 |
|
|
Apr 18 12:45:27 PM PDT 24 |
Apr 18 12:45:32 PM PDT 24 |
674139656 ps |
| T690 |
/workspace/coverage/default/21.spi_device_upload.39907498 |
|
|
Apr 18 12:45:05 PM PDT 24 |
Apr 18 12:45:24 PM PDT 24 |
5115063405 ps |
| T313 |
/workspace/coverage/default/28.spi_device_upload.3882654929 |
|
|
Apr 18 12:45:26 PM PDT 24 |
Apr 18 12:45:49 PM PDT 24 |
71593334956 ps |
| T691 |
/workspace/coverage/default/49.spi_device_csb_read.3514601941 |
|
|
Apr 18 12:46:21 PM PDT 24 |
Apr 18 12:46:22 PM PDT 24 |
16745217 ps |
| T692 |
/workspace/coverage/default/4.spi_device_flash_mode.768777034 |
|
|
Apr 18 12:44:21 PM PDT 24 |
Apr 18 12:45:38 PM PDT 24 |
11935548214 ps |
| T693 |
/workspace/coverage/default/31.spi_device_tpm_sts_read.887312962 |
|
|
Apr 18 12:45:31 PM PDT 24 |
Apr 18 12:45:33 PM PDT 24 |
51986080 ps |
| T264 |
/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1980147355 |
|
|
Apr 18 12:45:32 PM PDT 24 |
Apr 18 12:45:49 PM PDT 24 |
17387626990 ps |
| T366 |
/workspace/coverage/default/5.spi_device_tpm_all.2666906658 |
|
|
Apr 18 12:44:17 PM PDT 24 |
Apr 18 12:44:59 PM PDT 24 |
19657493866 ps |
| T328 |
/workspace/coverage/default/49.spi_device_pass_addr_payload_swap.848101523 |
|
|
Apr 18 12:46:22 PM PDT 24 |
Apr 18 12:46:32 PM PDT 24 |
754266267 ps |
| T694 |
/workspace/coverage/default/13.spi_device_tpm_read_hw_reg.489503916 |
|
|
Apr 18 12:44:35 PM PDT 24 |
Apr 18 12:44:55 PM PDT 24 |
26215586940 ps |
| T247 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1282567272 |
|
|
Apr 18 12:45:25 PM PDT 24 |
Apr 18 12:45:33 PM PDT 24 |
1628855839 ps |
| T695 |
/workspace/coverage/default/37.spi_device_alert_test.2231267408 |
|
|
Apr 18 12:45:58 PM PDT 24 |
Apr 18 12:46:01 PM PDT 24 |
23372431 ps |
| T696 |
/workspace/coverage/default/43.spi_device_flash_mode.1407717150 |
|
|
Apr 18 12:46:14 PM PDT 24 |
Apr 18 12:46:34 PM PDT 24 |
3286925040 ps |
| T318 |
/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1780635039 |
|
|
Apr 18 12:44:53 PM PDT 24 |
Apr 18 12:45:03 PM PDT 24 |
8445400585 ps |
| T697 |
/workspace/coverage/default/11.spi_device_tpm_sts_read.2359281100 |
|
|
Apr 18 12:44:32 PM PDT 24 |
Apr 18 12:44:33 PM PDT 24 |
96268955 ps |
| T698 |
/workspace/coverage/default/14.spi_device_tpm_rw.2180990809 |
|
|
Apr 18 12:44:35 PM PDT 24 |
Apr 18 12:44:38 PM PDT 24 |
54068735 ps |
| T699 |
/workspace/coverage/default/42.spi_device_alert_test.3554921019 |
|
|
Apr 18 12:46:00 PM PDT 24 |
Apr 18 12:46:04 PM PDT 24 |
82228254 ps |
| T336 |
/workspace/coverage/default/19.spi_device_pass_cmd_filtering.2296393055 |
|
|
Apr 18 12:44:54 PM PDT 24 |
Apr 18 12:44:58 PM PDT 24 |
887140198 ps |
| T700 |
/workspace/coverage/default/14.spi_device_flash_mode.358297168 |
|
|
Apr 18 12:44:46 PM PDT 24 |
Apr 18 12:45:55 PM PDT 24 |
4885528508 ps |
| T701 |
/workspace/coverage/default/26.spi_device_tpm_rw.1464429368 |
|
|
Apr 18 12:45:09 PM PDT 24 |
Apr 18 12:45:11 PM PDT 24 |
121988278 ps |
| T702 |
/workspace/coverage/default/34.spi_device_alert_test.1168270385 |
|
|
Apr 18 12:45:38 PM PDT 24 |
Apr 18 12:45:40 PM PDT 24 |
26752399 ps |
| T33 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2982934174 |
|
|
Apr 18 12:37:38 PM PDT 24 |
Apr 18 12:37:42 PM PDT 24 |
567939450 ps |
| T130 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2581319608 |
|
|
Apr 18 12:37:48 PM PDT 24 |
Apr 18 12:37:50 PM PDT 24 |
157811288 ps |
| T703 |
/workspace/coverage/cover_reg_top/7.spi_device_intr_test.2221355274 |
|
|
Apr 18 12:37:53 PM PDT 24 |
Apr 18 12:37:55 PM PDT 24 |
20569385 ps |
| T153 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.520419120 |
|
|
Apr 18 12:38:25 PM PDT 24 |
Apr 18 12:38:26 PM PDT 24 |
37152393 ps |
| T124 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2365025707 |
|
|
Apr 18 12:37:40 PM PDT 24 |
Apr 18 12:37:49 PM PDT 24 |
321028392 ps |
| T36 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.143610404 |
|
|
Apr 18 12:38:04 PM PDT 24 |
Apr 18 12:38:07 PM PDT 24 |
535289660 ps |
| T704 |
/workspace/coverage/cover_reg_top/26.spi_device_intr_test.2056923487 |
|
|
Apr 18 12:38:18 PM PDT 24 |
Apr 18 12:38:19 PM PDT 24 |
16452796 ps |
| T705 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.3210048031 |
|
|
Apr 18 12:38:24 PM PDT 24 |
Apr 18 12:38:25 PM PDT 24 |
49298220 ps |
| T154 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.2323856230 |
|
|
Apr 18 12:38:17 PM PDT 24 |
Apr 18 12:38:19 PM PDT 24 |
43349418 ps |
| T125 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3466983648 |
|
|
Apr 18 12:37:42 PM PDT 24 |
Apr 18 12:38:09 PM PDT 24 |
7249769534 ps |
| T37 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3959677583 |
|
|
Apr 18 12:37:47 PM PDT 24 |
Apr 18 12:37:50 PM PDT 24 |
80245716 ps |
| T38 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2705195688 |
|
|
Apr 18 12:37:53 PM PDT 24 |
Apr 18 12:37:56 PM PDT 24 |
61506279 ps |
| T34 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2562699013 |
|
|
Apr 18 12:37:47 PM PDT 24 |
Apr 18 12:37:51 PM PDT 24 |
332420191 ps |
| T155 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.3240118010 |
|
|
Apr 18 12:37:56 PM PDT 24 |
Apr 18 12:37:58 PM PDT 24 |
19927828 ps |
| T35 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2702989451 |
|
|
Apr 18 12:38:04 PM PDT 24 |
Apr 18 12:38:18 PM PDT 24 |
217371808 ps |
| T108 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2085946200 |
|
|
Apr 18 12:38:04 PM PDT 24 |
Apr 18 12:38:21 PM PDT 24 |
1081127732 ps |
| T107 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.747852393 |
|
|
Apr 18 12:37:55 PM PDT 24 |
Apr 18 12:37:58 PM PDT 24 |
106413693 ps |
| T131 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2717591076 |
|
|
Apr 18 12:37:36 PM PDT 24 |
Apr 18 12:38:08 PM PDT 24 |
4361207582 ps |
| T112 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3399963762 |
|
|
Apr 18 12:38:17 PM PDT 24 |
Apr 18 12:38:35 PM PDT 24 |
2478130377 ps |
| T140 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4182280922 |
|
|
Apr 18 12:37:50 PM PDT 24 |
Apr 18 12:37:55 PM PDT 24 |
160455953 ps |
| T706 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.2673506328 |
|
|
Apr 18 12:38:21 PM PDT 24 |
Apr 18 12:38:22 PM PDT 24 |
29538253 ps |
| T707 |
/workspace/coverage/cover_reg_top/48.spi_device_intr_test.1791490371 |
|
|
Apr 18 12:38:20 PM PDT 24 |
Apr 18 12:38:22 PM PDT 24 |
11158418 ps |
| T708 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3634804334 |
|
|
Apr 18 12:38:15 PM PDT 24 |
Apr 18 12:38:16 PM PDT 24 |
16911556 ps |
| T132 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3289304002 |
|
|
Apr 18 12:37:46 PM PDT 24 |
Apr 18 12:38:10 PM PDT 24 |
1264897475 ps |
| T709 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.2883866335 |
|
|
Apr 18 12:38:09 PM PDT 24 |
Apr 18 12:38:11 PM PDT 24 |
28336826 ps |
| T710 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.3576969350 |
|
|
Apr 18 12:37:42 PM PDT 24 |
Apr 18 12:37:43 PM PDT 24 |
103788602 ps |
| T133 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.247148087 |
|
|
Apr 18 12:38:10 PM PDT 24 |
Apr 18 12:38:14 PM PDT 24 |
199516013 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3156178723 |
|
|
Apr 18 12:37:48 PM PDT 24 |
Apr 18 12:37:52 PM PDT 24 |
122508490 ps |
| T114 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_errors.465914582 |
|
|
Apr 18 12:37:47 PM PDT 24 |
Apr 18 12:37:50 PM PDT 24 |
154733763 ps |
| T115 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1539080000 |
|
|
Apr 18 12:37:49 PM PDT 24 |
Apr 18 12:37:53 PM PDT 24 |
86204872 ps |
| T141 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3871807386 |
|
|
Apr 18 12:38:11 PM PDT 24 |
Apr 18 12:38:16 PM PDT 24 |
62602087 ps |
| T119 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.30424359 |
|
|
Apr 18 12:38:24 PM PDT 24 |
Apr 18 12:38:29 PM PDT 24 |
71624315 ps |
| T711 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.726784905 |
|
|
Apr 18 12:38:19 PM PDT 24 |
Apr 18 12:38:21 PM PDT 24 |
16408582 ps |
| T712 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.2262237581 |
|
|
Apr 18 12:38:16 PM PDT 24 |
Apr 18 12:38:18 PM PDT 24 |
26875307 ps |
| T713 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.765022205 |
|
|
Apr 18 12:37:53 PM PDT 24 |
Apr 18 12:37:55 PM PDT 24 |
71102113 ps |
| T714 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.3040554337 |
|
|
Apr 18 12:38:19 PM PDT 24 |
Apr 18 12:38:21 PM PDT 24 |
42377602 ps |
| T118 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.583750480 |
|
|
Apr 18 12:38:04 PM PDT 24 |
Apr 18 12:38:07 PM PDT 24 |
307673259 ps |
| T715 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.835661049 |
|
|
Apr 18 12:37:36 PM PDT 24 |
Apr 18 12:37:37 PM PDT 24 |
14337880 ps |
| T128 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1051367184 |
|
|
Apr 18 12:38:10 PM PDT 24 |
Apr 18 12:38:15 PM PDT 24 |
241615648 ps |
| T345 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.276596565 |
|
|
Apr 18 12:38:08 PM PDT 24 |
Apr 18 12:38:26 PM PDT 24 |
294655854 ps |
| T134 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2676610858 |
|
|
Apr 18 12:37:34 PM PDT 24 |
Apr 18 12:37:37 PM PDT 24 |
117911036 ps |
| T142 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2219784885 |
|
|
Apr 18 12:37:53 PM PDT 24 |
Apr 18 12:37:57 PM PDT 24 |
172358100 ps |
| T143 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.503303425 |
|
|
Apr 18 12:37:54 PM PDT 24 |
Apr 18 12:37:58 PM PDT 24 |
131669719 ps |
| T121 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.772726335 |
|
|
Apr 18 12:38:03 PM PDT 24 |
Apr 18 12:38:05 PM PDT 24 |
102530244 ps |
| T716 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3578554817 |
|
|
Apr 18 12:38:03 PM PDT 24 |
Apr 18 12:38:05 PM PDT 24 |
135438065 ps |
| T135 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3174434627 |
|
|
Apr 18 12:37:35 PM PDT 24 |
Apr 18 12:37:36 PM PDT 24 |
89683013 ps |
| T346 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1453979550 |
|
|
Apr 18 12:37:51 PM PDT 24 |
Apr 18 12:38:04 PM PDT 24 |
197199345 ps |
| T347 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2316992413 |
|
|
Apr 18 12:38:17 PM PDT 24 |
Apr 18 12:38:30 PM PDT 24 |
192079828 ps |
| T136 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3016129169 |
|
|
Apr 18 12:37:55 PM PDT 24 |
Apr 18 12:37:59 PM PDT 24 |
65754156 ps |
| T717 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2254161710 |
|
|
Apr 18 12:37:59 PM PDT 24 |
Apr 18 12:38:02 PM PDT 24 |
910999859 ps |
| T348 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2031354060 |
|
|
Apr 18 12:38:01 PM PDT 24 |
Apr 18 12:38:20 PM PDT 24 |
1172478994 ps |
| T718 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.432303655 |
|
|
Apr 18 12:38:08 PM PDT 24 |
Apr 18 12:38:10 PM PDT 24 |
14133273 ps |
| T719 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2040795909 |
|
|
Apr 18 12:38:13 PM PDT 24 |
Apr 18 12:38:17 PM PDT 24 |
88789740 ps |
| T137 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.530280591 |
|
|
Apr 18 12:37:48 PM PDT 24 |
Apr 18 12:38:11 PM PDT 24 |
1089892322 ps |
| T720 |
/workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1130992500 |
|
|
Apr 18 12:37:51 PM PDT 24 |
Apr 18 12:37:53 PM PDT 24 |
11216053 ps |
| T138 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2040953891 |
|
|
Apr 18 12:37:43 PM PDT 24 |
Apr 18 12:37:44 PM PDT 24 |
69589925 ps |
| T721 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.4278167443 |
|
|
Apr 18 12:38:14 PM PDT 24 |
Apr 18 12:38:16 PM PDT 24 |
14853654 ps |
| T120 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_errors.397165992 |
|
|
Apr 18 12:38:00 PM PDT 24 |
Apr 18 12:38:04 PM PDT 24 |
47830225 ps |
| T722 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2373782025 |
|
|
Apr 18 12:38:08 PM PDT 24 |
Apr 18 12:38:10 PM PDT 24 |
60312483 ps |
| T723 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.926317374 |
|
|
Apr 18 12:38:17 PM PDT 24 |
Apr 18 12:38:19 PM PDT 24 |
26513186 ps |
| T724 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3911350813 |
|
|
Apr 18 12:37:52 PM PDT 24 |
Apr 18 12:37:54 PM PDT 24 |
282495665 ps |
| T139 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2094891655 |
|
|
Apr 18 12:37:33 PM PDT 24 |
Apr 18 12:37:36 PM PDT 24 |
227535709 ps |
| T725 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.824530348 |
|
|
Apr 18 12:37:48 PM PDT 24 |
Apr 18 12:38:00 PM PDT 24 |
3129163565 ps |
| T726 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.2621387023 |
|
|
Apr 18 12:38:01 PM PDT 24 |
Apr 18 12:38:03 PM PDT 24 |
30987207 ps |
| T727 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.744631862 |
|
|
Apr 18 12:37:41 PM PDT 24 |
Apr 18 12:37:43 PM PDT 24 |
42830993 ps |
| T728 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1669718637 |
|
|
Apr 18 12:37:34 PM PDT 24 |
Apr 18 12:37:38 PM PDT 24 |
238173601 ps |
| T729 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.50962833 |
|
|
Apr 18 12:37:33 PM PDT 24 |
Apr 18 12:37:35 PM PDT 24 |
76802166 ps |
| T730 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.1709414855 |
|
|
Apr 18 12:38:16 PM PDT 24 |
Apr 18 12:38:18 PM PDT 24 |
36705052 ps |
| T731 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1836658411 |
|
|
Apr 18 12:38:02 PM PDT 24 |
Apr 18 12:38:05 PM PDT 24 |
43344197 ps |
| T732 |
/workspace/coverage/cover_reg_top/15.spi_device_intr_test.4250785845 |
|
|
Apr 18 12:38:08 PM PDT 24 |
Apr 18 12:38:10 PM PDT 24 |
13726513 ps |
| T733 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.2840237242 |
|
|
Apr 18 12:38:17 PM PDT 24 |
Apr 18 12:38:19 PM PDT 24 |
24521162 ps |
| T734 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.724941447 |
|
|
Apr 18 12:37:45 PM PDT 24 |
Apr 18 12:37:48 PM PDT 24 |
71678963 ps |
| T735 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.424870358 |
|
|
Apr 18 12:37:50 PM PDT 24 |
Apr 18 12:37:53 PM PDT 24 |
54813785 ps |
| T123 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1505494522 |
|
|
Apr 18 12:38:01 PM PDT 24 |
Apr 18 12:38:03 PM PDT 24 |
80505777 ps |
| T736 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.2214364907 |
|
|
Apr 18 12:38:04 PM PDT 24 |
Apr 18 12:38:06 PM PDT 24 |
14125382 ps |
| T352 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.620363335 |
|
|
Apr 18 12:38:03 PM PDT 24 |
Apr 18 12:38:11 PM PDT 24 |
321158724 ps |
| T737 |
/workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3726948135 |
|
|
Apr 18 12:38:16 PM PDT 24 |
Apr 18 12:38:20 PM PDT 24 |
106293564 ps |
| T738 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1047501585 |
|
|
Apr 18 12:38:19 PM PDT 24 |
Apr 18 12:38:21 PM PDT 24 |
14841916 ps |
| T739 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.645115309 |
|
|
Apr 18 12:37:40 PM PDT 24 |
Apr 18 12:38:14 PM PDT 24 |
8688054262 ps |
| T740 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3252646961 |
|
|
Apr 18 12:38:00 PM PDT 24 |
Apr 18 12:38:13 PM PDT 24 |
367402422 ps |
| T741 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.995173130 |
|
|
Apr 18 12:38:02 PM PDT 24 |
Apr 18 12:38:07 PM PDT 24 |
157406560 ps |
| T742 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1946031069 |
|
|
Apr 18 12:37:41 PM PDT 24 |
Apr 18 12:37:43 PM PDT 24 |
10594440 ps |
| T743 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1140196742 |
|
|
Apr 18 12:37:51 PM PDT 24 |
Apr 18 12:37:56 PM PDT 24 |
135319947 ps |
| T744 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3873210168 |
|
|
Apr 18 12:37:49 PM PDT 24 |
Apr 18 12:38:11 PM PDT 24 |
307180863 ps |
| T745 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3652731321 |
|
|
Apr 18 12:38:13 PM PDT 24 |
Apr 18 12:38:14 PM PDT 24 |
16743783 ps |
| T746 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.3183504531 |
|
|
Apr 18 12:38:17 PM PDT 24 |
Apr 18 12:38:18 PM PDT 24 |
122882348 ps |
| T747 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.4036150320 |
|
|
Apr 18 12:37:58 PM PDT 24 |
Apr 18 12:38:00 PM PDT 24 |
13134790 ps |
| T748 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.3109658413 |
|
|
Apr 18 12:37:55 PM PDT 24 |
Apr 18 12:37:56 PM PDT 24 |
19136212 ps |
| T749 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.986656766 |
|
|
Apr 18 12:38:06 PM PDT 24 |
Apr 18 12:38:15 PM PDT 24 |
1216641327 ps |
| T750 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3222076458 |
|
|
Apr 18 12:38:04 PM PDT 24 |
Apr 18 12:38:06 PM PDT 24 |
307895258 ps |
| T351 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3724491825 |
|
|
Apr 18 12:37:49 PM PDT 24 |
Apr 18 12:38:05 PM PDT 24 |
668936553 ps |
| T751 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3070596322 |
|
|
Apr 18 12:37:41 PM PDT 24 |
Apr 18 12:37:42 PM PDT 24 |
13774398 ps |
| T126 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3641666109 |
|
|
Apr 18 12:38:03 PM PDT 24 |
Apr 18 12:38:07 PM PDT 24 |
258733021 ps |
| T752 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3756800765 |
|
|
Apr 18 12:38:01 PM PDT 24 |
Apr 18 12:38:03 PM PDT 24 |
28550933 ps |
| T753 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3712867536 |
|
|
Apr 18 12:38:07 PM PDT 24 |
Apr 18 12:38:10 PM PDT 24 |
432277134 ps |
| T754 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2905111948 |
|
|
Apr 18 12:38:27 PM PDT 24 |
Apr 18 12:38:28 PM PDT 24 |
40821559 ps |
| T755 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.5583527 |
|
|
Apr 18 12:37:48 PM PDT 24 |
Apr 18 12:37:49 PM PDT 24 |
33759681 ps |
| T756 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3111263939 |
|
|
Apr 18 12:37:49 PM PDT 24 |
Apr 18 12:37:52 PM PDT 24 |
102377852 ps |
| T757 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_rw.569595170 |
|
|
Apr 18 12:38:18 PM PDT 24 |
Apr 18 12:38:21 PM PDT 24 |
117696432 ps |
| T90 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2513745574 |
|
|
Apr 18 12:37:44 PM PDT 24 |
Apr 18 12:37:46 PM PDT 24 |
180283566 ps |
| T758 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3386780092 |
|
|
Apr 18 12:37:41 PM PDT 24 |
Apr 18 12:37:57 PM PDT 24 |
1108216668 ps |