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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.10 97.49 92.80 98.61 80.85 95.83 90.96 88.18


Total test records in report: 824
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T759 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3580690320 Apr 18 12:38:14 PM PDT 24 Apr 18 12:38:18 PM PDT 24 163191237 ps
T760 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3434142728 Apr 18 12:38:05 PM PDT 24 Apr 18 12:38:08 PM PDT 24 144301711 ps
T761 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.45879839 Apr 18 12:37:40 PM PDT 24 Apr 18 12:37:41 PM PDT 24 29888957 ps
T762 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1868329363 Apr 18 12:38:28 PM PDT 24 Apr 18 12:38:30 PM PDT 24 15525903 ps
T350 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.444807317 Apr 18 12:38:02 PM PDT 24 Apr 18 12:38:17 PM PDT 24 1130278794 ps
T763 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.768396095 Apr 18 12:37:47 PM PDT 24 Apr 18 12:37:52 PM PDT 24 510488552 ps
T764 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1722863824 Apr 18 12:37:38 PM PDT 24 Apr 18 12:37:41 PM PDT 24 78682994 ps
T765 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2249963568 Apr 18 12:37:53 PM PDT 24 Apr 18 12:37:55 PM PDT 24 63341664 ps
T766 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2336394298 Apr 18 12:37:49 PM PDT 24 Apr 18 12:37:53 PM PDT 24 119232565 ps
T767 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3922684378 Apr 18 12:38:05 PM PDT 24 Apr 18 12:38:09 PM PDT 24 608458660 ps
T768 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2977149780 Apr 18 12:38:15 PM PDT 24 Apr 18 12:38:16 PM PDT 24 44972590 ps
T349 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3522574417 Apr 18 12:37:58 PM PDT 24 Apr 18 12:38:21 PM PDT 24 1026268501 ps
T769 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3496040528 Apr 18 12:37:51 PM PDT 24 Apr 18 12:37:55 PM PDT 24 62102712 ps
T770 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2482912251 Apr 18 12:37:49 PM PDT 24 Apr 18 12:37:54 PM PDT 24 165865569 ps
T771 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2563169172 Apr 18 12:38:05 PM PDT 24 Apr 18 12:38:06 PM PDT 24 59284084 ps
T772 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3483144147 Apr 18 12:37:52 PM PDT 24 Apr 18 12:38:11 PM PDT 24 985017618 ps
T773 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2935073498 Apr 18 12:38:10 PM PDT 24 Apr 18 12:38:12 PM PDT 24 35120807 ps
T774 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3488279850 Apr 18 12:38:16 PM PDT 24 Apr 18 12:38:17 PM PDT 24 11387982 ps
T775 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1930692543 Apr 18 12:38:21 PM PDT 24 Apr 18 12:38:22 PM PDT 24 12421146 ps
T776 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3651315750 Apr 18 12:37:59 PM PDT 24 Apr 18 12:38:01 PM PDT 24 47192057 ps
T777 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3207986787 Apr 18 12:37:33 PM PDT 24 Apr 18 12:37:34 PM PDT 24 53635439 ps
T778 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.824052020 Apr 18 12:38:13 PM PDT 24 Apr 18 12:38:15 PM PDT 24 25428446 ps
T779 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3276090998 Apr 18 12:38:14 PM PDT 24 Apr 18 12:38:16 PM PDT 24 96847157 ps
T780 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2835009651 Apr 18 12:37:46 PM PDT 24 Apr 18 12:38:19 PM PDT 24 525635277 ps
T781 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3459327156 Apr 18 12:38:00 PM PDT 24 Apr 18 12:38:02 PM PDT 24 77061867 ps
T782 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2847631753 Apr 18 12:38:19 PM PDT 24 Apr 18 12:38:22 PM PDT 24 369981737 ps
T91 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2990599345 Apr 18 12:37:43 PM PDT 24 Apr 18 12:37:45 PM PDT 24 50263535 ps
T122 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3026349902 Apr 18 12:37:52 PM PDT 24 Apr 18 12:37:56 PM PDT 24 487393842 ps
T783 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1722169588 Apr 18 12:37:54 PM PDT 24 Apr 18 12:38:03 PM PDT 24 299518459 ps
T784 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3176241002 Apr 18 12:37:46 PM PDT 24 Apr 18 12:38:01 PM PDT 24 657003862 ps
T785 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1945642220 Apr 18 12:38:14 PM PDT 24 Apr 18 12:38:17 PM PDT 24 200628525 ps
T786 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.322919617 Apr 18 12:37:51 PM PDT 24 Apr 18 12:38:13 PM PDT 24 605278579 ps
T787 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.695690731 Apr 18 12:37:50 PM PDT 24 Apr 18 12:37:54 PM PDT 24 479295917 ps
T127 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3673968321 Apr 18 12:38:14 PM PDT 24 Apr 18 12:38:18 PM PDT 24 147040484 ps
T788 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3905029389 Apr 18 12:38:14 PM PDT 24 Apr 18 12:38:16 PM PDT 24 34232738 ps
T789 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.732785759 Apr 18 12:38:16 PM PDT 24 Apr 18 12:38:18 PM PDT 24 44385019 ps
T790 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3987155074 Apr 18 12:37:44 PM PDT 24 Apr 18 12:37:47 PM PDT 24 39287999 ps
T344 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3900752328 Apr 18 12:37:35 PM PDT 24 Apr 18 12:37:38 PM PDT 24 305691608 ps
T791 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1646293468 Apr 18 12:38:06 PM PDT 24 Apr 18 12:38:09 PM PDT 24 82372422 ps
T792 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2913259649 Apr 18 12:37:45 PM PDT 24 Apr 18 12:37:49 PM PDT 24 495411152 ps
T92 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2675675606 Apr 18 12:37:38 PM PDT 24 Apr 18 12:37:40 PM PDT 24 22242037 ps
T793 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2677420288 Apr 18 12:37:37 PM PDT 24 Apr 18 12:37:51 PM PDT 24 2212705953 ps
T794 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.890318535 Apr 18 12:38:05 PM PDT 24 Apr 18 12:38:08 PM PDT 24 690752367 ps
T795 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3859276962 Apr 18 12:38:04 PM PDT 24 Apr 18 12:38:10 PM PDT 24 2829608124 ps
T796 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2372117028 Apr 18 12:38:06 PM PDT 24 Apr 18 12:38:09 PM PDT 24 45144813 ps
T797 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.478111213 Apr 18 12:37:46 PM PDT 24 Apr 18 12:37:49 PM PDT 24 39232295 ps
T798 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1286250705 Apr 18 12:37:52 PM PDT 24 Apr 18 12:37:57 PM PDT 24 243731619 ps
T799 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3089015727 Apr 18 12:38:16 PM PDT 24 Apr 18 12:38:17 PM PDT 24 29931984 ps
T800 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1708513237 Apr 18 12:37:58 PM PDT 24 Apr 18 12:38:01 PM PDT 24 26961017 ps
T801 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1311258165 Apr 18 12:38:13 PM PDT 24 Apr 18 12:38:15 PM PDT 24 13658912 ps
T802 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4213197575 Apr 18 12:38:17 PM PDT 24 Apr 18 12:38:21 PM PDT 24 137846501 ps
T803 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2718298494 Apr 18 12:38:19 PM PDT 24 Apr 18 12:38:21 PM PDT 24 67277313 ps
T804 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.927338491 Apr 18 12:38:04 PM PDT 24 Apr 18 12:38:09 PM PDT 24 212636078 ps
T805 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.337539841 Apr 18 12:38:17 PM PDT 24 Apr 18 12:38:19 PM PDT 24 24017917 ps
T806 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.282323057 Apr 18 12:38:07 PM PDT 24 Apr 18 12:38:10 PM PDT 24 127381704 ps
T807 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2312328945 Apr 18 12:38:13 PM PDT 24 Apr 18 12:38:29 PM PDT 24 2136634604 ps
T93 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3781242296 Apr 18 12:37:59 PM PDT 24 Apr 18 12:38:01 PM PDT 24 65212331 ps
T808 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3408616962 Apr 18 12:37:54 PM PDT 24 Apr 18 12:37:56 PM PDT 24 26468043 ps
T809 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2071175400 Apr 18 12:38:17 PM PDT 24 Apr 18 12:38:20 PM PDT 24 64031833 ps
T810 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.183452098 Apr 18 12:37:41 PM PDT 24 Apr 18 12:37:44 PM PDT 24 71179909 ps
T811 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.552108818 Apr 18 12:38:07 PM PDT 24 Apr 18 12:38:12 PM PDT 24 122746525 ps
T812 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4126812954 Apr 18 12:38:01 PM PDT 24 Apr 18 12:38:04 PM PDT 24 65690131 ps
T813 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2974724010 Apr 18 12:37:33 PM PDT 24 Apr 18 12:37:54 PM PDT 24 3882009830 ps
T814 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1360747555 Apr 18 12:38:17 PM PDT 24 Apr 18 12:38:19 PM PDT 24 22468091 ps
T815 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2032874225 Apr 18 12:38:13 PM PDT 24 Apr 18 12:38:15 PM PDT 24 30167427 ps
T816 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2858030230 Apr 18 12:37:43 PM PDT 24 Apr 18 12:37:45 PM PDT 24 28145137 ps
T817 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.973094615 Apr 18 12:37:50 PM PDT 24 Apr 18 12:37:52 PM PDT 24 60297438 ps
T818 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1633855793 Apr 18 12:38:19 PM PDT 24 Apr 18 12:38:21 PM PDT 24 121414497 ps
T819 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.168293964 Apr 18 12:38:18 PM PDT 24 Apr 18 12:38:22 PM PDT 24 135661817 ps
T820 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2809981861 Apr 18 12:38:08 PM PDT 24 Apr 18 12:38:12 PM PDT 24 200626460 ps
T821 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3602491758 Apr 18 12:37:34 PM PDT 24 Apr 18 12:37:37 PM PDT 24 96246714 ps
T822 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4275590935 Apr 18 12:38:06 PM PDT 24 Apr 18 12:38:09 PM PDT 24 477105423 ps
T823 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.107367439 Apr 18 12:38:19 PM PDT 24 Apr 18 12:38:20 PM PDT 24 21193752 ps
T824 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1334595892 Apr 18 12:38:28 PM PDT 24 Apr 18 12:38:30 PM PDT 24 14130153 ps

Test location /workspace/coverage/default/47.spi_device_mailbox.3434113313
Short name T5
Test name
Test status
Simulation time 5520440226 ps
CPU time 21.99 seconds
Started Apr 18 12:46:19 PM PDT 24
Finished Apr 18 12:46:42 PM PDT 24
Peak memory 224312 kb
Host smart-a025567f-d00f-47c9-b2dd-f04b874afa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434113313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3434113313
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3641634471
Short name T49
Test name
Test status
Simulation time 11908393159 ps
CPU time 47.39 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:47:04 PM PDT 24
Peak memory 216208 kb
Host smart-ae8208bf-7058-4f4e-91a7-79b534412af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641634471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3641634471
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1412351790
Short name T9
Test name
Test status
Simulation time 11780244043 ps
CPU time 48.74 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:46:21 PM PDT 24
Peak memory 224476 kb
Host smart-3307fbc9-32ec-4654-9f59-e3345eaf9151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412351790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1412351790
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_upload.947095342
Short name T28
Test name
Test status
Simulation time 4238465139 ps
CPU time 15.13 seconds
Started Apr 18 12:45:36 PM PDT 24
Finished Apr 18 12:45:53 PM PDT 24
Peak memory 238572 kb
Host smart-321537ed-9a91-4c19-aa2e-c81e63352f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947095342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.947095342
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2085946200
Short name T108
Test name
Test status
Simulation time 1081127732 ps
CPU time 15.83 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 214196 kb
Host smart-35f86bca-6a8e-4fa8-8fad-3b6fb6249d03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085946200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2085946200
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2609409504
Short name T19
Test name
Test status
Simulation time 98516210 ps
CPU time 1.04 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 206920 kb
Host smart-6d452647-833a-4f5c-8fd8-f65fe09136b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609409504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2609409504
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.431686254
Short name T367
Test name
Test status
Simulation time 11446009232 ps
CPU time 63.82 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:47:27 PM PDT 24
Peak memory 216208 kb
Host smart-62d6991d-dc92-449b-9a7a-6e5472c67fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431686254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.431686254
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2109426209
Short name T6
Test name
Test status
Simulation time 8117969721 ps
CPU time 27.25 seconds
Started Apr 18 12:45:11 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 224180 kb
Host smart-0f93d800-b074-40f6-9e60-c987f711459a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109426209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2109426209
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1647844768
Short name T42
Test name
Test status
Simulation time 17073595 ps
CPU time 0.81 seconds
Started Apr 18 12:44:04 PM PDT 24
Finished Apr 18 12:44:06 PM PDT 24
Peak memory 216132 kb
Host smart-0db3cc0b-e425-4bd5-afcc-2d369a7f4faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647844768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1647844768
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4247476632
Short name T10
Test name
Test status
Simulation time 2925622741 ps
CPU time 13.4 seconds
Started Apr 18 12:44:05 PM PDT 24
Finished Apr 18 12:44:20 PM PDT 24
Peak memory 218704 kb
Host smart-ee1164aa-d4dd-4dde-b6b5-5d4f82c0477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247476632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4247476632
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.707481075
Short name T360
Test name
Test status
Simulation time 29675125288 ps
CPU time 38.94 seconds
Started Apr 18 12:43:56 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 216272 kb
Host smart-36070ddf-23c0-45d6-ada0-099cf1d5a53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707481075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.707481075
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.671790867
Short name T44
Test name
Test status
Simulation time 813680090 ps
CPU time 17.14 seconds
Started Apr 18 12:45:02 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 220012 kb
Host smart-d5364356-6604-4ad5-ac34-ddd509ca8e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671790867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.671790867
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3707148507
Short name T145
Test name
Test status
Simulation time 527261017 ps
CPU time 17.16 seconds
Started Apr 18 12:44:29 PM PDT 24
Finished Apr 18 12:44:47 PM PDT 24
Peak memory 239652 kb
Host smart-c166071e-353d-426c-9eb8-d8aef0052fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707148507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3707148507
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2982934174
Short name T33
Test name
Test status
Simulation time 567939450 ps
CPU time 3.94 seconds
Started Apr 18 12:37:38 PM PDT 24
Finished Apr 18 12:37:42 PM PDT 24
Peak memory 215256 kb
Host smart-01652730-e6a3-4148-b977-e4632d013d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982934174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
982934174
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3109948161
Short name T370
Test name
Test status
Simulation time 10172950718 ps
CPU time 55.96 seconds
Started Apr 18 12:46:00 PM PDT 24
Finished Apr 18 12:46:59 PM PDT 24
Peak memory 216084 kb
Host smart-fd6aff10-3d11-46fd-8496-9e9eff5f49e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109948161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3109948161
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4293632588
Short name T32
Test name
Test status
Simulation time 392560352 ps
CPU time 1.25 seconds
Started Apr 18 12:44:00 PM PDT 24
Finished Apr 18 12:44:02 PM PDT 24
Peak memory 234888 kb
Host smart-2339ddb2-d663-4270-8cdd-8e882f600826
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293632588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4293632588
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2092048530
Short name T223
Test name
Test status
Simulation time 19451404896 ps
CPU time 170.96 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:47:10 PM PDT 24
Peak memory 224332 kb
Host smart-861f3119-88f7-40c2-baf9-e8a7eb4cc0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092048530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2092048530
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_upload.795946019
Short name T25
Test name
Test status
Simulation time 1638588680 ps
CPU time 7.26 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 227664 kb
Host smart-033f649f-3079-4b81-8fb5-b8cb95b0f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795946019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.795946019
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3918880144
Short name T60
Test name
Test status
Simulation time 1607072439 ps
CPU time 6.21 seconds
Started Apr 18 12:45:41 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 223344 kb
Host smart-c8e9fbd7-31bd-413f-b840-b87e1d70505d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918880144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3918880144
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1233211368
Short name T199
Test name
Test status
Simulation time 674804129 ps
CPU time 10.15 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:25 PM PDT 24
Peak memory 238092 kb
Host smart-0a8ac9ae-3ffa-470b-8cc1-b9a2078c5537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233211368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1233211368
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2233214941
Short name T85
Test name
Test status
Simulation time 1123089165 ps
CPU time 15.94 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 240620 kb
Host smart-64ba8276-c28e-4115-a5e2-2ae2aa737692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233214941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2233214941
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2676610858
Short name T134
Test name
Test status
Simulation time 117911036 ps
CPU time 2.77 seconds
Started Apr 18 12:37:34 PM PDT 24
Finished Apr 18 12:37:37 PM PDT 24
Peak memory 206912 kb
Host smart-21b0d9da-3312-4c5d-adf7-bb143ae73241
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676610858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
676610858
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.407753265
Short name T99
Test name
Test status
Simulation time 23317638812 ps
CPU time 28.3 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:45:49 PM PDT 24
Peak memory 216120 kb
Host smart-77dc295b-943e-4fe9-91f1-1dce8518c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407753265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.407753265
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.157636396
Short name T251
Test name
Test status
Simulation time 510065243 ps
CPU time 6.73 seconds
Started Apr 18 12:44:33 PM PDT 24
Finished Apr 18 12:44:41 PM PDT 24
Peak memory 235824 kb
Host smart-7bd8e799-24c0-4601-84a3-4882469c4af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157636396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.157636396
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.766931456
Short name T239
Test name
Test status
Simulation time 38765260185 ps
CPU time 17.87 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 218416 kb
Host smart-de7185ea-3f48-4ae7-abb6-fa804c88995c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766931456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.766931456
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1282567272
Short name T247
Test name
Test status
Simulation time 1628855839 ps
CPU time 7.61 seconds
Started Apr 18 12:45:25 PM PDT 24
Finished Apr 18 12:45:33 PM PDT 24
Peak memory 234624 kb
Host smart-f5b8e694-4b39-4c86-be15-7e3b02064d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282567272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1282567272
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2497083592
Short name T217
Test name
Test status
Simulation time 1010624878 ps
CPU time 9.83 seconds
Started Apr 18 12:44:22 PM PDT 24
Finished Apr 18 12:44:34 PM PDT 24
Peak memory 222744 kb
Host smart-1d573ba2-e455-4ea4-95df-8edef3515b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497083592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2497083592
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2334244030
Short name T206
Test name
Test status
Simulation time 1988833262 ps
CPU time 10.12 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:37 PM PDT 24
Peak memory 223228 kb
Host smart-bb2a2785-1916-4f74-ba98-b5ff5cb6bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334244030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2334244030
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3208498102
Short name T227
Test name
Test status
Simulation time 838275384 ps
CPU time 11.5 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:45:29 PM PDT 24
Peak memory 237572 kb
Host smart-941089a3-39ca-4ba1-b89b-2f5c5b42fa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208498102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3208498102
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.958676171
Short name T292
Test name
Test status
Simulation time 426855763 ps
CPU time 9.38 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 240640 kb
Host smart-1141caf2-2ffa-4e68-b0f3-0950d83f5e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958676171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.958676171
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3204425152
Short name T58
Test name
Test status
Simulation time 12820260152 ps
CPU time 20.5 seconds
Started Apr 18 12:46:03 PM PDT 24
Finished Apr 18 12:46:25 PM PDT 24
Peak memory 232604 kb
Host smart-9071e100-b917-40fe-8130-ebfb07a15a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204425152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3204425152
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1113033720
Short name T8
Test name
Test status
Simulation time 22892797777 ps
CPU time 15.1 seconds
Started Apr 18 12:45:32 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 218632 kb
Host smart-eaf144d7-8ef9-48ff-9d55-8154afa947e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113033720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1113033720
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3468811618
Short name T376
Test name
Test status
Simulation time 28561481007 ps
CPU time 44.84 seconds
Started Apr 18 12:46:12 PM PDT 24
Finished Apr 18 12:46:57 PM PDT 24
Peak memory 216232 kb
Host smart-9584a2ac-22fe-4e79-a4db-186741a79db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468811618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3468811618
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2016626075
Short name T162
Test name
Test status
Simulation time 416857157 ps
CPU time 4.26 seconds
Started Apr 18 12:45:33 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 216596 kb
Host smart-0b41dab8-9076-4199-be14-6b1bfd668eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016626075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2016626075
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1621134042
Short name T61
Test name
Test status
Simulation time 2024467681 ps
CPU time 8.54 seconds
Started Apr 18 12:44:26 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 218184 kb
Host smart-6fdbdbb2-3ac7-4423-b6b9-a8e085cb643a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621134042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1621134042
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_intercept.574598556
Short name T214
Test name
Test status
Simulation time 994164285 ps
CPU time 11.36 seconds
Started Apr 18 12:45:22 PM PDT 24
Finished Apr 18 12:45:34 PM PDT 24
Peak memory 223028 kb
Host smart-1b28cdc6-2c09-44c9-b1d0-d359df2e2385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574598556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.574598556
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3717804228
Short name T57
Test name
Test status
Simulation time 1150111443 ps
CPU time 3.76 seconds
Started Apr 18 12:44:37 PM PDT 24
Finished Apr 18 12:44:42 PM PDT 24
Peak memory 220920 kb
Host smart-977e67a1-7842-4289-9c7b-ceb3ee8c2ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717804228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3717804228
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3062786740
Short name T209
Test name
Test status
Simulation time 416840519 ps
CPU time 7.07 seconds
Started Apr 18 12:45:33 PM PDT 24
Finished Apr 18 12:45:41 PM PDT 24
Peak memory 224276 kb
Host smart-1ee3b86d-0c18-4e3e-a8b9-0538db801a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062786740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3062786740
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_upload.183626107
Short name T254
Test name
Test status
Simulation time 137735286903 ps
CPU time 30.61 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:57 PM PDT 24
Peak memory 232660 kb
Host smart-28eaa799-5742-4f2b-a15c-932b2f3dc339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183626107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.183626107
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1034873660
Short name T88
Test name
Test status
Simulation time 1835200666 ps
CPU time 7.95 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:31 PM PDT 24
Peak memory 224312 kb
Host smart-6edbc719-933c-4532-af9a-764fd3c5619e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034873660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1034873660
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2031354060
Short name T348
Test name
Test status
Simulation time 1172478994 ps
CPU time 17.78 seconds
Started Apr 18 12:38:01 PM PDT 24
Finished Apr 18 12:38:20 PM PDT 24
Peak memory 215096 kb
Host smart-b186c4b6-4e45-468e-9537-32142f06302b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031354060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2031354060
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2723223286
Short name T177
Test name
Test status
Simulation time 4006124040 ps
CPU time 11.33 seconds
Started Apr 18 12:44:34 PM PDT 24
Finished Apr 18 12:44:46 PM PDT 24
Peak memory 223084 kb
Host smart-c17e2c61-ee9e-4228-b126-b094e8762f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723223286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2723223286
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2986700894
Short name T187
Test name
Test status
Simulation time 9477774974 ps
CPU time 5.93 seconds
Started Apr 18 12:44:37 PM PDT 24
Finished Apr 18 12:44:44 PM PDT 24
Peak memory 220848 kb
Host smart-61ebdece-2ff4-46c2-93c8-c3cb0f061f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986700894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2986700894
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4154167655
Short name T63
Test name
Test status
Simulation time 704214748 ps
CPU time 4.41 seconds
Started Apr 18 12:45:03 PM PDT 24
Finished Apr 18 12:45:08 PM PDT 24
Peak memory 222736 kb
Host smart-b6a70d6c-0899-4c3c-bc78-3c979b35f82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154167655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4154167655
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2487115962
Short name T84
Test name
Test status
Simulation time 5125169963 ps
CPU time 11.23 seconds
Started Apr 18 12:45:02 PM PDT 24
Finished Apr 18 12:45:15 PM PDT 24
Peak memory 220984 kb
Host smart-368e8199-e17a-4535-ac9f-96348c1efdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487115962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2487115962
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3366770401
Short name T359
Test name
Test status
Simulation time 49234565943 ps
CPU time 70.73 seconds
Started Apr 18 12:45:12 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 216628 kb
Host smart-be38a45a-67c8-4a8b-905c-d58fd1968856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366770401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3366770401
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_intercept.20601576
Short name T298
Test name
Test status
Simulation time 652412621 ps
CPU time 7.18 seconds
Started Apr 18 12:46:15 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 219000 kb
Host smart-39b5c8e9-d17e-4ac7-b174-19455ddc90e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20601576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.20601576
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2716453394
Short name T290
Test name
Test status
Simulation time 3550603154 ps
CPU time 60.59 seconds
Started Apr 18 12:46:10 PM PDT 24
Finished Apr 18 12:47:11 PM PDT 24
Peak memory 241072 kb
Host smart-a90e198b-61bb-41e2-95bc-6d9d8003cc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716453394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2716453394
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.569287621
Short name T413
Test name
Test status
Simulation time 167529943 ps
CPU time 0.76 seconds
Started Apr 18 12:43:59 PM PDT 24
Finished Apr 18 12:44:00 PM PDT 24
Peak memory 205412 kb
Host smart-573aa08b-d078-4ade-b359-c0cc2e89c7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569287621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.569287621
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1136786585
Short name T159
Test name
Test status
Simulation time 16945344106 ps
CPU time 52.37 seconds
Started Apr 18 12:44:02 PM PDT 24
Finished Apr 18 12:44:56 PM PDT 24
Peak memory 232548 kb
Host smart-19610d07-b321-4ec7-9bdc-d571e219d741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136786585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1136786585
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3711006021
Short name T106
Test name
Test status
Simulation time 6107351074 ps
CPU time 19.33 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:44:13 PM PDT 24
Peak memory 216092 kb
Host smart-e147fa1c-2901-4970-b15f-b0d4905b15ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711006021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3711006021
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1604606374
Short name T67
Test name
Test status
Simulation time 1798016839 ps
CPU time 6.6 seconds
Started Apr 18 12:45:02 PM PDT 24
Finished Apr 18 12:45:10 PM PDT 24
Peak memory 223584 kb
Host smart-e69e30b5-d451-4750-906a-199064b05879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604606374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1604606374
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2834135786
Short name T234
Test name
Test status
Simulation time 6158122318 ps
CPU time 5.52 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:19 PM PDT 24
Peak memory 222948 kb
Host smart-1ceb9c5a-7573-43cc-92c1-4d19bed7e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834135786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2834135786
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1977000182
Short name T229
Test name
Test status
Simulation time 187055725 ps
CPU time 3.34 seconds
Started Apr 18 12:43:57 PM PDT 24
Finished Apr 18 12:44:01 PM PDT 24
Peak memory 218420 kb
Host smart-fcf0e87f-4047-4f05-9624-5673bf0f7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977000182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1977000182
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2433402889
Short name T233
Test name
Test status
Simulation time 1621673716 ps
CPU time 11.79 seconds
Started Apr 18 12:44:30 PM PDT 24
Finished Apr 18 12:44:43 PM PDT 24
Peak memory 239024 kb
Host smart-ce847e67-8e65-4209-b249-de163689464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433402889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2433402889
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.923545288
Short name T357
Test name
Test status
Simulation time 66217876512 ps
CPU time 43.27 seconds
Started Apr 18 12:44:48 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 216376 kb
Host smart-cacf05c1-03ff-4a87-a531-889b411139ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923545288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.923545288
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_upload.3755001110
Short name T26
Test name
Test status
Simulation time 2045301378 ps
CPU time 5.93 seconds
Started Apr 18 12:45:03 PM PDT 24
Finished Apr 18 12:45:10 PM PDT 24
Peak memory 218624 kb
Host smart-a028a4ad-ccfe-4398-8225-2c855e363614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755001110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3755001110
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1000043821
Short name T306
Test name
Test status
Simulation time 842551339 ps
CPU time 10.21 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:45:42 PM PDT 24
Peak memory 218788 kb
Host smart-1f9983e8-da16-44f4-8c89-a47e1636fd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000043821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1000043821
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2621085557
Short name T110
Test name
Test status
Simulation time 7026688525 ps
CPU time 44.12 seconds
Started Apr 18 12:45:39 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 218816 kb
Host smart-a0e2c962-9b68-4230-b01b-21583fcbd196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621085557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2621085557
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1149611821
Short name T243
Test name
Test status
Simulation time 73491245 ps
CPU time 2.32 seconds
Started Apr 18 12:45:35 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 216672 kb
Host smart-467d7ff3-55bb-453d-a3e1-a62cb7df640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149611821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1149611821
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_upload.2690396020
Short name T260
Test name
Test status
Simulation time 37394015295 ps
CPU time 32.94 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:48 PM PDT 24
Peak memory 235320 kb
Host smart-cc339d2d-bedc-47c6-82c9-9206a22df9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690396020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2690396020
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1027788966
Short name T208
Test name
Test status
Simulation time 4126353133 ps
CPU time 8.85 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:26 PM PDT 24
Peak memory 233572 kb
Host smart-44824bc2-5851-4f23-b75c-90e38d719e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027788966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1027788966
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3673968321
Short name T127
Test name
Test status
Simulation time 147040484 ps
CPU time 2.79 seconds
Started Apr 18 12:38:14 PM PDT 24
Finished Apr 18 12:38:18 PM PDT 24
Peak memory 215160 kb
Host smart-5370e6de-d539-47d8-8408-8e3b2973a119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673968321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3673968321
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1563020775
Short name T69
Test name
Test status
Simulation time 10841840649 ps
CPU time 19.77 seconds
Started Apr 18 12:44:01 PM PDT 24
Finished Apr 18 12:44:22 PM PDT 24
Peak memory 238348 kb
Host smart-0bbe1730-6741-4524-855c-807fa496d3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563020775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1563020775
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2093699846
Short name T210
Test name
Test status
Simulation time 42281897 ps
CPU time 2.61 seconds
Started Apr 18 12:44:41 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 222568 kb
Host smart-2c22fab8-8b29-4071-a746-d6f577968f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093699846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2093699846
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3267042513
Short name T68
Test name
Test status
Simulation time 6467974731 ps
CPU time 11.91 seconds
Started Apr 18 12:45:03 PM PDT 24
Finished Apr 18 12:45:16 PM PDT 24
Peak memory 218544 kb
Host smart-eb000aff-5e23-4568-a3b5-c0a1a8b91d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267042513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3267042513
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2993536631
Short name T89
Test name
Test status
Simulation time 24505550291 ps
CPU time 32.69 seconds
Started Apr 18 12:45:46 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 224376 kb
Host smart-526e0996-6af7-4a1c-8a83-f61edf21f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993536631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2993536631
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_intercept.135505947
Short name T216
Test name
Test status
Simulation time 311650444 ps
CPU time 2.2 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:45:58 PM PDT 24
Peak memory 216568 kb
Host smart-a7bb0d21-0e2b-47ab-b408-52725fd7688d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135505947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.135505947
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2780245155
Short name T191
Test name
Test status
Simulation time 12333551861 ps
CPU time 11.34 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:26 PM PDT 24
Peak memory 233696 kb
Host smart-2933c3bf-a8eb-4f13-9a4a-f49e715c7841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780245155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2780245155
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1522123345
Short name T186
Test name
Test status
Simulation time 38227213730 ps
CPU time 29.56 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:31 PM PDT 24
Peak memory 222964 kb
Host smart-163a2413-4be2-43a7-920c-adfa27e0b3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522123345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1522123345
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.269311913
Short name T96
Test name
Test status
Simulation time 15183426017 ps
CPU time 32.05 seconds
Started Apr 18 12:45:23 PM PDT 24
Finished Apr 18 12:45:56 PM PDT 24
Peak memory 232628 kb
Host smart-0f944c28-25f7-4b34-afe5-ca7552b2546f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269311913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.269311913
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2673506328
Short name T706
Test name
Test status
Simulation time 29538253 ps
CPU time 0.76 seconds
Started Apr 18 12:38:21 PM PDT 24
Finished Apr 18 12:38:22 PM PDT 24
Peak memory 203440 kb
Host smart-c69ac6d8-fa80-4a1b-8a67-4a06f155b87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673506328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2673506328
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3483144147
Short name T772
Test name
Test status
Simulation time 985017618 ps
CPU time 18.19 seconds
Started Apr 18 12:37:52 PM PDT 24
Finished Apr 18 12:38:11 PM PDT 24
Peak memory 216540 kb
Host smart-78e9d9b5-2777-4908-a6d3-4bcd386f713d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483144147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3483144147
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_upload.3856253667
Short name T337
Test name
Test status
Simulation time 16277798521 ps
CPU time 15.43 seconds
Started Apr 18 12:43:59 PM PDT 24
Finished Apr 18 12:44:15 PM PDT 24
Peak memory 224224 kb
Host smart-6d04da5f-6441-47c6-a0da-970b1f49851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856253667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3856253667
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3517692695
Short name T160
Test name
Test status
Simulation time 9737733248 ps
CPU time 17.42 seconds
Started Apr 18 12:44:03 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 235768 kb
Host smart-65493b02-30ed-4aea-8698-89f8a7ef0cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517692695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3517692695
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4135927377
Short name T258
Test name
Test status
Simulation time 263166528 ps
CPU time 3.21 seconds
Started Apr 18 12:44:32 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 222580 kb
Host smart-c553686a-5d3c-4651-8bfe-337e4705d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135927377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4135927377
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3565202188
Short name T64
Test name
Test status
Simulation time 21412390108 ps
CPU time 26.76 seconds
Started Apr 18 12:44:31 PM PDT 24
Finished Apr 18 12:44:58 PM PDT 24
Peak memory 226512 kb
Host smart-d7a13275-fd70-4dd9-b04e-fb1b0ae0d2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565202188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3565202188
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.271186702
Short name T262
Test name
Test status
Simulation time 245550472 ps
CPU time 5.31 seconds
Started Apr 18 12:44:47 PM PDT 24
Finished Apr 18 12:44:54 PM PDT 24
Peak memory 224044 kb
Host smart-62cc40d7-7416-4bc8-b70e-5fe6d0014da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271186702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.271186702
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2581824426
Short name T272
Test name
Test status
Simulation time 9024806206 ps
CPU time 25.35 seconds
Started Apr 18 12:44:52 PM PDT 24
Finished Apr 18 12:45:19 PM PDT 24
Peak memory 232664 kb
Host smart-10240162-71ff-4c2f-9016-e9625ff4da56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581824426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2581824426
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1555475010
Short name T56
Test name
Test status
Simulation time 962729101 ps
CPU time 4.42 seconds
Started Apr 18 12:44:49 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 218888 kb
Host smart-9df1e4b1-6793-408c-a1a5-b0ac18c0e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555475010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1555475010
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3941535534
Short name T87
Test name
Test status
Simulation time 24737534538 ps
CPU time 24.57 seconds
Started Apr 18 12:44:55 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 218456 kb
Host smart-3840563b-4134-4bbc-a652-cb144b2c7606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941535534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3941535534
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.654685611
Short name T268
Test name
Test status
Simulation time 4731861441 ps
CPU time 11.69 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:45:08 PM PDT 24
Peak memory 222780 kb
Host smart-7ff30a19-dea5-43c3-ada8-910e0fbc8856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654685611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.654685611
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3960311379
Short name T284
Test name
Test status
Simulation time 3914524326 ps
CPU time 50.53 seconds
Started Apr 18 12:45:01 PM PDT 24
Finished Apr 18 12:45:52 PM PDT 24
Peak memory 240620 kb
Host smart-897e9d39-0430-4321-b37d-2d6a767068fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960311379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3960311379
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3184531131
Short name T182
Test name
Test status
Simulation time 2784509427 ps
CPU time 35.45 seconds
Started Apr 18 12:45:08 PM PDT 24
Finished Apr 18 12:45:45 PM PDT 24
Peak memory 232636 kb
Host smart-fb369ab6-56ad-4030-8a64-fa2d68b0b47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184531131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3184531131
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2175957909
Short name T274
Test name
Test status
Simulation time 722757232 ps
CPU time 3.84 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 216592 kb
Host smart-dcb31394-40a5-415c-85f1-e9c48cb52fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175957909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2175957909
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.177796249
Short name T289
Test name
Test status
Simulation time 9843013585 ps
CPU time 23.64 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:43 PM PDT 24
Peak memory 248996 kb
Host smart-190f0083-f7f5-4f86-a671-09f373f66f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177796249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.177796249
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3467339596
Short name T167
Test name
Test status
Simulation time 4060650274 ps
CPU time 4.9 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:24 PM PDT 24
Peak memory 218408 kb
Host smart-0b9149db-2546-47cc-a6ea-342fdc6645a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467339596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3467339596
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2418275761
Short name T271
Test name
Test status
Simulation time 12844313064 ps
CPU time 33.32 seconds
Started Apr 18 12:45:28 PM PDT 24
Finished Apr 18 12:46:02 PM PDT 24
Peak memory 216952 kb
Host smart-62b29702-1596-4007-a244-b9c5c5e5bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418275761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2418275761
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3550562866
Short name T190
Test name
Test status
Simulation time 733638042 ps
CPU time 9.41 seconds
Started Apr 18 12:45:24 PM PDT 24
Finished Apr 18 12:45:34 PM PDT 24
Peak memory 217240 kb
Host smart-c1fd25a4-5938-4d46-889e-5132eac0e237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550562866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3550562866
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.560953592
Short name T65
Test name
Test status
Simulation time 590149394 ps
CPU time 4.58 seconds
Started Apr 18 12:45:56 PM PDT 24
Finished Apr 18 12:46:04 PM PDT 24
Peak memory 216648 kb
Host smart-e7bddcb2-cf0c-4582-a829-e2fc25f8dce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560953592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.560953592
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2697968310
Short name T249
Test name
Test status
Simulation time 16763558152 ps
CPU time 70.45 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:47:13 PM PDT 24
Peak memory 236016 kb
Host smart-0364c8b3-7138-4c25-8750-306835678058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697968310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2697968310
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3974316522
Short name T66
Test name
Test status
Simulation time 2694358900 ps
CPU time 4.12 seconds
Started Apr 18 12:46:18 PM PDT 24
Finished Apr 18 12:46:23 PM PDT 24
Peak memory 218252 kb
Host smart-ca1f1e9b-9909-4578-b798-164cbffcf100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974316522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3974316522
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1262587909
Short name T269
Test name
Test status
Simulation time 844536149 ps
CPU time 8.25 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:26 PM PDT 24
Peak memory 216480 kb
Host smart-6114d60a-a628-47d2-9c92-e701aaf95c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262587909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1262587909
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2613284001
Short name T231
Test name
Test status
Simulation time 1535053097 ps
CPU time 12.07 seconds
Started Apr 18 12:44:17 PM PDT 24
Finished Apr 18 12:44:29 PM PDT 24
Peak memory 237404 kb
Host smart-80106dc0-7e6b-4983-b367-253b96252c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613284001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2613284001
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2819355323
Short name T172
Test name
Test status
Simulation time 1627512090 ps
CPU time 13.15 seconds
Started Apr 18 12:44:17 PM PDT 24
Finished Apr 18 12:44:31 PM PDT 24
Peak memory 218896 kb
Host smart-7b0b35b0-e3eb-4f4c-b366-6a7d2d64d62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819355323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2819355323
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3670673361
Short name T13
Test name
Test status
Simulation time 5142816629 ps
CPU time 49.1 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:56 PM PDT 24
Peak memory 216320 kb
Host smart-66de4fcf-308e-4460-9964-35f87748c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670673361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3670673361
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3278691413
Short name T79
Test name
Test status
Simulation time 37707415 ps
CPU time 2.22 seconds
Started Apr 18 12:45:39 PM PDT 24
Finished Apr 18 12:45:42 PM PDT 24
Peak memory 222412 kb
Host smart-39bca252-3f77-488f-816a-8c7059204166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278691413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3278691413
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3900752328
Short name T344
Test name
Test status
Simulation time 305691608 ps
CPU time 2.54 seconds
Started Apr 18 12:37:35 PM PDT 24
Finished Apr 18 12:37:38 PM PDT 24
Peak memory 215368 kb
Host smart-56ff1bf1-2eaf-4a93-8e0d-cdb6a231d473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900752328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
900752328
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1214050989
Short name T72
Test name
Test status
Simulation time 2560794039 ps
CPU time 10.61 seconds
Started Apr 18 12:43:56 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 222480 kb
Host smart-a757d863-6d72-42d4-9c8f-d29d724d512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214050989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1214050989
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3525178965
Short name T285
Test name
Test status
Simulation time 5057882427 ps
CPU time 22.48 seconds
Started Apr 18 12:43:58 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 232584 kb
Host smart-e6c09a64-d974-4141-8a01-4a1a626bd55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525178965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3525178965
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3395170280
Short name T197
Test name
Test status
Simulation time 305998601 ps
CPU time 3.48 seconds
Started Apr 18 12:44:02 PM PDT 24
Finished Apr 18 12:44:06 PM PDT 24
Peak memory 218348 kb
Host smart-c3aadca5-4644-4e8c-a3a7-8513e3eff600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395170280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3395170280
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_upload.3945972281
Short name T169
Test name
Test status
Simulation time 1139714802 ps
CPU time 3.66 seconds
Started Apr 18 12:43:58 PM PDT 24
Finished Apr 18 12:44:02 PM PDT 24
Peak memory 216108 kb
Host smart-18bfb462-ab96-4b3f-8b32-eeaeea4e71d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945972281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3945972281
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1569721721
Short name T316
Test name
Test status
Simulation time 5522681649 ps
CPU time 8.38 seconds
Started Apr 18 12:44:25 PM PDT 24
Finished Apr 18 12:44:35 PM PDT 24
Peak memory 223812 kb
Host smart-8cec5c0b-4b9c-43d6-9596-a251c82ea260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569721721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1569721721
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.975049183
Short name T178
Test name
Test status
Simulation time 10104097545 ps
CPU time 26.68 seconds
Started Apr 18 12:44:35 PM PDT 24
Finished Apr 18 12:45:03 PM PDT 24
Peak memory 221904 kb
Host smart-be169763-197d-4186-aa1e-0c3c68db2079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975049183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.975049183
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1899482071
Short name T297
Test name
Test status
Simulation time 2333801299 ps
CPU time 36.07 seconds
Started Apr 18 12:44:29 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 232376 kb
Host smart-90dd8236-2cf7-4ebf-b4c4-ab8c8ac4978c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899482071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1899482071
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_upload.1180110069
Short name T259
Test name
Test status
Simulation time 237128862 ps
CPU time 2.66 seconds
Started Apr 18 12:44:25 PM PDT 24
Finished Apr 18 12:44:29 PM PDT 24
Peak memory 221852 kb
Host smart-9028b846-aa7c-41b8-b5fc-0346635b6ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180110069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1180110069
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_intercept.593099330
Short name T230
Test name
Test status
Simulation time 546786661 ps
CPU time 8.61 seconds
Started Apr 18 12:44:32 PM PDT 24
Finished Apr 18 12:44:41 PM PDT 24
Peak memory 217756 kb
Host smart-86499c78-cae2-4d72-a23c-fd04cf21ced8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593099330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.593099330
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1792302234
Short name T204
Test name
Test status
Simulation time 4357933716 ps
CPU time 8.4 seconds
Started Apr 18 12:44:26 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 238348 kb
Host smart-4b275909-3ca4-4ada-937a-ba44869ea7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792302234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1792302234
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_upload.883524212
Short name T180
Test name
Test status
Simulation time 7165394437 ps
CPU time 31.49 seconds
Started Apr 18 12:44:29 PM PDT 24
Finished Apr 18 12:45:01 PM PDT 24
Peak memory 224848 kb
Host smart-6656f321-28d9-4c9d-9034-a9e8f357db1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883524212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.883524212
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_intercept.962453726
Short name T299
Test name
Test status
Simulation time 21679160514 ps
CPU time 17.45 seconds
Started Apr 18 12:44:37 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 223564 kb
Host smart-e54d9f8d-1cdb-4d44-8f3a-6579e75ed929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962453726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.962453726
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3522010227
Short name T308
Test name
Test status
Simulation time 10378543005 ps
CPU time 23.33 seconds
Started Apr 18 12:44:35 PM PDT 24
Finished Apr 18 12:45:00 PM PDT 24
Peak memory 218396 kb
Host smart-570f8310-9a63-4b49-9eac-e549a1b6da83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522010227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3522010227
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3926408242
Short name T314
Test name
Test status
Simulation time 1898554976 ps
CPU time 7.43 seconds
Started Apr 18 12:45:02 PM PDT 24
Finished Apr 18 12:45:11 PM PDT 24
Peak memory 222988 kb
Host smart-c7ea66a1-1597-4dca-a248-689d22b214e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926408242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3926408242
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2119201329
Short name T179
Test name
Test status
Simulation time 14020331971 ps
CPU time 27.46 seconds
Started Apr 18 12:44:47 PM PDT 24
Finished Apr 18 12:45:16 PM PDT 24
Peak memory 217204 kb
Host smart-fabaa943-3f55-43e4-a38b-605eb211829c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119201329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2119201329
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2296393055
Short name T336
Test name
Test status
Simulation time 887140198 ps
CPU time 3.12 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:44:58 PM PDT 24
Peak memory 218376 kb
Host smart-758e4e7d-cf36-49bc-852e-a4994ee2aca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296393055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2296393055
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.135986266
Short name T280
Test name
Test status
Simulation time 6773939559 ps
CPU time 77.71 seconds
Started Apr 18 12:45:02 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 234656 kb
Host smart-f612d3b1-c28c-4e9f-b312-6f01d6850072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135986266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.135986266
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.144840255
Short name T317
Test name
Test status
Simulation time 8206769242 ps
CPU time 77.29 seconds
Started Apr 18 12:45:00 PM PDT 24
Finished Apr 18 12:46:18 PM PDT 24
Peak memory 220632 kb
Host smart-1704530c-973f-4dac-8716-ff538b4fbb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144840255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.144840255
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1308952581
Short name T256
Test name
Test status
Simulation time 6093951977 ps
CPU time 12.62 seconds
Started Apr 18 12:45:10 PM PDT 24
Finished Apr 18 12:45:24 PM PDT 24
Peak memory 232496 kb
Host smart-71be4932-5558-401e-8c07-f738fd13e190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308952581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1308952581
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3491637722
Short name T213
Test name
Test status
Simulation time 8772598750 ps
CPU time 22.84 seconds
Started Apr 18 12:45:09 PM PDT 24
Finished Apr 18 12:45:33 PM PDT 24
Peak memory 234076 kb
Host smart-ae24350a-3fab-47e7-ab6d-97a35efa74d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491637722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3491637722
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2898835864
Short name T325
Test name
Test status
Simulation time 92177635 ps
CPU time 2.07 seconds
Started Apr 18 12:45:05 PM PDT 24
Finished Apr 18 12:45:09 PM PDT 24
Peak memory 216692 kb
Host smart-c3c6cbd4-b92d-4925-8983-3fe19bb715a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898835864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2898835864
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2113343607
Short name T240
Test name
Test status
Simulation time 33000427144 ps
CPU time 85.98 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:46:43 PM PDT 24
Peak memory 240548 kb
Host smart-2804109e-1c2e-4385-91f9-d91c0471d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113343607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2113343607
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.22520468
Short name T228
Test name
Test status
Simulation time 2046184465 ps
CPU time 7.07 seconds
Started Apr 18 12:45:08 PM PDT 24
Finished Apr 18 12:45:16 PM PDT 24
Peak memory 222908 kb
Host smart-9e152929-ff61-4ab2-af2b-ec0774de8a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22520468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.22520468
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2208991613
Short name T300
Test name
Test status
Simulation time 12123804310 ps
CPU time 37.35 seconds
Started Apr 18 12:45:06 PM PDT 24
Finished Apr 18 12:45:45 PM PDT 24
Peak memory 223016 kb
Host smart-318b7f04-38d9-4757-9418-0c0ceb7968ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208991613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2208991613
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.646762954
Short name T164
Test name
Test status
Simulation time 389195917 ps
CPU time 5.29 seconds
Started Apr 18 12:45:05 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 224244 kb
Host smart-5cf166f4-5dcc-4010-a63f-1784034860ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646762954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.646762954
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_upload.3882654929
Short name T313
Test name
Test status
Simulation time 71593334956 ps
CPU time 23.05 seconds
Started Apr 18 12:45:26 PM PDT 24
Finished Apr 18 12:45:49 PM PDT 24
Peak memory 218512 kb
Host smart-aa7a59da-f70d-491d-ab24-ddfb352db477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882654929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3882654929
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1847263650
Short name T174
Test name
Test status
Simulation time 6169579991 ps
CPU time 14.75 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:22 PM PDT 24
Peak memory 222872 kb
Host smart-437c77b7-9b0e-4a15-9099-f67fdb238779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847263650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1847263650
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.660336644
Short name T322
Test name
Test status
Simulation time 459207499 ps
CPU time 4.8 seconds
Started Apr 18 12:44:05 PM PDT 24
Finished Apr 18 12:44:11 PM PDT 24
Peak memory 218404 kb
Host smart-f41f8b33-49a8-4a82-8cb6-293c1a95bea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660336644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
660336644
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2492075756
Short name T320
Test name
Test status
Simulation time 265279422 ps
CPU time 4.91 seconds
Started Apr 18 12:45:31 PM PDT 24
Finished Apr 18 12:45:37 PM PDT 24
Peak memory 221248 kb
Host smart-f7bbb2a6-e445-4427-a234-cc2ce9a94e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492075756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2492075756
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_upload.195813038
Short name T207
Test name
Test status
Simulation time 1016900659 ps
CPU time 5.13 seconds
Started Apr 18 12:45:24 PM PDT 24
Finished Apr 18 12:45:30 PM PDT 24
Peak memory 222476 kb
Host smart-c6ecf5dd-8558-42f0-85b9-a37d6987a082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195813038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.195813038
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1980147355
Short name T264
Test name
Test status
Simulation time 17387626990 ps
CPU time 15.46 seconds
Started Apr 18 12:45:32 PM PDT 24
Finished Apr 18 12:45:49 PM PDT 24
Peak memory 223552 kb
Host smart-6bbfc81a-7ebe-4aa8-b544-33feb9aab483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980147355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1980147355
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.808146084
Short name T235
Test name
Test status
Simulation time 39136360737 ps
CPU time 51.91 seconds
Started Apr 18 12:45:41 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 223612 kb
Host smart-fc3517b1-cb9d-4c91-98b5-1fd7adcb2363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808146084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.808146084
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2009218739
Short name T166
Test name
Test status
Simulation time 2081354849 ps
CPU time 10.96 seconds
Started Apr 18 12:45:50 PM PDT 24
Finished Apr 18 12:46:02 PM PDT 24
Peak memory 225412 kb
Host smart-ebcc7911-c66a-4e39-a0c6-0b54803b91ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009218739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2009218739
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3164148451
Short name T245
Test name
Test status
Simulation time 1492955651 ps
CPU time 8.42 seconds
Started Apr 18 12:45:53 PM PDT 24
Finished Apr 18 12:46:04 PM PDT 24
Peak memory 228796 kb
Host smart-2ce568ff-6b8a-492d-9932-cf7d9999d25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164148451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3164148451
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3077324891
Short name T236
Test name
Test status
Simulation time 18668641660 ps
CPU time 26.65 seconds
Started Apr 18 12:45:47 PM PDT 24
Finished Apr 18 12:46:14 PM PDT 24
Peak memory 219268 kb
Host smart-94b67086-0260-468d-a5d0-13abe72d8ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077324891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3077324891
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_upload.2687541872
Short name T301
Test name
Test status
Simulation time 2194260201 ps
CPU time 10.19 seconds
Started Apr 18 12:46:00 PM PDT 24
Finished Apr 18 12:46:13 PM PDT 24
Peak memory 223560 kb
Host smart-b2d4ae01-7a8e-4bd0-8b3d-eac2e76442af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687541872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2687541872
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2619767889
Short name T270
Test name
Test status
Simulation time 1708764166 ps
CPU time 12.58 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:14 PM PDT 24
Peak memory 216560 kb
Host smart-737faf0a-4f54-48cb-b0eb-d0022a402650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619767889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2619767889
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1074760486
Short name T329
Test name
Test status
Simulation time 12270549217 ps
CPU time 32.93 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:48 PM PDT 24
Peak memory 235048 kb
Host smart-48818c02-032c-4f09-ada2-1f42fa0e203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074760486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1074760486
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.243434721
Short name T304
Test name
Test status
Simulation time 478487351 ps
CPU time 3.88 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 218508 kb
Host smart-ded64e3c-3c0c-4ecd-aeab-77975e726e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243434721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.243434721
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2822601989
Short name T326
Test name
Test status
Simulation time 78649626 ps
CPU time 2.4 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:03 PM PDT 24
Peak memory 216556 kb
Host smart-9533d33f-cc89-4ce3-8426-10a18729d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822601989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2822601989
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.623686209
Short name T319
Test name
Test status
Simulation time 2896822885 ps
CPU time 3.92 seconds
Started Apr 18 12:46:05 PM PDT 24
Finished Apr 18 12:46:10 PM PDT 24
Peak memory 216848 kb
Host smart-5030fa7a-1e06-4e20-be47-48d22c8817d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623686209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.623686209
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3976189544
Short name T327
Test name
Test status
Simulation time 1253596452 ps
CPU time 9.07 seconds
Started Apr 18 12:46:12 PM PDT 24
Finished Apr 18 12:46:22 PM PDT 24
Peak memory 224420 kb
Host smart-044c8442-8b59-4c29-a225-b8c068f2768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976189544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3976189544
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.443698014
Short name T76
Test name
Test status
Simulation time 456618009 ps
CPU time 6.44 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 240720 kb
Host smart-f63712dd-b863-45af-ba4f-f26b186a78a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443698014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.443698014
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2970630231
Short name T246
Test name
Test status
Simulation time 6981971259 ps
CPU time 17.78 seconds
Started Apr 18 12:46:15 PM PDT 24
Finished Apr 18 12:46:35 PM PDT 24
Peak memory 224424 kb
Host smart-de81b0ea-4c0e-4f20-b310-a22d4fa16255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970630231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2970630231
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.848101523
Short name T328
Test name
Test status
Simulation time 754266267 ps
CPU time 8.99 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 221088 kb
Host smart-8510e3a7-7173-473e-aa5c-fb7cd33af811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848101523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.848101523
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3761746758
Short name T202
Test name
Test status
Simulation time 2684303130 ps
CPU time 11.74 seconds
Started Apr 18 12:44:17 PM PDT 24
Finished Apr 18 12:44:30 PM PDT 24
Peak memory 224248 kb
Host smart-cf04d167-788c-4f58-aebf-db181c8d7ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761746758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3761746758
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.131945566
Short name T323
Test name
Test status
Simulation time 1038212255 ps
CPU time 4.71 seconds
Started Apr 18 12:44:19 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 222416 kb
Host smart-26f20cdc-3a43-4d1e-b355-5af09df00009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131945566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
131945566
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3613436384
Short name T62
Test name
Test status
Simulation time 584833562 ps
CPU time 6 seconds
Started Apr 18 12:44:25 PM PDT 24
Finished Apr 18 12:44:32 PM PDT 24
Peak memory 232492 kb
Host smart-52d3e674-91be-437c-85cf-689926a89522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613436384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3613436384
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.159504106
Short name T276
Test name
Test status
Simulation time 18638367550 ps
CPU time 13.71 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:37 PM PDT 24
Peak memory 222656 kb
Host smart-f30ed705-8d99-4444-ba10-95fa06e5bc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159504106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
159504106
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.376434135
Short name T224
Test name
Test status
Simulation time 3004266983 ps
CPU time 9.33 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:32 PM PDT 24
Peak memory 216608 kb
Host smart-33f79f75-334c-43a4-ab81-cd6220a56866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376434135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
376434135
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.381831858
Short name T3
Test name
Test status
Simulation time 108513995 ps
CPU time 4.31 seconds
Started Apr 18 12:44:49 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 222564 kb
Host smart-144d859f-795b-4d62-afc4-0dfb375b3710
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=381831858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.381831858
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1505494522
Short name T123
Test name
Test status
Simulation time 80505777 ps
CPU time 1.73 seconds
Started Apr 18 12:38:01 PM PDT 24
Finished Apr 18 12:38:03 PM PDT 24
Peak memory 215128 kb
Host smart-a5a2fc0b-7cec-4496-a39a-38e5e0da2654
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505494522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1505494522
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2513745574
Short name T90
Test name
Test status
Simulation time 180283566 ps
CPU time 1.48 seconds
Started Apr 18 12:37:44 PM PDT 24
Finished Apr 18 12:37:46 PM PDT 24
Peak memory 206764 kb
Host smart-83e86b0b-7781-4b21-9dc6-34eb03f5024c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513745574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2513745574
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.322931017
Short name T78
Test name
Test status
Simulation time 1120872409 ps
CPU time 11.59 seconds
Started Apr 18 12:44:53 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 232596 kb
Host smart-db774734-349f-4fd2-945c-bc640751e5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322931017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.322931017
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2365025707
Short name T124
Test name
Test status
Simulation time 321028392 ps
CPU time 8.12 seconds
Started Apr 18 12:37:40 PM PDT 24
Finished Apr 18 12:37:49 PM PDT 24
Peak memory 215044 kb
Host smart-2c7c3459-290f-4177-adb5-7f86e6e58a41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365025707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2365025707
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.645115309
Short name T739
Test name
Test status
Simulation time 8688054262 ps
CPU time 33.29 seconds
Started Apr 18 12:37:40 PM PDT 24
Finished Apr 18 12:38:14 PM PDT 24
Peak memory 206860 kb
Host smart-04e9cbb3-d06f-4de4-a23c-55a0259eb140
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645115309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.645115309
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2675675606
Short name T92
Test name
Test status
Simulation time 22242037 ps
CPU time 0.95 seconds
Started Apr 18 12:37:38 PM PDT 24
Finished Apr 18 12:37:40 PM PDT 24
Peak memory 206464 kb
Host smart-e4092bc0-c7b5-4572-965f-273684024ac3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675675606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2675675606
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2562699013
Short name T34
Test name
Test status
Simulation time 332420191 ps
CPU time 3.45 seconds
Started Apr 18 12:37:47 PM PDT 24
Finished Apr 18 12:37:51 PM PDT 24
Peak memory 216588 kb
Host smart-b68ae1c7-0080-4ad4-8b49-c3e15cdf0664
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562699013 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2562699013
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3207986787
Short name T777
Test name
Test status
Simulation time 53635439 ps
CPU time 0.72 seconds
Started Apr 18 12:37:33 PM PDT 24
Finished Apr 18 12:37:34 PM PDT 24
Peak memory 203524 kb
Host smart-11b3c376-d2d9-4122-a139-28ed772fccd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207986787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
207986787
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2094891655
Short name T139
Test name
Test status
Simulation time 227535709 ps
CPU time 2.09 seconds
Started Apr 18 12:37:33 PM PDT 24
Finished Apr 18 12:37:36 PM PDT 24
Peak memory 215124 kb
Host smart-8334eb9c-2f62-4f13-a318-b135295e6a4d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094891655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2094891655
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.45879839
Short name T761
Test name
Test status
Simulation time 29888957 ps
CPU time 0.64 seconds
Started Apr 18 12:37:40 PM PDT 24
Finished Apr 18 12:37:41 PM PDT 24
Peak memory 203672 kb
Host smart-0db17d29-f5d5-46b7-a5dd-8bde4bc7e2c8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45879839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_
walk.45879839
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2858030230
Short name T816
Test name
Test status
Simulation time 28145137 ps
CPU time 1.62 seconds
Started Apr 18 12:37:43 PM PDT 24
Finished Apr 18 12:37:45 PM PDT 24
Peak memory 214932 kb
Host smart-cd198430-bfca-4427-bb58-bedf4d2c1926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858030230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2858030230
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2913259649
Short name T792
Test name
Test status
Simulation time 495411152 ps
CPU time 3.37 seconds
Started Apr 18 12:37:45 PM PDT 24
Finished Apr 18 12:37:49 PM PDT 24
Peak memory 215236 kb
Host smart-5d92458f-a4f6-481f-9b7d-eaa39e862541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913259649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
913259649
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2677420288
Short name T793
Test name
Test status
Simulation time 2212705953 ps
CPU time 13.7 seconds
Started Apr 18 12:37:37 PM PDT 24
Finished Apr 18 12:37:51 PM PDT 24
Peak memory 215116 kb
Host smart-935e17ac-10db-45c5-9e3b-e7fceb88ab6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677420288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2677420288
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.322919617
Short name T786
Test name
Test status
Simulation time 605278579 ps
CPU time 21.21 seconds
Started Apr 18 12:37:51 PM PDT 24
Finished Apr 18 12:38:13 PM PDT 24
Peak memory 206856 kb
Host smart-97f996f0-d15e-47f2-b4ad-e40e0e781061
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322919617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.322919617
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2835009651
Short name T780
Test name
Test status
Simulation time 525635277 ps
CPU time 32.74 seconds
Started Apr 18 12:37:46 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 206880 kb
Host smart-35929bf8-20ab-44a3-9e03-4f91bdda7b7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835009651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2835009651
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2990599345
Short name T91
Test name
Test status
Simulation time 50263535 ps
CPU time 1.4 seconds
Started Apr 18 12:37:43 PM PDT 24
Finished Apr 18 12:37:45 PM PDT 24
Peak memory 215984 kb
Host smart-e1f5ec6f-ccf0-4a36-b2aa-f2234872b3f7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990599345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2990599345
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.724941447
Short name T734
Test name
Test status
Simulation time 71678963 ps
CPU time 2.36 seconds
Started Apr 18 12:37:45 PM PDT 24
Finished Apr 18 12:37:48 PM PDT 24
Peak memory 216092 kb
Host smart-2e9805c1-98d1-4c1d-8e62-8b62b35be1b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724941447 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.724941447
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3602491758
Short name T821
Test name
Test status
Simulation time 96246714 ps
CPU time 2.52 seconds
Started Apr 18 12:37:34 PM PDT 24
Finished Apr 18 12:37:37 PM PDT 24
Peak memory 206844 kb
Host smart-d79aba1a-61c1-45da-8cfe-130f9ea320c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602491758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
602491758
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.5583527
Short name T755
Test name
Test status
Simulation time 33759681 ps
CPU time 0.71 seconds
Started Apr 18 12:37:48 PM PDT 24
Finished Apr 18 12:37:49 PM PDT 24
Peak memory 203424 kb
Host smart-e2c6dacd-cd8e-4ddb-a430-a9818ac02483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5583527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.5583527
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.183452098
Short name T810
Test name
Test status
Simulation time 71179909 ps
CPU time 1.47 seconds
Started Apr 18 12:37:41 PM PDT 24
Finished Apr 18 12:37:44 PM PDT 24
Peak memory 215020 kb
Host smart-0ab97cab-121d-4a5c-a659-5be63e9684d6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183452098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.183452098
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1130992500
Short name T720
Test name
Test status
Simulation time 11216053 ps
CPU time 0.66 seconds
Started Apr 18 12:37:51 PM PDT 24
Finished Apr 18 12:37:53 PM PDT 24
Peak memory 203384 kb
Host smart-dce7e83a-d736-4dc3-a916-33afcdeed61c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130992500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1130992500
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1722863824
Short name T764
Test name
Test status
Simulation time 78682994 ps
CPU time 2.67 seconds
Started Apr 18 12:37:38 PM PDT 24
Finished Apr 18 12:37:41 PM PDT 24
Peak memory 215084 kb
Host smart-8498ea8a-4091-4acd-9cfc-0fd3becd61ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722863824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1722863824
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3176241002
Short name T784
Test name
Test status
Simulation time 657003862 ps
CPU time 14.57 seconds
Started Apr 18 12:37:46 PM PDT 24
Finished Apr 18 12:38:01 PM PDT 24
Peak memory 215004 kb
Host smart-8891a2a4-61c1-443c-b092-b3ea0d11cf5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176241002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3176241002
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1708513237
Short name T800
Test name
Test status
Simulation time 26961017 ps
CPU time 1.66 seconds
Started Apr 18 12:37:58 PM PDT 24
Finished Apr 18 12:38:01 PM PDT 24
Peak memory 216068 kb
Host smart-48ce4c0f-bbfb-417d-8e19-e44b71b1c1e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708513237 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1708513237
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2254161710
Short name T717
Test name
Test status
Simulation time 910999859 ps
CPU time 2.41 seconds
Started Apr 18 12:37:59 PM PDT 24
Finished Apr 18 12:38:02 PM PDT 24
Peak memory 215232 kb
Host smart-7c101e36-0322-44a5-a2bc-1fb10504e478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254161710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2254161710
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2621387023
Short name T726
Test name
Test status
Simulation time 30987207 ps
CPU time 0.82 seconds
Started Apr 18 12:38:01 PM PDT 24
Finished Apr 18 12:38:03 PM PDT 24
Peak memory 203548 kb
Host smart-75874b56-4409-4c23-a3db-485d00ecdcab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621387023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2621387023
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.995173130
Short name T741
Test name
Test status
Simulation time 157406560 ps
CPU time 4.34 seconds
Started Apr 18 12:38:02 PM PDT 24
Finished Apr 18 12:38:07 PM PDT 24
Peak memory 215052 kb
Host smart-6d87bbbe-351e-44b8-bd29-e2350b1ca1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995173130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.995173130
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.397165992
Short name T120
Test name
Test status
Simulation time 47830225 ps
CPU time 3.64 seconds
Started Apr 18 12:38:00 PM PDT 24
Finished Apr 18 12:38:04 PM PDT 24
Peak memory 215216 kb
Host smart-27743799-02d3-4ff1-8b4f-2dc45d732cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397165992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.397165992
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2702989451
Short name T35
Test name
Test status
Simulation time 217371808 ps
CPU time 13.07 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:18 PM PDT 24
Peak memory 215032 kb
Host smart-c5a3a4d9-6748-47cd-86dd-9c5402f76754
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702989451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2702989451
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4275590935
Short name T822
Test name
Test status
Simulation time 477105423 ps
CPU time 2.76 seconds
Started Apr 18 12:38:06 PM PDT 24
Finished Apr 18 12:38:09 PM PDT 24
Peak memory 216256 kb
Host smart-8d683a55-a133-4a10-a300-19df49376314
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275590935 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4275590935
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3712867536
Short name T753
Test name
Test status
Simulation time 432277134 ps
CPU time 2.45 seconds
Started Apr 18 12:38:07 PM PDT 24
Finished Apr 18 12:38:10 PM PDT 24
Peak memory 214900 kb
Host smart-df22c3d0-f08a-4892-be56-7246770608c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712867536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3712867536
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2214364907
Short name T736
Test name
Test status
Simulation time 14125382 ps
CPU time 0.72 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:06 PM PDT 24
Peak memory 203812 kb
Host smart-f28c5f8f-6ff9-4e41-a82c-489810c6bae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214364907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2214364907
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.143610404
Short name T36
Test name
Test status
Simulation time 535289660 ps
CPU time 3.01 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:07 PM PDT 24
Peak memory 215040 kb
Host smart-5d57c313-0073-4f58-8239-d289ebe66e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143610404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.143610404
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3252646961
Short name T740
Test name
Test status
Simulation time 367402422 ps
CPU time 12.43 seconds
Started Apr 18 12:38:00 PM PDT 24
Finished Apr 18 12:38:13 PM PDT 24
Peak memory 215048 kb
Host smart-4d3855e1-c105-4aa2-93e4-f930d6f1adcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252646961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3252646961
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3922684378
Short name T767
Test name
Test status
Simulation time 608458660 ps
CPU time 3.72 seconds
Started Apr 18 12:38:05 PM PDT 24
Finished Apr 18 12:38:09 PM PDT 24
Peak memory 216924 kb
Host smart-dea90605-5380-4756-9418-c7b0711dc2da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922684378 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3922684378
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1945642220
Short name T785
Test name
Test status
Simulation time 200628525 ps
CPU time 1.84 seconds
Started Apr 18 12:38:14 PM PDT 24
Finished Apr 18 12:38:17 PM PDT 24
Peak memory 214596 kb
Host smart-fb9ad5df-120b-44a6-9eaa-5d8c34c062cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945642220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1945642220
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1311258165
Short name T801
Test name
Test status
Simulation time 13658912 ps
CPU time 0.69 seconds
Started Apr 18 12:38:13 PM PDT 24
Finished Apr 18 12:38:15 PM PDT 24
Peak memory 203352 kb
Host smart-244029b6-56c7-4243-ae01-4da2df10f2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311258165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1311258165
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1646293468
Short name T791
Test name
Test status
Simulation time 82372422 ps
CPU time 1.93 seconds
Started Apr 18 12:38:06 PM PDT 24
Finished Apr 18 12:38:09 PM PDT 24
Peak memory 214968 kb
Host smart-2dd07629-e1a5-4b64-a732-65213f653ba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646293468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1646293468
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.583750480
Short name T118
Test name
Test status
Simulation time 307673259 ps
CPU time 2.5 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:07 PM PDT 24
Peak memory 215216 kb
Host smart-e4056a0c-1085-4529-a866-0cacac7c86b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583750480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.583750480
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3578554817
Short name T716
Test name
Test status
Simulation time 135438065 ps
CPU time 1.66 seconds
Started Apr 18 12:38:03 PM PDT 24
Finished Apr 18 12:38:05 PM PDT 24
Peak memory 215140 kb
Host smart-37e56646-563e-45ef-bea9-a1a6921b0fc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578554817 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3578554817
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.4126812954
Short name T812
Test name
Test status
Simulation time 65690131 ps
CPU time 2.42 seconds
Started Apr 18 12:38:01 PM PDT 24
Finished Apr 18 12:38:04 PM PDT 24
Peak memory 214960 kb
Host smart-5dfd2ff4-f966-4553-a5bd-0e5db23e5dff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126812954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
4126812954
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.432303655
Short name T718
Test name
Test status
Simulation time 14133273 ps
CPU time 0.74 seconds
Started Apr 18 12:38:08 PM PDT 24
Finished Apr 18 12:38:10 PM PDT 24
Peak memory 203444 kb
Host smart-7c575028-7fe2-4293-8302-954f7b2a5166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432303655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.432303655
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1836658411
Short name T731
Test name
Test status
Simulation time 43344197 ps
CPU time 1.71 seconds
Started Apr 18 12:38:02 PM PDT 24
Finished Apr 18 12:38:05 PM PDT 24
Peak memory 215072 kb
Host smart-2aead32b-d5f0-48fd-bc54-5a6fa90d16a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836658411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1836658411
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2809981861
Short name T820
Test name
Test status
Simulation time 200626460 ps
CPU time 3.37 seconds
Started Apr 18 12:38:08 PM PDT 24
Finished Apr 18 12:38:12 PM PDT 24
Peak memory 215176 kb
Host smart-f2fb07a8-c842-4749-822a-1e4017bf591b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809981861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2809981861
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2040795909
Short name T719
Test name
Test status
Simulation time 88789740 ps
CPU time 2.88 seconds
Started Apr 18 12:38:13 PM PDT 24
Finished Apr 18 12:38:17 PM PDT 24
Peak memory 216568 kb
Host smart-76dfd9de-3e61-40d2-b864-a7f413f342b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040795909 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2040795909
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3434142728
Short name T760
Test name
Test status
Simulation time 144301711 ps
CPU time 2.27 seconds
Started Apr 18 12:38:05 PM PDT 24
Finished Apr 18 12:38:08 PM PDT 24
Peak memory 215104 kb
Host smart-a1258bbd-d103-4804-9ac2-f08e1ca281f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434142728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3434142728
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2563169172
Short name T771
Test name
Test status
Simulation time 59284084 ps
CPU time 0.75 seconds
Started Apr 18 12:38:05 PM PDT 24
Finished Apr 18 12:38:06 PM PDT 24
Peak memory 203516 kb
Host smart-a449c7c4-e891-4b51-9ce5-4e61454d46fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563169172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2563169172
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.927338491
Short name T804
Test name
Test status
Simulation time 212636078 ps
CPU time 4.5 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:09 PM PDT 24
Peak memory 215024 kb
Host smart-31107fe4-d1ef-4488-96da-1873688db1d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927338491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.927338491
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3641666109
Short name T126
Test name
Test status
Simulation time 258733021 ps
CPU time 3.71 seconds
Started Apr 18 12:38:03 PM PDT 24
Finished Apr 18 12:38:07 PM PDT 24
Peak memory 216136 kb
Host smart-9f3732f6-b3cc-4166-bbcb-b4e31f7d1418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641666109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3641666109
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2312328945
Short name T807
Test name
Test status
Simulation time 2136634604 ps
CPU time 15.14 seconds
Started Apr 18 12:38:13 PM PDT 24
Finished Apr 18 12:38:29 PM PDT 24
Peak memory 215328 kb
Host smart-be886dd1-7a60-48c9-97dd-4e0673d8d780
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312328945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2312328945
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.890318535
Short name T794
Test name
Test status
Simulation time 690752367 ps
CPU time 2.46 seconds
Started Apr 18 12:38:05 PM PDT 24
Finished Apr 18 12:38:08 PM PDT 24
Peak memory 215056 kb
Host smart-b4911f04-f1df-4a45-b904-1b7412ba019e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890318535 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.890318535
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.247148087
Short name T133
Test name
Test status
Simulation time 199516013 ps
CPU time 2.36 seconds
Started Apr 18 12:38:10 PM PDT 24
Finished Apr 18 12:38:14 PM PDT 24
Peak memory 206736 kb
Host smart-0a9b0095-53c8-4282-9683-021494465f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247148087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.247148087
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4250785845
Short name T732
Test name
Test status
Simulation time 13726513 ps
CPU time 0.72 seconds
Started Apr 18 12:38:08 PM PDT 24
Finished Apr 18 12:38:10 PM PDT 24
Peak memory 203756 kb
Host smart-aa019157-f573-48cc-8a35-789822b0f604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250785845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4250785845
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2032874225
Short name T815
Test name
Test status
Simulation time 30167427 ps
CPU time 1.88 seconds
Started Apr 18 12:38:13 PM PDT 24
Finished Apr 18 12:38:15 PM PDT 24
Peak memory 214964 kb
Host smart-eb490504-745d-4e74-a7bd-a665783f9da9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032874225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2032874225
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.276596565
Short name T345
Test name
Test status
Simulation time 294655854 ps
CPU time 17.45 seconds
Started Apr 18 12:38:08 PM PDT 24
Finished Apr 18 12:38:26 PM PDT 24
Peak memory 215124 kb
Host smart-512c5c7e-0947-42ec-8270-0d5fa37aff05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276596565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.276596565
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2372117028
Short name T796
Test name
Test status
Simulation time 45144813 ps
CPU time 1.84 seconds
Started Apr 18 12:38:06 PM PDT 24
Finished Apr 18 12:38:09 PM PDT 24
Peak memory 216140 kb
Host smart-f47c20f3-8f04-485e-b17e-cfe4f77695a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372117028 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2372117028
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2373782025
Short name T722
Test name
Test status
Simulation time 60312483 ps
CPU time 2.02 seconds
Started Apr 18 12:38:08 PM PDT 24
Finished Apr 18 12:38:10 PM PDT 24
Peak memory 215036 kb
Host smart-525313c4-9179-401b-a90e-e2ba0367993a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373782025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2373782025
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2883866335
Short name T709
Test name
Test status
Simulation time 28336826 ps
CPU time 0.7 seconds
Started Apr 18 12:38:09 PM PDT 24
Finished Apr 18 12:38:11 PM PDT 24
Peak memory 203404 kb
Host smart-2b7290f1-deca-4487-b4d3-e34824d8fe31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883866335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2883866335
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3871807386
Short name T141
Test name
Test status
Simulation time 62602087 ps
CPU time 3.78 seconds
Started Apr 18 12:38:11 PM PDT 24
Finished Apr 18 12:38:16 PM PDT 24
Peak memory 214996 kb
Host smart-339f2953-96d4-43b7-9d3f-ec026e804c8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871807386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3871807386
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3859276962
Short name T795
Test name
Test status
Simulation time 2829608124 ps
CPU time 5.35 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:10 PM PDT 24
Peak memory 215248 kb
Host smart-82fed917-38a7-4a75-85b1-e41a3b35a975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859276962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3859276962
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.620363335
Short name T352
Test name
Test status
Simulation time 321158724 ps
CPU time 7.63 seconds
Started Apr 18 12:38:03 PM PDT 24
Finished Apr 18 12:38:11 PM PDT 24
Peak memory 216352 kb
Host smart-c3d75df9-459b-4111-8888-25179cabff82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620363335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.620363335
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1051367184
Short name T128
Test name
Test status
Simulation time 241615648 ps
CPU time 3.75 seconds
Started Apr 18 12:38:10 PM PDT 24
Finished Apr 18 12:38:15 PM PDT 24
Peak memory 217896 kb
Host smart-14e8a2c6-db1f-4050-ade4-f14615e95166
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051367184 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1051367184
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.282323057
Short name T806
Test name
Test status
Simulation time 127381704 ps
CPU time 2.12 seconds
Started Apr 18 12:38:07 PM PDT 24
Finished Apr 18 12:38:10 PM PDT 24
Peak memory 215020 kb
Host smart-79ea474f-e6be-4558-9aec-ea0235cb6e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282323057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.282323057
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2935073498
Short name T773
Test name
Test status
Simulation time 35120807 ps
CPU time 0.69 seconds
Started Apr 18 12:38:10 PM PDT 24
Finished Apr 18 12:38:12 PM PDT 24
Peak memory 203448 kb
Host smart-f5ac0ce6-4673-4b54-9bc8-2ce0c850c069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935073498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2935073498
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3580690320
Short name T759
Test name
Test status
Simulation time 163191237 ps
CPU time 3 seconds
Started Apr 18 12:38:14 PM PDT 24
Finished Apr 18 12:38:18 PM PDT 24
Peak memory 215052 kb
Host smart-f1ffd96a-c032-4857-8459-639da5f38c50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580690320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3580690320
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.30424359
Short name T119
Test name
Test status
Simulation time 71624315 ps
CPU time 4.06 seconds
Started Apr 18 12:38:24 PM PDT 24
Finished Apr 18 12:38:29 PM PDT 24
Peak memory 215320 kb
Host smart-aa9471c5-62dd-4229-9e14-1a1e0775eda3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30424359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.30424359
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.986656766
Short name T749
Test name
Test status
Simulation time 1216641327 ps
CPU time 8.14 seconds
Started Apr 18 12:38:06 PM PDT 24
Finished Apr 18 12:38:15 PM PDT 24
Peak memory 216232 kb
Host smart-73a39e9c-eb81-49a4-8dd6-241d060e262c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986656766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.986656766
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4213197575
Short name T802
Test name
Test status
Simulation time 137846501 ps
CPU time 3.33 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 217496 kb
Host smart-5dc1109c-1cbf-42bb-9ff6-cbd2efa84c65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213197575 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4213197575
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.569595170
Short name T757
Test name
Test status
Simulation time 117696432 ps
CPU time 2.76 seconds
Started Apr 18 12:38:18 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 214992 kb
Host smart-d939aea1-0986-457d-a288-04f913511229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569595170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.569595170
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3276090998
Short name T779
Test name
Test status
Simulation time 96847157 ps
CPU time 0.75 seconds
Started Apr 18 12:38:14 PM PDT 24
Finished Apr 18 12:38:16 PM PDT 24
Peak memory 203484 kb
Host smart-62f8ad21-ed40-499c-bfb4-c2e6a6cf533e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276090998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3276090998
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2847631753
Short name T782
Test name
Test status
Simulation time 369981737 ps
CPU time 2.03 seconds
Started Apr 18 12:38:19 PM PDT 24
Finished Apr 18 12:38:22 PM PDT 24
Peak memory 214972 kb
Host smart-4d715eaf-cb8f-4285-a892-2c522590441d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847631753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2847631753
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.552108818
Short name T811
Test name
Test status
Simulation time 122746525 ps
CPU time 3.81 seconds
Started Apr 18 12:38:07 PM PDT 24
Finished Apr 18 12:38:12 PM PDT 24
Peak memory 215216 kb
Host smart-893309d7-52ae-4137-9090-ce5a666f03a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552108818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.552108818
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2316992413
Short name T347
Test name
Test status
Simulation time 192079828 ps
CPU time 11.44 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:30 PM PDT 24
Peak memory 214968 kb
Host smart-a9b08d2e-baa9-47ad-a68f-a15db2d6171c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316992413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2316992413
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2071175400
Short name T809
Test name
Test status
Simulation time 64031833 ps
CPU time 1.81 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:20 PM PDT 24
Peak memory 216116 kb
Host smart-37e208e3-42b4-4d88-9b3b-62a49aafd8f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071175400 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2071175400
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3905029389
Short name T788
Test name
Test status
Simulation time 34232738 ps
CPU time 1.24 seconds
Started Apr 18 12:38:14 PM PDT 24
Finished Apr 18 12:38:16 PM PDT 24
Peak memory 214996 kb
Host smart-7519cb6f-29c7-4f3d-801a-615bec06fcab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905029389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3905029389
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1047501585
Short name T738
Test name
Test status
Simulation time 14841916 ps
CPU time 0.7 seconds
Started Apr 18 12:38:19 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 203416 kb
Host smart-8a2bed06-261c-4daf-98f9-c16dc6887922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047501585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1047501585
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3726948135
Short name T737
Test name
Test status
Simulation time 106293564 ps
CPU time 3.1 seconds
Started Apr 18 12:38:16 PM PDT 24
Finished Apr 18 12:38:20 PM PDT 24
Peak memory 215180 kb
Host smart-395028ce-ee91-4d2e-aed5-551b3576cd70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726948135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3726948135
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.168293964
Short name T819
Test name
Test status
Simulation time 135661817 ps
CPU time 2.39 seconds
Started Apr 18 12:38:18 PM PDT 24
Finished Apr 18 12:38:22 PM PDT 24
Peak memory 215224 kb
Host smart-8e6cea3d-67d7-43ee-a19e-608d2f543f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168293964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.168293964
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3399963762
Short name T112
Test name
Test status
Simulation time 2478130377 ps
CPU time 17.02 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:35 PM PDT 24
Peak memory 216112 kb
Host smart-0920224b-27ae-429b-b1dc-ced4ae6ad93e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399963762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3399963762
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3289304002
Short name T132
Test name
Test status
Simulation time 1264897475 ps
CPU time 24.18 seconds
Started Apr 18 12:37:46 PM PDT 24
Finished Apr 18 12:38:10 PM PDT 24
Peak memory 214992 kb
Host smart-ac7849b5-8560-4681-8bb6-ee66e12951f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289304002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3289304002
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3466983648
Short name T125
Test name
Test status
Simulation time 7249769534 ps
CPU time 25.77 seconds
Started Apr 18 12:37:42 PM PDT 24
Finished Apr 18 12:38:09 PM PDT 24
Peak memory 206880 kb
Host smart-71335f2d-4c18-4ff6-95ea-fe2f80b4aafb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466983648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3466983648
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1669718637
Short name T728
Test name
Test status
Simulation time 238173601 ps
CPU time 3.84 seconds
Started Apr 18 12:37:34 PM PDT 24
Finished Apr 18 12:37:38 PM PDT 24
Peak memory 217580 kb
Host smart-02bb232d-0d6d-430d-94f4-39dc57c25234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669718637 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1669718637
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3174434627
Short name T135
Test name
Test status
Simulation time 89683013 ps
CPU time 1.14 seconds
Started Apr 18 12:37:35 PM PDT 24
Finished Apr 18 12:37:36 PM PDT 24
Peak memory 206860 kb
Host smart-e09d5f55-1df9-411b-95e0-df9c36b55937
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174434627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
174434627
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.744631862
Short name T727
Test name
Test status
Simulation time 42830993 ps
CPU time 0.78 seconds
Started Apr 18 12:37:41 PM PDT 24
Finished Apr 18 12:37:43 PM PDT 24
Peak memory 203460 kb
Host smart-caf840d8-7218-492d-87a2-3a324a210413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744631862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.744631862
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.50962833
Short name T729
Test name
Test status
Simulation time 76802166 ps
CPU time 1.61 seconds
Started Apr 18 12:37:33 PM PDT 24
Finished Apr 18 12:37:35 PM PDT 24
Peak memory 215208 kb
Host smart-58920fbc-5475-46b3-a72f-2d9c046787e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50962833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_d
evice_mem_partial_access.50962833
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3070596322
Short name T751
Test name
Test status
Simulation time 13774398 ps
CPU time 0.68 seconds
Started Apr 18 12:37:41 PM PDT 24
Finished Apr 18 12:37:42 PM PDT 24
Peak memory 203324 kb
Host smart-9887387f-dcf4-4522-8e7b-7963f741da1d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070596322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3070596322
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3111263939
Short name T756
Test name
Test status
Simulation time 102377852 ps
CPU time 1.75 seconds
Started Apr 18 12:37:49 PM PDT 24
Finished Apr 18 12:37:52 PM PDT 24
Peak memory 214992 kb
Host smart-a9e2f6a7-7367-4278-9309-d4ae6d255287
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111263939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3111263939
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.768396095
Short name T763
Test name
Test status
Simulation time 510488552 ps
CPU time 4.16 seconds
Started Apr 18 12:37:47 PM PDT 24
Finished Apr 18 12:37:52 PM PDT 24
Peak memory 215224 kb
Host smart-40fef923-e358-453e-9c4d-9c9ec92eb631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768396095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.768396095
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3386780092
Short name T758
Test name
Test status
Simulation time 1108216668 ps
CPU time 14.58 seconds
Started Apr 18 12:37:41 PM PDT 24
Finished Apr 18 12:37:57 PM PDT 24
Peak memory 215048 kb
Host smart-83391b8a-8c87-443f-b680-b06bafb2167a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386780092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3386780092
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3652731321
Short name T745
Test name
Test status
Simulation time 16743783 ps
CPU time 0.76 seconds
Started Apr 18 12:38:13 PM PDT 24
Finished Apr 18 12:38:14 PM PDT 24
Peak memory 203528 kb
Host smart-dff1889d-ed2f-4d57-9953-48dd287ac607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652731321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3652731321
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4278167443
Short name T721
Test name
Test status
Simulation time 14853654 ps
CPU time 0.77 seconds
Started Apr 18 12:38:14 PM PDT 24
Finished Apr 18 12:38:16 PM PDT 24
Peak memory 203440 kb
Host smart-80ed8231-1c4e-4e18-a142-99e67c7ade6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278167443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4278167443
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1360747555
Short name T814
Test name
Test status
Simulation time 22468091 ps
CPU time 0.76 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 203800 kb
Host smart-371f44eb-281f-4534-a4c4-4735bb601eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360747555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1360747555
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.337539841
Short name T805
Test name
Test status
Simulation time 24017917 ps
CPU time 0.79 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 203516 kb
Host smart-c349f57a-dc5c-4492-a284-8991f7aa550c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337539841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.337539841
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2323856230
Short name T154
Test name
Test status
Simulation time 43349418 ps
CPU time 0.68 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 203740 kb
Host smart-5bea45b0-405e-4125-89a4-f559eb4c1e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323856230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2323856230
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.926317374
Short name T723
Test name
Test status
Simulation time 26513186 ps
CPU time 0.73 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 203720 kb
Host smart-eb07870c-5b0b-4b3e-809d-980b08ac6fa4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926317374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.926317374
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2056923487
Short name T704
Test name
Test status
Simulation time 16452796 ps
CPU time 0.77 seconds
Started Apr 18 12:38:18 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 203792 kb
Host smart-b77c5ba9-d18a-4536-b0dd-c875549f7445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056923487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2056923487
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3183504531
Short name T746
Test name
Test status
Simulation time 122882348 ps
CPU time 0.81 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:18 PM PDT 24
Peak memory 203776 kb
Host smart-b3331a87-5e18-4ef3-81cc-44816070d7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183504531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3183504531
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2840237242
Short name T733
Test name
Test status
Simulation time 24521162 ps
CPU time 0.8 seconds
Started Apr 18 12:38:17 PM PDT 24
Finished Apr 18 12:38:19 PM PDT 24
Peak memory 203804 kb
Host smart-d387ba83-77ba-409a-8474-957553ddb6ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840237242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2840237242
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.107367439
Short name T823
Test name
Test status
Simulation time 21193752 ps
CPU time 0.78 seconds
Started Apr 18 12:38:19 PM PDT 24
Finished Apr 18 12:38:20 PM PDT 24
Peak memory 203424 kb
Host smart-3b70059c-1e80-4858-b0f4-b37f10850757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107367439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.107367439
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3873210168
Short name T744
Test name
Test status
Simulation time 307180863 ps
CPU time 21.02 seconds
Started Apr 18 12:37:49 PM PDT 24
Finished Apr 18 12:38:11 PM PDT 24
Peak memory 214996 kb
Host smart-a0898544-b8d3-4902-ab51-872ac10c7736
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873210168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3873210168
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.824530348
Short name T725
Test name
Test status
Simulation time 3129163565 ps
CPU time 11.92 seconds
Started Apr 18 12:37:48 PM PDT 24
Finished Apr 18 12:38:00 PM PDT 24
Peak memory 206804 kb
Host smart-1932fb49-065d-4173-bfe0-055783710bbc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824530348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.824530348
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.973094615
Short name T817
Test name
Test status
Simulation time 60297438 ps
CPU time 1.25 seconds
Started Apr 18 12:37:50 PM PDT 24
Finished Apr 18 12:37:52 PM PDT 24
Peak memory 206752 kb
Host smart-448cf223-6906-492e-9d9f-d191a63bcfb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973094615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.973094615
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3156178723
Short name T113
Test name
Test status
Simulation time 122508490 ps
CPU time 2.98 seconds
Started Apr 18 12:37:48 PM PDT 24
Finished Apr 18 12:37:52 PM PDT 24
Peak memory 215856 kb
Host smart-7123c968-b991-4fac-984e-70ea9a478430
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156178723 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3156178723
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2040953891
Short name T138
Test name
Test status
Simulation time 69589925 ps
CPU time 1.27 seconds
Started Apr 18 12:37:43 PM PDT 24
Finished Apr 18 12:37:44 PM PDT 24
Peak memory 206844 kb
Host smart-b4db5994-af83-4161-b85f-8325f18c718f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040953891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
040953891
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3576969350
Short name T710
Test name
Test status
Simulation time 103788602 ps
CPU time 0.69 seconds
Started Apr 18 12:37:42 PM PDT 24
Finished Apr 18 12:37:43 PM PDT 24
Peak memory 203744 kb
Host smart-9ef7227c-5d07-44c1-8681-1d9c8b53bb49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576969350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
576969350
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.424870358
Short name T735
Test name
Test status
Simulation time 54813785 ps
CPU time 1.98 seconds
Started Apr 18 12:37:50 PM PDT 24
Finished Apr 18 12:37:53 PM PDT 24
Peak memory 215116 kb
Host smart-7fdc9bd8-4fa3-468e-96e8-bb98f080e289
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424870358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.424870358
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1946031069
Short name T742
Test name
Test status
Simulation time 10594440 ps
CPU time 0.65 seconds
Started Apr 18 12:37:41 PM PDT 24
Finished Apr 18 12:37:43 PM PDT 24
Peak memory 203288 kb
Host smart-df6fcf0d-53e9-4d3e-9379-e44f1e321391
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946031069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1946031069
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2705195688
Short name T38
Test name
Test status
Simulation time 61506279 ps
CPU time 1.75 seconds
Started Apr 18 12:37:53 PM PDT 24
Finished Apr 18 12:37:56 PM PDT 24
Peak memory 214940 kb
Host smart-1120cc08-ac59-4218-bb58-727fa08c7c3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705195688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2705195688
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2974724010
Short name T813
Test name
Test status
Simulation time 3882009830 ps
CPU time 20.02 seconds
Started Apr 18 12:37:33 PM PDT 24
Finished Apr 18 12:37:54 PM PDT 24
Peak memory 215156 kb
Host smart-18987e72-60a1-47e3-8806-423df776c010
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974724010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2974724010
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2718298494
Short name T803
Test name
Test status
Simulation time 67277313 ps
CPU time 0.74 seconds
Started Apr 18 12:38:19 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 203800 kb
Host smart-42f7b000-4c70-4140-ac3d-ec31cc89b55d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718298494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2718298494
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.726784905
Short name T711
Test name
Test status
Simulation time 16408582 ps
CPU time 0.79 seconds
Started Apr 18 12:38:19 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 203496 kb
Host smart-adcdd89c-5acd-4e12-a26b-790a55625c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726784905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.726784905
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2977149780
Short name T768
Test name
Test status
Simulation time 44972590 ps
CPU time 0.78 seconds
Started Apr 18 12:38:15 PM PDT 24
Finished Apr 18 12:38:16 PM PDT 24
Peak memory 204068 kb
Host smart-584391e4-7ab5-4f70-b18d-d362da99434a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977149780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2977149780
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.732785759
Short name T789
Test name
Test status
Simulation time 44385019 ps
CPU time 0.73 seconds
Started Apr 18 12:38:16 PM PDT 24
Finished Apr 18 12:38:18 PM PDT 24
Peak memory 203416 kb
Host smart-9a4bf7b4-3bf7-40d6-b366-35f012295d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732785759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.732785759
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3634804334
Short name T708
Test name
Test status
Simulation time 16911556 ps
CPU time 0.77 seconds
Started Apr 18 12:38:15 PM PDT 24
Finished Apr 18 12:38:16 PM PDT 24
Peak memory 203764 kb
Host smart-8acc6f47-88d8-4f3d-bad5-e1ee6e8512b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634804334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3634804334
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3040554337
Short name T714
Test name
Test status
Simulation time 42377602 ps
CPU time 0.73 seconds
Started Apr 18 12:38:19 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 203452 kb
Host smart-ad9af5a5-9d46-43b3-a5cf-9e87d9c86549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040554337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3040554337
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3089015727
Short name T799
Test name
Test status
Simulation time 29931984 ps
CPU time 0.73 seconds
Started Apr 18 12:38:16 PM PDT 24
Finished Apr 18 12:38:17 PM PDT 24
Peak memory 203440 kb
Host smart-b15cb207-1389-4ca9-a2a6-bdd773bff441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089015727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3089015727
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.824052020
Short name T778
Test name
Test status
Simulation time 25428446 ps
CPU time 0.72 seconds
Started Apr 18 12:38:13 PM PDT 24
Finished Apr 18 12:38:15 PM PDT 24
Peak memory 203480 kb
Host smart-79e2ef59-9971-488e-82d5-23c01236e939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824052020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.824052020
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1709414855
Short name T730
Test name
Test status
Simulation time 36705052 ps
CPU time 0.73 seconds
Started Apr 18 12:38:16 PM PDT 24
Finished Apr 18 12:38:18 PM PDT 24
Peak memory 203788 kb
Host smart-063cacd5-434a-4322-98f8-003486c46ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709414855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1709414855
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3488279850
Short name T774
Test name
Test status
Simulation time 11387982 ps
CPU time 0.79 seconds
Started Apr 18 12:38:16 PM PDT 24
Finished Apr 18 12:38:17 PM PDT 24
Peak memory 203408 kb
Host smart-158131f9-03fe-4da9-a88b-f6a6fba284e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488279850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3488279850
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.530280591
Short name T137
Test name
Test status
Simulation time 1089892322 ps
CPU time 21.88 seconds
Started Apr 18 12:37:48 PM PDT 24
Finished Apr 18 12:38:11 PM PDT 24
Peak memory 214820 kb
Host smart-621ee2b0-078e-49fb-b071-b50a579cd3ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530280591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.530280591
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2717591076
Short name T131
Test name
Test status
Simulation time 4361207582 ps
CPU time 31.14 seconds
Started Apr 18 12:37:36 PM PDT 24
Finished Apr 18 12:38:08 PM PDT 24
Peak memory 206944 kb
Host smart-d6ab3163-c870-43be-939b-37899899ce2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717591076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2717591076
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3781242296
Short name T93
Test name
Test status
Simulation time 65212331 ps
CPU time 1.2 seconds
Started Apr 18 12:37:59 PM PDT 24
Finished Apr 18 12:38:01 PM PDT 24
Peak memory 216056 kb
Host smart-343f16bb-de0f-4595-9056-7796c8175996
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781242296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3781242296
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3987155074
Short name T790
Test name
Test status
Simulation time 39287999 ps
CPU time 2.87 seconds
Started Apr 18 12:37:44 PM PDT 24
Finished Apr 18 12:37:47 PM PDT 24
Peak memory 218072 kb
Host smart-97e62f73-f3b2-48e4-a868-a848b58e53cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987155074 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3987155074
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2219784885
Short name T142
Test name
Test status
Simulation time 172358100 ps
CPU time 2.64 seconds
Started Apr 18 12:37:53 PM PDT 24
Finished Apr 18 12:37:57 PM PDT 24
Peak memory 215080 kb
Host smart-2322e27d-7deb-4453-bb5e-d0d7b5de1d26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219784885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
219784885
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4036150320
Short name T747
Test name
Test status
Simulation time 13134790 ps
CPU time 0.71 seconds
Started Apr 18 12:37:58 PM PDT 24
Finished Apr 18 12:38:00 PM PDT 24
Peak memory 203412 kb
Host smart-e82233fd-ff29-4e66-a712-af61f8941b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036150320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
036150320
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2581319608
Short name T130
Test name
Test status
Simulation time 157811288 ps
CPU time 1.6 seconds
Started Apr 18 12:37:48 PM PDT 24
Finished Apr 18 12:37:50 PM PDT 24
Peak memory 214944 kb
Host smart-447a9078-c4d5-4ce2-ada6-13a44a1efa7b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581319608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2581319608
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3408616962
Short name T808
Test name
Test status
Simulation time 26468043 ps
CPU time 0.71 seconds
Started Apr 18 12:37:54 PM PDT 24
Finished Apr 18 12:37:56 PM PDT 24
Peak memory 203304 kb
Host smart-1ef3ee83-1342-4d6d-b55c-3580c5dcaea3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408616962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3408616962
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2482912251
Short name T770
Test name
Test status
Simulation time 165865569 ps
CPU time 4.09 seconds
Started Apr 18 12:37:49 PM PDT 24
Finished Apr 18 12:37:54 PM PDT 24
Peak memory 215112 kb
Host smart-77b852c5-c8b5-41ed-b9ef-c6772e91e1f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482912251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2482912251
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.478111213
Short name T797
Test name
Test status
Simulation time 39232295 ps
CPU time 2.65 seconds
Started Apr 18 12:37:46 PM PDT 24
Finished Apr 18 12:37:49 PM PDT 24
Peak memory 215096 kb
Host smart-d2b857e4-39ee-4980-a9c5-1dd66dc7ce79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478111213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.478111213
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.444807317
Short name T350
Test name
Test status
Simulation time 1130278794 ps
CPU time 14.48 seconds
Started Apr 18 12:38:02 PM PDT 24
Finished Apr 18 12:38:17 PM PDT 24
Peak memory 215480 kb
Host smart-45502051-9379-4e4e-986a-8eb281638669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444807317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.444807317
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1868329363
Short name T762
Test name
Test status
Simulation time 15525903 ps
CPU time 0.69 seconds
Started Apr 18 12:38:28 PM PDT 24
Finished Apr 18 12:38:30 PM PDT 24
Peak memory 203460 kb
Host smart-9343cccf-f32b-47fd-8e48-2aa73d77f497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868329363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1868329363
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3210048031
Short name T705
Test name
Test status
Simulation time 49298220 ps
CPU time 0.76 seconds
Started Apr 18 12:38:24 PM PDT 24
Finished Apr 18 12:38:25 PM PDT 24
Peak memory 203420 kb
Host smart-8a4bfcf9-702c-4d67-8a8e-69c87d4e519a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210048031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3210048031
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.520419120
Short name T153
Test name
Test status
Simulation time 37152393 ps
CPU time 0.67 seconds
Started Apr 18 12:38:25 PM PDT 24
Finished Apr 18 12:38:26 PM PDT 24
Peak memory 203720 kb
Host smart-a1145b56-379e-47e7-b2e9-5b33ac856f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520419120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.520419120
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1633855793
Short name T818
Test name
Test status
Simulation time 121414497 ps
CPU time 0.73 seconds
Started Apr 18 12:38:19 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 203404 kb
Host smart-28650e6d-d742-4e89-a7ca-8d5219ab4f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633855793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1633855793
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1930692543
Short name T775
Test name
Test status
Simulation time 12421146 ps
CPU time 0.76 seconds
Started Apr 18 12:38:21 PM PDT 24
Finished Apr 18 12:38:22 PM PDT 24
Peak memory 203440 kb
Host smart-c7d14aae-16e6-45d3-b366-7e5a51575afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930692543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1930692543
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2905111948
Short name T754
Test name
Test status
Simulation time 40821559 ps
CPU time 0.71 seconds
Started Apr 18 12:38:27 PM PDT 24
Finished Apr 18 12:38:28 PM PDT 24
Peak memory 203464 kb
Host smart-d873a28a-b367-4051-9962-9cba07ca87a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905111948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2905111948
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1334595892
Short name T824
Test name
Test status
Simulation time 14130153 ps
CPU time 0.76 seconds
Started Apr 18 12:38:28 PM PDT 24
Finished Apr 18 12:38:30 PM PDT 24
Peak memory 203436 kb
Host smart-940b4823-c070-49f2-ba2d-b0a8907a45ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334595892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1334595892
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1791490371
Short name T707
Test name
Test status
Simulation time 11158418 ps
CPU time 0.71 seconds
Started Apr 18 12:38:20 PM PDT 24
Finished Apr 18 12:38:22 PM PDT 24
Peak memory 203440 kb
Host smart-2fe76284-5c5a-4e80-a86a-a91c35ebdda6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791490371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1791490371
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2262237581
Short name T712
Test name
Test status
Simulation time 26875307 ps
CPU time 0.68 seconds
Started Apr 18 12:38:16 PM PDT 24
Finished Apr 18 12:38:18 PM PDT 24
Peak memory 203480 kb
Host smart-712137ee-3e25-437d-8a30-5b16cb570c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262237581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2262237581
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.695690731
Short name T787
Test name
Test status
Simulation time 479295917 ps
CPU time 3.83 seconds
Started Apr 18 12:37:50 PM PDT 24
Finished Apr 18 12:37:54 PM PDT 24
Peak memory 216364 kb
Host smart-ecd6c22f-e32b-4d25-9447-78b724854ae3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695690731 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.695690731
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3459327156
Short name T781
Test name
Test status
Simulation time 77061867 ps
CPU time 1.33 seconds
Started Apr 18 12:38:00 PM PDT 24
Finished Apr 18 12:38:02 PM PDT 24
Peak memory 206772 kb
Host smart-b72171e3-227f-41f2-bd1c-2916204629a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459327156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
459327156
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.835661049
Short name T715
Test name
Test status
Simulation time 14337880 ps
CPU time 0.73 seconds
Started Apr 18 12:37:36 PM PDT 24
Finished Apr 18 12:37:37 PM PDT 24
Peak memory 203420 kb
Host smart-a6572888-98ff-4815-83e7-deb0bef4d6a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835661049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.835661049
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4182280922
Short name T140
Test name
Test status
Simulation time 160455953 ps
CPU time 4.52 seconds
Started Apr 18 12:37:50 PM PDT 24
Finished Apr 18 12:37:55 PM PDT 24
Peak memory 215084 kb
Host smart-33d4e4d6-6ca4-4f06-943d-c2e6defe070c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182280922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4182280922
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.465914582
Short name T114
Test name
Test status
Simulation time 154733763 ps
CPU time 1.73 seconds
Started Apr 18 12:37:47 PM PDT 24
Finished Apr 18 12:37:50 PM PDT 24
Peak memory 215164 kb
Host smart-814d8ca5-0619-4bf2-8a6d-3d547d204450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465914582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.465914582
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1453979550
Short name T346
Test name
Test status
Simulation time 197199345 ps
CPU time 11.66 seconds
Started Apr 18 12:37:51 PM PDT 24
Finished Apr 18 12:38:04 PM PDT 24
Peak memory 215124 kb
Host smart-ebc8903f-7234-4897-86dd-86814c7514e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453979550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1453979550
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1140196742
Short name T743
Test name
Test status
Simulation time 135319947 ps
CPU time 3.96 seconds
Started Apr 18 12:37:51 PM PDT 24
Finished Apr 18 12:37:56 PM PDT 24
Peak memory 217308 kb
Host smart-746d04ab-bd7f-41d8-8a8b-49432651b6d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140196742 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1140196742
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2249963568
Short name T765
Test name
Test status
Simulation time 63341664 ps
CPU time 1.24 seconds
Started Apr 18 12:37:53 PM PDT 24
Finished Apr 18 12:37:55 PM PDT 24
Peak memory 206868 kb
Host smart-d5e20342-38df-4042-beaf-0de6d4bdbda8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249963568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
249963568
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.765022205
Short name T713
Test name
Test status
Simulation time 71102113 ps
CPU time 0.67 seconds
Started Apr 18 12:37:53 PM PDT 24
Finished Apr 18 12:37:55 PM PDT 24
Peak memory 203448 kb
Host smart-344c9c49-848e-44dd-9893-f1b3baa24bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765022205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.765022205
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3496040528
Short name T769
Test name
Test status
Simulation time 62102712 ps
CPU time 3.89 seconds
Started Apr 18 12:37:51 PM PDT 24
Finished Apr 18 12:37:55 PM PDT 24
Peak memory 215024 kb
Host smart-0b84a89b-bd38-4fb0-9ee2-60db04a503c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496040528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3496040528
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1286250705
Short name T798
Test name
Test status
Simulation time 243731619 ps
CPU time 3.62 seconds
Started Apr 18 12:37:52 PM PDT 24
Finished Apr 18 12:37:57 PM PDT 24
Peak memory 215224 kb
Host smart-506332c3-a0bc-453f-8975-9b38ed837a91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286250705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
286250705
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3724491825
Short name T351
Test name
Test status
Simulation time 668936553 ps
CPU time 15.34 seconds
Started Apr 18 12:37:49 PM PDT 24
Finished Apr 18 12:38:05 PM PDT 24
Peak memory 215056 kb
Host smart-76750752-4644-4816-8df7-5dc8f2800417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724491825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3724491825
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3911350813
Short name T724
Test name
Test status
Simulation time 282495665 ps
CPU time 1.59 seconds
Started Apr 18 12:37:52 PM PDT 24
Finished Apr 18 12:37:54 PM PDT 24
Peak memory 215064 kb
Host smart-ee6ab1f8-fd28-4623-a28e-706326dbbcef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911350813 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3911350813
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3222076458
Short name T750
Test name
Test status
Simulation time 307895258 ps
CPU time 2.06 seconds
Started Apr 18 12:38:04 PM PDT 24
Finished Apr 18 12:38:06 PM PDT 24
Peak memory 215080 kb
Host smart-ff3aa803-8c29-4c20-a0e4-7a170b793e3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222076458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
222076458
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2221355274
Short name T703
Test name
Test status
Simulation time 20569385 ps
CPU time 0.67 seconds
Started Apr 18 12:37:53 PM PDT 24
Finished Apr 18 12:37:55 PM PDT 24
Peak memory 203392 kb
Host smart-ca70c93f-f2ee-4c40-8617-dbd82b0bce22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221355274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
221355274
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3959677583
Short name T37
Test name
Test status
Simulation time 80245716 ps
CPU time 2.6 seconds
Started Apr 18 12:37:47 PM PDT 24
Finished Apr 18 12:37:50 PM PDT 24
Peak memory 215012 kb
Host smart-529d3f2b-65c0-4aca-92e7-948e584b7a93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959677583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3959677583
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3026349902
Short name T122
Test name
Test status
Simulation time 487393842 ps
CPU time 3.01 seconds
Started Apr 18 12:37:52 PM PDT 24
Finished Apr 18 12:37:56 PM PDT 24
Peak memory 215200 kb
Host smart-c1b96335-c28b-4538-aad7-db1ed41db2a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026349902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
026349902
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3522574417
Short name T349
Test name
Test status
Simulation time 1026268501 ps
CPU time 22.88 seconds
Started Apr 18 12:37:58 PM PDT 24
Finished Apr 18 12:38:21 PM PDT 24
Peak memory 215440 kb
Host smart-bc3b623b-3713-4816-bed4-0c6672316d45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522574417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3522574417
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3756800765
Short name T752
Test name
Test status
Simulation time 28550933 ps
CPU time 1.84 seconds
Started Apr 18 12:38:01 PM PDT 24
Finished Apr 18 12:38:03 PM PDT 24
Peak memory 215064 kb
Host smart-a331879b-8537-43a5-9ee7-5c54e1794103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756800765 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3756800765
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3016129169
Short name T136
Test name
Test status
Simulation time 65754156 ps
CPU time 1.91 seconds
Started Apr 18 12:37:55 PM PDT 24
Finished Apr 18 12:37:59 PM PDT 24
Peak memory 214976 kb
Host smart-71e0b7ef-fe33-4b04-8daf-efb50e069923
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016129169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
016129169
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3240118010
Short name T155
Test name
Test status
Simulation time 19927828 ps
CPU time 0.77 seconds
Started Apr 18 12:37:56 PM PDT 24
Finished Apr 18 12:37:58 PM PDT 24
Peak memory 203496 kb
Host smart-472f1345-73eb-4004-962c-d79c8a6288c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240118010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
240118010
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2336394298
Short name T766
Test name
Test status
Simulation time 119232565 ps
CPU time 2.91 seconds
Started Apr 18 12:37:49 PM PDT 24
Finished Apr 18 12:37:53 PM PDT 24
Peak memory 215064 kb
Host smart-5ff12508-3f52-454f-9369-654a094aadd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336394298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2336394298
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1539080000
Short name T115
Test name
Test status
Simulation time 86204872 ps
CPU time 2.6 seconds
Started Apr 18 12:37:49 PM PDT 24
Finished Apr 18 12:37:53 PM PDT 24
Peak memory 215176 kb
Host smart-93a88529-b6dc-4980-aaa2-c11c8ff095d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539080000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
539080000
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.747852393
Short name T107
Test name
Test status
Simulation time 106413693 ps
CPU time 2.74 seconds
Started Apr 18 12:37:55 PM PDT 24
Finished Apr 18 12:37:58 PM PDT 24
Peak memory 217768 kb
Host smart-a0116996-ed6b-4e88-a7ee-7b83b6eae3a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747852393 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.747852393
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3651315750
Short name T776
Test name
Test status
Simulation time 47192057 ps
CPU time 1.46 seconds
Started Apr 18 12:37:59 PM PDT 24
Finished Apr 18 12:38:01 PM PDT 24
Peak memory 207112 kb
Host smart-64ff6205-091c-432c-92a5-4cb51d0bb142
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651315750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
651315750
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3109658413
Short name T748
Test name
Test status
Simulation time 19136212 ps
CPU time 0.72 seconds
Started Apr 18 12:37:55 PM PDT 24
Finished Apr 18 12:37:56 PM PDT 24
Peak memory 203436 kb
Host smart-35898306-28e9-4b8e-bff5-12400f6f2a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109658413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
109658413
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.503303425
Short name T143
Test name
Test status
Simulation time 131669719 ps
CPU time 3.02 seconds
Started Apr 18 12:37:54 PM PDT 24
Finished Apr 18 12:37:58 PM PDT 24
Peak memory 215116 kb
Host smart-03eb2126-65b1-46d0-8dcb-e5b2d60ee826
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503303425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.503303425
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.772726335
Short name T121
Test name
Test status
Simulation time 102530244 ps
CPU time 1.94 seconds
Started Apr 18 12:38:03 PM PDT 24
Finished Apr 18 12:38:05 PM PDT 24
Peak memory 215220 kb
Host smart-e704e8a9-7dd8-4fa3-b286-5b02b5d69a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772726335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.772726335
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1722169588
Short name T783
Test name
Test status
Simulation time 299518459 ps
CPU time 7.52 seconds
Started Apr 18 12:37:54 PM PDT 24
Finished Apr 18 12:38:03 PM PDT 24
Peak memory 215024 kb
Host smart-bbc19996-db2d-4404-b45c-9101414ac958
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722169588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1722169588
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.799635123
Short name T545
Test name
Test status
Simulation time 88375610 ps
CPU time 0.84 seconds
Started Apr 18 12:43:52 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 206488 kb
Host smart-99d2021a-cb24-4ed7-b27b-6482799ca6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799635123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.799635123
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3685701713
Short name T339
Test name
Test status
Simulation time 1243839163 ps
CPU time 31.92 seconds
Started Apr 18 12:43:58 PM PDT 24
Finished Apr 18 12:44:30 PM PDT 24
Peak memory 248816 kb
Host smart-e933c412-844f-412b-a66c-6a9a55c8d6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685701713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3685701713
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2733954639
Short name T275
Test name
Test status
Simulation time 1760233149 ps
CPU time 11.29 seconds
Started Apr 18 12:44:00 PM PDT 24
Finished Apr 18 12:44:12 PM PDT 24
Peak memory 221840 kb
Host smart-e7346da4-2d20-4ced-8ea4-5e76d837326e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733954639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2733954639
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.486584543
Short name T461
Test name
Test status
Simulation time 2784957752 ps
CPU time 22.85 seconds
Started Apr 18 12:43:59 PM PDT 24
Finished Apr 18 12:44:23 PM PDT 24
Peak memory 222288 kb
Host smart-45592755-c58c-4a36-857d-11ab9131ceec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=486584543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.486584543
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2598824187
Short name T564
Test name
Test status
Simulation time 518161220 ps
CPU time 2.71 seconds
Started Apr 18 12:43:51 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 216236 kb
Host smart-b0c7dc4a-b8ea-4c91-b5c3-f86490a59d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598824187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2598824187
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.479743870
Short name T653
Test name
Test status
Simulation time 49523103 ps
CPU time 0.81 seconds
Started Apr 18 12:43:53 PM PDT 24
Finished Apr 18 12:43:54 PM PDT 24
Peak memory 205572 kb
Host smart-3cb72ac9-2eef-47f8-a63c-3927230ff5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479743870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.479743870
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1863518841
Short name T420
Test name
Test status
Simulation time 11852852 ps
CPU time 0.72 seconds
Started Apr 18 12:44:07 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 205284 kb
Host smart-10b09283-f34f-4fa5-a990-e1e43a9f4d65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863518841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
863518841
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1074755835
Short name T82
Test name
Test status
Simulation time 573916298 ps
CPU time 4.11 seconds
Started Apr 18 12:44:02 PM PDT 24
Finished Apr 18 12:44:07 PM PDT 24
Peak memory 222872 kb
Host smart-cad6e0d3-bc36-48ce-ab40-e6715877346d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074755835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1074755835
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2540239577
Short name T622
Test name
Test status
Simulation time 25134543 ps
CPU time 0.84 seconds
Started Apr 18 12:44:01 PM PDT 24
Finished Apr 18 12:44:03 PM PDT 24
Peak memory 206824 kb
Host smart-4e15c290-2f56-4daa-8ab3-f3338b76cbb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540239577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2540239577
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4178093533
Short name T463
Test name
Test status
Simulation time 158575463 ps
CPU time 3.68 seconds
Started Apr 18 12:43:58 PM PDT 24
Finished Apr 18 12:44:02 PM PDT 24
Peak memory 219860 kb
Host smart-24c6e7f4-3c41-4150-8e2a-f7e904ec272c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4178093533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4178093533
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2611291224
Short name T47
Test name
Test status
Simulation time 347883260 ps
CPU time 1.21 seconds
Started Apr 18 12:44:13 PM PDT 24
Finished Apr 18 12:44:15 PM PDT 24
Peak memory 234880 kb
Host smart-1513b962-2220-4c86-9b89-9437b9986a01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611291224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2611291224
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1263528617
Short name T621
Test name
Test status
Simulation time 9601615269 ps
CPU time 53.95 seconds
Started Apr 18 12:43:58 PM PDT 24
Finished Apr 18 12:44:53 PM PDT 24
Peak memory 216180 kb
Host smart-eef993dc-6538-464f-ab58-166e2c4b2179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263528617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1263528617
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3050913779
Short name T418
Test name
Test status
Simulation time 804209978 ps
CPU time 4.4 seconds
Started Apr 18 12:44:03 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 216100 kb
Host smart-6b1284c8-c20b-4694-ab2c-3899ecce9bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050913779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3050913779
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3469989219
Short name T556
Test name
Test status
Simulation time 82111970 ps
CPU time 1.48 seconds
Started Apr 18 12:44:00 PM PDT 24
Finished Apr 18 12:44:02 PM PDT 24
Peak memory 216152 kb
Host smart-732481d8-621e-4376-9003-73223cd768f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469989219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3469989219
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2039270841
Short name T544
Test name
Test status
Simulation time 1553172023 ps
CPU time 1.07 seconds
Started Apr 18 12:43:59 PM PDT 24
Finished Apr 18 12:44:01 PM PDT 24
Peak memory 206564 kb
Host smart-2b49eeeb-1149-4040-9059-0d723173e295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039270841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2039270841
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2855431155
Short name T482
Test name
Test status
Simulation time 24320250 ps
CPU time 0.72 seconds
Started Apr 18 12:44:29 PM PDT 24
Finished Apr 18 12:44:31 PM PDT 24
Peak memory 204676 kb
Host smart-e535251b-8820-4162-8ade-4cdf0712d313
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855431155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2855431155
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.826588428
Short name T409
Test name
Test status
Simulation time 28710283 ps
CPU time 0.75 seconds
Started Apr 18 12:44:31 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 206376 kb
Host smart-4bf089ac-a562-475e-8854-634995cffec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826588428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.826588428
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3632262608
Short name T117
Test name
Test status
Simulation time 49347104962 ps
CPU time 103.52 seconds
Started Apr 18 12:44:36 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 219056 kb
Host smart-fff8de51-bc29-4f3f-9448-f02f9ce9a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632262608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3632262608
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1836017288
Short name T580
Test name
Test status
Simulation time 5232099771 ps
CPU time 11.52 seconds
Started Apr 18 12:44:35 PM PDT 24
Finished Apr 18 12:44:48 PM PDT 24
Peak memory 218740 kb
Host smart-698e7951-ee81-4d24-9ef3-ef9e7ef67f59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1836017288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1836017288
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1859888151
Short name T371
Test name
Test status
Simulation time 3540443118 ps
CPU time 27.7 seconds
Started Apr 18 12:44:30 PM PDT 24
Finished Apr 18 12:44:59 PM PDT 24
Peak memory 216660 kb
Host smart-2056b214-abd5-4de5-a248-c893eae3cdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859888151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1859888151
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3937312452
Short name T660
Test name
Test status
Simulation time 3488256901 ps
CPU time 7.62 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 216140 kb
Host smart-dce6e01e-bc5d-4204-892b-5b50c37fe648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937312452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3937312452
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.773104454
Short name T654
Test name
Test status
Simulation time 29710644 ps
CPU time 0.99 seconds
Started Apr 18 12:44:34 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 206584 kb
Host smart-655ecda2-3072-4158-a36c-9872caa7c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773104454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.773104454
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3921616902
Short name T21
Test name
Test status
Simulation time 101301375 ps
CPU time 0.82 seconds
Started Apr 18 12:44:25 PM PDT 24
Finished Apr 18 12:44:28 PM PDT 24
Peak memory 205684 kb
Host smart-539bcbcd-cf06-466c-8302-b37c07303621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921616902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3921616902
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3848284823
Short name T652
Test name
Test status
Simulation time 12516069 ps
CPU time 0.71 seconds
Started Apr 18 12:44:31 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 204784 kb
Host smart-76d9a1d0-328c-47b9-94d9-51d5cc0c79b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848284823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3848284823
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1072897170
Short name T632
Test name
Test status
Simulation time 97772827 ps
CPU time 0.82 seconds
Started Apr 18 12:44:25 PM PDT 24
Finished Apr 18 12:44:28 PM PDT 24
Peak memory 206456 kb
Host smart-1808acbc-6ea6-4b3e-912d-dad85b2b1002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072897170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1072897170
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.221038469
Short name T609
Test name
Test status
Simulation time 18422883043 ps
CPU time 79.47 seconds
Started Apr 18 12:44:25 PM PDT 24
Finished Apr 18 12:45:46 PM PDT 24
Peak memory 237184 kb
Host smart-43ad5d24-9b98-45cc-ada8-01f7f6a8cdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221038469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.221038469
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2484517498
Short name T586
Test name
Test status
Simulation time 8778971158 ps
CPU time 13.38 seconds
Started Apr 18 12:44:33 PM PDT 24
Finished Apr 18 12:44:47 PM PDT 24
Peak memory 222812 kb
Host smart-991bb8a7-7634-476d-a89f-774114572bef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2484517498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2484517498
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.582603625
Short name T40
Test name
Test status
Simulation time 73544142 ps
CPU time 1.01 seconds
Started Apr 18 12:44:44 PM PDT 24
Finished Apr 18 12:44:47 PM PDT 24
Peak memory 207000 kb
Host smart-c4595469-8b69-46c3-862b-8ac79630a46c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582603625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.582603625
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2850285636
Short name T361
Test name
Test status
Simulation time 897323894 ps
CPU time 7.72 seconds
Started Apr 18 12:44:28 PM PDT 24
Finished Apr 18 12:44:37 PM PDT 24
Peak memory 216064 kb
Host smart-295aa739-39e4-4517-87c7-a8d80fcae61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850285636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2850285636
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4024338547
Short name T599
Test name
Test status
Simulation time 2488305260 ps
CPU time 3.66 seconds
Started Apr 18 12:44:27 PM PDT 24
Finished Apr 18 12:44:32 PM PDT 24
Peak memory 216156 kb
Host smart-4542db8f-6999-4e1a-801c-99055d5ec63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024338547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4024338547
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2556450133
Short name T504
Test name
Test status
Simulation time 183790832 ps
CPU time 2.02 seconds
Started Apr 18 12:44:28 PM PDT 24
Finished Apr 18 12:44:31 PM PDT 24
Peak memory 216072 kb
Host smart-cecd65fd-bc85-49e0-ae0c-0d30f66b85d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556450133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2556450133
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2359281100
Short name T697
Test name
Test status
Simulation time 96268955 ps
CPU time 0.95 seconds
Started Apr 18 12:44:32 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 205576 kb
Host smart-b45e88ee-d14b-4bcb-a035-b2acaad75cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359281100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2359281100
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2608848785
Short name T617
Test name
Test status
Simulation time 11512555 ps
CPU time 0.73 seconds
Started Apr 18 12:44:34 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 205264 kb
Host smart-09c2525c-ccbf-4824-a7ec-e1d6fc6db2f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608848785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2608848785
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.393087152
Short name T410
Test name
Test status
Simulation time 64508182 ps
CPU time 0.75 seconds
Started Apr 18 12:44:31 PM PDT 24
Finished Apr 18 12:44:32 PM PDT 24
Peak memory 206728 kb
Host smart-c38922e8-1aa9-4586-84e6-3720e1bef3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393087152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.393087152
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2974812548
Short name T624
Test name
Test status
Simulation time 17954647477 ps
CPU time 126.14 seconds
Started Apr 18 12:44:26 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 239628 kb
Host smart-d653b8bc-f14c-4e73-8ea6-4b6becb5bb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974812548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2974812548
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2840925678
Short name T109
Test name
Test status
Simulation time 114308345493 ps
CPU time 267.14 seconds
Started Apr 18 12:44:33 PM PDT 24
Finished Apr 18 12:49:01 PM PDT 24
Peak memory 232448 kb
Host smart-c6e2efbc-bbfd-4dfe-84f0-cb349b5342c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840925678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2840925678
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3654556301
Short name T440
Test name
Test status
Simulation time 406652940 ps
CPU time 6.4 seconds
Started Apr 18 12:44:45 PM PDT 24
Finished Apr 18 12:44:52 PM PDT 24
Peak memory 219052 kb
Host smart-d6d6c0a0-d83f-47e2-b7e6-1dcdcdaeeb1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3654556301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3654556301
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3097288130
Short name T369
Test name
Test status
Simulation time 1667039073 ps
CPU time 9.49 seconds
Started Apr 18 12:44:26 PM PDT 24
Finished Apr 18 12:44:37 PM PDT 24
Peak memory 216284 kb
Host smart-5f72c86d-d8cd-4952-9d01-d1dcf7d8a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097288130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3097288130
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.198593720
Short name T465
Test name
Test status
Simulation time 3152709054 ps
CPU time 15.87 seconds
Started Apr 18 12:44:32 PM PDT 24
Finished Apr 18 12:44:48 PM PDT 24
Peak memory 216180 kb
Host smart-8fe37ae5-2197-4dc9-b1db-ed564d5cb584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198593720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.198593720
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1736633498
Short name T646
Test name
Test status
Simulation time 21357668 ps
CPU time 1.06 seconds
Started Apr 18 12:44:55 PM PDT 24
Finished Apr 18 12:44:57 PM PDT 24
Peak memory 207744 kb
Host smart-52334ac3-351d-4a74-b588-52afd9adf244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736633498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1736633498
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4072892891
Short name T594
Test name
Test status
Simulation time 197578964 ps
CPU time 0.75 seconds
Started Apr 18 12:44:28 PM PDT 24
Finished Apr 18 12:44:35 PM PDT 24
Peak memory 205540 kb
Host smart-12a2b495-5d5a-4d4c-ab9d-68f30ef4e28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072892891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4072892891
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2411365310
Short name T442
Test name
Test status
Simulation time 19188193 ps
CPU time 0.71 seconds
Started Apr 18 12:44:36 PM PDT 24
Finished Apr 18 12:44:38 PM PDT 24
Peak memory 204760 kb
Host smart-1e04dc72-273a-46d0-a8a5-0d2b90c44885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411365310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2411365310
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.84410995
Short name T484
Test name
Test status
Simulation time 12290529 ps
CPU time 0.74 seconds
Started Apr 18 12:44:41 PM PDT 24
Finished Apr 18 12:44:43 PM PDT 24
Peak memory 205788 kb
Host smart-313fe416-b679-4a54-95ac-36287532f62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84410995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.84410995
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1805669485
Short name T296
Test name
Test status
Simulation time 62647226584 ps
CPU time 51.94 seconds
Started Apr 18 12:44:32 PM PDT 24
Finished Apr 18 12:45:25 PM PDT 24
Peak memory 232496 kb
Host smart-61aeab24-f9eb-4a07-851d-4d1601063625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805669485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1805669485
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2986281375
Short name T263
Test name
Test status
Simulation time 56337318162 ps
CPU time 57.2 seconds
Started Apr 18 12:44:38 PM PDT 24
Finished Apr 18 12:45:36 PM PDT 24
Peak memory 235396 kb
Host smart-96a9f5b4-4a3b-4fd5-8f7a-eb06b1fac1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986281375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2986281375
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1017743630
Short name T305
Test name
Test status
Simulation time 44279028276 ps
CPU time 33.29 seconds
Started Apr 18 12:44:39 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 232664 kb
Host smart-098d9f41-f148-4c27-bcd2-f5fd060427be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017743630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1017743630
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2722140046
Short name T355
Test name
Test status
Simulation time 2446159302 ps
CPU time 30.68 seconds
Started Apr 18 12:44:40 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 216204 kb
Host smart-0304b45b-8ba7-4c26-a779-7eddce9d5d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722140046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2722140046
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.489503916
Short name T694
Test name
Test status
Simulation time 26215586940 ps
CPU time 18.65 seconds
Started Apr 18 12:44:35 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 216100 kb
Host smart-aa19fc9b-9b28-4645-af05-a0408b99a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489503916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.489503916
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3204527503
Short name T382
Test name
Test status
Simulation time 45118860 ps
CPU time 1.98 seconds
Started Apr 18 12:44:42 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 216280 kb
Host smart-1f8ed014-605e-46b1-8c14-b0f12f0114eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204527503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3204527503
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.910216296
Short name T687
Test name
Test status
Simulation time 92931268 ps
CPU time 0.93 seconds
Started Apr 18 12:44:38 PM PDT 24
Finished Apr 18 12:44:40 PM PDT 24
Peak memory 206704 kb
Host smart-f9449782-2eef-41b5-93c0-f9f9c721b145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910216296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.910216296
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1053278166
Short name T315
Test name
Test status
Simulation time 127198698 ps
CPU time 3.22 seconds
Started Apr 18 12:44:34 PM PDT 24
Finished Apr 18 12:44:38 PM PDT 24
Peak memory 222788 kb
Host smart-dccddb27-0394-4420-af92-066c7feaeccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053278166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1053278166
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2404936308
Short name T497
Test name
Test status
Simulation time 12718201 ps
CPU time 0.72 seconds
Started Apr 18 12:44:31 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 205720 kb
Host smart-8176bb81-295b-4279-b0c7-94b1f67dbe11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404936308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2404936308
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3853412333
Short name T587
Test name
Test status
Simulation time 33188593 ps
CPU time 0.73 seconds
Started Apr 18 12:44:38 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 205472 kb
Host smart-a85faebe-8727-4aee-befc-ab3ba8667411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853412333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3853412333
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.358297168
Short name T700
Test name
Test status
Simulation time 4885528508 ps
CPU time 67.3 seconds
Started Apr 18 12:44:46 PM PDT 24
Finished Apr 18 12:45:55 PM PDT 24
Peak memory 248916 kb
Host smart-84061bb9-8e4c-440c-a975-8a160fc7b1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358297168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.358297168
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1589841181
Short name T589
Test name
Test status
Simulation time 2039925637 ps
CPU time 26.23 seconds
Started Apr 18 12:44:45 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 220256 kb
Host smart-07ac6abb-7d50-4b1c-a32a-3034215c541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589841181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1589841181
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.425836444
Short name T255
Test name
Test status
Simulation time 19350325129 ps
CPU time 12.42 seconds
Started Apr 18 12:44:50 PM PDT 24
Finished Apr 18 12:45:03 PM PDT 24
Peak memory 219740 kb
Host smart-3326634c-1ebe-43cf-b676-f13db46d01c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425836444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.425836444
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1692752374
Short name T635
Test name
Test status
Simulation time 1676995292 ps
CPU time 9.94 seconds
Started Apr 18 12:44:34 PM PDT 24
Finished Apr 18 12:44:46 PM PDT 24
Peak memory 222868 kb
Host smart-cc68cd1d-eae6-4918-a2e1-a6a8c0963ba3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692752374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1692752374
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.697806476
Short name T368
Test name
Test status
Simulation time 8380233935 ps
CPU time 46.93 seconds
Started Apr 18 12:44:44 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 216136 kb
Host smart-3ac50ff5-f3dd-4f3c-a813-3f21bce42d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697806476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.697806476
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2337302467
Short name T402
Test name
Test status
Simulation time 10030822371 ps
CPU time 16.07 seconds
Started Apr 18 12:44:35 PM PDT 24
Finished Apr 18 12:44:53 PM PDT 24
Peak memory 216128 kb
Host smart-d7300604-86c2-47fe-9bdc-2d8da5e765dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337302467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2337302467
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2180990809
Short name T698
Test name
Test status
Simulation time 54068735 ps
CPU time 1.13 seconds
Started Apr 18 12:44:35 PM PDT 24
Finished Apr 18 12:44:38 PM PDT 24
Peak memory 207552 kb
Host smart-19b0fdc2-891a-4a42-9fed-3c40691df721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180990809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2180990809
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.998791305
Short name T673
Test name
Test status
Simulation time 90373204 ps
CPU time 0.92 seconds
Started Apr 18 12:44:34 PM PDT 24
Finished Apr 18 12:44:35 PM PDT 24
Peak memory 206672 kb
Host smart-bfbbd707-dd95-478c-9b83-39d3090707ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998791305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.998791305
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.472040128
Short name T194
Test name
Test status
Simulation time 1151752363 ps
CPU time 9.28 seconds
Started Apr 18 12:44:36 PM PDT 24
Finished Apr 18 12:44:47 PM PDT 24
Peak memory 223092 kb
Host smart-0dc51c5f-42b8-4852-a6c8-e2c38a85d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472040128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.472040128
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.792955059
Short name T437
Test name
Test status
Simulation time 17605989 ps
CPU time 0.72 seconds
Started Apr 18 12:44:48 PM PDT 24
Finished Apr 18 12:44:50 PM PDT 24
Peak memory 205376 kb
Host smart-3d887ded-e8e5-470c-8642-b7269f414964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792955059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.792955059
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2412751531
Short name T394
Test name
Test status
Simulation time 17043109 ps
CPU time 0.74 seconds
Started Apr 18 12:44:37 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 205348 kb
Host smart-2359869f-beca-4292-963c-710a5dc06c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412751531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2412751531
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1806302303
Short name T294
Test name
Test status
Simulation time 968706896 ps
CPU time 24.18 seconds
Started Apr 18 12:44:50 PM PDT 24
Finished Apr 18 12:45:15 PM PDT 24
Peak memory 236172 kb
Host smart-9a270a26-cf16-4e60-ab1e-969c92f8bed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806302303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1806302303
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.418250040
Short name T156
Test name
Test status
Simulation time 491001881 ps
CPU time 4.84 seconds
Started Apr 18 12:44:39 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 223660 kb
Host smart-c661d178-5761-47cd-909f-ad56a0c0f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418250040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.418250040
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3915574467
Short name T537
Test name
Test status
Simulation time 4326490075 ps
CPU time 14.05 seconds
Started Apr 18 12:44:37 PM PDT 24
Finished Apr 18 12:44:52 PM PDT 24
Peak memory 219780 kb
Host smart-9b06ba43-a56e-4199-b05b-f077affedcfb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3915574467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3915574467
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.595788589
Short name T548
Test name
Test status
Simulation time 44931973 ps
CPU time 1.01 seconds
Started Apr 18 12:44:40 PM PDT 24
Finished Apr 18 12:44:41 PM PDT 24
Peak memory 207036 kb
Host smart-36dbb435-475a-44c8-b059-f4ede8666b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595788589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.595788589
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2427808230
Short name T667
Test name
Test status
Simulation time 1056045530 ps
CPU time 6.7 seconds
Started Apr 18 12:44:32 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 216012 kb
Host smart-dc8a6ed3-2efe-4557-a173-dfef37da8e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427808230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2427808230
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1150287797
Short name T527
Test name
Test status
Simulation time 1440992683 ps
CPU time 3.97 seconds
Started Apr 18 12:44:36 PM PDT 24
Finished Apr 18 12:44:41 PM PDT 24
Peak memory 216196 kb
Host smart-8be872f1-cc8e-4ede-ad20-bc6ff388fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150287797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1150287797
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1806343295
Short name T629
Test name
Test status
Simulation time 34236595 ps
CPU time 0.86 seconds
Started Apr 18 12:44:39 PM PDT 24
Finished Apr 18 12:44:41 PM PDT 24
Peak memory 206704 kb
Host smart-e11fb2d9-3e92-44eb-9f05-b7d4ef266c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806343295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1806343295
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2583479528
Short name T532
Test name
Test status
Simulation time 11229357 ps
CPU time 0.68 seconds
Started Apr 18 12:44:49 PM PDT 24
Finished Apr 18 12:44:51 PM PDT 24
Peak memory 204692 kb
Host smart-34e939a1-474d-4faa-aa03-02887d0cf5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583479528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2583479528
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.786588411
Short name T452
Test name
Test status
Simulation time 18152471 ps
CPU time 0.77 seconds
Started Apr 18 12:44:50 PM PDT 24
Finished Apr 18 12:44:52 PM PDT 24
Peak memory 205464 kb
Host smart-a96cfb20-4d9f-4d7d-861a-c3f9cff6654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786588411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.786588411
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2146044355
Short name T502
Test name
Test status
Simulation time 3657610786 ps
CPU time 56.8 seconds
Started Apr 18 12:44:41 PM PDT 24
Finished Apr 18 12:45:40 PM PDT 24
Peak memory 253680 kb
Host smart-bfb8eace-0962-4702-9f89-a4531f15093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146044355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2146044355
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2743729359
Short name T111
Test name
Test status
Simulation time 19206802403 ps
CPU time 52.93 seconds
Started Apr 18 12:44:36 PM PDT 24
Finished Apr 18 12:45:31 PM PDT 24
Peak memory 237324 kb
Host smart-e7227b43-4564-404e-811d-c1d9738330ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743729359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2743729359
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1769660656
Short name T170
Test name
Test status
Simulation time 1230448388 ps
CPU time 5.92 seconds
Started Apr 18 12:44:38 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 220716 kb
Host smart-ecc2dacc-fce6-4e2d-b031-7afbf90ee1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769660656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1769660656
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.734809330
Short name T150
Test name
Test status
Simulation time 3583115042 ps
CPU time 8.94 seconds
Started Apr 18 12:44:39 PM PDT 24
Finished Apr 18 12:44:49 PM PDT 24
Peak memory 221604 kb
Host smart-0e28ea24-3c54-4e76-b412-6d2c7725ed5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=734809330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.734809330
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2034089125
Short name T341
Test name
Test status
Simulation time 46747888 ps
CPU time 1.06 seconds
Started Apr 18 12:44:43 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 207000 kb
Host smart-8e02aa43-70bb-4222-a6c6-ec226c21d999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034089125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2034089125
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3227491078
Short name T531
Test name
Test status
Simulation time 8869363295 ps
CPU time 30.83 seconds
Started Apr 18 12:44:39 PM PDT 24
Finished Apr 18 12:45:11 PM PDT 24
Peak memory 217612 kb
Host smart-773445d9-19e2-4576-ba8a-7e004a023ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227491078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3227491078
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2002155376
Short name T50
Test name
Test status
Simulation time 3438124052 ps
CPU time 5.16 seconds
Started Apr 18 12:44:46 PM PDT 24
Finished Apr 18 12:44:52 PM PDT 24
Peak memory 216268 kb
Host smart-e90c58e5-db88-4c0a-8904-85dfe8598522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002155376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2002155376
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3885185398
Short name T444
Test name
Test status
Simulation time 89831648 ps
CPU time 3.17 seconds
Started Apr 18 12:44:38 PM PDT 24
Finished Apr 18 12:44:43 PM PDT 24
Peak memory 216228 kb
Host smart-d3b275e3-331c-4087-bf40-f7cc3a33e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885185398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3885185398
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2734702147
Short name T616
Test name
Test status
Simulation time 54178459 ps
CPU time 0.88 seconds
Started Apr 18 12:44:52 PM PDT 24
Finished Apr 18 12:44:54 PM PDT 24
Peak memory 206692 kb
Host smart-b08fba4b-b03f-48ed-b52e-237a8a81271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734702147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2734702147
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.467786544
Short name T226
Test name
Test status
Simulation time 144134640 ps
CPU time 2.54 seconds
Started Apr 18 12:44:41 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 218816 kb
Host smart-57f4a6ca-ede6-493e-9028-0aead998a8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467786544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.467786544
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1232691448
Short name T15
Test name
Test status
Simulation time 22466796 ps
CPU time 0.72 seconds
Started Apr 18 12:44:57 PM PDT 24
Finished Apr 18 12:44:58 PM PDT 24
Peak memory 205696 kb
Host smart-b29ce5bb-8072-41f1-8e82-54e8cd9fda08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232691448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1232691448
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.751995351
Short name T408
Test name
Test status
Simulation time 20821699 ps
CPU time 0.86 seconds
Started Apr 18 12:44:55 PM PDT 24
Finished Apr 18 12:44:58 PM PDT 24
Peak memory 206344 kb
Host smart-e17bce68-44e0-4646-8a7c-99dba50f29c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751995351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.751995351
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4188607145
Short name T278
Test name
Test status
Simulation time 13317533200 ps
CPU time 51.56 seconds
Started Apr 18 12:44:55 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 234572 kb
Host smart-1db46740-b4d6-4644-afc0-15746dd96529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188607145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4188607145
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.882383415
Short name T330
Test name
Test status
Simulation time 8175098519 ps
CPU time 17.15 seconds
Started Apr 18 12:44:49 PM PDT 24
Finished Apr 18 12:45:07 PM PDT 24
Peak memory 232176 kb
Host smart-e49953cb-d139-4d14-8582-9f5e0b58823b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882383415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.882383415
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1093008302
Short name T242
Test name
Test status
Simulation time 2039275475 ps
CPU time 29.03 seconds
Started Apr 18 12:44:47 PM PDT 24
Finished Apr 18 12:45:18 PM PDT 24
Peak memory 218680 kb
Host smart-62e840bb-34ef-4081-ba32-e0300e3470fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093008302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1093008302
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3740220694
Short name T499
Test name
Test status
Simulation time 703769833 ps
CPU time 5.68 seconds
Started Apr 18 12:44:53 PM PDT 24
Finished Apr 18 12:45:00 PM PDT 24
Peak memory 219052 kb
Host smart-5cb7adcc-74bb-4637-bc73-c271d338d627
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3740220694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3740220694
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.96440332
Short name T363
Test name
Test status
Simulation time 7590158276 ps
CPU time 42.51 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 216224 kb
Host smart-ba97565e-d29b-41ea-8aff-4358bb204913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96440332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.96440332
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1003906327
Short name T469
Test name
Test status
Simulation time 26541966021 ps
CPU time 7.85 seconds
Started Apr 18 12:44:41 PM PDT 24
Finished Apr 18 12:44:50 PM PDT 24
Peak memory 215784 kb
Host smart-64919c14-44b0-40c6-a540-6d2c8b8f8667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003906327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1003906327
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.4248138970
Short name T448
Test name
Test status
Simulation time 28538098 ps
CPU time 0.78 seconds
Started Apr 18 12:44:43 PM PDT 24
Finished Apr 18 12:44:45 PM PDT 24
Peak memory 205712 kb
Host smart-6a219b06-11ad-4de8-9799-09bf0fd196fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248138970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.4248138970
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.374437885
Short name T505
Test name
Test status
Simulation time 267170316 ps
CPU time 0.87 seconds
Started Apr 18 12:44:51 PM PDT 24
Finished Apr 18 12:44:53 PM PDT 24
Peak memory 206700 kb
Host smart-591562ca-16d0-47be-a638-5dbc9723d69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374437885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.374437885
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.104190109
Short name T488
Test name
Test status
Simulation time 40973550 ps
CPU time 0.72 seconds
Started Apr 18 12:44:55 PM PDT 24
Finished Apr 18 12:44:58 PM PDT 24
Peak memory 205600 kb
Host smart-d73e9f41-1e0c-4bbf-9061-9a0ae02719af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104190109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.104190109
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3468000642
Short name T80
Test name
Test status
Simulation time 883516784 ps
CPU time 5.57 seconds
Started Apr 18 12:44:50 PM PDT 24
Finished Apr 18 12:44:57 PM PDT 24
Peak memory 224092 kb
Host smart-6f224f3b-983d-49fa-a4fb-82f8eeec3594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468000642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3468000642
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2396205894
Short name T424
Test name
Test status
Simulation time 19847546 ps
CPU time 0.72 seconds
Started Apr 18 12:44:47 PM PDT 24
Finished Apr 18 12:44:49 PM PDT 24
Peak memory 205448 kb
Host smart-81c94f37-dea8-4922-855e-f2f7347df38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396205894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2396205894
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.672065015
Short name T680
Test name
Test status
Simulation time 477427154 ps
CPU time 4 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:44:59 PM PDT 24
Peak memory 220944 kb
Host smart-aa0b6a49-8d60-4bfe-b96e-0d86c6cfd06b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=672065015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.672065015
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3131846301
Short name T565
Test name
Test status
Simulation time 11993750291 ps
CPU time 30.39 seconds
Started Apr 18 12:44:56 PM PDT 24
Finished Apr 18 12:45:28 PM PDT 24
Peak memory 216192 kb
Host smart-d0697d2e-b78c-4773-9436-30625b82e637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131846301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3131846301
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1004103474
Short name T608
Test name
Test status
Simulation time 1443547347 ps
CPU time 5.81 seconds
Started Apr 18 12:44:49 PM PDT 24
Finished Apr 18 12:44:56 PM PDT 24
Peak memory 216144 kb
Host smart-62993416-7ae1-4d6b-8837-ca7fef665ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004103474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1004103474
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3526037295
Short name T451
Test name
Test status
Simulation time 131501387 ps
CPU time 0.76 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:44:56 PM PDT 24
Peak memory 205536 kb
Host smart-3451c4f7-7178-4d1e-a4cf-1460e738129e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526037295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3526037295
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.660274128
Short name T536
Test name
Test status
Simulation time 65279746 ps
CPU time 0.89 seconds
Started Apr 18 12:44:50 PM PDT 24
Finished Apr 18 12:44:52 PM PDT 24
Peak memory 205636 kb
Host smart-ce129440-fc91-4587-a3fa-887da731ad13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660274128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.660274128
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4033147640
Short name T485
Test name
Test status
Simulation time 13601502 ps
CPU time 0.7 seconds
Started Apr 18 12:44:59 PM PDT 24
Finished Apr 18 12:45:00 PM PDT 24
Peak memory 204688 kb
Host smart-72af4ce9-27e6-4378-9394-3c69052f4e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033147640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4033147640
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3855383470
Short name T416
Test name
Test status
Simulation time 164122733 ps
CPU time 0.75 seconds
Started Apr 18 12:44:53 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 206476 kb
Host smart-4eab5509-adf1-457f-b7b6-8f24d6e2e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855383470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3855383470
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.770673332
Short name T282
Test name
Test status
Simulation time 2509234359 ps
CPU time 25.39 seconds
Started Apr 18 12:44:53 PM PDT 24
Finished Apr 18 12:45:19 PM PDT 24
Peak memory 232612 kb
Host smart-3e77f848-c3e2-40de-a10e-1dd0b61d5d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770673332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.770673332
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3887366087
Short name T241
Test name
Test status
Simulation time 1106684324 ps
CPU time 16.94 seconds
Started Apr 18 12:44:55 PM PDT 24
Finished Apr 18 12:45:14 PM PDT 24
Peak memory 218276 kb
Host smart-3f89731b-de3f-4cc7-b2f7-b9ede164177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887366087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3887366087
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1780635039
Short name T318
Test name
Test status
Simulation time 8445400585 ps
CPU time 8.05 seconds
Started Apr 18 12:44:53 PM PDT 24
Finished Apr 18 12:45:03 PM PDT 24
Peak memory 218384 kb
Host smart-83ae467f-6165-415d-b4dc-4796a506fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780635039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1780635039
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3845962845
Short name T573
Test name
Test status
Simulation time 14485197634 ps
CPU time 18.33 seconds
Started Apr 18 12:44:53 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 219696 kb
Host smart-dec96ba2-8dc9-4af2-b91b-769c815bfb4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3845962845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3845962845
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3274289881
Short name T374
Test name
Test status
Simulation time 9471074373 ps
CPU time 56.14 seconds
Started Apr 18 12:44:49 PM PDT 24
Finished Apr 18 12:45:47 PM PDT 24
Peak memory 216428 kb
Host smart-89b384c9-8a8c-460a-86f6-044ac71a5d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274289881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3274289881
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3389408006
Short name T672
Test name
Test status
Simulation time 71333842747 ps
CPU time 15.47 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:45:10 PM PDT 24
Peak memory 217312 kb
Host smart-a3646d5e-3b09-4eb0-8bc1-df3ca0218c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389408006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3389408006
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3932199935
Short name T54
Test name
Test status
Simulation time 246007085 ps
CPU time 3.35 seconds
Started Apr 18 12:44:57 PM PDT 24
Finished Apr 18 12:45:01 PM PDT 24
Peak memory 216124 kb
Host smart-8cca612e-1b9e-456c-9f20-39ef0c68ad7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932199935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3932199935
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3544664850
Short name T663
Test name
Test status
Simulation time 106695211 ps
CPU time 0.92 seconds
Started Apr 18 12:44:54 PM PDT 24
Finished Apr 18 12:44:57 PM PDT 24
Peak memory 206564 kb
Host smart-ee84e20a-f170-4a4c-845d-d79eca8e67ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544664850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3544664850
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2704624439
Short name T584
Test name
Test status
Simulation time 22974879 ps
CPU time 0.72 seconds
Started Apr 18 12:44:05 PM PDT 24
Finished Apr 18 12:44:07 PM PDT 24
Peak memory 205584 kb
Host smart-4ef7e99f-71bf-4a39-9eb2-0dc049bedfa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704624439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
704624439
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1127103959
Short name T392
Test name
Test status
Simulation time 15957427 ps
CPU time 0.76 seconds
Started Apr 18 12:44:03 PM PDT 24
Finished Apr 18 12:44:04 PM PDT 24
Peak memory 205448 kb
Host smart-c0b16984-407a-4539-87e7-907112168ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127103959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1127103959
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1626143688
Short name T288
Test name
Test status
Simulation time 440394773 ps
CPU time 10.68 seconds
Started Apr 18 12:44:17 PM PDT 24
Finished Apr 18 12:44:29 PM PDT 24
Peak memory 224276 kb
Host smart-866ee68b-0059-4674-9e86-3bb9646c8e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626143688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1626143688
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2654452701
Short name T71
Test name
Test status
Simulation time 263541447 ps
CPU time 2.66 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:10 PM PDT 24
Peak memory 219368 kb
Host smart-0247d010-f357-4f18-abe4-4640e0cda728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654452701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2654452701
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.154204089
Short name T513
Test name
Test status
Simulation time 6243431384 ps
CPU time 20.11 seconds
Started Apr 18 12:44:12 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 220080 kb
Host smart-3e7b46c8-0068-497a-aac7-124316763538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154204089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.154204089
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1468933925
Short name T265
Test name
Test status
Simulation time 11060169791 ps
CPU time 13.95 seconds
Started Apr 18 12:44:08 PM PDT 24
Finished Apr 18 12:44:22 PM PDT 24
Peak memory 221748 kb
Host smart-f55ee5f3-227e-4bdb-92b6-af241437d6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468933925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1468933925
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2265523285
Short name T193
Test name
Test status
Simulation time 681611556 ps
CPU time 3.32 seconds
Started Apr 18 12:44:05 PM PDT 24
Finished Apr 18 12:44:10 PM PDT 24
Peak memory 220384 kb
Host smart-5bd09579-436b-480c-8754-1181cfb39501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265523285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2265523285
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1936350309
Short name T493
Test name
Test status
Simulation time 4548542621 ps
CPU time 12.56 seconds
Started Apr 18 12:44:03 PM PDT 24
Finished Apr 18 12:44:16 PM PDT 24
Peak memory 221356 kb
Host smart-97b27373-f41c-451b-85aa-378cfb74611d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1936350309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1936350309
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2779588819
Short name T16
Test name
Test status
Simulation time 514730773 ps
CPU time 1.12 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 234840 kb
Host smart-f519fc52-baae-4a3b-817b-59a980621f28
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779588819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2779588819
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1678719011
Short name T441
Test name
Test status
Simulation time 7871714849 ps
CPU time 24.94 seconds
Started Apr 18 12:44:05 PM PDT 24
Finished Apr 18 12:44:31 PM PDT 24
Peak memory 216116 kb
Host smart-8d72d088-7b09-41e2-a37c-419c67d4c230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678719011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1678719011
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.682051896
Short name T460
Test name
Test status
Simulation time 104267975 ps
CPU time 1.66 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:09 PM PDT 24
Peak memory 216068 kb
Host smart-2b6d4afc-0777-4861-b599-bb4ef0630c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682051896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.682051896
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2161766156
Short name T619
Test name
Test status
Simulation time 586516237 ps
CPU time 1.01 seconds
Started Apr 18 12:44:07 PM PDT 24
Finished Apr 18 12:44:09 PM PDT 24
Peak memory 206780 kb
Host smart-856c076b-f18c-4047-b999-cfb763386222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161766156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2161766156
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3290543908
Short name T591
Test name
Test status
Simulation time 12631271 ps
CPU time 0.73 seconds
Started Apr 18 12:44:59 PM PDT 24
Finished Apr 18 12:45:00 PM PDT 24
Peak memory 205376 kb
Host smart-c3711de2-0eff-4af9-9173-1cdad638abab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290543908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3290543908
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3043122564
Short name T677
Test name
Test status
Simulation time 170885934 ps
CPU time 2.45 seconds
Started Apr 18 12:44:52 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 218484 kb
Host smart-91fa1f57-1568-4811-b442-a8e5f1e0f6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043122564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3043122564
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3170001711
Short name T390
Test name
Test status
Simulation time 91822575 ps
CPU time 0.7 seconds
Started Apr 18 12:45:04 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 205424 kb
Host smart-ca586531-27c4-47c9-9dcc-67d208170eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170001711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3170001711
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.55830444
Short name T650
Test name
Test status
Simulation time 639923448 ps
CPU time 4.46 seconds
Started Apr 18 12:45:05 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 222332 kb
Host smart-81a91f57-3ce6-4f06-b996-acf2f141d0c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=55830444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direc
t.55830444
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.853096968
Short name T675
Test name
Test status
Simulation time 502473848 ps
CPU time 2.28 seconds
Started Apr 18 12:45:08 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 216284 kb
Host smart-fab4d4ea-20d8-4666-bc50-0eee8ea90caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853096968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.853096968
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1766408098
Short name T494
Test name
Test status
Simulation time 1107173326 ps
CPU time 2.17 seconds
Started Apr 18 12:45:03 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 215860 kb
Host smart-16588175-0fda-4139-96d3-1099e8ef2aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766408098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1766408098
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.343594775
Short name T595
Test name
Test status
Simulation time 78780396 ps
CPU time 3.03 seconds
Started Apr 18 12:45:01 PM PDT 24
Finished Apr 18 12:45:05 PM PDT 24
Peak memory 216180 kb
Host smart-41ae3d40-fcb4-4cd5-bae3-f453fed3af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343594775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.343594775
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3766285034
Short name T446
Test name
Test status
Simulation time 155081515 ps
CPU time 0.99 seconds
Started Apr 18 12:44:57 PM PDT 24
Finished Apr 18 12:44:59 PM PDT 24
Peak memory 206680 kb
Host smart-1da0100e-6723-405d-8fbb-1c954d6c1ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766285034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3766285034
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.758006066
Short name T30
Test name
Test status
Simulation time 50327141 ps
CPU time 0.77 seconds
Started Apr 18 12:45:14 PM PDT 24
Finished Apr 18 12:45:15 PM PDT 24
Peak memory 204784 kb
Host smart-d8acd369-3552-48a2-8db9-7964dba47394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758006066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.758006066
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1845451632
Short name T430
Test name
Test status
Simulation time 27591711 ps
CPU time 0.79 seconds
Started Apr 18 12:44:55 PM PDT 24
Finished Apr 18 12:44:58 PM PDT 24
Peak memory 206448 kb
Host smart-b6a4a26a-dbb3-49ad-8919-80e449365eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845451632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1845451632
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2015885914
Short name T221
Test name
Test status
Simulation time 5139418710 ps
CPU time 11.09 seconds
Started Apr 18 12:44:58 PM PDT 24
Finished Apr 18 12:45:10 PM PDT 24
Peak memory 232596 kb
Host smart-28a07f26-86ee-4210-9b87-fcaf65f524cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015885914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2015885914
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.472716697
Short name T152
Test name
Test status
Simulation time 206363923 ps
CPU time 4.08 seconds
Started Apr 18 12:45:01 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 219088 kb
Host smart-5b19d11e-2af0-4956-9d08-835b9267cc6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=472716697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.472716697
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3112627152
Short name T610
Test name
Test status
Simulation time 4582672297 ps
CPU time 16.11 seconds
Started Apr 18 12:45:15 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 218880 kb
Host smart-35024b2f-d9ef-459d-a2cc-f0da1526b4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112627152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3112627152
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3315198902
Short name T669
Test name
Test status
Simulation time 22366218300 ps
CPU time 8.17 seconds
Started Apr 18 12:45:02 PM PDT 24
Finished Apr 18 12:45:11 PM PDT 24
Peak memory 216176 kb
Host smart-e746461d-a3f4-4c8a-8f0f-52178cc8da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315198902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3315198902
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4034236406
Short name T377
Test name
Test status
Simulation time 27008778 ps
CPU time 1.28 seconds
Started Apr 18 12:45:03 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 216052 kb
Host smart-dd9119a5-e283-43d3-8354-21ba5043ae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034236406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4034236406
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2646232035
Short name T561
Test name
Test status
Simulation time 21345764 ps
CPU time 0.77 seconds
Started Apr 18 12:45:05 PM PDT 24
Finished Apr 18 12:45:08 PM PDT 24
Peak memory 205680 kb
Host smart-82318957-9c65-4044-a196-bbd705e6cc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646232035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2646232035
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.39907498
Short name T690
Test name
Test status
Simulation time 5115063405 ps
CPU time 16.43 seconds
Started Apr 18 12:45:05 PM PDT 24
Finished Apr 18 12:45:24 PM PDT 24
Peak memory 218776 kb
Host smart-69ba8cd9-6e08-4e18-baf4-8858bdbf38f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39907498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.39907498
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.21280232
Short name T481
Test name
Test status
Simulation time 14444523 ps
CPU time 0.74 seconds
Started Apr 18 12:45:09 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 205332 kb
Host smart-c19c8cb2-cad0-485e-bd29-3b6b1533a7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21280232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.21280232
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.800597791
Short name T185
Test name
Test status
Simulation time 1863055373 ps
CPU time 4.28 seconds
Started Apr 18 12:45:06 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 218256 kb
Host smart-4a09aae9-7cba-470b-beaa-835653009227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800597791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.800597791
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2340443052
Short name T557
Test name
Test status
Simulation time 109920881 ps
CPU time 0.78 seconds
Started Apr 18 12:45:04 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 206828 kb
Host smart-792e39b5-425e-41bd-808d-aec49dfc729f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340443052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2340443052
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1962789268
Short name T252
Test name
Test status
Simulation time 49743409702 ps
CPU time 23.52 seconds
Started Apr 18 12:45:09 PM PDT 24
Finished Apr 18 12:45:34 PM PDT 24
Peak memory 239256 kb
Host smart-881a29dd-11d5-43f3-bb8b-330eb097693e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962789268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1962789268
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3250106033
Short name T432
Test name
Test status
Simulation time 1118971455 ps
CPU time 6.37 seconds
Started Apr 18 12:45:15 PM PDT 24
Finished Apr 18 12:45:23 PM PDT 24
Peak memory 222740 kb
Host smart-4e1e41fd-eba6-4cba-b67c-3a137fb0454a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3250106033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3250106033
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3942159482
Short name T380
Test name
Test status
Simulation time 1506609548 ps
CPU time 7.86 seconds
Started Apr 18 12:45:06 PM PDT 24
Finished Apr 18 12:45:16 PM PDT 24
Peak memory 216044 kb
Host smart-d3a6f931-88b8-4fb5-81f5-2cbfd17a6421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942159482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3942159482
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2650323068
Short name T581
Test name
Test status
Simulation time 2075505847 ps
CPU time 3.46 seconds
Started Apr 18 12:45:04 PM PDT 24
Finished Apr 18 12:45:09 PM PDT 24
Peak memory 216148 kb
Host smart-9b5a8515-a6cb-4a86-8b88-961140ea28fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650323068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2650323068
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3355570136
Short name T476
Test name
Test status
Simulation time 318608556 ps
CPU time 1.96 seconds
Started Apr 18 12:45:04 PM PDT 24
Finished Apr 18 12:45:08 PM PDT 24
Peak memory 216124 kb
Host smart-8cb7ab8d-b548-47a7-b031-71da053ba2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355570136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3355570136
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3645089721
Short name T631
Test name
Test status
Simulation time 101907145 ps
CPU time 0.92 seconds
Started Apr 18 12:45:02 PM PDT 24
Finished Apr 18 12:45:04 PM PDT 24
Peak memory 206244 kb
Host smart-5e3e3dde-304d-428e-b0e2-dc01b40b4304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645089721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3645089721
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1617297178
Short name T415
Test name
Test status
Simulation time 16312445 ps
CPU time 0.75 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 205268 kb
Host smart-3b2fd9a1-fec9-4f20-ba1f-fe74770c3754
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617297178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1617297178
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2964163834
Short name T553
Test name
Test status
Simulation time 181360031 ps
CPU time 4.27 seconds
Started Apr 18 12:45:01 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 216580 kb
Host smart-6817a8bf-fa14-4fdd-9f8f-e87f457c7535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964163834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2964163834
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2520081109
Short name T525
Test name
Test status
Simulation time 79551784 ps
CPU time 0.77 seconds
Started Apr 18 12:45:04 PM PDT 24
Finished Apr 18 12:45:07 PM PDT 24
Peak memory 206844 kb
Host smart-edc3939f-2b61-4159-bc84-6f1b2b961e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520081109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2520081109
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3972476114
Short name T165
Test name
Test status
Simulation time 452682915 ps
CPU time 3.67 seconds
Started Apr 18 12:45:07 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 232384 kb
Host smart-eabeddbb-4152-4976-af31-6feb4d1dd5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972476114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3972476114
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3084860273
Short name T261
Test name
Test status
Simulation time 376999976 ps
CPU time 3.39 seconds
Started Apr 18 12:45:04 PM PDT 24
Finished Apr 18 12:45:09 PM PDT 24
Peak memory 222024 kb
Host smart-30dc4562-f460-454b-91d0-c5a275af0841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084860273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3084860273
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2146964361
Short name T511
Test name
Test status
Simulation time 549879731 ps
CPU time 5.51 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:45:22 PM PDT 24
Peak memory 219888 kb
Host smart-39aeb524-5f3e-4e03-af19-a6905f78b249
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2146964361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2146964361
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4056817957
Short name T520
Test name
Test status
Simulation time 801701411 ps
CPU time 2.44 seconds
Started Apr 18 12:45:08 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 207780 kb
Host smart-666b4de4-bc1e-44a8-8716-42fec79ff5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056817957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4056817957
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2157168629
Short name T491
Test name
Test status
Simulation time 240192492 ps
CPU time 1.68 seconds
Started Apr 18 12:45:01 PM PDT 24
Finished Apr 18 12:45:04 PM PDT 24
Peak memory 216188 kb
Host smart-338f3de3-b0e2-4396-a9af-ec1eccf95537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157168629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2157168629
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.76800902
Short name T519
Test name
Test status
Simulation time 59366268 ps
CPU time 0.75 seconds
Started Apr 18 12:45:07 PM PDT 24
Finished Apr 18 12:45:09 PM PDT 24
Peak memory 205704 kb
Host smart-a3cf7e45-9c80-4084-8a9f-9ce6a9c4549c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76800902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.76800902
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4193376255
Short name T563
Test name
Test status
Simulation time 12137592 ps
CPU time 0.71 seconds
Started Apr 18 12:45:12 PM PDT 24
Finished Apr 18 12:45:14 PM PDT 24
Peak memory 205620 kb
Host smart-52d7f23a-3113-4e3c-b9fe-75aef4a8323d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193376255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4193376255
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1472883176
Short name T682
Test name
Test status
Simulation time 48655529 ps
CPU time 0.78 seconds
Started Apr 18 12:45:15 PM PDT 24
Finished Apr 18 12:45:16 PM PDT 24
Peak memory 206368 kb
Host smart-75dc538f-b858-4464-8cab-e54d3f34ddd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472883176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1472883176
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2145433436
Short name T604
Test name
Test status
Simulation time 88960267 ps
CPU time 2.46 seconds
Started Apr 18 12:45:11 PM PDT 24
Finished Apr 18 12:45:14 PM PDT 24
Peak memory 218564 kb
Host smart-a2833ce3-9bd4-40a2-a408-6722868c381a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145433436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2145433436
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2552590312
Short name T447
Test name
Test status
Simulation time 2037307895 ps
CPU time 12.79 seconds
Started Apr 18 12:45:08 PM PDT 24
Finished Apr 18 12:45:22 PM PDT 24
Peak memory 222344 kb
Host smart-d8a587ec-1b54-4792-a36a-5377b1cac62f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2552590312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2552590312
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1190643014
Short name T98
Test name
Test status
Simulation time 5380467662 ps
CPU time 32.89 seconds
Started Apr 18 12:45:09 PM PDT 24
Finished Apr 18 12:45:44 PM PDT 24
Peak memory 216252 kb
Host smart-9ce8366b-4f8c-4c9f-8daa-0be5bf13079b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190643014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1190643014
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1515526010
Short name T467
Test name
Test status
Simulation time 2095210699 ps
CPU time 4.07 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:45:24 PM PDT 24
Peak memory 216112 kb
Host smart-d2acd369-5e04-4337-9984-8786c6550882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515526010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1515526010
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1396402165
Short name T627
Test name
Test status
Simulation time 543013780 ps
CPU time 5.44 seconds
Started Apr 18 12:45:05 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 216224 kb
Host smart-78534fe1-24e0-4b59-bed8-da61e11ad502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396402165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1396402165
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.403194355
Short name T639
Test name
Test status
Simulation time 114749660 ps
CPU time 0.79 seconds
Started Apr 18 12:45:11 PM PDT 24
Finished Apr 18 12:45:13 PM PDT 24
Peak memory 205540 kb
Host smart-04f7fb3e-9a18-42c5-b345-c2b5432cc0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403194355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.403194355
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.971237156
Short name T173
Test name
Test status
Simulation time 2639470035 ps
CPU time 10.77 seconds
Started Apr 18 12:45:12 PM PDT 24
Finished Apr 18 12:45:24 PM PDT 24
Peak memory 217376 kb
Host smart-b48dfe27-45d7-48a2-bb50-7ef2db6a8925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971237156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.971237156
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3272343665
Short name T552
Test name
Test status
Simulation time 40450996 ps
CPU time 0.69 seconds
Started Apr 18 12:45:04 PM PDT 24
Finished Apr 18 12:45:06 PM PDT 24
Peak memory 205596 kb
Host smart-0cee448c-2ced-42d5-b893-c53ef86298ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272343665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3272343665
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.307192464
Short name T480
Test name
Test status
Simulation time 72515733 ps
CPU time 0.82 seconds
Started Apr 18 12:45:31 PM PDT 24
Finished Apr 18 12:45:33 PM PDT 24
Peak memory 206380 kb
Host smart-82b7cffd-363a-48a9-a26f-5f129e4d1ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307192464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.307192464
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2235717607
Short name T668
Test name
Test status
Simulation time 1257627324 ps
CPU time 15.53 seconds
Started Apr 18 12:45:17 PM PDT 24
Finished Apr 18 12:45:34 PM PDT 24
Peak memory 218524 kb
Host smart-9e8137b9-04a4-4b4d-a548-3e8992892434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235717607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2235717607
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1861815554
Short name T307
Test name
Test status
Simulation time 28488616427 ps
CPU time 20.43 seconds
Started Apr 18 12:45:08 PM PDT 24
Finished Apr 18 12:45:30 PM PDT 24
Peak memory 219732 kb
Host smart-5c0faf8d-4662-42c2-9c50-17ba4cfacf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861815554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1861815554
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1087238184
Short name T146
Test name
Test status
Simulation time 74831081 ps
CPU time 3.7 seconds
Started Apr 18 12:45:11 PM PDT 24
Finished Apr 18 12:45:15 PM PDT 24
Peak memory 219000 kb
Host smart-84710239-e887-46b9-8892-623fa4984552
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1087238184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1087238184
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3249558932
Short name T358
Test name
Test status
Simulation time 7505344554 ps
CPU time 30.53 seconds
Started Apr 18 12:45:03 PM PDT 24
Finished Apr 18 12:45:35 PM PDT 24
Peak memory 216144 kb
Host smart-d4a21762-4396-411a-90c7-d79d1dce1664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249558932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3249558932
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.933809761
Short name T14
Test name
Test status
Simulation time 2500757822 ps
CPU time 6.72 seconds
Started Apr 18 12:45:11 PM PDT 24
Finished Apr 18 12:45:19 PM PDT 24
Peak memory 216156 kb
Host smart-06c26856-ed6f-47b6-a777-df3712d058e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933809761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.933809761
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3615095396
Short name T643
Test name
Test status
Simulation time 349355338 ps
CPU time 3.69 seconds
Started Apr 18 12:45:22 PM PDT 24
Finished Apr 18 12:45:27 PM PDT 24
Peak memory 216080 kb
Host smart-899f968b-645d-4230-8ddc-44317aa54ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615095396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3615095396
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3514627046
Short name T435
Test name
Test status
Simulation time 663578459 ps
CPU time 0.92 seconds
Started Apr 18 12:45:13 PM PDT 24
Finished Apr 18 12:45:15 PM PDT 24
Peak memory 206600 kb
Host smart-fdd92fea-d800-4078-a881-aee13ac9a6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514627046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3514627046
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.629673432
Short name T31
Test name
Test status
Simulation time 21046188 ps
CPU time 0.73 seconds
Started Apr 18 12:45:20 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 204804 kb
Host smart-54c277c7-6b48-4221-b8f0-703fe33f91c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629673432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.629673432
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2670681156
Short name T657
Test name
Test status
Simulation time 24658063 ps
CPU time 0.79 seconds
Started Apr 18 12:45:06 PM PDT 24
Finished Apr 18 12:45:09 PM PDT 24
Peak memory 206384 kb
Host smart-2ef18ab3-48a0-4222-b7fc-10f26accd167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670681156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2670681156
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.365359083
Short name T295
Test name
Test status
Simulation time 636561779 ps
CPU time 15.11 seconds
Started Apr 18 12:45:14 PM PDT 24
Finished Apr 18 12:45:30 PM PDT 24
Peak memory 233580 kb
Host smart-a02ea967-8468-4371-864e-0faee43889b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365359083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.365359083
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1422425101
Short name T248
Test name
Test status
Simulation time 20355733749 ps
CPU time 17.76 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 222912 kb
Host smart-307aa73d-50d4-4031-9420-c5993485c5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422425101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1422425101
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1752019572
Short name T73
Test name
Test status
Simulation time 23527263796 ps
CPU time 13.2 seconds
Started Apr 18 12:45:23 PM PDT 24
Finished Apr 18 12:45:37 PM PDT 24
Peak memory 220360 kb
Host smart-148935d3-c61f-43ff-9975-68cda40bb50e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1752019572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1752019572
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1991105369
Short name T540
Test name
Test status
Simulation time 304515329 ps
CPU time 1.19 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:45:18 PM PDT 24
Peak memory 206924 kb
Host smart-cf3498bf-da1f-474a-9461-cbbeffe5154f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991105369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1991105369
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2837573076
Short name T379
Test name
Test status
Simulation time 13825601094 ps
CPU time 77.91 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:46:38 PM PDT 24
Peak memory 216164 kb
Host smart-cfe570e9-b16f-4105-a1b5-16aefabf41cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837573076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2837573076
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.334425741
Short name T647
Test name
Test status
Simulation time 4157269758 ps
CPU time 3.43 seconds
Started Apr 18 12:45:07 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 216048 kb
Host smart-db6bcd91-503c-4d6a-8b7c-00a17f20addc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334425741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.334425741
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1464429368
Short name T701
Test name
Test status
Simulation time 121988278 ps
CPU time 1.19 seconds
Started Apr 18 12:45:09 PM PDT 24
Finished Apr 18 12:45:11 PM PDT 24
Peak memory 207784 kb
Host smart-407c3a5c-6951-4283-a9c3-568abb1d0c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464429368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1464429368
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4025243613
Short name T615
Test name
Test status
Simulation time 110744487 ps
CPU time 0.85 seconds
Started Apr 18 12:45:10 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 205580 kb
Host smart-fc4756f4-e16c-4636-8c95-d221eb69c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025243613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4025243613
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3268519592
Short name T535
Test name
Test status
Simulation time 12194486 ps
CPU time 0.78 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:45:18 PM PDT 24
Peak memory 205360 kb
Host smart-91fb78f9-90c8-4cfd-b8bf-27aa2805a635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268519592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3268519592
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2377464033
Short name T611
Test name
Test status
Simulation time 51158854 ps
CPU time 0.73 seconds
Started Apr 18 12:45:22 PM PDT 24
Finished Apr 18 12:45:24 PM PDT 24
Peak memory 205348 kb
Host smart-dbc0f7af-c9f6-44cd-b78b-730b318d4eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377464033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2377464033
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_intercept.558624540
Short name T225
Test name
Test status
Simulation time 10901929309 ps
CPU time 27.92 seconds
Started Apr 18 12:45:12 PM PDT 24
Finished Apr 18 12:45:41 PM PDT 24
Peak memory 232612 kb
Host smart-b27aa81b-595a-4867-9cc6-37dd17c00417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558624540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.558624540
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2734453694
Short name T116
Test name
Test status
Simulation time 29770293111 ps
CPU time 46.55 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 222876 kb
Host smart-2e5aed95-a320-4fe3-aaf9-26e1e2c41270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734453694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2734453694
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2137301264
Short name T492
Test name
Test status
Simulation time 1577298962 ps
CPU time 13.12 seconds
Started Apr 18 12:45:13 PM PDT 24
Finished Apr 18 12:45:27 PM PDT 24
Peak memory 219828 kb
Host smart-0402d187-e705-4efd-b2d4-97c50c7e747f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2137301264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2137301264
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1082188397
Short name T549
Test name
Test status
Simulation time 3216568815 ps
CPU time 8.46 seconds
Started Apr 18 12:45:27 PM PDT 24
Finished Apr 18 12:45:36 PM PDT 24
Peak memory 216244 kb
Host smart-117a1473-d55e-4410-886b-d39d9c12984b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082188397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1082188397
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3329968685
Short name T541
Test name
Test status
Simulation time 29943352824 ps
CPU time 30.04 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:50 PM PDT 24
Peak memory 216136 kb
Host smart-b9feaf07-1614-45f3-8dcd-973902f7c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329968685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3329968685
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3986870102
Short name T55
Test name
Test status
Simulation time 38143369 ps
CPU time 1.36 seconds
Started Apr 18 12:45:14 PM PDT 24
Finished Apr 18 12:45:16 PM PDT 24
Peak memory 216200 kb
Host smart-ab90d0c5-3e6b-4609-99db-fbc6f2fe4e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986870102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3986870102
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.269815253
Short name T104
Test name
Test status
Simulation time 261676077 ps
CPU time 0.94 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 205572 kb
Host smart-2d4cf2a3-b350-410b-94e5-0ac1e8581c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269815253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.269815253
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2081855101
Short name T253
Test name
Test status
Simulation time 5126064565 ps
CPU time 4.75 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:45:25 PM PDT 24
Peak memory 219620 kb
Host smart-1328077b-dba2-410a-9564-8fe9b9ef75d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081855101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2081855101
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2749815971
Short name T517
Test name
Test status
Simulation time 13493572 ps
CPU time 0.73 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 205192 kb
Host smart-5216b782-1fd1-46db-b989-df1b6759f6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749815971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2749815971
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.114660904
Short name T649
Test name
Test status
Simulation time 3511811562 ps
CPU time 13.59 seconds
Started Apr 18 12:45:23 PM PDT 24
Finished Apr 18 12:45:37 PM PDT 24
Peak memory 223156 kb
Host smart-00321fff-0612-4067-adbe-161924153aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114660904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.114660904
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2877702132
Short name T387
Test name
Test status
Simulation time 21134575 ps
CPU time 0.85 seconds
Started Apr 18 12:45:10 PM PDT 24
Finished Apr 18 12:45:12 PM PDT 24
Peak memory 206488 kb
Host smart-866e241b-be6a-4806-a0e3-fe214d233ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877702132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2877702132
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3705243596
Short name T633
Test name
Test status
Simulation time 64372098741 ps
CPU time 201.42 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:48:42 PM PDT 24
Peak memory 257096 kb
Host smart-562acf76-283c-4f3f-9195-7d714f396d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705243596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3705243596
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.398306078
Short name T158
Test name
Test status
Simulation time 3399779264 ps
CPU time 24.25 seconds
Started Apr 18 12:45:27 PM PDT 24
Finished Apr 18 12:45:53 PM PDT 24
Peak memory 224176 kb
Host smart-f5460b31-87ed-44b7-bcd9-e0602b728fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398306078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.398306078
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.129358693
Short name T324
Test name
Test status
Simulation time 674139656 ps
CPU time 4.14 seconds
Started Apr 18 12:45:27 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 222344 kb
Host smart-da2a99f6-848a-454f-8802-dfdc180a6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129358693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.129358693
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1252971832
Short name T218
Test name
Test status
Simulation time 1236042534 ps
CPU time 5.22 seconds
Started Apr 18 12:45:19 PM PDT 24
Finished Apr 18 12:45:25 PM PDT 24
Peak memory 218816 kb
Host smart-b2feb011-8007-449f-b429-6f11025233af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252971832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1252971832
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.797335421
Short name T462
Test name
Test status
Simulation time 905697740 ps
CPU time 10.05 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:45:41 PM PDT 24
Peak memory 222772 kb
Host smart-eca8c15c-3241-409c-8e4b-5c50cd7d4ef0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=797335421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.797335421
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1191386488
Short name T661
Test name
Test status
Simulation time 6009353016 ps
CPU time 31.77 seconds
Started Apr 18 12:45:23 PM PDT 24
Finished Apr 18 12:45:56 PM PDT 24
Peak memory 216120 kb
Host smart-08270bbd-9786-4d8d-b6ed-bc6d57a089d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191386488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1191386488
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.93204134
Short name T683
Test name
Test status
Simulation time 6141321895 ps
CPU time 4.97 seconds
Started Apr 18 12:45:17 PM PDT 24
Finished Apr 18 12:45:23 PM PDT 24
Peak memory 216216 kb
Host smart-db52e618-3e4e-4b53-a948-2aad352b308c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93204134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.93204134
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1896368451
Short name T521
Test name
Test status
Simulation time 15592251 ps
CPU time 0.95 seconds
Started Apr 18 12:45:15 PM PDT 24
Finished Apr 18 12:45:17 PM PDT 24
Peak memory 206600 kb
Host smart-84b3c66e-6c1f-4e24-9b28-533373f00a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896368451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1896368451
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3357579706
Short name T570
Test name
Test status
Simulation time 87136573 ps
CPU time 0.97 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:45:19 PM PDT 24
Peak memory 205608 kb
Host smart-98f87f76-5715-4fca-9a7e-a23bb1de2e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357579706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3357579706
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2029857776
Short name T509
Test name
Test status
Simulation time 43955913 ps
CPU time 0.73 seconds
Started Apr 18 12:45:20 PM PDT 24
Finished Apr 18 12:45:21 PM PDT 24
Peak memory 205364 kb
Host smart-840d7449-384d-487e-96b8-bea31e126efc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029857776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2029857776
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2720405083
Short name T29
Test name
Test status
Simulation time 376080151 ps
CPU time 2.21 seconds
Started Apr 18 12:45:28 PM PDT 24
Finished Apr 18 12:45:31 PM PDT 24
Peak memory 218224 kb
Host smart-652c4b2e-bf80-4c85-be7a-3654232354a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720405083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2720405083
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1854305978
Short name T644
Test name
Test status
Simulation time 49221860 ps
CPU time 0.73 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:31 PM PDT 24
Peak memory 205468 kb
Host smart-f7a64bd7-c8cf-4548-b5b4-d77c9269fd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854305978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1854305978
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2179043334
Short name T287
Test name
Test status
Simulation time 2146936518 ps
CPU time 26.39 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:46 PM PDT 24
Peak memory 249600 kb
Host smart-6750bffe-3df8-4008-a9a2-d827b9d90e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179043334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2179043334
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.299554547
Short name T332
Test name
Test status
Simulation time 966924112 ps
CPU time 6.35 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:26 PM PDT 24
Peak memory 224284 kb
Host smart-3ad5db32-cf9f-436a-af51-e5c8b98d6e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299554547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.299554547
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.243406352
Short name T257
Test name
Test status
Simulation time 1938133552 ps
CPU time 15.42 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:50 PM PDT 24
Peak memory 220208 kb
Host smart-b671cf3b-27e0-402b-b93a-23f1520b0448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243406352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.243406352
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1738193832
Short name T538
Test name
Test status
Simulation time 477115780 ps
CPU time 5.65 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:37 PM PDT 24
Peak memory 222812 kb
Host smart-1c062f04-a3ac-4145-854c-0c7e4be87f4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1738193832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1738193832
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3671595595
Short name T688
Test name
Test status
Simulation time 3541747838 ps
CPU time 42.53 seconds
Started Apr 18 12:45:17 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 216300 kb
Host smart-bfd3cc7c-c2f4-49d7-a56a-571ea5103aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671595595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3671595595
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2589937690
Short name T403
Test name
Test status
Simulation time 2611521344 ps
CPU time 5.63 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:25 PM PDT 24
Peak memory 216180 kb
Host smart-5c2da8c8-1691-49c5-8fa2-ec9f6ed5dedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589937690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2589937690
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2281898887
Short name T52
Test name
Test status
Simulation time 339243423 ps
CPU time 1.29 seconds
Started Apr 18 12:45:16 PM PDT 24
Finished Apr 18 12:45:19 PM PDT 24
Peak memory 216084 kb
Host smart-cef086d7-9453-46ab-a3f8-31894daa73a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281898887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2281898887
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1849282303
Short name T530
Test name
Test status
Simulation time 169816794 ps
CPU time 0.83 seconds
Started Apr 18 12:45:27 PM PDT 24
Finished Apr 18 12:45:29 PM PDT 24
Peak memory 205724 kb
Host smart-cb7f2186-43a5-4686-9ff6-31dce12b88ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849282303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1849282303
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1414507002
Short name T559
Test name
Test status
Simulation time 66414089 ps
CPU time 0.79 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:15 PM PDT 24
Peak memory 205224 kb
Host smart-a5a07674-3789-43ae-8c3a-c5756fc2a79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414507002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
414507002
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2922683056
Short name T414
Test name
Test status
Simulation time 57771370 ps
CPU time 0.8 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:07 PM PDT 24
Peak memory 206520 kb
Host smart-64966a7b-abbe-4069-8902-594eecee7309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922683056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2922683056
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4026872427
Short name T334
Test name
Test status
Simulation time 1023492293 ps
CPU time 21.64 seconds
Started Apr 18 12:44:08 PM PDT 24
Finished Apr 18 12:44:30 PM PDT 24
Peak memory 234328 kb
Host smart-55c992e0-2bd2-4941-8514-83ab15f6748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026872427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4026872427
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1703380834
Short name T250
Test name
Test status
Simulation time 165584647 ps
CPU time 2.67 seconds
Started Apr 18 12:44:05 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 222472 kb
Host smart-478d60a8-856a-474e-a7ea-081835842f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703380834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1703380834
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.957810993
Short name T147
Test name
Test status
Simulation time 1374588640 ps
CPU time 5.48 seconds
Started Apr 18 12:44:17 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 219880 kb
Host smart-17bf1e36-2cbe-4cd8-b5c5-067ad42dfe66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=957810993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.957810993
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1515452857
Short name T46
Test name
Test status
Simulation time 37551841 ps
CPU time 1.06 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 234428 kb
Host smart-1be6cd09-5eb3-4932-a862-9312d50f68af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515452857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1515452857
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3179581516
Short name T375
Test name
Test status
Simulation time 6854540403 ps
CPU time 16.85 seconds
Started Apr 18 12:44:05 PM PDT 24
Finished Apr 18 12:44:22 PM PDT 24
Peak memory 216120 kb
Host smart-86141712-2fb7-4c60-9926-43b0af574ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179581516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3179581516
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.130425793
Short name T105
Test name
Test status
Simulation time 1115327471 ps
CPU time 6.77 seconds
Started Apr 18 12:44:03 PM PDT 24
Finished Apr 18 12:44:11 PM PDT 24
Peak memory 215960 kb
Host smart-66396bc5-d381-4f68-b152-d3e3c93ed090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130425793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.130425793
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.716773240
Short name T576
Test name
Test status
Simulation time 141165059 ps
CPU time 1.4 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:08 PM PDT 24
Peak memory 216040 kb
Host smart-5e21fcc2-76a3-41f6-ace5-c8c636527bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716773240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.716773240
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1635215795
Short name T459
Test name
Test status
Simulation time 85517699 ps
CPU time 1.01 seconds
Started Apr 18 12:44:04 PM PDT 24
Finished Apr 18 12:44:05 PM PDT 24
Peak memory 206560 kb
Host smart-bcc119b2-82a6-4c44-8528-92d970e5db17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635215795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1635215795
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.937096344
Short name T192
Test name
Test status
Simulation time 26433224076 ps
CPU time 20.91 seconds
Started Apr 18 12:44:06 PM PDT 24
Finished Apr 18 12:44:28 PM PDT 24
Peak memory 220112 kb
Host smart-0b9d35d6-9da9-4401-8b94-69aa7a0f11d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937096344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.937096344
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2784240885
Short name T597
Test name
Test status
Simulation time 30787473 ps
CPU time 0.68 seconds
Started Apr 18 12:45:27 PM PDT 24
Finished Apr 18 12:45:29 PM PDT 24
Peak memory 205228 kb
Host smart-bae1e5ab-366e-4d5c-b1b2-4b432ac7701f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784240885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2784240885
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2324973617
Short name T550
Test name
Test status
Simulation time 16229916 ps
CPU time 0.74 seconds
Started Apr 18 12:45:28 PM PDT 24
Finished Apr 18 12:45:31 PM PDT 24
Peak memory 205480 kb
Host smart-b3b3680a-554f-4a2c-aab2-11b898f56f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324973617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2324973617
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2647519346
Short name T293
Test name
Test status
Simulation time 40176219409 ps
CPU time 112.01 seconds
Started Apr 18 12:45:24 PM PDT 24
Finished Apr 18 12:47:17 PM PDT 24
Peak memory 234564 kb
Host smart-f25f5cff-b130-4885-abe4-faae15dd2005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647519346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2647519346
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.350142678
Short name T510
Test name
Test status
Simulation time 2637588285 ps
CPU time 17.63 seconds
Started Apr 18 12:45:24 PM PDT 24
Finished Apr 18 12:45:43 PM PDT 24
Peak memory 234788 kb
Host smart-7dcdba8a-37ae-4a93-be2e-24af1ae11345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350142678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.350142678
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1380480539
Short name T266
Test name
Test status
Simulation time 1452084674 ps
CPU time 6.04 seconds
Started Apr 18 12:45:28 PM PDT 24
Finished Apr 18 12:45:36 PM PDT 24
Peak memory 223148 kb
Host smart-6375b739-06e9-42e8-acb4-1f4b3db41402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380480539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1380480539
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1750953765
Short name T479
Test name
Test status
Simulation time 1387147766 ps
CPU time 7.86 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 218832 kb
Host smart-aac3d3a9-f80f-4e01-8b7e-b2d8c5eaa5e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1750953765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1750953765
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1284202154
Short name T558
Test name
Test status
Simulation time 11512419723 ps
CPU time 30.7 seconds
Started Apr 18 12:45:18 PM PDT 24
Finished Apr 18 12:45:50 PM PDT 24
Peak memory 216256 kb
Host smart-ac2fbb72-7da1-4171-8c5a-8f2ba2ff4c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284202154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1284202154
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.980527996
Short name T17
Test name
Test status
Simulation time 54871400 ps
CPU time 1.35 seconds
Started Apr 18 12:45:26 PM PDT 24
Finished Apr 18 12:45:28 PM PDT 24
Peak memory 208004 kb
Host smart-fb720ea1-5ff8-4b07-b142-fd06e85d8151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980527996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.980527996
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3469598242
Short name T601
Test name
Test status
Simulation time 148173226 ps
CPU time 0.92 seconds
Started Apr 18 12:45:17 PM PDT 24
Finished Apr 18 12:45:19 PM PDT 24
Peak memory 205684 kb
Host smart-d01d654c-9cc6-4941-a0ec-e7767dcac5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469598242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3469598242
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4106863317
Short name T219
Test name
Test status
Simulation time 1613724476 ps
CPU time 3.72 seconds
Started Apr 18 12:45:25 PM PDT 24
Finished Apr 18 12:45:29 PM PDT 24
Peak memory 216188 kb
Host smart-ef66be58-b7ae-45f7-aad8-9b62d161c1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106863317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4106863317
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3075685883
Short name T641
Test name
Test status
Simulation time 43606944 ps
CPU time 0.73 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 205596 kb
Host smart-e17d6797-b5f9-4016-b7a7-7de079b0dba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075685883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3075685883
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3994354248
Short name T508
Test name
Test status
Simulation time 38839017 ps
CPU time 0.73 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:32 PM PDT 24
Peak memory 206500 kb
Host smart-0f70b614-bc49-4685-9490-f8e35d326d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994354248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3994354248
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2904214584
Short name T291
Test name
Test status
Simulation time 1784013828 ps
CPU time 17.74 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 224284 kb
Host smart-acda4826-dca0-4538-a75c-d54d652d5781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904214584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2904214584
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2751297593
Short name T176
Test name
Test status
Simulation time 11448545294 ps
CPU time 41.9 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:46:12 PM PDT 24
Peak memory 232088 kb
Host smart-c75425d2-3d6a-4163-a863-580f7aa9e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751297593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2751297593
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1918996901
Short name T168
Test name
Test status
Simulation time 53627992523 ps
CPU time 101.74 seconds
Started Apr 18 12:45:32 PM PDT 24
Finished Apr 18 12:47:15 PM PDT 24
Peak memory 232672 kb
Host smart-aa8a91ea-a531-4c64-acfd-3816cf4f4cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918996901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1918996901
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2838814049
Short name T321
Test name
Test status
Simulation time 15552349971 ps
CPU time 13.16 seconds
Started Apr 18 12:45:33 PM PDT 24
Finished Apr 18 12:45:47 PM PDT 24
Peak memory 222836 kb
Host smart-ae0daddb-7e3d-457c-abc0-f6a187ddf6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838814049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2838814049
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.179206126
Short name T175
Test name
Test status
Simulation time 186961302 ps
CPU time 3.09 seconds
Started Apr 18 12:45:29 PM PDT 24
Finished Apr 18 12:45:33 PM PDT 24
Peak memory 222620 kb
Host smart-0b71e5d9-bbd1-497d-b822-65b7ea538cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179206126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.179206126
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2333670552
Short name T562
Test name
Test status
Simulation time 1499208978 ps
CPU time 4.63 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:45:40 PM PDT 24
Peak memory 221652 kb
Host smart-f9b49e5a-b5b1-44bb-811b-4b2f7264afd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2333670552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2333670552
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3298004067
Short name T592
Test name
Test status
Simulation time 1915289822 ps
CPU time 24.97 seconds
Started Apr 18 12:45:24 PM PDT 24
Finished Apr 18 12:45:49 PM PDT 24
Peak memory 216544 kb
Host smart-c4692afd-a72d-42e2-b076-6c886a7710c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298004067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3298004067
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.757432831
Short name T567
Test name
Test status
Simulation time 54603291533 ps
CPU time 33.18 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:46:04 PM PDT 24
Peak memory 216256 kb
Host smart-e3698afd-3854-423f-9ea9-32e6c25e7664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757432831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.757432831
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1191266601
Short name T560
Test name
Test status
Simulation time 99893462 ps
CPU time 1.93 seconds
Started Apr 18 12:45:31 PM PDT 24
Finished Apr 18 12:45:34 PM PDT 24
Peak memory 216080 kb
Host smart-d38bfcc8-6f91-4087-87d7-c80b639eb90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191266601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1191266601
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.887312962
Short name T693
Test name
Test status
Simulation time 51986080 ps
CPU time 0.8 seconds
Started Apr 18 12:45:31 PM PDT 24
Finished Apr 18 12:45:33 PM PDT 24
Peak memory 205692 kb
Host smart-55fd6e43-328d-4f10-bd0f-78a833f27713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887312962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.887312962
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3415627470
Short name T577
Test name
Test status
Simulation time 14502550 ps
CPU time 0.72 seconds
Started Apr 18 12:45:40 PM PDT 24
Finished Apr 18 12:45:41 PM PDT 24
Peak memory 205368 kb
Host smart-e78c556b-f223-4db5-af28-0d0264aa08d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415627470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3415627470
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.650066538
Short name T489
Test name
Test status
Simulation time 20790867 ps
CPU time 0.74 seconds
Started Apr 18 12:45:33 PM PDT 24
Finished Apr 18 12:45:35 PM PDT 24
Peak memory 206404 kb
Host smart-dbfd1331-e172-491d-a25e-5017e7eeeca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650066538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.650066538
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2711436629
Short name T148
Test name
Test status
Simulation time 16885795220 ps
CPU time 103.63 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:47:16 PM PDT 24
Peak memory 249180 kb
Host smart-8b7e37c9-ce80-45c9-a9a6-5154b7cee63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711436629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2711436629
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1919168468
Short name T215
Test name
Test status
Simulation time 8870253941 ps
CPU time 46.08 seconds
Started Apr 18 12:45:31 PM PDT 24
Finished Apr 18 12:46:18 PM PDT 24
Peak memory 233664 kb
Host smart-9ce52288-086e-47a6-b1f4-ea16fda34bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919168468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1919168468
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2398265163
Short name T343
Test name
Test status
Simulation time 26725570061 ps
CPU time 20.13 seconds
Started Apr 18 12:45:41 PM PDT 24
Finished Apr 18 12:46:02 PM PDT 24
Peak memory 221496 kb
Host smart-44de6fe3-bf21-487a-ad01-c1b18d01ad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398265163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2398265163
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2059478996
Short name T640
Test name
Test status
Simulation time 824065601 ps
CPU time 9.55 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:45:41 PM PDT 24
Peak memory 219996 kb
Host smart-b6a7ebf8-d3ca-4fe3-ab63-883cd164c835
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2059478996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2059478996
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3705476281
Short name T12
Test name
Test status
Simulation time 21141918741 ps
CPU time 62.34 seconds
Started Apr 18 12:45:31 PM PDT 24
Finished Apr 18 12:46:35 PM PDT 24
Peak memory 216040 kb
Host smart-e5f97de7-d4a4-4ee5-be5d-e210bfe35d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705476281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3705476281
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2372434507
Short name T498
Test name
Test status
Simulation time 13501055557 ps
CPU time 30.77 seconds
Started Apr 18 12:45:30 PM PDT 24
Finished Apr 18 12:46:02 PM PDT 24
Peak memory 216144 kb
Host smart-e7e4b1a4-8dd2-4c70-9f66-b945ea87d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372434507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2372434507
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3104640090
Short name T477
Test name
Test status
Simulation time 45922991 ps
CPU time 1.26 seconds
Started Apr 18 12:45:37 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 216148 kb
Host smart-5395fed5-7523-4f44-8f2f-6dee1c510ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104640090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3104640090
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2737811017
Short name T585
Test name
Test status
Simulation time 130157361 ps
CPU time 0.8 seconds
Started Apr 18 12:45:36 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 206612 kb
Host smart-2926a834-3517-4c93-a7ab-be559026ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737811017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2737811017
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3536666587
Short name T18
Test name
Test status
Simulation time 8084391347 ps
CPU time 28 seconds
Started Apr 18 12:45:31 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 221216 kb
Host smart-8d505309-14ba-4c29-bf0b-c5ec58243cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536666587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3536666587
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.839146555
Short name T685
Test name
Test status
Simulation time 13088789 ps
CPU time 0.72 seconds
Started Apr 18 12:45:40 PM PDT 24
Finished Apr 18 12:45:41 PM PDT 24
Peak memory 205304 kb
Host smart-6717242e-d318-4332-80f5-50ebf9d06233
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839146555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.839146555
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3195575431
Short name T670
Test name
Test status
Simulation time 23791264 ps
CPU time 0.7 seconds
Started Apr 18 12:45:33 PM PDT 24
Finished Apr 18 12:45:35 PM PDT 24
Peak memory 205436 kb
Host smart-520349e2-a0dc-4464-8703-3b1aae2083a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195575431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3195575431
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2979068620
Short name T286
Test name
Test status
Simulation time 346976791 ps
CPU time 14.59 seconds
Started Apr 18 12:45:32 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 233560 kb
Host smart-ee0047c2-49c6-4e3e-bc9d-612b99be084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979068620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2979068620
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3550921828
Short name T95
Test name
Test status
Simulation time 8649740923 ps
CPU time 92.53 seconds
Started Apr 18 12:45:36 PM PDT 24
Finished Apr 18 12:47:10 PM PDT 24
Peak memory 246764 kb
Host smart-d24e8029-d760-43bc-85bb-d75920133ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550921828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3550921828
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2578517546
Short name T238
Test name
Test status
Simulation time 867590949 ps
CPU time 4.58 seconds
Started Apr 18 12:45:35 PM PDT 24
Finished Apr 18 12:45:41 PM PDT 24
Peak memory 218412 kb
Host smart-5d98aa4f-ee15-4c81-a0f3-68f60e6004b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578517546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2578517546
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.70586837
Short name T393
Test name
Test status
Simulation time 1054860717 ps
CPU time 4.43 seconds
Started Apr 18 12:45:32 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 220288 kb
Host smart-0c1862ea-1943-4503-bac3-f545994c73da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=70586837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direc
t.70586837
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1177313566
Short name T515
Test name
Test status
Simulation time 2253677950 ps
CPU time 36.4 seconds
Started Apr 18 12:45:35 PM PDT 24
Finished Apr 18 12:46:12 PM PDT 24
Peak memory 216532 kb
Host smart-0c43734e-146e-4a1d-af01-210a0ebe02de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177313566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1177313566
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1482111634
Short name T523
Test name
Test status
Simulation time 6400920766 ps
CPU time 25.08 seconds
Started Apr 18 12:45:34 PM PDT 24
Finished Apr 18 12:46:00 PM PDT 24
Peak memory 216272 kb
Host smart-a2054b39-bed6-4435-97bd-0ced46461454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482111634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1482111634
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.928999205
Short name T384
Test name
Test status
Simulation time 290461443 ps
CPU time 1.43 seconds
Started Apr 18 12:45:32 PM PDT 24
Finished Apr 18 12:45:35 PM PDT 24
Peak memory 216140 kb
Host smart-d452cce3-d226-42ce-bf9d-771de7a0ca75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928999205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.928999205
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.164101297
Short name T603
Test name
Test status
Simulation time 76140146 ps
CPU time 0.87 seconds
Started Apr 18 12:45:34 PM PDT 24
Finished Apr 18 12:45:35 PM PDT 24
Peak memory 205560 kb
Host smart-261a09f2-2397-42ab-a458-8eb5aaa10264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164101297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.164101297
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1168270385
Short name T702
Test name
Test status
Simulation time 26752399 ps
CPU time 0.7 seconds
Started Apr 18 12:45:38 PM PDT 24
Finished Apr 18 12:45:40 PM PDT 24
Peak memory 204840 kb
Host smart-84598014-d306-4e1c-90dc-50be5b04b823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168270385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1168270385
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3452866622
Short name T607
Test name
Test status
Simulation time 15472252 ps
CPU time 0.8 seconds
Started Apr 18 12:45:38 PM PDT 24
Finished Apr 18 12:45:40 PM PDT 24
Peak memory 206712 kb
Host smart-8a89d95e-8db9-4692-8ad7-2a29ebcf0711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452866622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3452866622
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3358348962
Short name T283
Test name
Test status
Simulation time 4897525839 ps
CPU time 30.86 seconds
Started Apr 18 12:45:36 PM PDT 24
Finished Apr 18 12:46:08 PM PDT 24
Peak memory 249812 kb
Host smart-3494ebca-c9e7-4198-a96e-bfd889177b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358348962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3358348962
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2444262441
Short name T189
Test name
Test status
Simulation time 207414044 ps
CPU time 2.24 seconds
Started Apr 18 12:45:36 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 216652 kb
Host smart-31b024d7-bdec-4997-87d7-c3c45a540fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444262441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2444262441
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3239721936
Short name T2
Test name
Test status
Simulation time 2214023612 ps
CPU time 6.51 seconds
Started Apr 18 12:45:38 PM PDT 24
Finished Apr 18 12:45:46 PM PDT 24
Peak memory 224424 kb
Host smart-a6439a90-9a85-4f71-a909-7b00c7b7ee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239721936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3239721936
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1622661228
Short name T466
Test name
Test status
Simulation time 570050228 ps
CPU time 4.21 seconds
Started Apr 18 12:45:39 PM PDT 24
Finished Apr 18 12:45:44 PM PDT 24
Peak memory 222764 kb
Host smart-3a820fff-39e9-4efd-af59-ebf926151c97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1622661228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1622661228
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2973638044
Short name T614
Test name
Test status
Simulation time 4615289671 ps
CPU time 44.59 seconds
Started Apr 18 12:45:36 PM PDT 24
Finished Apr 18 12:46:22 PM PDT 24
Peak memory 216208 kb
Host smart-70b31a4a-09ca-41ec-9269-7757b4be6e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973638044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2973638044
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1292107193
Short name T547
Test name
Test status
Simulation time 23760078399 ps
CPU time 30.57 seconds
Started Apr 18 12:45:36 PM PDT 24
Finished Apr 18 12:46:08 PM PDT 24
Peak memory 216228 kb
Host smart-70c0222e-65a8-4d71-a00c-ad432a996c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292107193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1292107193
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3619298022
Short name T53
Test name
Test status
Simulation time 582930497 ps
CPU time 2.07 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:04 PM PDT 24
Peak memory 215876 kb
Host smart-52833300-ad65-46f3-86e9-df0fbd5cacdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619298022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3619298022
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.784575740
Short name T470
Test name
Test status
Simulation time 111746900 ps
CPU time 0.95 seconds
Started Apr 18 12:45:34 PM PDT 24
Finished Apr 18 12:45:36 PM PDT 24
Peak memory 206692 kb
Host smart-6bf60f12-1c1d-4c31-b975-1be790a40d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784575740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.784575740
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3143517070
Short name T70
Test name
Test status
Simulation time 8211947375 ps
CPU time 19.88 seconds
Started Apr 18 12:45:35 PM PDT 24
Finished Apr 18 12:45:56 PM PDT 24
Peak memory 222880 kb
Host smart-9624b6ec-6c90-4e29-8173-bcc1062bcd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143517070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3143517070
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.197871310
Short name T501
Test name
Test status
Simulation time 123943608 ps
CPU time 0.71 seconds
Started Apr 18 12:45:41 PM PDT 24
Finished Apr 18 12:45:43 PM PDT 24
Peak memory 204764 kb
Host smart-c9079e92-6501-4537-a308-ee1fc022567f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197871310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.197871310
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3775238518
Short name T417
Test name
Test status
Simulation time 62230554 ps
CPU time 0.76 seconds
Started Apr 18 12:45:38 PM PDT 24
Finished Apr 18 12:45:39 PM PDT 24
Peak memory 205520 kb
Host smart-e55f9feb-b89c-495e-811c-c29ecfef5733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775238518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3775238518
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3851227959
Short name T279
Test name
Test status
Simulation time 18879835724 ps
CPU time 61.49 seconds
Started Apr 18 12:45:42 PM PDT 24
Finished Apr 18 12:46:44 PM PDT 24
Peak memory 240816 kb
Host smart-24c058c3-46ef-4859-9df8-3e686a0dfd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851227959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3851227959
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1058866965
Short name T496
Test name
Test status
Simulation time 319552609 ps
CPU time 4.73 seconds
Started Apr 18 12:45:39 PM PDT 24
Finished Apr 18 12:45:45 PM PDT 24
Peak memory 216500 kb
Host smart-5344bd01-fb67-48d6-b1f6-099c283f3883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058866965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1058866965
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3660525764
Short name T490
Test name
Test status
Simulation time 6449034531 ps
CPU time 58.18 seconds
Started Apr 18 12:45:37 PM PDT 24
Finished Apr 18 12:46:36 PM PDT 24
Peak memory 226576 kb
Host smart-b5279d87-3149-4a42-828a-73e16a561529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660525764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3660525764
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1576216987
Short name T144
Test name
Test status
Simulation time 1032021927 ps
CPU time 6.51 seconds
Started Apr 18 12:45:38 PM PDT 24
Finished Apr 18 12:45:46 PM PDT 24
Peak memory 236820 kb
Host smart-0995839e-c671-4695-8bd8-394a219de238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576216987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1576216987
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3129263329
Short name T566
Test name
Test status
Simulation time 227817661 ps
CPU time 3.89 seconds
Started Apr 18 12:45:37 PM PDT 24
Finished Apr 18 12:45:42 PM PDT 24
Peak memory 222880 kb
Host smart-1a4ad260-ed8e-47a2-a19d-8c6c9dd6cd78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3129263329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3129263329
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.30817545
Short name T41
Test name
Test status
Simulation time 134112100 ps
CPU time 0.96 seconds
Started Apr 18 12:45:42 PM PDT 24
Finished Apr 18 12:45:44 PM PDT 24
Peak memory 206796 kb
Host smart-e09f133a-4309-4355-96c7-278a3c09249b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30817545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress
_all.30817545
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2378428925
Short name T356
Test name
Test status
Simulation time 12256022677 ps
CPU time 8.2 seconds
Started Apr 18 12:45:35 PM PDT 24
Finished Apr 18 12:45:45 PM PDT 24
Peak memory 217904 kb
Host smart-857fc160-7f64-4f7d-aad6-b2a1e4655d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378428925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2378428925
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3021489076
Short name T516
Test name
Test status
Simulation time 848006220 ps
CPU time 2.61 seconds
Started Apr 18 12:45:41 PM PDT 24
Finished Apr 18 12:45:45 PM PDT 24
Peak memory 216104 kb
Host smart-847487e8-dc41-42cd-a073-2ab72fe9d750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021489076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3021489076
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2216335534
Short name T487
Test name
Test status
Simulation time 121374805 ps
CPU time 6.43 seconds
Started Apr 18 12:45:39 PM PDT 24
Finished Apr 18 12:45:47 PM PDT 24
Peak memory 216232 kb
Host smart-47ffbfbf-39e3-4953-adc4-1855719bd3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216335534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2216335534
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.976113288
Short name T404
Test name
Test status
Simulation time 107725253 ps
CPU time 0.87 seconds
Started Apr 18 12:45:34 PM PDT 24
Finished Apr 18 12:45:36 PM PDT 24
Peak memory 205684 kb
Host smart-19302128-dcb5-41fc-b674-dd5fdde04f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976113288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.976113288
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3925626412
Short name T606
Test name
Test status
Simulation time 13673953 ps
CPU time 0.69 seconds
Started Apr 18 12:45:52 PM PDT 24
Finished Apr 18 12:45:54 PM PDT 24
Peak memory 205356 kb
Host smart-c0742645-b933-4cb0-9000-4edc4c6c1cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925626412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3925626412
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.327426557
Short name T568
Test name
Test status
Simulation time 106804427 ps
CPU time 3.65 seconds
Started Apr 18 12:45:52 PM PDT 24
Finished Apr 18 12:45:58 PM PDT 24
Peak memory 224388 kb
Host smart-bd79d4f0-69b1-4e89-9298-2cd69b3380e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327426557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.327426557
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3440942362
Short name T407
Test name
Test status
Simulation time 38931584 ps
CPU time 0.76 seconds
Started Apr 18 12:45:42 PM PDT 24
Finished Apr 18 12:45:44 PM PDT 24
Peak memory 206668 kb
Host smart-d19adf8a-a873-490d-a9ec-25191970fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440942362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3440942362
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_intercept.499866391
Short name T196
Test name
Test status
Simulation time 233623931 ps
CPU time 5.06 seconds
Started Apr 18 12:45:46 PM PDT 24
Finished Apr 18 12:45:51 PM PDT 24
Peak memory 223780 kb
Host smart-1d0581cd-6249-4c2a-afd7-12b86ed0577d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499866391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.499866391
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1092676525
Short name T506
Test name
Test status
Simulation time 1247601606 ps
CPU time 5.14 seconds
Started Apr 18 12:45:42 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 220288 kb
Host smart-4f4a9eff-f93e-44c3-b823-c4824df34c67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1092676525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1092676525
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1782006048
Short name T684
Test name
Test status
Simulation time 8740892828 ps
CPU time 11.12 seconds
Started Apr 18 12:45:41 PM PDT 24
Finished Apr 18 12:45:53 PM PDT 24
Peak memory 216268 kb
Host smart-76c7993a-3f30-4de8-acc8-4b9dc37e612e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782006048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1782006048
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1827988154
Short name T457
Test name
Test status
Simulation time 6046024287 ps
CPU time 10.16 seconds
Started Apr 18 12:45:47 PM PDT 24
Finished Apr 18 12:45:58 PM PDT 24
Peak memory 216220 kb
Host smart-c8fa4344-e465-4d3d-9712-c41d3446bee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827988154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1827988154
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2898591695
Short name T689
Test name
Test status
Simulation time 1022289923 ps
CPU time 3.12 seconds
Started Apr 18 12:45:41 PM PDT 24
Finished Apr 18 12:45:45 PM PDT 24
Peak memory 216116 kb
Host smart-a3e01ab1-4cd4-49a0-9939-6b27872ffb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898591695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2898591695
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.131360542
Short name T473
Test name
Test status
Simulation time 137059335 ps
CPU time 1.09 seconds
Started Apr 18 12:45:42 PM PDT 24
Finished Apr 18 12:45:44 PM PDT 24
Peak memory 205664 kb
Host smart-8bdd96aa-4c03-453d-afdc-6148c22452d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131360542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.131360542
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3075841682
Short name T267
Test name
Test status
Simulation time 1627664005 ps
CPU time 4.43 seconds
Started Apr 18 12:45:43 PM PDT 24
Finished Apr 18 12:45:48 PM PDT 24
Peak memory 221576 kb
Host smart-af822408-13e8-4a99-a473-305227da250c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075841682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3075841682
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2231267408
Short name T695
Test name
Test status
Simulation time 23372431 ps
CPU time 0.72 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 204808 kb
Host smart-afa88832-6dcb-4cde-b75c-3d4c758f7ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231267408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2231267408
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1149250349
Short name T596
Test name
Test status
Simulation time 37046299 ps
CPU time 0.74 seconds
Started Apr 18 12:45:50 PM PDT 24
Finished Apr 18 12:45:51 PM PDT 24
Peak memory 205316 kb
Host smart-0478e8e6-177b-45da-806c-05e6be6a5cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149250349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1149250349
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3471917463
Short name T662
Test name
Test status
Simulation time 6400853527 ps
CPU time 91.34 seconds
Started Apr 18 12:45:48 PM PDT 24
Finished Apr 18 12:47:20 PM PDT 24
Peak memory 233520 kb
Host smart-9f5f77ed-b0eb-4035-b2c7-58cbfb65afd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471917463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3471917463
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3133198109
Short name T188
Test name
Test status
Simulation time 622667881 ps
CPU time 7.85 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:09 PM PDT 24
Peak memory 232404 kb
Host smart-a9650416-7a0d-4e19-80e8-c91e1c7a9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133198109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3133198109
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3444948822
Short name T4
Test name
Test status
Simulation time 565432267 ps
CPU time 4.28 seconds
Started Apr 18 12:45:56 PM PDT 24
Finished Apr 18 12:46:03 PM PDT 24
Peak memory 218580 kb
Host smart-4d73e3d4-b004-4d71-a409-2492753c4d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444948822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3444948822
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1703151472
Short name T572
Test name
Test status
Simulation time 280111380 ps
CPU time 5.73 seconds
Started Apr 18 12:46:05 PM PDT 24
Finished Apr 18 12:46:11 PM PDT 24
Peak memory 222216 kb
Host smart-91a99416-23c6-444c-8661-efb3cd739287
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1703151472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1703151472
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3838960109
Short name T528
Test name
Test status
Simulation time 2905132233 ps
CPU time 20.48 seconds
Started Apr 18 12:45:53 PM PDT 24
Finished Apr 18 12:46:16 PM PDT 24
Peak memory 216252 kb
Host smart-63d340be-2117-4bf2-9744-83a6fa71959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838960109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3838960109
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1913800876
Short name T658
Test name
Test status
Simulation time 11156081334 ps
CPU time 11.39 seconds
Started Apr 18 12:45:48 PM PDT 24
Finished Apr 18 12:46:00 PM PDT 24
Peak memory 216224 kb
Host smart-dd0ee13c-0dea-4bf5-b483-eff258d2e8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913800876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1913800876
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1911277034
Short name T381
Test name
Test status
Simulation time 14187001 ps
CPU time 0.81 seconds
Started Apr 18 12:45:48 PM PDT 24
Finished Apr 18 12:45:49 PM PDT 24
Peak memory 206544 kb
Host smart-15cb4bd9-4eff-411c-b24c-94af12e7821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911277034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1911277034
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1902969145
Short name T507
Test name
Test status
Simulation time 228158986 ps
CPU time 0.93 seconds
Started Apr 18 12:45:45 PM PDT 24
Finished Apr 18 12:45:47 PM PDT 24
Peak memory 206716 kb
Host smart-cad694d5-0c00-4586-9ee4-342b00026997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902969145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1902969145
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3196001899
Short name T237
Test name
Test status
Simulation time 9704452131 ps
CPU time 12.67 seconds
Started Apr 18 12:45:47 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 222988 kb
Host smart-fb05bba0-aabc-4e8d-bca9-6819c3282d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196001899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3196001899
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1077548841
Short name T638
Test name
Test status
Simulation time 44341687 ps
CPU time 0.67 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:45:58 PM PDT 24
Peak memory 205272 kb
Host smart-5614757d-324a-4f1e-8bae-c0af6b63f304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077548841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1077548841
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1158005816
Short name T212
Test name
Test status
Simulation time 3871061857 ps
CPU time 13.1 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:13 PM PDT 24
Peak memory 223548 kb
Host smart-06d3109b-13ea-4518-bcde-7424fa264a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158005816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1158005816
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.773703345
Short name T620
Test name
Test status
Simulation time 26851872 ps
CPU time 0.75 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:02 PM PDT 24
Peak memory 205316 kb
Host smart-de1b0b80-bab0-46f5-93d1-97a153190415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773703345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.773703345
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3499775253
Short name T302
Test name
Test status
Simulation time 21750931016 ps
CPU time 57.44 seconds
Started Apr 18 12:45:53 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 238520 kb
Host smart-0ac38d77-bcd2-4e9e-a2a7-d9217d7de935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499775253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3499775253
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.309226830
Short name T59
Test name
Test status
Simulation time 4367536632 ps
CPU time 8.78 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:46:05 PM PDT 24
Peak memory 234568 kb
Host smart-69caf64e-cc1a-4511-9e59-1919d7c330a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309226830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.309226830
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.56941670
Short name T526
Test name
Test status
Simulation time 384689738 ps
CPU time 4.11 seconds
Started Apr 18 12:45:57 PM PDT 24
Finished Apr 18 12:46:04 PM PDT 24
Peak memory 222688 kb
Host smart-43b8d8bd-bd05-4d15-adb6-0c603d9723c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=56941670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direc
t.56941670
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2916270359
Short name T372
Test name
Test status
Simulation time 3275308446 ps
CPU time 25.72 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:27 PM PDT 24
Peak memory 216364 kb
Host smart-98336563-7dbe-4771-b1a6-a8f69ccf7183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916270359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2916270359
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.452212882
Short name T582
Test name
Test status
Simulation time 8788185505 ps
CPU time 4.7 seconds
Started Apr 18 12:45:51 PM PDT 24
Finished Apr 18 12:45:57 PM PDT 24
Peak memory 216192 kb
Host smart-aac6ce1c-2a4a-47bc-8bd1-f76ee34cf134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452212882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.452212882
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3390389835
Short name T681
Test name
Test status
Simulation time 186447501 ps
CPU time 1.54 seconds
Started Apr 18 12:45:47 PM PDT 24
Finished Apr 18 12:45:49 PM PDT 24
Peak memory 208008 kb
Host smart-46120044-aab8-43aa-9fcd-655957adf3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390389835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3390389835
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3828577051
Short name T512
Test name
Test status
Simulation time 94061717 ps
CPU time 0.97 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:15 PM PDT 24
Peak memory 206612 kb
Host smart-29666cc5-5438-4358-9e2a-6e309871b8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828577051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3828577051
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4120323001
Short name T455
Test name
Test status
Simulation time 41989467 ps
CPU time 0.7 seconds
Started Apr 18 12:45:52 PM PDT 24
Finished Apr 18 12:45:54 PM PDT 24
Peak memory 205204 kb
Host smart-e7834b30-4740-458a-b4c5-d3dedd43f8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120323001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4120323001
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1563889350
Short name T83
Test name
Test status
Simulation time 162020137 ps
CPU time 4.54 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:05 PM PDT 24
Peak memory 222940 kb
Host smart-01e7933b-3376-4649-83bf-3a145e13b286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563889350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1563889350
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.188956505
Short name T503
Test name
Test status
Simulation time 31632265 ps
CPU time 0.76 seconds
Started Apr 18 12:46:03 PM PDT 24
Finished Apr 18 12:46:05 PM PDT 24
Peak memory 205776 kb
Host smart-d434d7f0-1473-42ff-8128-a3fb630bb1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188956505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.188956505
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2072591693
Short name T281
Test name
Test status
Simulation time 2243421083 ps
CPU time 37.44 seconds
Started Apr 18 12:45:57 PM PDT 24
Finished Apr 18 12:46:37 PM PDT 24
Peak memory 240576 kb
Host smart-dafd48aa-bdc7-4876-8288-c0bf8611f381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072591693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2072591693
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3422667737
Short name T389
Test name
Test status
Simulation time 1372132758 ps
CPU time 4.49 seconds
Started Apr 18 12:45:57 PM PDT 24
Finished Apr 18 12:46:04 PM PDT 24
Peak memory 222444 kb
Host smart-a27d7847-293a-4573-8e55-fde02c6d080d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422667737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3422667737
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3934300822
Short name T161
Test name
Test status
Simulation time 15826324720 ps
CPU time 9.46 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:11 PM PDT 24
Peak memory 218356 kb
Host smart-5f9b5b09-0698-4523-b7ec-7af0b0d2c212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934300822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3934300822
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4145829652
Short name T468
Test name
Test status
Simulation time 1300445999 ps
CPU time 6.83 seconds
Started Apr 18 12:45:53 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 218856 kb
Host smart-125a129a-0331-4e5f-ac65-6e8bd028b0ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4145829652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4145829652
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.607774518
Short name T388
Test name
Test status
Simulation time 72803442 ps
CPU time 1.24 seconds
Started Apr 18 12:46:01 PM PDT 24
Finished Apr 18 12:46:05 PM PDT 24
Peak memory 206940 kb
Host smart-a62cc018-1654-4925-a088-695efa140875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607774518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.607774518
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2597152111
Short name T518
Test name
Test status
Simulation time 4709865293 ps
CPU time 35.81 seconds
Started Apr 18 12:45:52 PM PDT 24
Finished Apr 18 12:46:29 PM PDT 24
Peak memory 216100 kb
Host smart-c1ee7f18-7ee2-4b3a-829b-06c17dbe28ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597152111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2597152111
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1797550552
Short name T605
Test name
Test status
Simulation time 5477583288 ps
CPU time 4.49 seconds
Started Apr 18 12:45:48 PM PDT 24
Finished Apr 18 12:45:53 PM PDT 24
Peak memory 216216 kb
Host smart-70b97573-7213-4e67-acb5-b92961409a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797550552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1797550552
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2803929029
Short name T386
Test name
Test status
Simulation time 946716137 ps
CPU time 3.97 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:46:01 PM PDT 24
Peak memory 216056 kb
Host smart-d0930f95-645d-440f-8f9e-9f29f025c805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803929029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2803929029
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1332221314
Short name T686
Test name
Test status
Simulation time 81536702 ps
CPU time 0.87 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:45:59 PM PDT 24
Peak memory 205544 kb
Host smart-c8129710-cfa5-4003-bb4b-d725e74e4099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332221314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1332221314
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3707035688
Short name T436
Test name
Test status
Simulation time 13372101 ps
CPU time 0.71 seconds
Started Apr 18 12:44:15 PM PDT 24
Finished Apr 18 12:44:16 PM PDT 24
Peak memory 205204 kb
Host smart-fcdd560b-d6f2-4890-a24d-954efeddb91c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707035688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
707035688
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.105226957
Short name T419
Test name
Test status
Simulation time 51061154 ps
CPU time 0.75 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:15 PM PDT 24
Peak memory 206508 kb
Host smart-106a1938-a7cd-4035-8bc5-af695627176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105226957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.105226957
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.768777034
Short name T692
Test name
Test status
Simulation time 11935548214 ps
CPU time 74.52 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:45:38 PM PDT 24
Peak memory 253660 kb
Host smart-6047d17f-698f-4fc8-a724-d70688f9f069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768777034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.768777034
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.648720366
Short name T86
Test name
Test status
Simulation time 4313912287 ps
CPU time 12.25 seconds
Started Apr 18 12:44:13 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 223788 kb
Host smart-99d3dd13-3169-4fee-b1d1-acabe224b77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648720366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.648720366
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1957669001
Short name T220
Test name
Test status
Simulation time 889662003 ps
CPU time 6.79 seconds
Started Apr 18 12:44:13 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 220904 kb
Host smart-b9064778-3efd-4b56-9875-1d62ef1eb9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957669001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1957669001
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2698793290
Short name T539
Test name
Test status
Simulation time 4357709862 ps
CPU time 16.81 seconds
Started Apr 18 12:44:19 PM PDT 24
Finished Apr 18 12:44:37 PM PDT 24
Peak memory 218940 kb
Host smart-aa54ea5b-094c-411c-b312-2c883c6c2ffb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698793290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2698793290
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.165412251
Short name T45
Test name
Test status
Simulation time 153726341 ps
CPU time 1.22 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 234764 kb
Host smart-875cb6da-b263-4e0f-9b56-6cdaec1ef819
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165412251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.165412251
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2207557034
Short name T102
Test name
Test status
Simulation time 17749510225 ps
CPU time 21.99 seconds
Started Apr 18 12:44:13 PM PDT 24
Finished Apr 18 12:44:36 PM PDT 24
Peak memory 216224 kb
Host smart-bea4bb21-551b-4171-82a7-238625be6733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207557034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2207557034
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1003459927
Short name T664
Test name
Test status
Simulation time 13558391920 ps
CPU time 32.28 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:48 PM PDT 24
Peak memory 216132 kb
Host smart-7cc947b3-6406-4ce4-86c6-0567a8b43ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003459927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1003459927
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4038492921
Short name T569
Test name
Test status
Simulation time 63403215 ps
CPU time 0.91 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:44:20 PM PDT 24
Peak memory 206372 kb
Host smart-7a7e5b9f-4918-47a9-9880-78e9a1e9edac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038492921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4038492921
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.762536658
Short name T433
Test name
Test status
Simulation time 194681268 ps
CPU time 0.81 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:15 PM PDT 24
Peak memory 205672 kb
Host smart-1f9c1a4e-0a20-4b42-891a-c4e8962c9871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762536658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.762536658
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3629342077
Short name T449
Test name
Test status
Simulation time 20493007 ps
CPU time 0.71 seconds
Started Apr 18 12:46:00 PM PDT 24
Finished Apr 18 12:46:03 PM PDT 24
Peak memory 204784 kb
Host smart-26538ddb-d2ef-468e-b1a2-cd315edaf492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629342077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3629342077
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2796632678
Short name T396
Test name
Test status
Simulation time 17442643 ps
CPU time 0.81 seconds
Started Apr 18 12:45:57 PM PDT 24
Finished Apr 18 12:46:00 PM PDT 24
Peak memory 206348 kb
Host smart-1f4c0204-6ffb-4c08-817b-6a3f56d4a9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796632678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2796632678
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4213992425
Short name T151
Test name
Test status
Simulation time 866287362 ps
CPU time 25.1 seconds
Started Apr 18 12:45:52 PM PDT 24
Finished Apr 18 12:46:19 PM PDT 24
Peak memory 248712 kb
Host smart-d84b9071-e153-4134-bf42-884c5c4dbcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213992425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4213992425
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4105861388
Short name T232
Test name
Test status
Simulation time 5924697081 ps
CPU time 15.53 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:16 PM PDT 24
Peak memory 233680 kb
Host smart-0c603493-fed8-4ded-9015-686429902cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105861388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4105861388
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.971661022
Short name T200
Test name
Test status
Simulation time 2965826784 ps
CPU time 11.75 seconds
Started Apr 18 12:45:52 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 235868 kb
Host smart-ebd72869-8909-4c8b-9ea3-09a0f4f37c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971661022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.971661022
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.836626413
Short name T583
Test name
Test status
Simulation time 1488649249 ps
CPU time 11.44 seconds
Started Apr 18 12:45:53 PM PDT 24
Finished Apr 18 12:46:07 PM PDT 24
Peak memory 222732 kb
Host smart-5c38ce7d-0cdf-4669-9923-720db3afaf8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=836626413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.836626413
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3754004666
Short name T353
Test name
Test status
Simulation time 7348300836 ps
CPU time 18.74 seconds
Started Apr 18 12:45:55 PM PDT 24
Finished Apr 18 12:46:17 PM PDT 24
Peak memory 216312 kb
Host smart-c45581ae-b7f8-4bd2-b10c-5099c16386a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754004666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3754004666
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3210140723
Short name T456
Test name
Test status
Simulation time 5697278314 ps
CPU time 8.93 seconds
Started Apr 18 12:45:53 PM PDT 24
Finished Apr 18 12:46:05 PM PDT 24
Peak memory 216132 kb
Host smart-07fbdcf9-230e-41ff-854f-85972005b1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210140723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3210140723
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3935802450
Short name T378
Test name
Test status
Simulation time 356937643 ps
CPU time 4.29 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 216188 kb
Host smart-3c23e92f-d914-4436-aad9-62a7d44a3109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935802450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3935802450
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1553451321
Short name T483
Test name
Test status
Simulation time 514217790 ps
CPU time 1.16 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:02 PM PDT 24
Peak memory 206680 kb
Host smart-c1e96ca5-669c-46b1-a4c4-6da3713f87ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553451321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1553451321
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3226167251
Short name T495
Test name
Test status
Simulation time 16161259 ps
CPU time 0.75 seconds
Started Apr 18 12:46:03 PM PDT 24
Finished Apr 18 12:46:05 PM PDT 24
Peak memory 204656 kb
Host smart-2bc3fb5c-8950-4581-8a18-6fd511bc1572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226167251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3226167251
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1813097661
Short name T423
Test name
Test status
Simulation time 326450042 ps
CPU time 2.67 seconds
Started Apr 18 12:46:08 PM PDT 24
Finished Apr 18 12:46:11 PM PDT 24
Peak memory 218404 kb
Host smart-5fbe3372-0257-402d-ac5a-ee70529420ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813097661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1813097661
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3935070778
Short name T406
Test name
Test status
Simulation time 42970204 ps
CPU time 0.78 seconds
Started Apr 18 12:45:54 PM PDT 24
Finished Apr 18 12:45:58 PM PDT 24
Peak memory 206728 kb
Host smart-14f744b9-3b83-4726-b60b-2cd1f3485422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935070778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3935070778
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3102837119
Short name T181
Test name
Test status
Simulation time 4353098879 ps
CPU time 14.24 seconds
Started Apr 18 12:46:00 PM PDT 24
Finished Apr 18 12:46:17 PM PDT 24
Peak memory 232200 kb
Host smart-fa716529-6de6-4454-bc4a-1b78b6018760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102837119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3102837119
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.640992761
Short name T311
Test name
Test status
Simulation time 1871397207 ps
CPU time 5.53 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:07 PM PDT 24
Peak memory 216832 kb
Host smart-b8db0e20-6e2e-4197-b27b-05b18d838204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640992761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.640992761
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1840751477
Short name T613
Test name
Test status
Simulation time 3040344533 ps
CPU time 11.14 seconds
Started Apr 18 12:45:58 PM PDT 24
Finished Apr 18 12:46:12 PM PDT 24
Peak memory 220312 kb
Host smart-f29be263-6b5a-40a4-975e-6792189f8b75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1840751477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1840751477
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4026223944
Short name T642
Test name
Test status
Simulation time 4852327991 ps
CPU time 7.88 seconds
Started Apr 18 12:46:23 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 216260 kb
Host smart-ae1bacc9-7d27-4abd-a167-ae75bd5777f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026223944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4026223944
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3780877082
Short name T551
Test name
Test status
Simulation time 44740203 ps
CPU time 0.96 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:33 PM PDT 24
Peak memory 206772 kb
Host smart-e7c94e26-616f-419f-ad03-9b254276f992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780877082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3780877082
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1931947293
Short name T500
Test name
Test status
Simulation time 67616014 ps
CPU time 0.93 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:02 PM PDT 24
Peak memory 206016 kb
Host smart-525d8c50-32b5-43a7-9bf8-9303742889ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931947293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1931947293
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1882014348
Short name T184
Test name
Test status
Simulation time 4477932889 ps
CPU time 22.06 seconds
Started Apr 18 12:46:11 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 240696 kb
Host smart-f249943a-fc02-4708-8d96-3001c6ec7003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882014348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1882014348
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3554921019
Short name T699
Test name
Test status
Simulation time 82228254 ps
CPU time 0.76 seconds
Started Apr 18 12:46:00 PM PDT 24
Finished Apr 18 12:46:04 PM PDT 24
Peak memory 205344 kb
Host smart-ef2078fc-062a-433a-b1a0-0e5578223751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554921019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3554921019
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1092531780
Short name T400
Test name
Test status
Simulation time 72063967 ps
CPU time 0.73 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:15 PM PDT 24
Peak memory 205684 kb
Host smart-287e5591-18ce-47ce-9786-fa7b741840bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092531780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1092531780
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2710635530
Short name T659
Test name
Test status
Simulation time 11966204303 ps
CPU time 41.7 seconds
Started Apr 18 12:46:00 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 250648 kb
Host smart-3a9c95b5-9a2a-4a53-bec6-609533963982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710635530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2710635530
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1445117002
Short name T11
Test name
Test status
Simulation time 17187185156 ps
CPU time 34.2 seconds
Started Apr 18 12:46:04 PM PDT 24
Finished Apr 18 12:46:39 PM PDT 24
Peak memory 223380 kb
Host smart-d80a7c16-dac7-4ced-80df-b5acb98ad9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445117002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1445117002
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3364648585
Short name T198
Test name
Test status
Simulation time 3905887130 ps
CPU time 5.85 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:08 PM PDT 24
Peak memory 224380 kb
Host smart-92162bdb-71f2-44d6-9a64-290a744d1797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364648585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3364648585
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2785772018
Short name T434
Test name
Test status
Simulation time 866307913 ps
CPU time 5.18 seconds
Started Apr 18 12:46:01 PM PDT 24
Finished Apr 18 12:46:09 PM PDT 24
Peak memory 222956 kb
Host smart-97f9921c-1a6c-43be-8cc7-d00bdf42ed1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2785772018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2785772018
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.965022383
Short name T543
Test name
Test status
Simulation time 1879720087 ps
CPU time 8.15 seconds
Started Apr 18 12:46:00 PM PDT 24
Finished Apr 18 12:46:11 PM PDT 24
Peak memory 216204 kb
Host smart-4121f8e1-3eb7-4fe6-a7c5-5cd3f4d77a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965022383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.965022383
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.20833582
Short name T450
Test name
Test status
Simulation time 3215062702 ps
CPU time 15.56 seconds
Started Apr 18 12:46:02 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 216284 kb
Host smart-07a75f7a-b61d-4f48-885f-bf25d1f0b94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20833582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.20833582
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2347846442
Short name T431
Test name
Test status
Simulation time 207762593 ps
CPU time 3.35 seconds
Started Apr 18 12:45:59 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 216140 kb
Host smart-aefa8eae-665b-49be-98ce-022b2e9e961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347846442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2347846442
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4104960129
Short name T453
Test name
Test status
Simulation time 160693136 ps
CPU time 0.86 seconds
Started Apr 18 12:46:06 PM PDT 24
Finished Apr 18 12:46:08 PM PDT 24
Peak memory 205700 kb
Host smart-e47e101d-6bec-4c59-8b0a-237b3378f292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104960129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4104960129
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.914050977
Short name T522
Test name
Test status
Simulation time 53040764 ps
CPU time 0.71 seconds
Started Apr 18 12:46:04 PM PDT 24
Finished Apr 18 12:46:06 PM PDT 24
Peak memory 205708 kb
Host smart-0b9b4809-e4b8-473f-ae9e-5ab2d28d4fe9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914050977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.914050977
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3625705120
Short name T81
Test name
Test status
Simulation time 101623505 ps
CPU time 3.04 seconds
Started Apr 18 12:46:07 PM PDT 24
Finished Apr 18 12:46:10 PM PDT 24
Peak memory 218860 kb
Host smart-31717ff6-a874-4065-b516-394ea2f27bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625705120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3625705120
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1504402410
Short name T630
Test name
Test status
Simulation time 40344200 ps
CPU time 0.77 seconds
Started Apr 18 12:46:03 PM PDT 24
Finished Apr 18 12:46:05 PM PDT 24
Peak memory 206468 kb
Host smart-d005faf4-66c1-40cc-b733-bd3d081be6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504402410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1504402410
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1407717150
Short name T696
Test name
Test status
Simulation time 3286925040 ps
CPU time 18.93 seconds
Started Apr 18 12:46:14 PM PDT 24
Finished Apr 18 12:46:34 PM PDT 24
Peak memory 232612 kb
Host smart-ba2a1c2f-4664-41db-9dc5-fdf82fae9de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407717150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1407717150
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2328806599
Short name T333
Test name
Test status
Simulation time 14838203099 ps
CPU time 97.98 seconds
Started Apr 18 12:46:12 PM PDT 24
Finished Apr 18 12:47:50 PM PDT 24
Peak memory 227064 kb
Host smart-f368859c-16b4-45f0-9402-28c5528c0b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328806599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2328806599
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1037114182
Short name T331
Test name
Test status
Simulation time 5208274307 ps
CPU time 8.81 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:23 PM PDT 24
Peak memory 222680 kb
Host smart-e4094848-fd77-46bc-bd18-c0131b6bbb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037114182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1037114182
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1593578757
Short name T474
Test name
Test status
Simulation time 2057068789 ps
CPU time 6.98 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:21 PM PDT 24
Peak memory 222824 kb
Host smart-9165f6d4-acd7-4763-8751-d8e13cabfb0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1593578757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1593578757
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1151754240
Short name T571
Test name
Test status
Simulation time 13591130579 ps
CPU time 10.14 seconds
Started Apr 18 12:46:08 PM PDT 24
Finished Apr 18 12:46:19 PM PDT 24
Peak memory 216272 kb
Host smart-793acfc0-3df5-4ce7-942b-8e9c6ff5c6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151754240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1151754240
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2834687011
Short name T421
Test name
Test status
Simulation time 505936699 ps
CPU time 3.33 seconds
Started Apr 18 12:46:05 PM PDT 24
Finished Apr 18 12:46:09 PM PDT 24
Peak memory 216232 kb
Host smart-7c9e609e-480e-4d7e-bcc0-02b8a76e6d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834687011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2834687011
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3508863558
Short name T472
Test name
Test status
Simulation time 561959591 ps
CPU time 0.85 seconds
Started Apr 18 12:46:11 PM PDT 24
Finished Apr 18 12:46:12 PM PDT 24
Peak memory 205608 kb
Host smart-5cb78ab8-37db-4424-820f-935a3d295460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508863558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3508863558
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.33456633
Short name T222
Test name
Test status
Simulation time 15557932838 ps
CPU time 28.21 seconds
Started Apr 18 12:46:10 PM PDT 24
Finished Apr 18 12:46:39 PM PDT 24
Peak memory 239184 kb
Host smart-c1169b44-d5de-423b-9db5-cce8fbe58609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33456633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.33456633
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3585654474
Short name T428
Test name
Test status
Simulation time 26659339 ps
CPU time 0.69 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:14 PM PDT 24
Peak memory 204680 kb
Host smart-b8b37782-73c9-4eaf-af33-026330dea70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585654474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3585654474
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1974317520
Short name T20
Test name
Test status
Simulation time 48484248 ps
CPU time 0.81 seconds
Started Apr 18 12:46:08 PM PDT 24
Finished Apr 18 12:46:10 PM PDT 24
Peak memory 206364 kb
Host smart-299fb10f-8b53-4e2f-854d-536154291b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974317520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1974317520
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_intercept.260450001
Short name T401
Test name
Test status
Simulation time 95756004 ps
CPU time 1.99 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:16 PM PDT 24
Peak memory 217740 kb
Host smart-1d7d443d-4974-46a2-8d73-a25e9c7b0149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260450001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.260450001
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.113401484
Short name T634
Test name
Test status
Simulation time 855501542 ps
CPU time 3.4 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:18 PM PDT 24
Peak memory 218848 kb
Host smart-19565dfb-bfbf-45d8-b37c-5d2d566e0786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113401484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.113401484
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3314681049
Short name T195
Test name
Test status
Simulation time 151379395 ps
CPU time 3.83 seconds
Started Apr 18 12:46:11 PM PDT 24
Finished Apr 18 12:46:16 PM PDT 24
Peak memory 232160 kb
Host smart-bbc51922-c50e-4cbf-bef8-07efd059a62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314681049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3314681049
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1062450371
Short name T579
Test name
Test status
Simulation time 538659967 ps
CPU time 3.69 seconds
Started Apr 18 12:46:17 PM PDT 24
Finished Apr 18 12:46:22 PM PDT 24
Peak memory 222900 kb
Host smart-ba9b47b3-74e0-4d71-b78c-1a71def8424f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1062450371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1062450371
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2757112650
Short name T524
Test name
Test status
Simulation time 26374879310 ps
CPU time 35.7 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:50 PM PDT 24
Peak memory 216244 kb
Host smart-eb62057d-36b6-4eaa-b245-e4063d568052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757112650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2757112650
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3082909378
Short name T397
Test name
Test status
Simulation time 26079145139 ps
CPU time 14.88 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:29 PM PDT 24
Peak memory 216256 kb
Host smart-53fc763f-8dee-4c50-8e3e-f821cbae935d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082909378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3082909378
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2914198206
Short name T676
Test name
Test status
Simulation time 70676815 ps
CPU time 2.16 seconds
Started Apr 18 12:46:05 PM PDT 24
Finished Apr 18 12:46:09 PM PDT 24
Peak memory 216144 kb
Host smart-f01a258f-5289-4a3f-b260-4094505f3ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914198206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2914198206
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2479194632
Short name T590
Test name
Test status
Simulation time 130991802 ps
CPU time 0.81 seconds
Started Apr 18 12:46:06 PM PDT 24
Finished Apr 18 12:46:08 PM PDT 24
Peak memory 205592 kb
Host smart-5054b1b8-8eed-4364-b717-8d3e728ffa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479194632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2479194632
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3747570346
Short name T335
Test name
Test status
Simulation time 2757464924 ps
CPU time 6.8 seconds
Started Apr 18 12:46:05 PM PDT 24
Finished Apr 18 12:46:13 PM PDT 24
Peak memory 219196 kb
Host smart-35c19fe3-9803-4581-b300-4222d6006711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747570346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3747570346
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3526621832
Short name T398
Test name
Test status
Simulation time 26956288 ps
CPU time 0.69 seconds
Started Apr 18 12:46:12 PM PDT 24
Finished Apr 18 12:46:14 PM PDT 24
Peak memory 204672 kb
Host smart-3f49dcc0-c71c-4ff1-86e2-f8733b3d736a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526621832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3526621832
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3826026851
Short name T425
Test name
Test status
Simulation time 40161702 ps
CPU time 2.8 seconds
Started Apr 18 12:46:14 PM PDT 24
Finished Apr 18 12:46:18 PM PDT 24
Peak memory 222800 kb
Host smart-45164cfb-91ed-46a8-92f1-0a082eca0095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826026851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3826026851
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1184983961
Short name T478
Test name
Test status
Simulation time 66616582 ps
CPU time 0.75 seconds
Started Apr 18 12:46:15 PM PDT 24
Finished Apr 18 12:46:16 PM PDT 24
Peak memory 206824 kb
Host smart-5acb2538-d447-45cc-9a7f-e5adfa797590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184983961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1184983961
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1851499719
Short name T277
Test name
Test status
Simulation time 236395647 ps
CPU time 12.73 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 232488 kb
Host smart-6a8c31ef-daab-479d-ac25-706f2914e950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851499719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1851499719
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3943711942
Short name T391
Test name
Test status
Simulation time 2182898443 ps
CPU time 2.97 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 218692 kb
Host smart-60d53477-eafe-4112-97ca-75c00f85ec90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943711942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3943711942
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.797153943
Short name T129
Test name
Test status
Simulation time 11421949660 ps
CPU time 93.64 seconds
Started Apr 18 12:46:12 PM PDT 24
Finished Apr 18 12:47:46 PM PDT 24
Peak memory 240408 kb
Host smart-d4779eeb-e5af-422d-9412-e1861a2ca54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797153943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.797153943
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2236584466
Short name T163
Test name
Test status
Simulation time 1194618371 ps
CPU time 5.97 seconds
Started Apr 18 12:46:14 PM PDT 24
Finished Apr 18 12:46:21 PM PDT 24
Peak memory 222492 kb
Host smart-d5986619-dc23-4a2c-9552-11206b36cda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236584466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2236584466
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3516785594
Short name T655
Test name
Test status
Simulation time 1001009057 ps
CPU time 10.6 seconds
Started Apr 18 12:46:15 PM PDT 24
Finished Apr 18 12:46:27 PM PDT 24
Peak memory 222716 kb
Host smart-0b169e25-fa51-4771-9fb8-8c6a8f3de9d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3516785594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3516785594
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1704418918
Short name T100
Test name
Test status
Simulation time 943414400 ps
CPU time 3.04 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 216216 kb
Host smart-8440d7be-e0d4-46b1-9418-1f031e3631b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704418918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1704418918
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1099155792
Short name T103
Test name
Test status
Simulation time 45026563319 ps
CPU time 30.45 seconds
Started Apr 18 12:46:14 PM PDT 24
Finished Apr 18 12:46:46 PM PDT 24
Peak memory 216176 kb
Host smart-e2f6b4cf-ab80-473f-b49f-74d85d054ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099155792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1099155792
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3008866455
Short name T383
Test name
Test status
Simulation time 381163399 ps
CPU time 5.25 seconds
Started Apr 18 12:46:17 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 216216 kb
Host smart-d5fd2a72-8e29-47bf-bdb4-a8c5e950533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008866455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3008866455
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.543616213
Short name T678
Test name
Test status
Simulation time 256626773 ps
CPU time 1.02 seconds
Started Apr 18 12:46:14 PM PDT 24
Finished Apr 18 12:46:16 PM PDT 24
Peak memory 206608 kb
Host smart-2772eead-c1f6-4641-8e80-fce4de1e502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543616213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.543616213
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.42591149
Short name T94
Test name
Test status
Simulation time 1935300905 ps
CPU time 10.47 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:25 PM PDT 24
Peak memory 224372 kb
Host smart-ae9940fc-8e8a-47a5-a9e8-35363519d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42591149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.42591149
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4024810552
Short name T671
Test name
Test status
Simulation time 22782773 ps
CPU time 0.74 seconds
Started Apr 18 12:46:18 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 205660 kb
Host smart-3fc09e1b-df4f-444a-b629-a8be7295bd0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024810552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4024810552
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3965340681
Short name T578
Test name
Test status
Simulation time 19803895 ps
CPU time 0.84 seconds
Started Apr 18 12:46:14 PM PDT 24
Finished Apr 18 12:46:16 PM PDT 24
Peak memory 206456 kb
Host smart-1efe963e-3f76-49cc-9c2f-902340f84e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965340681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3965340681
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2184021583
Short name T546
Test name
Test status
Simulation time 5778563655 ps
CPU time 78.36 seconds
Started Apr 18 12:46:17 PM PDT 24
Finished Apr 18 12:47:36 PM PDT 24
Peak memory 240764 kb
Host smart-6a52d9aa-579b-4ff4-85e7-bd7dba8e8b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184021583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2184021583
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1165096014
Short name T542
Test name
Test status
Simulation time 289844602 ps
CPU time 5.19 seconds
Started Apr 18 12:46:13 PM PDT 24
Finished Apr 18 12:46:19 PM PDT 24
Peak memory 218936 kb
Host smart-3e653700-b4e3-427c-bcdb-f61535df8f19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1165096014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1165096014
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1028724296
Short name T1
Test name
Test status
Simulation time 1370473206 ps
CPU time 4.42 seconds
Started Apr 18 12:46:18 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 216192 kb
Host smart-c7983b6a-fd11-4cdf-8515-9fb424026cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028724296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1028724296
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.154644235
Short name T602
Test name
Test status
Simulation time 42545700 ps
CPU time 1.43 seconds
Started Apr 18 12:46:17 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 216152 kb
Host smart-b36c6e99-af42-4e01-980b-b5b3839dd149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154644235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.154644235
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2574635516
Short name T422
Test name
Test status
Simulation time 77050535 ps
CPU time 0.84 seconds
Started Apr 18 12:46:15 PM PDT 24
Finished Apr 18 12:46:18 PM PDT 24
Peak memory 205688 kb
Host smart-e606610a-7a0d-46b5-a0cb-f565520288b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574635516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2574635516
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.106328314
Short name T27
Test name
Test status
Simulation time 786715830 ps
CPU time 7.39 seconds
Started Apr 18 12:46:12 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 222556 kb
Host smart-d063cd2a-29c1-4e09-878d-6124f347d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106328314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.106328314
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1550643105
Short name T612
Test name
Test status
Simulation time 19666839 ps
CPU time 0.69 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 204788 kb
Host smart-299ad6d7-0c03-4f5d-8da3-fe8a41df7725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550643105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1550643105
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1373841732
Short name T575
Test name
Test status
Simulation time 18769748 ps
CPU time 0.75 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:46:23 PM PDT 24
Peak memory 206844 kb
Host smart-2c17e319-efc1-4d86-bf3b-d61e080d5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373841732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1373841732
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3691904115
Short name T273
Test name
Test status
Simulation time 1015832407 ps
CPU time 5.36 seconds
Started Apr 18 12:46:17 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 222612 kb
Host smart-562690fc-a9c4-40c4-9535-32b9f2120689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691904115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3691904115
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1799691002
Short name T310
Test name
Test status
Simulation time 6656756272 ps
CPU time 20.62 seconds
Started Apr 18 12:46:23 PM PDT 24
Finished Apr 18 12:46:45 PM PDT 24
Peak memory 235576 kb
Host smart-ebc73e83-0f0a-4c16-9c90-85574de1fbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799691002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1799691002
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4051510654
Short name T651
Test name
Test status
Simulation time 1053396261 ps
CPU time 3.98 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:21 PM PDT 24
Peak memory 218676 kb
Host smart-53b556b3-a5c6-4783-b086-b774b9ab32dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051510654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4051510654
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3156659890
Short name T39
Test name
Test status
Simulation time 261705941 ps
CPU time 1.11 seconds
Started Apr 18 12:46:24 PM PDT 24
Finished Apr 18 12:46:26 PM PDT 24
Peak memory 207280 kb
Host smart-0ffa9d6c-ab38-4dd6-8e32-6bc6a2966a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156659890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3156659890
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2931990257
Short name T364
Test name
Test status
Simulation time 4051522491 ps
CPU time 10.7 seconds
Started Apr 18 12:46:18 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 216112 kb
Host smart-4d9bb091-e582-4863-8428-aa69396a905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931990257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2931990257
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2433400869
Short name T636
Test name
Test status
Simulation time 40891205209 ps
CPU time 30.5 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:46:53 PM PDT 24
Peak memory 216260 kb
Host smart-c7acf135-3527-48d9-83ac-f7f456ff81fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433400869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2433400869
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3392220620
Short name T648
Test name
Test status
Simulation time 83605906 ps
CPU time 1.4 seconds
Started Apr 18 12:46:23 PM PDT 24
Finished Apr 18 12:46:25 PM PDT 24
Peak memory 216208 kb
Host smart-a2179e72-5fcd-413a-a8a3-4caeeeb7b294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392220620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3392220620
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.653156407
Short name T445
Test name
Test status
Simulation time 940092040 ps
CPU time 1.07 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:18 PM PDT 24
Peak memory 206672 kb
Host smart-b9a90fe0-98ce-4911-a3bd-3dadef688cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653156407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.653156407
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1221261068
Short name T171
Test name
Test status
Simulation time 33651270245 ps
CPU time 52.08 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:47:09 PM PDT 24
Peak memory 235868 kb
Host smart-d9febb76-f989-4c2d-9ab1-dee452b42e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221261068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1221261068
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1731050722
Short name T574
Test name
Test status
Simulation time 18258237 ps
CPU time 0.73 seconds
Started Apr 18 12:46:18 PM PDT 24
Finished Apr 18 12:46:20 PM PDT 24
Peak memory 204804 kb
Host smart-abc88100-4c4b-4b08-8043-f79aa5f8029a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731050722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1731050722
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3476182959
Short name T24
Test name
Test status
Simulation time 7025849454 ps
CPU time 44.15 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:47:07 PM PDT 24
Peak memory 232328 kb
Host smart-b7d3a8c0-34e4-4d8a-8050-66f94f7ae761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476182959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3476182959
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2353834044
Short name T22
Test name
Test status
Simulation time 23152924 ps
CPU time 0.85 seconds
Started Apr 18 12:46:19 PM PDT 24
Finished Apr 18 12:46:21 PM PDT 24
Peak memory 206468 kb
Host smart-44b1fc1e-b280-4465-b7ea-41cecb112197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353834044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2353834044
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2790478501
Short name T534
Test name
Test status
Simulation time 18689845661 ps
CPU time 54.01 seconds
Started Apr 18 12:46:20 PM PDT 24
Finished Apr 18 12:47:15 PM PDT 24
Peak memory 232632 kb
Host smart-2e8a9efb-aab4-487d-980a-a664684bf6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790478501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2790478501
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1812228354
Short name T303
Test name
Test status
Simulation time 123964269 ps
CPU time 2.67 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:46:25 PM PDT 24
Peak memory 222716 kb
Host smart-b8a6b36d-076f-4ee4-a95e-13edc2efbaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812228354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1812228354
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.28761034
Short name T157
Test name
Test status
Simulation time 2565641537 ps
CPU time 18.21 seconds
Started Apr 18 12:46:22 PM PDT 24
Finished Apr 18 12:46:41 PM PDT 24
Peak memory 224620 kb
Host smart-f65ea32c-3453-4365-97fd-14ee213b3efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28761034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.28761034
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.364035180
Short name T74
Test name
Test status
Simulation time 1484060567 ps
CPU time 13.52 seconds
Started Apr 18 12:46:47 PM PDT 24
Finished Apr 18 12:47:01 PM PDT 24
Peak memory 221572 kb
Host smart-2c3c5aa8-a980-4d9e-81bc-600b380d58db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=364035180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.364035180
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.511644743
Short name T529
Test name
Test status
Simulation time 15739471110 ps
CPU time 6.49 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:24 PM PDT 24
Peak memory 216092 kb
Host smart-930fb2ef-884f-4a9c-86a9-0c623f496eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511644743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.511644743
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1124825751
Short name T51
Test name
Test status
Simulation time 776434861 ps
CPU time 3.07 seconds
Started Apr 18 12:46:16 PM PDT 24
Finished Apr 18 12:46:21 PM PDT 24
Peak memory 216268 kb
Host smart-94eb6d52-4112-47b4-a877-09078dcc2f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124825751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1124825751
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.952568594
Short name T405
Test name
Test status
Simulation time 34695679 ps
CPU time 0.92 seconds
Started Apr 18 12:46:17 PM PDT 24
Finished Apr 18 12:46:19 PM PDT 24
Peak memory 205656 kb
Host smart-651f564c-cd61-444a-96c7-212c6bffd29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952568594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.952568594
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2879699725
Short name T201
Test name
Test status
Simulation time 4398265975 ps
CPU time 18.5 seconds
Started Apr 18 12:46:21 PM PDT 24
Finished Apr 18 12:46:40 PM PDT 24
Peak memory 238824 kb
Host smart-26df8deb-8b39-4d88-b3b3-dd00db02f5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879699725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2879699725
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3781828057
Short name T623
Test name
Test status
Simulation time 23453269 ps
CPU time 0.73 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:27 PM PDT 24
Peak memory 204820 kb
Host smart-55a8b33e-f678-42a9-812d-adbdb3edda95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781828057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3781828057
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.376968618
Short name T23
Test name
Test status
Simulation time 839164831 ps
CPU time 5.71 seconds
Started Apr 18 12:46:25 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 223848 kb
Host smart-6cd41745-e1ee-4fe5-a115-776992832758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376968618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.376968618
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3514601941
Short name T691
Test name
Test status
Simulation time 16745217 ps
CPU time 0.76 seconds
Started Apr 18 12:46:21 PM PDT 24
Finished Apr 18 12:46:22 PM PDT 24
Peak memory 205360 kb
Host smart-e4351130-743a-47f2-a05d-cea01686bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514601941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3514601941
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3087551638
Short name T205
Test name
Test status
Simulation time 4278235123 ps
CPU time 7.29 seconds
Started Apr 18 12:46:23 PM PDT 24
Finished Apr 18 12:46:31 PM PDT 24
Peak memory 216144 kb
Host smart-04494be8-d24f-42d2-aa38-09cbce672b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087551638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3087551638
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1879060338
Short name T679
Test name
Test status
Simulation time 308733375 ps
CPU time 3.66 seconds
Started Apr 18 12:46:26 PM PDT 24
Finished Apr 18 12:46:30 PM PDT 24
Peak memory 218964 kb
Host smart-6db45d3b-8dff-4c35-ab2a-a2ab3e2f87b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1879060338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1879060338
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.990580497
Short name T514
Test name
Test status
Simulation time 2448992219 ps
CPU time 6.02 seconds
Started Apr 18 12:46:24 PM PDT 24
Finished Apr 18 12:46:31 PM PDT 24
Peak memory 216256 kb
Host smart-c0c7e709-d93b-4308-bd16-65a648ba73f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990580497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.990580497
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3700049320
Short name T533
Test name
Test status
Simulation time 4162926799 ps
CPU time 12.05 seconds
Started Apr 18 12:46:15 PM PDT 24
Finished Apr 18 12:46:29 PM PDT 24
Peak memory 216212 kb
Host smart-b1cc86c6-4688-4e19-9887-91a771a4964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700049320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3700049320
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2602100144
Short name T373
Test name
Test status
Simulation time 679267967 ps
CPU time 5.89 seconds
Started Apr 18 12:46:25 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 216180 kb
Host smart-54abab7e-787b-49a4-abc6-3d6ff08e99a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602100144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2602100144
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2247374963
Short name T395
Test name
Test status
Simulation time 78081851 ps
CPU time 0.76 seconds
Started Apr 18 12:46:30 PM PDT 24
Finished Apr 18 12:46:32 PM PDT 24
Peak memory 205660 kb
Host smart-3fb26694-c228-4657-b0b5-72957c19a1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247374963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2247374963
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1677270740
Short name T309
Test name
Test status
Simulation time 1957399654 ps
CPU time 10.85 seconds
Started Apr 18 12:46:24 PM PDT 24
Finished Apr 18 12:46:35 PM PDT 24
Peak memory 233360 kb
Host smart-34da71b2-d20c-40dc-8970-5ecd8391e7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677270740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1677270740
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2351180954
Short name T626
Test name
Test status
Simulation time 43019461 ps
CPU time 0.72 seconds
Started Apr 18 12:44:16 PM PDT 24
Finished Apr 18 12:44:18 PM PDT 24
Peak memory 204800 kb
Host smart-0f538df5-3a4e-403d-8f36-6d860a81dbe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351180954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
351180954
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.424070999
Short name T628
Test name
Test status
Simulation time 17706173 ps
CPU time 0.8 seconds
Started Apr 18 12:44:13 PM PDT 24
Finished Apr 18 12:44:14 PM PDT 24
Peak memory 206328 kb
Host smart-0f2486ef-ecd6-4c2d-9069-0897f9eb9eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424070999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.424070999
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1590093532
Short name T75
Test name
Test status
Simulation time 426028238 ps
CPU time 16.08 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:31 PM PDT 24
Peak memory 232588 kb
Host smart-92101c09-c443-454b-8b36-de86306357e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590093532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1590093532
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.435665091
Short name T43
Test name
Test status
Simulation time 2020424830 ps
CPU time 7.55 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 222340 kb
Host smart-9fb8aa05-de64-4f34-8ada-dcb57036fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435665091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.435665091
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1465737107
Short name T593
Test name
Test status
Simulation time 13715072877 ps
CPU time 24.81 seconds
Started Apr 18 12:44:17 PM PDT 24
Finished Apr 18 12:44:43 PM PDT 24
Peak memory 232656 kb
Host smart-fbcccc32-6632-466b-8b98-dba72122fbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465737107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1465737107
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2960568353
Short name T244
Test name
Test status
Simulation time 626308389 ps
CPU time 9.07 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 231812 kb
Host smart-78ad73d6-3e4b-48cc-b261-c7aa9afc7359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960568353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2960568353
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3763250516
Short name T588
Test name
Test status
Simulation time 711927071 ps
CPU time 7.95 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:23 PM PDT 24
Peak memory 219540 kb
Host smart-91f3150e-73ad-4015-aa89-bc1d3320da40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3763250516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3763250516
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2666906658
Short name T366
Test name
Test status
Simulation time 19657493866 ps
CPU time 40.68 seconds
Started Apr 18 12:44:17 PM PDT 24
Finished Apr 18 12:44:59 PM PDT 24
Peak memory 216560 kb
Host smart-d43cb5b2-af1b-41a9-8f54-22e11f3b44a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666906658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2666906658
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1883511312
Short name T625
Test name
Test status
Simulation time 3161247994 ps
CPU time 10.68 seconds
Started Apr 18 12:44:12 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 216176 kb
Host smart-6ab9bf96-7cef-4eb8-9847-553a43ae8538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883511312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1883511312
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2765523682
Short name T439
Test name
Test status
Simulation time 309865844 ps
CPU time 3.22 seconds
Started Apr 18 12:44:16 PM PDT 24
Finished Apr 18 12:44:20 PM PDT 24
Peak memory 216152 kb
Host smart-60d0fdf7-6abe-4f44-827d-da229bdd1d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765523682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2765523682
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.832073152
Short name T464
Test name
Test status
Simulation time 97087870 ps
CPU time 0.94 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:16 PM PDT 24
Peak memory 205732 kb
Host smart-13d6b28a-4fa2-46d9-8484-7dc401d633ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832073152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.832073152
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3714824643
Short name T312
Test name
Test status
Simulation time 13222425403 ps
CPU time 40.68 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:45:00 PM PDT 24
Peak memory 230444 kb
Host smart-0c9ec791-405e-45ba-86d6-a95cc060fa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714824643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3714824643
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.467826012
Short name T598
Test name
Test status
Simulation time 13880882 ps
CPU time 0.73 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 205340 kb
Host smart-757b2e22-aeb6-4255-81e6-7ca1f1e90ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467826012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.467826012
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1241126755
Short name T674
Test name
Test status
Simulation time 163619684 ps
CPU time 0.77 seconds
Started Apr 18 12:44:14 PM PDT 24
Finished Apr 18 12:44:16 PM PDT 24
Peak memory 206876 kb
Host smart-2cf3694b-1cc5-41d4-80dc-bbd9b1f538c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241126755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1241126755
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2696406210
Short name T665
Test name
Test status
Simulation time 18047415027 ps
CPU time 123.49 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:46:27 PM PDT 24
Peak memory 248904 kb
Host smart-8c9272b0-a05e-4a78-9b30-5862aee17c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696406210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2696406210
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.303099931
Short name T97
Test name
Test status
Simulation time 384935694 ps
CPU time 3.14 seconds
Started Apr 18 12:44:19 PM PDT 24
Finished Apr 18 12:44:23 PM PDT 24
Peak memory 220084 kb
Host smart-9c4a4ddb-3ce5-4ff1-8b48-9b05e91355d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303099931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.303099931
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2698824191
Short name T183
Test name
Test status
Simulation time 3577704294 ps
CPU time 7.96 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 218876 kb
Host smart-e0c7bbd6-7046-4918-93a6-bab3c7858741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698824191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2698824191
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3174818355
Short name T471
Test name
Test status
Simulation time 3322662188 ps
CPU time 11.94 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:35 PM PDT 24
Peak memory 220556 kb
Host smart-c4973ddc-f626-4da6-b0c4-47c1f859a7ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3174818355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3174818355
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.908534833
Short name T340
Test name
Test status
Simulation time 154307567 ps
CPU time 0.93 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 206712 kb
Host smart-8d82163f-ea46-451e-a9aa-0c2f7bcea4d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908534833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.908534833
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3437462328
Short name T362
Test name
Test status
Simulation time 850700015 ps
CPU time 7.12 seconds
Started Apr 18 12:44:19 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 216212 kb
Host smart-1f3e075b-21b8-4b15-9ae7-40b1574d19e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437462328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3437462328
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2808156599
Short name T618
Test name
Test status
Simulation time 14697125344 ps
CPU time 19.11 seconds
Started Apr 18 12:44:19 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 216216 kb
Host smart-2b3a1178-70be-4177-8e7b-8cc389d2e033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808156599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2808156599
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3418923874
Short name T48
Test name
Test status
Simulation time 20536944 ps
CPU time 0.8 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:23 PM PDT 24
Peak memory 206256 kb
Host smart-7409c493-fd9c-45f7-a192-d06d26cbe6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418923874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3418923874
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1138811014
Short name T645
Test name
Test status
Simulation time 114140749 ps
CPU time 0.9 seconds
Started Apr 18 12:44:20 PM PDT 24
Finished Apr 18 12:44:22 PM PDT 24
Peak memory 205548 kb
Host smart-50bc60fd-48e8-47f6-b0cd-bbb5f5214517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138811014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1138811014
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2549934511
Short name T554
Test name
Test status
Simulation time 59985357 ps
CPU time 0.73 seconds
Started Apr 18 12:44:19 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 205344 kb
Host smart-03def066-a9b0-4e6f-b56c-d10adae91056
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549934511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
549934511
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1256523113
Short name T412
Test name
Test status
Simulation time 18045527 ps
CPU time 0.79 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:44:20 PM PDT 24
Peak memory 206728 kb
Host smart-b2bb638e-d8d4-4212-9eb4-66fb0e56e8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256523113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1256523113
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.409344831
Short name T458
Test name
Test status
Simulation time 1435601798 ps
CPU time 28.69 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:55 PM PDT 24
Peak memory 240820 kb
Host smart-4c04c334-1b65-4cec-adfb-925adda8e451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409344831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.409344831
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3197537415
Short name T438
Test name
Test status
Simulation time 2376193293 ps
CPU time 24.4 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:47 PM PDT 24
Peak memory 221884 kb
Host smart-ee4743ba-3b98-4152-817b-58ee64a14cbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3197537415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3197537415
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.266372581
Short name T365
Test name
Test status
Simulation time 2667781374 ps
CPU time 9.4 seconds
Started Apr 18 12:44:20 PM PDT 24
Finished Apr 18 12:44:31 PM PDT 24
Peak memory 216304 kb
Host smart-082e5405-87c3-4f9c-814d-119f4e534581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266372581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.266372581
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.185975227
Short name T7
Test name
Test status
Simulation time 1091914430 ps
CPU time 7.63 seconds
Started Apr 18 12:44:20 PM PDT 24
Finished Apr 18 12:44:29 PM PDT 24
Peak memory 216076 kb
Host smart-483ece84-8e78-40ff-a8f3-c6af6215d0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185975227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.185975227
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1315355254
Short name T656
Test name
Test status
Simulation time 278836903 ps
CPU time 1.47 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:28 PM PDT 24
Peak memory 216244 kb
Host smart-e98516fc-4eef-46d0-b212-1c6aaee9444b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315355254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1315355254
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4036838227
Short name T475
Test name
Test status
Simulation time 179636430 ps
CPU time 0.92 seconds
Started Apr 18 12:44:19 PM PDT 24
Finished Apr 18 12:44:21 PM PDT 24
Peak memory 205540 kb
Host smart-a6c8d462-b087-4772-9686-08fad4f616ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036838227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4036838227
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3124686866
Short name T427
Test name
Test status
Simulation time 44158638 ps
CPU time 0.71 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 205596 kb
Host smart-10e4ad84-ecce-4dff-82c2-3e53b465676e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124686866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
124686866
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1716772184
Short name T429
Test name
Test status
Simulation time 37043597 ps
CPU time 0.76 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:23 PM PDT 24
Peak memory 205388 kb
Host smart-581ec98b-61fd-49df-9bdd-9060d6996dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716772184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1716772184
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2737848253
Short name T637
Test name
Test status
Simulation time 1262183600 ps
CPU time 13.28 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:40 PM PDT 24
Peak memory 232624 kb
Host smart-5a94d0ca-3a7c-45c7-8567-58e8c9110787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737848253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2737848253
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.544082736
Short name T203
Test name
Test status
Simulation time 563333542 ps
CPU time 7.04 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:30 PM PDT 24
Peak memory 221772 kb
Host smart-ea0474de-a715-477c-bd57-fa8742dc453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544082736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.544082736
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2619978410
Short name T149
Test name
Test status
Simulation time 250554490 ps
CPU time 3.8 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 220236 kb
Host smart-d17dec6a-7517-4228-88ee-a074871b5348
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2619978410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2619978410
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1149691160
Short name T342
Test name
Test status
Simulation time 44710354 ps
CPU time 0.9 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 206868 kb
Host smart-e9270e48-e3bf-4fd2-a8ce-35674d44b627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149691160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1149691160
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.155500993
Short name T354
Test name
Test status
Simulation time 10460579303 ps
CPU time 17.2 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:40 PM PDT 24
Peak memory 216180 kb
Host smart-ded6b44b-913d-4b52-b125-139b25ad607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155500993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.155500993
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3314712615
Short name T666
Test name
Test status
Simulation time 2274544401 ps
CPU time 8.9 seconds
Started Apr 18 12:44:22 PM PDT 24
Finished Apr 18 12:44:33 PM PDT 24
Peak memory 216228 kb
Host smart-5ec2e682-1e67-4f36-b607-3b7aba859f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314712615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3314712615
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4237283785
Short name T486
Test name
Test status
Simulation time 501997529 ps
CPU time 3.66 seconds
Started Apr 18 12:44:23 PM PDT 24
Finished Apr 18 12:44:29 PM PDT 24
Peak memory 216196 kb
Host smart-51f4a81a-768f-4eaf-944e-f976a7f42994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237283785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4237283785
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3136309612
Short name T399
Test name
Test status
Simulation time 52841664 ps
CPU time 0.91 seconds
Started Apr 18 12:44:21 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 205712 kb
Host smart-44c3c07e-0c65-45c8-96bf-ea226c2ab7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136309612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3136309612
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.460959342
Short name T454
Test name
Test status
Simulation time 13388758 ps
CPU time 0.72 seconds
Started Apr 18 12:44:22 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 205236 kb
Host smart-b6fa85a2-6c89-48ab-9197-bb927433676b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460959342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.460959342
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1944592706
Short name T443
Test name
Test status
Simulation time 14414372 ps
CPU time 0.77 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 206828 kb
Host smart-9e427c6c-9f65-4423-83fa-57c3c416bbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944592706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1944592706
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4077177349
Short name T77
Test name
Test status
Simulation time 2086514063 ps
CPU time 14.91 seconds
Started Apr 18 12:44:24 PM PDT 24
Finished Apr 18 12:44:41 PM PDT 24
Peak memory 239920 kb
Host smart-f9f2b67e-416e-4931-a278-2d09fcf19041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077177349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4077177349
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4157359582
Short name T555
Test name
Test status
Simulation time 66311912 ps
CPU time 2.75 seconds
Started Apr 18 12:44:20 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 223580 kb
Host smart-4fecac57-a49c-4841-a6f0-0a0fc0d99aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157359582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4157359582
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3350092159
Short name T211
Test name
Test status
Simulation time 1460837493 ps
CPU time 4.53 seconds
Started Apr 18 12:44:18 PM PDT 24
Finished Apr 18 12:44:24 PM PDT 24
Peak memory 217928 kb
Host smart-fe86ae5f-dfa3-4630-811d-c6affa4ed805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350092159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3350092159
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.843258339
Short name T338
Test name
Test status
Simulation time 3959321768 ps
CPU time 14.71 seconds
Started Apr 18 12:44:22 PM PDT 24
Finished Apr 18 12:44:39 PM PDT 24
Peak memory 222352 kb
Host smart-ce0e2e8e-b7e6-4e14-b00d-67d1f0d5287d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843258339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.843258339
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.357201860
Short name T426
Test name
Test status
Simulation time 270129510 ps
CPU time 5.15 seconds
Started Apr 18 12:44:35 PM PDT 24
Finished Apr 18 12:44:41 PM PDT 24
Peak memory 221540 kb
Host smart-3e885b48-9f12-4fbf-ab52-a9dc1f1bf7d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=357201860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.357201860
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3322561226
Short name T101
Test name
Test status
Simulation time 4033641241 ps
CPU time 6.44 seconds
Started Apr 18 12:44:23 PM PDT 24
Finished Apr 18 12:44:32 PM PDT 24
Peak memory 216228 kb
Host smart-8df5681d-664e-4df8-98e4-52369976fdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322561226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3322561226
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.341925298
Short name T600
Test name
Test status
Simulation time 862448839 ps
CPU time 4.13 seconds
Started Apr 18 12:44:20 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 216096 kb
Host smart-fb019bf9-04a9-4c42-817a-029b0d065cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341925298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.341925298
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3129794647
Short name T385
Test name
Test status
Simulation time 125381763 ps
CPU time 1.71 seconds
Started Apr 18 12:44:23 PM PDT 24
Finished Apr 18 12:44:27 PM PDT 24
Peak memory 216236 kb
Host smart-918fdfa2-fac9-44a0-957b-7100cc03a04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129794647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3129794647
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1717058026
Short name T411
Test name
Test status
Simulation time 366452891 ps
CPU time 0.92 seconds
Started Apr 18 12:44:22 PM PDT 24
Finished Apr 18 12:44:25 PM PDT 24
Peak memory 205684 kb
Host smart-9584c0dd-8f17-42e7-a077-c24a4b272171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717058026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1717058026
Directory /workspace/9.spi_device_tpm_sts_read/latest
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