Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1405777	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1627062

1

T1

48

T2

12317

T3

690

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2378199	1			T1	4752		T2	16775		T3	1
values[0x0]	326086	1			T1	22		T2	1957		T3	424
values[0x1]	328554	1			T1	21		T2	2034		T3	439

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1075582	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1957257

1

T1

1589

T2

14051

T3

730

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18200	1			T1	28		T2	99		T7	193
valid_sources[0x01]	17556	1			T1	15		T2	86		T7	185
valid_sources[0x02]	15596	1			T1	19		T2	86		T7	184
valid_sources[0x03]	8895	1			T1	7		T2	83		T7	185
valid_sources[0x04]	9757	1			T1	45		T2	79		T7	174
valid_sources[0x05]	10493	1			T1	4		T2	90		T7	189
valid_sources[0x06]	9870	1			T1	27		T2	70		T7	173
valid_sources[0x07]	9943	1			T1	18		T2	69		T7	158
valid_sources[0x08]	8896	1			T1	12		T2	86		T7	208
valid_sources[0x09]	11573	1			T1	23		T2	73		T7	193
valid_sources[0x0a]	10361	1			T1	20		T2	86		T7	196
valid_sources[0x0b]	8945	1			T1	6		T2	76		T7	175
valid_sources[0x0c]	11440	1			T1	25		T2	72		T7	203
valid_sources[0x0d]	10307	1			T1	18		T2	91		T7	177
valid_sources[0x0e]	9843	1			T1	29		T2	81		T7	187
valid_sources[0x0f]	12075	1			T1	15		T2	66		T7	215
valid_sources[0x10]	12203	1			T1	16		T2	80		T7	150
valid_sources[0x11]	9321	1			T1	40		T2	71		T7	176
valid_sources[0x12]	10492	1			T1	17		T2	91		T7	175
valid_sources[0x13]	10941	1			T1	14		T2	104		T7	178
valid_sources[0x14]	9624	1			T1	28		T2	72		T7	197
valid_sources[0x15]	10495	1			T1	19		T2	72		T7	180
valid_sources[0x16]	11925	1			T1	30		T2	82		T7	240
valid_sources[0x17]	11155	1			T1	11		T2	101		T7	200
valid_sources[0x18]	12772	1			T1	5		T2	68		T7	209
valid_sources[0x19]	10294	1			T1	13		T2	62		T7	179
valid_sources[0x1a]	9324	1			T1	41		T2	87		T7	193
valid_sources[0x1b]	16295	1			T1	5		T2	75		T7	186
valid_sources[0x1c]	9563	1			T1	14		T2	75		T7	194
valid_sources[0x1d]	11159	1			T1	23		T2	106		T7	217
valid_sources[0x1e]	8604	1			T1	2		T2	72		T7	167
valid_sources[0x1f]	10059	1			T1	18		T2	77		T7	190
valid_sources[0x20]	10239	1			T1	15		T2	83		T7	177
valid_sources[0x21]	9195	1			T1	16		T2	71		T7	181
valid_sources[0x22]	10430	1			T1	16		T2	67		T7	179
valid_sources[0x23]	9747	1			T1	21		T2	77		T7	198
valid_sources[0x24]	10288	1			T1	11		T2	75		T7	181
valid_sources[0x25]	9874	1			T1	9		T2	93		T7	198
valid_sources[0x26]	34983	1			T1	15		T2	108		T7	215
valid_sources[0x27]	10471	1			T1	18		T2	85		T7	181
valid_sources[0x28]	10774	1			T1	16		T2	83		T7	188
valid_sources[0x29]	10596	1			T1	24		T2	93		T7	192
valid_sources[0x2a]	9615	1			T1	14		T2	84		T7	205
valid_sources[0x2b]	9732	1			T1	14		T2	91		T7	180
valid_sources[0x2c]	15743	1			T1	35		T2	97		T7	203
valid_sources[0x2d]	9317	1			T1	10		T2	64		T7	199
valid_sources[0x2e]	10683	1			T1	11		T2	80		T7	184
valid_sources[0x2f]	9284	1			T1	32		T2	83		T7	194
valid_sources[0x30]	9708	1			T1	25		T2	90		T7	206
valid_sources[0x31]	10503	1			T1	8		T2	88		T7	182
valid_sources[0x32]	10010	1			T1	16		T2	80		T7	184
valid_sources[0x33]	11889	1			T1	14		T2	68		T7	186
valid_sources[0x34]	11370	1			T1	4		T2	64		T7	217
valid_sources[0x35]	11527	1			T1	13		T2	101		T7	224
valid_sources[0x36]	10428	1			T1	12		T2	80		T7	188
valid_sources[0x37]	11464	1			T1	23		T2	89		T7	160
valid_sources[0x38]	9431	1			T1	14		T2	81		T7	184
valid_sources[0x39]	11171	1			T1	15		T2	63		T7	214
valid_sources[0x3a]	11899	1			T1	18		T2	58		T7	181
valid_sources[0x3b]	10309	1			T1	17		T2	83		T7	189
valid_sources[0x3c]	11266	1			T1	12		T2	82		T7	199
valid_sources[0x3d]	17629	1			T1	18		T2	85		T7	174
valid_sources[0x3e]	9242	1			T1	3		T2	70		T7	190
valid_sources[0x3f]	16463	1			T1	26		T2	96		T7	197
valid_sources[0x40]	9876	1			T1	24		T2	97		T7	196
valid_sources[0x41]	9814	1			T1	16		T2	92		T7	175
valid_sources[0x42]	10573	1			T1	10		T2	90		T7	192
valid_sources[0x43]	9801	1			T1	19		T2	95		T7	186
valid_sources[0x44]	9133	1			T1	15		T2	85		T7	170
valid_sources[0x45]	11416	1			T1	31		T2	85		T7	192
valid_sources[0x46]	19545	1			T1	30		T2	67		T7	172
valid_sources[0x47]	9234	1			T1	19		T2	101		T7	202
valid_sources[0x48]	9111	1			T1	14		T2	86		T7	207
valid_sources[0x49]	17048	1			T1	5		T2	85		T7	202
valid_sources[0x4a]	10455	1			T1	9		T2	78		T7	165
valid_sources[0x4b]	9653	1			T1	26		T2	83		T7	172
valid_sources[0x4c]	8987	1			T1	14		T2	89		T7	189
valid_sources[0x4d]	9835	1			T1	17		T2	107		T7	213
valid_sources[0x4e]	10055	1			T1	4		T2	83		T7	198
valid_sources[0x4f]	10230	1			T1	16		T2	97		T7	195
valid_sources[0x50]	27031	1			T1	6		T2	71		T7	185
valid_sources[0x51]	12024	1			T1	21		T2	89		T7	165
valid_sources[0x52]	11294	1			T1	18		T2	78		T7	185
valid_sources[0x53]	15482	1			T1	26		T2	92		T7	167
valid_sources[0x54]	12263	1			T1	14		T2	76		T7	174
valid_sources[0x55]	14040	1			T1	16		T2	76		T7	159
valid_sources[0x56]	9885	1			T1	28		T2	84		T7	200
valid_sources[0x57]	11106	1			T1	28		T2	88		T7	181
valid_sources[0x58]	14066	1			T1	19		T2	87		T7	210
valid_sources[0x59]	10077	1			T1	29		T2	72		T7	190
valid_sources[0x5a]	9601	1			T1	19		T2	84		T7	198
valid_sources[0x5b]	17096	1			T1	10		T2	61		T7	204
valid_sources[0x5c]	10326	1			T1	18		T2	71		T7	156
valid_sources[0x5d]	21844	1			T1	24		T2	88		T7	213
valid_sources[0x5e]	10192	1			T1	14		T2	82		T7	178
valid_sources[0x5f]	10040	1			T1	4		T2	77		T7	187
valid_sources[0x60]	16304	1			T1	28		T2	77		T7	189
valid_sources[0x61]	25126	1			T1	9		T2	76		T7	153
valid_sources[0x62]	10064	1			T1	23		T2	77		T7	181
valid_sources[0x63]	12501	1			T1	13		T2	89		T7	199
valid_sources[0x64]	18775	1			T1	42		T2	72		T7	197
valid_sources[0x65]	16002	1			T1	34		T2	79		T7	205
valid_sources[0x66]	10510	1			T1	38		T2	99		T7	193
valid_sources[0x67]	10598	1			T1	14		T2	81		T7	190
valid_sources[0x68]	9581	1			T1	14		T2	84		T7	177
valid_sources[0x69]	14065	1			T1	39		T2	74		T7	180
valid_sources[0x6a]	20463	1			T1	21		T2	66		T7	207
valid_sources[0x6b]	9764	1			T1	18		T2	70		T7	202
valid_sources[0x6c]	10310	1			T1	18		T2	80		T7	226
valid_sources[0x6d]	10269	1			T1	35		T2	93		T7	177
valid_sources[0x6e]	9723	1			T1	16		T2	81		T7	174
valid_sources[0x6f]	10308	1			T1	21		T2	90		T7	176
valid_sources[0x70]	10058	1			T1	38		T2	76		T7	187
valid_sources[0x71]	9813	1			T1	17		T2	77		T7	174
valid_sources[0x72]	10365	1			T1	19		T2	85		T7	201
valid_sources[0x73]	9668	1			T1	14		T2	82		T7	197
valid_sources[0x74]	9439	1			T1	23		T2	77		T7	235
valid_sources[0x75]	11463	1			T1	5		T2	82		T7	190
valid_sources[0x76]	11949	1			T1	9		T2	89		T7	224
valid_sources[0x77]	13602	1			T1	15		T2	80		T7	198
valid_sources[0x78]	11075	1			T1	15		T2	78		T7	181
valid_sources[0x79]	11376	1			T1	3		T2	95		T7	186
valid_sources[0x7a]	9257	1			T1	16		T2	73		T7	185
valid_sources[0x7b]	10708	1			T1	20		T2	82		T7	183
valid_sources[0x7c]	11724	1			T1	26		T2	73		T7	212
valid_sources[0x7d]	11184	1			T1	21		T2	89		T7	171
valid_sources[0x7e]	10245	1			T1	16		T2	75		T7	215
valid_sources[0x7f]	10797	1			T1	12		T2	81		T7	179
valid_sources[0x80]	9234	1			T1	24		T2	84		T7	197

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1032351

1

T1

42

T2

8350

T7

23503

values[0x0]

all_enables

biggest_size

299777

1

T1

4

T2

1944

T3

336

values[0x1]

all_enables

biggest_size

294934

1

T1

2

T2

2023

T3

354