Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1425041

1

T1

4747

T2

8449

T3

174

full_word

1628048

1

T1

48

T2

12317

T3

690

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3052719	1			T1	4795		T2	20766		T3	864
auto[TlIntgErrCmd]	113	1			T35	7		T36	4		T112	3
auto[TlIntgErrData]	134	1			T35	11		T36	3		T112	11
auto[TlIntgErrBoth]	123	1			T35	12		T36	3		T112	16

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381037

1

T1

4752

T2

16775

T3

1

auto[1]

672052

1

T1

43

T2

3991

T3

863

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1348302	1			T1	4710		T2	8425		T3	1
auto[TlIntgErrNone]	partial	auto[1]	76397	1			T1	37		T2	24		T3	173
auto[TlIntgErrNone]	full_word	auto[0]	1032565	1			T1	42		T2	8350		T7	23503
auto[TlIntgErrNone]	full_word	auto[1]	595455	1			T1	6		T2	3967		T3	690
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T36	2		T112	1		T136	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T35	7		T36	1		T112	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T135	1		T364	1		T365	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T36	1		T366	1		T367	2
auto[TlIntgErrData]	partial	auto[0]	66	1			T35	5		T36	1		T112	6
auto[TlIntgErrData]	partial	auto[1]	57	1			T35	6		T36	1		T112	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T112	1		T136	1		T156	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T36	1		T112	1		T362	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1			T35	5		T36	1		T112	6
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T35	7		T36	1		T112	10
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T368	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T36	1		T136	1		T135	1