Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	149506890	548327	0	0
gen_wmask[1].MaskCheckPortA_A	149506890	548327	0	0
gen_wmask[2].MaskCheckPortA_A	149506890	548327	0	0
gen_wmask[3].MaskCheckPortA_A	149506890	548327	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149506890	548327	0	0
T1	1344	143	0	0
T2	502478	3904	0	0
T3	419399	0	0	0
T4	110984	832	0	0
T5	600025	1344	0	0
T6	271369	2624	0	0
T7	1130402	832	0	0
T8	167968	832	0	0
T9	141245	832	0	0
T10	0	832	0	0
T13	9673	224	0	0
T14	0	4705	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149506890	548327	0	0
T1	1344	143	0	0
T2	502478	3904	0	0
T3	419399	0	0	0
T4	110984	832	0	0
T5	600025	1344	0	0
T6	271369	2624	0	0
T7	1130402	832	0	0
T8	167968	832	0	0
T9	141245	832	0	0
T10	0	832	0	0
T13	9673	224	0	0
T14	0	4705	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149506890	548327	0	0
T1	1344	143	0	0
T2	502478	3904	0	0
T3	419399	0	0	0
T4	110984	832	0	0
T5	600025	1344	0	0
T6	271369	2624	0	0
T7	1130402	832	0	0
T8	167968	832	0	0
T9	141245	832	0	0
T10	0	832	0	0
T13	9673	224	0	0
T14	0	4705	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149506890	548327	0	0
T1	1344	143	0	0
T2	502478	3904	0	0
T3	419399	0	0	0
T4	110984	832	0	0
T5	600025	1344	0	0
T6	271369	2624	0	0
T7	1130402	832	0	0
T8	167968	832	0	0
T9	141245	832	0	0
T10	0	832	0	0
T13	9673	224	0	0
T14	0	4705	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	112281857	412718	0	0
gen_wmask[1].MaskCheckPortA_A	112281857	412718	0	0
gen_wmask[2].MaskCheckPortA_A	112281857	412718	0	0
gen_wmask[3].MaskCheckPortA_A	112281857	412718	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	412718	0	0
T2	337559	3904	0	0
T3	283095	0	0	0
T4	57009	832	0	0
T5	480619	1344	0	0
T6	0	2624	0	0
T7	968935	832	0	0
T8	0	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	5727	40	0	0
T14	0	1581	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	412718	0	0
T2	337559	3904	0	0
T3	283095	0	0	0
T4	57009	832	0	0
T5	480619	1344	0	0
T6	0	2624	0	0
T7	968935	832	0	0
T8	0	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	5727	40	0	0
T14	0	1581	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	412718	0	0
T2	337559	3904	0	0
T3	283095	0	0	0
T4	57009	832	0	0
T5	480619	1344	0	0
T6	0	2624	0	0
T7	968935	832	0	0
T8	0	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	5727	40	0	0
T14	0	1581	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	412718	0	0
T2	337559	3904	0	0
T3	283095	0	0	0
T4	57009	832	0	0
T5	480619	1344	0	0
T6	0	2624	0	0
T7	968935	832	0	0
T8	0	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T13	5727	40	0	0
T14	0	1581	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	37225033	135609	0	0
gen_wmask[1].MaskCheckPortA_A	37225033	135609	0	0
gen_wmask[2].MaskCheckPortA_A	37225033	135609	0	0
gen_wmask[3].MaskCheckPortA_A	37225033	135609	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	135609	0	0
T1	1344	143	0	0
T2	164919	0	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	184	0	0
T14	0	3124	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	135609	0	0
T1	1344	143	0	0
T2	164919	0	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	184	0	0
T14	0	3124	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	135609	0	0
T1	1344	143	0	0
T2	164919	0	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	184	0	0
T14	0	3124	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	135609	0	0
T1	1344	143	0	0
T2	164919	0	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	184	0	0
T14	0	3124	0	0
T19	0	477	0	0
T20	0	642	0	0
T49	0	76	0	0
T50	0	188	0	0
T51	0	3227	0	0
T52	0	1077	0	0
T53	0	242	0	0