Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	98.94	91.20		91.67	95.48	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.37	60.00			73.08	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.37	60.00			73.08	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.36	85.00	45.45			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.29	94.37	60.00			73.08	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.83	94.37	68.33			84.62	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Not Covered
1	1	Covered	T2,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T7,T4
0	0	Covered	T2,T7,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37225033	5313720	0	0
DepthKnown_A	37225033	23684237	0	0
RvalidKnown_A	37225033	23684237	0	0
WreadyKnown_A	37225033	23684237	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37225033	5313720	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	5313720	0	0
T2	164919	63913	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	13786	0	0
T6	271369	43974	0	0
T7	161467	0	0	0
T8	167968	59224	0	0
T9	141245	914	0	0
T10	0	10751	0	0
T11	0	40422	0	0
T12	0	3972	0	0
T13	3946	0	0	0
T14	216861	0	0	0
T43	0	2162	0	0
T82	0	19091	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	5313720	0	0
T2	164919	63913	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	13786	0	0
T6	271369	43974	0	0
T7	161467	0	0	0
T8	167968	59224	0	0
T9	141245	914	0	0
T10	0	10751	0	0
T11	0	40422	0	0
T12	0	3972	0	0
T13	3946	0	0	0
T14	216861	0	0	0
T43	0	2162	0	0
T82	0	19091	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Not Covered
1	1	Covered	T2,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T4
1	0	1	Covered	T2,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T5,T6
1	1	0	Not Covered
1	1	1	Covered	T2,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T7,T4
0	0	Covered	T2,T7,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37225033	5594743	0	0
DepthKnown_A	37225033	23684237	0	0
RvalidKnown_A	37225033	23684237	0	0
WreadyKnown_A	37225033	23684237	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37225033	5594743	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	5594743	0	0
T2	164919	67110	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	14689	0	0
T6	271369	45863	0	0
T7	161467	0	0	0
T8	167968	63664	0	0
T9	141245	1038	0	0
T10	0	11723	0	0
T11	0	41712	0	0
T12	0	4096	0	0
T13	3946	0	0	0
T14	216861	0	0	0
T43	0	2290	0	0
T82	0	21373	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	5594743	0	0
T2	164919	67110	0	0
T3	136304	0	0	0
T4	53975	0	0	0
T5	119406	14689	0	0
T6	271369	45863	0	0
T7	161467	0	0	0
T8	167968	63664	0	0
T9	141245	1038	0	0
T10	0	11723	0	0
T11	0	41712	0	0
T12	0	4096	0	0
T13	3946	0	0	0
T14	216861	0	0	0
T43	0	2290	0	0
T82	0	21373	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T7,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T7,T4
0	0	Covered	T2,T7,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37225033	0	0	0
DepthKnown_A	37225033	23684237	0	0
RvalidKnown_A	37225033	23684237	0	0
WreadyKnown_A	37225033	23684237	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37225033	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	23684237	0	0
T2	164919	164470	0	0
T3	136304	0	0	0
T4	53975	53660	0	0
T5	119406	118985	0	0
T6	271369	271263	0	0
T7	161467	160416	0	0
T8	167968	167568	0	0
T9	141245	140784	0	0
T10	0	12043	0	0
T11	0	72578	0	0
T12	0	68528	0	0
T13	3946	0	0	0
T14	216861	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T13

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Not Covered
1	1	Covered	T13,T14,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T13,T14,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T14,T19
1	0	1	Covered	T13,T14,T19
1	1	0	Not Covered
1	1	1	Covered	T13,T14,T19

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T19

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T14,T19

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T19
1	0	Covered	T13,T14,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T13
0	0	Covered	T1,T3,T13

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37225033	1888508	0	0
DepthKnown_A	37225033	12986952	0	0
RvalidKnown_A	37225033	12986952	0	0
WreadyKnown_A	37225033	12986952	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37225033	1888508	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	1888508	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T10	12043	0	0	0
T11	73076	0	0	0
T13	3946	1252	0	0
T14	216861	49018	0	0
T19	19208	5465	0	0
T20	26184	13268	0	0
T49	0	975	0	0
T50	0	447	0	0
T51	0	43938	0	0
T52	0	19968	0	0
T53	0	1204	0	0
T54	0	81478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	12986952	0	0
T1	1344	1344	0	0
T2	164919	0	0	0
T3	136304	128984	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	3936	0	0
T14	0	210944	0	0
T19	0	16792	0	0
T20	0	24432	0	0
T21	0	26744	0	0
T22	0	99632	0	0
T23	0	138352	0	0
T49	0	1976	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	12986952	0	0
T1	1344	1344	0	0
T2	164919	0	0	0
T3	136304	128984	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	3936	0	0
T14	0	210944	0	0
T19	0	16792	0	0
T20	0	24432	0	0
T21	0	26744	0	0
T22	0	99632	0	0
T23	0	138352	0	0
T49	0	1976	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	12986952	0	0
T1	1344	1344	0	0
T2	164919	0	0	0
T3	136304	128984	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	3936	0	0
T14	0	210944	0	0
T19	0	16792	0	0
T20	0	24432	0	0
T21	0	26744	0	0
T22	0	99632	0	0
T23	0	138352	0	0
T49	0	1976	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	1888508	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T10	12043	0	0	0
T11	73076	0	0	0
T13	3946	1252	0	0
T14	216861	49018	0	0
T19	19208	5465	0	0
T20	26184	13268	0	0
T49	0	975	0	0
T50	0	447	0	0
T51	0	43938	0	0
T52	0	19968	0	0
T53	0	1204	0	0
T54	0	81478	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T13

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T13
1	0	Not Covered
1	1	Covered	T13,T14,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T13,T14,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T13,T14,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T13,T14,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T13,T14,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T13
0	0	Covered	T1,T3,T13

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T13,T14,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	37225033	60718	0	0
DepthKnown_A	37225033	12986952	0	0
RvalidKnown_A	37225033	12986952	0	0
WreadyKnown_A	37225033	12986952	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	37225033	60718	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	60718	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T10	12043	0	0	0
T11	73076	0	0	0
T13	3946	40	0	0
T14	216861	1581	0	0
T19	19208	173	0	0
T20	26184	423	0	0
T49	0	31	0	0
T50	0	15	0	0
T51	0	1405	0	0
T52	0	641	0	0
T53	0	38	0	0
T54	0	2623	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	12986952	0	0
T1	1344	1344	0	0
T2	164919	0	0	0
T3	136304	128984	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	3936	0	0
T14	0	210944	0	0
T19	0	16792	0	0
T20	0	24432	0	0
T21	0	26744	0	0
T22	0	99632	0	0
T23	0	138352	0	0
T49	0	1976	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	12986952	0	0
T1	1344	1344	0	0
T2	164919	0	0	0
T3	136304	128984	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	3936	0	0
T14	0	210944	0	0
T19	0	16792	0	0
T20	0	24432	0	0
T21	0	26744	0	0
T22	0	99632	0	0
T23	0	138352	0	0
T49	0	1976	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	12986952	0	0
T1	1344	1344	0	0
T2	164919	0	0	0
T3	136304	128984	0	0
T4	53975	0	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T7	161467	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T13	3946	3936	0	0
T14	0	210944	0	0
T19	0	16792	0	0
T20	0	24432	0	0
T21	0	26744	0	0
T22	0	99632	0	0
T23	0	138352	0	0
T49	0	1976	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	37225033	60718	0	0
T5	119406	0	0	0
T6	271369	0	0	0
T8	167968	0	0	0
T9	141245	0	0	0
T10	12043	0	0	0
T11	73076	0	0	0
T13	3946	40	0	0
T14	216861	1581	0	0
T19	19208	173	0	0
T20	26184	423	0	0
T49	0	31	0	0
T50	0	15	0	0
T51	0	1405	0	0
T52	0	641	0	0
T53	0	38	0	0
T54	0	2623	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T7,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T9,T11
1	1	0	Not Covered
1	1	1	Covered	T2,T7,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T7,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T7,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112281857	476686	0	0
DepthKnown_A	112281857	112221129	0	0
RvalidKnown_A	112281857	112221129	0	0
WreadyKnown_A	112281857	112221129	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112281857	476686	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	476686	0	0
T2	337559	3904	0	0
T3	283095	0	0	0
T4	57009	832	0	0
T5	480619	1344	0	0
T6	0	2624	0	0
T7	968935	832	0	0
T8	0	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T11	0	2502	0	0
T12	0	832	0	0
T13	5727	0	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	476686	0	0
T2	337559	3904	0	0
T3	283095	0	0	0
T4	57009	832	0	0
T5	480619	1344	0	0
T6	0	2624	0	0
T7	968935	832	0	0
T8	0	832	0	0
T9	0	832	0	0
T10	0	832	0	0
T11	0	2502	0	0
T12	0	832	0	0
T13	5727	0	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112281857	0	0	0
DepthKnown_A	112281857	112221129	0	0
RvalidKnown_A	112281857	112221129	0	0
WreadyKnown_A	112281857	112221129	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112281857	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112281857	0	0	0
DepthKnown_A	112281857	112221129	0	0
RvalidKnown_A	112281857	112221129	0	0
WreadyKnown_A	112281857	112221129	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112281857	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T13,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T14,T19,T51
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T14

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T13,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112281857	79852	0	0
DepthKnown_A	112281857	112221129	0	0
RvalidKnown_A	112281857	112221129	0	0
WreadyKnown_A	112281857	112221129	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112281857	79852	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	79852	0	0
T1	10397	37	0	0
T2	337559	0	0	0
T3	283095	0	0	0
T4	57009	0	0	0
T7	968935	0	0	0
T13	5727	48	0	0
T14	0	3598	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0
T19	0	580	0	0
T20	0	170	0	0
T49	0	19	0	0
T50	0	48	0	0
T51	0	3801	0	0
T52	0	278	0	0
T53	0	178	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	112221129	0	0
T1	10397	10297	0	0
T2	337559	337466	0	0
T3	283095	283020	0	0
T4	57009	56924	0	0
T7	968935	968837	0	0
T13	5727	5671	0	0
T15	731	669	0	0
T16	8288	5964	0	0
T17	2930	2690	0	0
T18	791	709	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112281857	79852	0	0
T1	10397	37	0	0
T2	337559	0	0	0
T3	283095	0	0	0
T4	57009	0	0	0
T7	968935	0	0	0
T13	5727	48	0	0
T14	0	3598	0	0
T15	731	0	0	0
T16	8288	0	0	0
T17	2930	0	0	0
T18	791	0	0	0
T19	0	580	0	0
T20	0	170	0	0
T49	0	19	0	0
T50	0	48	0	0
T51	0	3801	0	0
T52	0	278	0	0
T53	0	178	0	0