Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
3123 |
0 |
0 |
T35 |
28985 |
3 |
0 |
0 |
T36 |
34643 |
2 |
0 |
0 |
T37 |
3849 |
6 |
0 |
0 |
T110 |
8265 |
10 |
0 |
0 |
T111 |
4181 |
189 |
0 |
0 |
T112 |
91275 |
6 |
0 |
0 |
T117 |
3235 |
99 |
0 |
0 |
T118 |
2983 |
139 |
0 |
0 |
T134 |
2207 |
10 |
0 |
0 |
T136 |
19633 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2322 |
0 |
0 |
T36 |
34643 |
28 |
0 |
0 |
T39 |
74482 |
494 |
0 |
0 |
T112 |
91275 |
53 |
0 |
0 |
T128 |
14251 |
27 |
0 |
0 |
T130 |
6885 |
2 |
0 |
0 |
T139 |
8584 |
4 |
0 |
0 |
T152 |
19617 |
107 |
0 |
0 |
T156 |
72321 |
74 |
0 |
0 |
T157 |
10520 |
9 |
0 |
0 |
T158 |
13234 |
37 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2273 |
0 |
0 |
T36 |
34643 |
40 |
0 |
0 |
T39 |
74482 |
495 |
0 |
0 |
T112 |
91275 |
48 |
0 |
0 |
T128 |
14251 |
35 |
0 |
0 |
T139 |
8584 |
4 |
0 |
0 |
T152 |
19617 |
29 |
0 |
0 |
T156 |
72321 |
86 |
0 |
0 |
T157 |
10520 |
14 |
0 |
0 |
T158 |
13234 |
42 |
0 |
0 |
T159 |
10559 |
23 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2656 |
0 |
0 |
T36 |
34643 |
45 |
0 |
0 |
T39 |
74482 |
496 |
0 |
0 |
T112 |
91275 |
141 |
0 |
0 |
T128 |
14251 |
33 |
0 |
0 |
T139 |
8584 |
9 |
0 |
0 |
T152 |
19617 |
75 |
0 |
0 |
T156 |
72321 |
166 |
0 |
0 |
T157 |
10520 |
11 |
0 |
0 |
T158 |
13234 |
24 |
0 |
0 |
T159 |
10559 |
8 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
11961 |
0 |
0 |
T36 |
34643 |
747 |
0 |
0 |
T39 |
74482 |
534 |
0 |
0 |
T112 |
91275 |
987 |
0 |
0 |
T128 |
14251 |
152 |
0 |
0 |
T139 |
8584 |
230 |
0 |
0 |
T152 |
19617 |
122 |
0 |
0 |
T156 |
72321 |
1683 |
0 |
0 |
T157 |
10520 |
140 |
0 |
0 |
T158 |
13234 |
25 |
0 |
0 |
T159 |
10559 |
245 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
11009 |
0 |
0 |
T36 |
34643 |
668 |
0 |
0 |
T39 |
74482 |
487 |
0 |
0 |
T112 |
91275 |
1262 |
0 |
0 |
T123 |
22692 |
7 |
0 |
0 |
T128 |
14251 |
23 |
0 |
0 |
T139 |
8584 |
128 |
0 |
0 |
T152 |
19617 |
89 |
0 |
0 |
T154 |
4112 |
2 |
0 |
0 |
T156 |
72321 |
1488 |
0 |
0 |
T157 |
10520 |
8 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
10556 |
0 |
0 |
T36 |
34643 |
693 |
0 |
0 |
T39 |
74482 |
538 |
0 |
0 |
T112 |
91275 |
1163 |
0 |
0 |
T128 |
14251 |
285 |
0 |
0 |
T139 |
8584 |
9 |
0 |
0 |
T152 |
19617 |
79 |
0 |
0 |
T154 |
4112 |
3 |
0 |
0 |
T156 |
72321 |
1094 |
0 |
0 |
T157 |
10520 |
259 |
0 |
0 |
T158 |
13234 |
57 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
11378 |
0 |
0 |
T36 |
34643 |
784 |
0 |
0 |
T39 |
74482 |
505 |
0 |
0 |
T112 |
91275 |
1223 |
0 |
0 |
T128 |
14251 |
114 |
0 |
0 |
T139 |
8584 |
3 |
0 |
0 |
T152 |
19617 |
46 |
0 |
0 |
T154 |
4112 |
80 |
0 |
0 |
T156 |
72321 |
1466 |
0 |
0 |
T157 |
10520 |
12 |
0 |
0 |
T158 |
13234 |
37 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
11846 |
0 |
0 |
T36 |
34643 |
722 |
0 |
0 |
T39 |
74482 |
475 |
0 |
0 |
T112 |
91275 |
795 |
0 |
0 |
T128 |
14251 |
418 |
0 |
0 |
T139 |
8584 |
214 |
0 |
0 |
T152 |
19617 |
57 |
0 |
0 |
T154 |
4112 |
92 |
0 |
0 |
T156 |
72321 |
1488 |
0 |
0 |
T157 |
10520 |
126 |
0 |
0 |
T158 |
13234 |
80 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
10456 |
0 |
0 |
T36 |
34643 |
585 |
0 |
0 |
T39 |
74482 |
468 |
0 |
0 |
T112 |
91275 |
1188 |
0 |
0 |
T128 |
14251 |
165 |
0 |
0 |
T139 |
8584 |
204 |
0 |
0 |
T152 |
19617 |
43 |
0 |
0 |
T154 |
4112 |
70 |
0 |
0 |
T156 |
72321 |
1333 |
0 |
0 |
T157 |
10520 |
121 |
0 |
0 |
T158 |
13234 |
4 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
10720 |
0 |
0 |
T36 |
34643 |
675 |
0 |
0 |
T39 |
74482 |
510 |
0 |
0 |
T112 |
91275 |
860 |
0 |
0 |
T128 |
14251 |
380 |
0 |
0 |
T130 |
6885 |
4 |
0 |
0 |
T139 |
8584 |
123 |
0 |
0 |
T152 |
19617 |
46 |
0 |
0 |
T154 |
4112 |
5 |
0 |
0 |
T156 |
72321 |
1337 |
0 |
0 |
T157 |
10520 |
129 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
10936 |
0 |
0 |
T36 |
34643 |
760 |
0 |
0 |
T39 |
74482 |
480 |
0 |
0 |
T112 |
91275 |
1057 |
0 |
0 |
T128 |
14251 |
25 |
0 |
0 |
T139 |
8584 |
209 |
0 |
0 |
T152 |
19617 |
64 |
0 |
0 |
T156 |
72321 |
1404 |
0 |
0 |
T157 |
10520 |
268 |
0 |
0 |
T158 |
13234 |
80 |
0 |
0 |
T159 |
10559 |
162 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5771 |
0 |
0 |
T36 |
34643 |
160 |
0 |
0 |
T39 |
74482 |
468 |
0 |
0 |
T112 |
91275 |
422 |
0 |
0 |
T124 |
11047 |
6 |
0 |
0 |
T128 |
14251 |
124 |
0 |
0 |
T139 |
8584 |
66 |
0 |
0 |
T152 |
19617 |
44 |
0 |
0 |
T154 |
4112 |
30 |
0 |
0 |
T156 |
72321 |
568 |
0 |
0 |
T157 |
10520 |
51 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5490 |
0 |
0 |
T36 |
34643 |
279 |
0 |
0 |
T39 |
74482 |
469 |
0 |
0 |
T112 |
91275 |
509 |
0 |
0 |
T128 |
14251 |
21 |
0 |
0 |
T139 |
8584 |
48 |
0 |
0 |
T152 |
19617 |
52 |
0 |
0 |
T156 |
72321 |
697 |
0 |
0 |
T157 |
10520 |
11 |
0 |
0 |
T158 |
13234 |
30 |
0 |
0 |
T159 |
10559 |
67 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5524 |
0 |
0 |
T36 |
34643 |
242 |
0 |
0 |
T39 |
74482 |
452 |
0 |
0 |
T112 |
91275 |
358 |
0 |
0 |
T128 |
14251 |
99 |
0 |
0 |
T139 |
8584 |
2 |
0 |
0 |
T152 |
19617 |
35 |
0 |
0 |
T154 |
4112 |
3 |
0 |
0 |
T156 |
72321 |
476 |
0 |
0 |
T157 |
10520 |
62 |
0 |
0 |
T158 |
13234 |
42 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5493 |
0 |
0 |
T36 |
34643 |
317 |
0 |
0 |
T39 |
74482 |
481 |
0 |
0 |
T112 |
91275 |
565 |
0 |
0 |
T124 |
11047 |
4 |
0 |
0 |
T128 |
14251 |
74 |
0 |
0 |
T139 |
8584 |
8 |
0 |
0 |
T152 |
19617 |
57 |
0 |
0 |
T154 |
4112 |
1 |
0 |
0 |
T156 |
72321 |
503 |
0 |
0 |
T157 |
10520 |
95 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5438 |
0 |
0 |
T36 |
34643 |
245 |
0 |
0 |
T39 |
74482 |
463 |
0 |
0 |
T112 |
91275 |
347 |
0 |
0 |
T128 |
14251 |
78 |
0 |
0 |
T139 |
8584 |
106 |
0 |
0 |
T152 |
19617 |
49 |
0 |
0 |
T154 |
4112 |
35 |
0 |
0 |
T156 |
72321 |
483 |
0 |
0 |
T157 |
10520 |
76 |
0 |
0 |
T158 |
13234 |
55 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5318 |
0 |
0 |
T36 |
34643 |
374 |
0 |
0 |
T39 |
74482 |
520 |
0 |
0 |
T112 |
91275 |
504 |
0 |
0 |
T128 |
14251 |
72 |
0 |
0 |
T139 |
8584 |
10 |
0 |
0 |
T152 |
19617 |
76 |
0 |
0 |
T154 |
4112 |
19 |
0 |
0 |
T156 |
72321 |
399 |
0 |
0 |
T157 |
10520 |
61 |
0 |
0 |
T158 |
13234 |
13 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5590 |
0 |
0 |
T36 |
34643 |
52 |
0 |
0 |
T39 |
74482 |
488 |
0 |
0 |
T112 |
91275 |
343 |
0 |
0 |
T128 |
14251 |
80 |
0 |
0 |
T139 |
8584 |
114 |
0 |
0 |
T152 |
19617 |
45 |
0 |
0 |
T154 |
4112 |
37 |
0 |
0 |
T156 |
72321 |
592 |
0 |
0 |
T157 |
10520 |
54 |
0 |
0 |
T158 |
13234 |
33 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5317 |
0 |
0 |
T36 |
34643 |
276 |
0 |
0 |
T39 |
74482 |
540 |
0 |
0 |
T112 |
91275 |
439 |
0 |
0 |
T128 |
14251 |
140 |
0 |
0 |
T139 |
8584 |
8 |
0 |
0 |
T152 |
19617 |
39 |
0 |
0 |
T156 |
72321 |
407 |
0 |
0 |
T157 |
10520 |
76 |
0 |
0 |
T158 |
13234 |
30 |
0 |
0 |
T159 |
10559 |
115 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5494 |
0 |
0 |
T36 |
34643 |
190 |
0 |
0 |
T39 |
74482 |
500 |
0 |
0 |
T112 |
91275 |
432 |
0 |
0 |
T128 |
14251 |
116 |
0 |
0 |
T139 |
8584 |
6 |
0 |
0 |
T152 |
19617 |
58 |
0 |
0 |
T154 |
4112 |
12 |
0 |
0 |
T156 |
72321 |
649 |
0 |
0 |
T157 |
10520 |
67 |
0 |
0 |
T158 |
13234 |
39 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5816 |
0 |
0 |
T36 |
34643 |
257 |
0 |
0 |
T39 |
74482 |
467 |
0 |
0 |
T112 |
91275 |
514 |
0 |
0 |
T128 |
14251 |
33 |
0 |
0 |
T139 |
8584 |
108 |
0 |
0 |
T152 |
19617 |
55 |
0 |
0 |
T154 |
4112 |
10 |
0 |
0 |
T156 |
72321 |
503 |
0 |
0 |
T157 |
10520 |
102 |
0 |
0 |
T158 |
13234 |
80 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5462 |
0 |
0 |
T36 |
34643 |
250 |
0 |
0 |
T39 |
74482 |
489 |
0 |
0 |
T112 |
91275 |
403 |
0 |
0 |
T128 |
14251 |
114 |
0 |
0 |
T139 |
8584 |
63 |
0 |
0 |
T152 |
19617 |
50 |
0 |
0 |
T154 |
4112 |
3 |
0 |
0 |
T156 |
72321 |
520 |
0 |
0 |
T157 |
10520 |
23 |
0 |
0 |
T158 |
13234 |
24 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5394 |
0 |
0 |
T36 |
34643 |
303 |
0 |
0 |
T39 |
74482 |
505 |
0 |
0 |
T112 |
91275 |
356 |
0 |
0 |
T128 |
14251 |
28 |
0 |
0 |
T139 |
8584 |
53 |
0 |
0 |
T152 |
19617 |
112 |
0 |
0 |
T156 |
72321 |
489 |
0 |
0 |
T157 |
10520 |
52 |
0 |
0 |
T158 |
13234 |
61 |
0 |
0 |
T159 |
10559 |
95 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5302 |
0 |
0 |
T36 |
34643 |
162 |
0 |
0 |
T39 |
74482 |
417 |
0 |
0 |
T112 |
91275 |
465 |
0 |
0 |
T124 |
11047 |
4 |
0 |
0 |
T128 |
14251 |
77 |
0 |
0 |
T139 |
8584 |
3 |
0 |
0 |
T152 |
19617 |
26 |
0 |
0 |
T154 |
4112 |
5 |
0 |
0 |
T156 |
72321 |
477 |
0 |
0 |
T157 |
10520 |
120 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5321 |
0 |
0 |
T36 |
34643 |
230 |
0 |
0 |
T39 |
74482 |
520 |
0 |
0 |
T112 |
91275 |
388 |
0 |
0 |
T128 |
14251 |
105 |
0 |
0 |
T152 |
19617 |
21 |
0 |
0 |
T154 |
4112 |
21 |
0 |
0 |
T156 |
72321 |
515 |
0 |
0 |
T157 |
10520 |
89 |
0 |
0 |
T158 |
13234 |
22 |
0 |
0 |
T159 |
10559 |
89 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5674 |
0 |
0 |
T36 |
34643 |
282 |
0 |
0 |
T39 |
74482 |
465 |
0 |
0 |
T112 |
91275 |
416 |
0 |
0 |
T128 |
14251 |
81 |
0 |
0 |
T139 |
8584 |
9 |
0 |
0 |
T152 |
19617 |
64 |
0 |
0 |
T154 |
4112 |
34 |
0 |
0 |
T156 |
72321 |
422 |
0 |
0 |
T157 |
10520 |
115 |
0 |
0 |
T158 |
13234 |
87 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5577 |
0 |
0 |
T36 |
34643 |
388 |
0 |
0 |
T39 |
74482 |
510 |
0 |
0 |
T112 |
91275 |
382 |
0 |
0 |
T128 |
14251 |
115 |
0 |
0 |
T139 |
8584 |
111 |
0 |
0 |
T152 |
19617 |
63 |
0 |
0 |
T154 |
4112 |
29 |
0 |
0 |
T156 |
72321 |
546 |
0 |
0 |
T157 |
10520 |
26 |
0 |
0 |
T158 |
13234 |
68 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5436 |
0 |
0 |
T36 |
34643 |
460 |
0 |
0 |
T39 |
74482 |
487 |
0 |
0 |
T112 |
91275 |
357 |
0 |
0 |
T128 |
14251 |
74 |
0 |
0 |
T139 |
8584 |
51 |
0 |
0 |
T152 |
19617 |
82 |
0 |
0 |
T154 |
4112 |
46 |
0 |
0 |
T156 |
72321 |
560 |
0 |
0 |
T157 |
10520 |
45 |
0 |
0 |
T158 |
13234 |
19 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
6286 |
0 |
0 |
T36 |
34643 |
308 |
0 |
0 |
T39 |
74482 |
507 |
0 |
0 |
T112 |
91275 |
500 |
0 |
0 |
T128 |
14251 |
187 |
0 |
0 |
T139 |
8584 |
48 |
0 |
0 |
T152 |
19617 |
51 |
0 |
0 |
T154 |
4112 |
7 |
0 |
0 |
T156 |
72321 |
353 |
0 |
0 |
T157 |
10520 |
77 |
0 |
0 |
T158 |
13234 |
70 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5149 |
0 |
0 |
T36 |
34643 |
142 |
0 |
0 |
T39 |
74482 |
471 |
0 |
0 |
T112 |
91275 |
408 |
0 |
0 |
T128 |
14251 |
194 |
0 |
0 |
T139 |
8584 |
4 |
0 |
0 |
T152 |
19617 |
107 |
0 |
0 |
T154 |
4112 |
36 |
0 |
0 |
T156 |
72321 |
539 |
0 |
0 |
T157 |
10520 |
53 |
0 |
0 |
T158 |
13234 |
20 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5351 |
0 |
0 |
T36 |
34643 |
389 |
0 |
0 |
T39 |
74482 |
551 |
0 |
0 |
T112 |
91275 |
452 |
0 |
0 |
T128 |
14251 |
16 |
0 |
0 |
T139 |
8584 |
83 |
0 |
0 |
T152 |
19617 |
52 |
0 |
0 |
T154 |
4112 |
7 |
0 |
0 |
T156 |
72321 |
283 |
0 |
0 |
T157 |
10520 |
118 |
0 |
0 |
T158 |
13234 |
48 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5619 |
0 |
0 |
T36 |
34643 |
327 |
0 |
0 |
T39 |
74482 |
547 |
0 |
0 |
T112 |
91275 |
550 |
0 |
0 |
T128 |
14251 |
57 |
0 |
0 |
T139 |
8584 |
73 |
0 |
0 |
T152 |
19617 |
34 |
0 |
0 |
T154 |
4112 |
18 |
0 |
0 |
T156 |
72321 |
248 |
0 |
0 |
T157 |
10520 |
12 |
0 |
0 |
T158 |
13234 |
45 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5632 |
0 |
0 |
T36 |
34643 |
330 |
0 |
0 |
T39 |
74482 |
460 |
0 |
0 |
T112 |
91275 |
424 |
0 |
0 |
T128 |
14251 |
70 |
0 |
0 |
T139 |
8584 |
91 |
0 |
0 |
T152 |
19617 |
60 |
0 |
0 |
T154 |
4112 |
8 |
0 |
0 |
T156 |
72321 |
453 |
0 |
0 |
T157 |
10520 |
93 |
0 |
0 |
T158 |
13234 |
27 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5379 |
0 |
0 |
T36 |
34643 |
287 |
0 |
0 |
T39 |
74482 |
454 |
0 |
0 |
T112 |
91275 |
502 |
0 |
0 |
T128 |
14251 |
100 |
0 |
0 |
T139 |
8584 |
36 |
0 |
0 |
T152 |
19617 |
94 |
0 |
0 |
T154 |
4112 |
4 |
0 |
0 |
T156 |
72321 |
517 |
0 |
0 |
T157 |
10520 |
59 |
0 |
0 |
T158 |
13234 |
34 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
5401 |
0 |
0 |
T36 |
34643 |
258 |
0 |
0 |
T39 |
74482 |
496 |
0 |
0 |
T112 |
91275 |
352 |
0 |
0 |
T128 |
14251 |
92 |
0 |
0 |
T139 |
8584 |
45 |
0 |
0 |
T152 |
19617 |
69 |
0 |
0 |
T156 |
72321 |
607 |
0 |
0 |
T157 |
10520 |
15 |
0 |
0 |
T158 |
13234 |
50 |
0 |
0 |
T159 |
10559 |
95 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2439 |
0 |
0 |
T36 |
34643 |
76 |
0 |
0 |
T39 |
74482 |
474 |
0 |
0 |
T112 |
91275 |
93 |
0 |
0 |
T128 |
14251 |
18 |
0 |
0 |
T139 |
8584 |
9 |
0 |
0 |
T152 |
19617 |
60 |
0 |
0 |
T156 |
72321 |
102 |
0 |
0 |
T157 |
10520 |
17 |
0 |
0 |
T158 |
13234 |
7 |
0 |
0 |
T159 |
10559 |
34 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2463 |
0 |
0 |
T36 |
34643 |
62 |
0 |
0 |
T39 |
74482 |
514 |
0 |
0 |
T112 |
91275 |
122 |
0 |
0 |
T128 |
14251 |
17 |
0 |
0 |
T139 |
8584 |
17 |
0 |
0 |
T152 |
19617 |
56 |
0 |
0 |
T154 |
4112 |
9 |
0 |
0 |
T156 |
72321 |
100 |
0 |
0 |
T157 |
10520 |
14 |
0 |
0 |
T158 |
13234 |
16 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2461 |
0 |
0 |
T36 |
34643 |
44 |
0 |
0 |
T39 |
74482 |
460 |
0 |
0 |
T112 |
91275 |
79 |
0 |
0 |
T128 |
14251 |
26 |
0 |
0 |
T139 |
8584 |
25 |
0 |
0 |
T152 |
19617 |
77 |
0 |
0 |
T154 |
4112 |
8 |
0 |
0 |
T156 |
72321 |
100 |
0 |
0 |
T157 |
10520 |
17 |
0 |
0 |
T158 |
13234 |
9 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2736 |
0 |
0 |
T36 |
34643 |
80 |
0 |
0 |
T39 |
74482 |
442 |
0 |
0 |
T112 |
91275 |
117 |
0 |
0 |
T128 |
14251 |
46 |
0 |
0 |
T139 |
8584 |
7 |
0 |
0 |
T152 |
19617 |
52 |
0 |
0 |
T156 |
72321 |
129 |
0 |
0 |
T157 |
10520 |
12 |
0 |
0 |
T158 |
13234 |
25 |
0 |
0 |
T159 |
10559 |
22 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
3238 |
0 |
0 |
T36 |
34643 |
101 |
0 |
0 |
T39 |
74482 |
541 |
0 |
0 |
T112 |
91275 |
183 |
0 |
0 |
T128 |
14251 |
60 |
0 |
0 |
T139 |
8584 |
17 |
0 |
0 |
T152 |
19617 |
34 |
0 |
0 |
T154 |
4112 |
8 |
0 |
0 |
T156 |
72321 |
252 |
0 |
0 |
T157 |
10520 |
25 |
0 |
0 |
T158 |
13234 |
48 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
4417 |
0 |
0 |
T36 |
0 |
143 |
0 |
0 |
T39 |
0 |
507 |
0 |
0 |
T70 |
451729 |
0 |
0 |
0 |
T112 |
0 |
290 |
0 |
0 |
T128 |
0 |
51 |
0 |
0 |
T139 |
0 |
69 |
0 |
0 |
T152 |
0 |
38 |
0 |
0 |
T160 |
4577 |
60 |
0 |
0 |
T161 |
0 |
46 |
0 |
0 |
T162 |
0 |
51 |
0 |
0 |
T163 |
0 |
28 |
0 |
0 |
T164 |
970 |
0 |
0 |
0 |
T165 |
440145 |
0 |
0 |
0 |
T166 |
4478 |
0 |
0 |
0 |
T167 |
219738 |
0 |
0 |
0 |
T168 |
3751 |
0 |
0 |
0 |
T169 |
8607 |
0 |
0 |
0 |
T170 |
4818 |
0 |
0 |
0 |
T171 |
42908 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2576 |
0 |
0 |
T36 |
34643 |
86 |
0 |
0 |
T39 |
74482 |
535 |
0 |
0 |
T112 |
91275 |
129 |
0 |
0 |
T128 |
14251 |
18 |
0 |
0 |
T139 |
8584 |
16 |
0 |
0 |
T152 |
19617 |
49 |
0 |
0 |
T154 |
4112 |
3 |
0 |
0 |
T156 |
72321 |
107 |
0 |
0 |
T157 |
10520 |
17 |
0 |
0 |
T158 |
13234 |
58 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2478 |
0 |
0 |
T36 |
34643 |
43 |
0 |
0 |
T39 |
74482 |
554 |
0 |
0 |
T112 |
91275 |
122 |
0 |
0 |
T128 |
14251 |
13 |
0 |
0 |
T139 |
8584 |
14 |
0 |
0 |
T152 |
19617 |
25 |
0 |
0 |
T154 |
4112 |
6 |
0 |
0 |
T156 |
72321 |
111 |
0 |
0 |
T157 |
10520 |
16 |
0 |
0 |
T158 |
13234 |
8 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2303 |
0 |
0 |
T36 |
34643 |
53 |
0 |
0 |
T39 |
74482 |
513 |
0 |
0 |
T112 |
91275 |
38 |
0 |
0 |
T128 |
14251 |
11 |
0 |
0 |
T139 |
8584 |
5 |
0 |
0 |
T152 |
19617 |
47 |
0 |
0 |
T154 |
4112 |
10 |
0 |
0 |
T156 |
72321 |
54 |
0 |
0 |
T157 |
10520 |
17 |
0 |
0 |
T158 |
13234 |
36 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2342 |
0 |
0 |
T36 |
34643 |
44 |
0 |
0 |
T39 |
74482 |
516 |
0 |
0 |
T112 |
91275 |
90 |
0 |
0 |
T128 |
14251 |
29 |
0 |
0 |
T139 |
8584 |
9 |
0 |
0 |
T152 |
19617 |
57 |
0 |
0 |
T154 |
4112 |
7 |
0 |
0 |
T156 |
72321 |
84 |
0 |
0 |
T157 |
10520 |
23 |
0 |
0 |
T158 |
13234 |
67 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2210 |
0 |
0 |
T36 |
34643 |
44 |
0 |
0 |
T39 |
74482 |
447 |
0 |
0 |
T112 |
91275 |
83 |
0 |
0 |
T128 |
14251 |
18 |
0 |
0 |
T139 |
8584 |
10 |
0 |
0 |
T152 |
19617 |
44 |
0 |
0 |
T156 |
72321 |
79 |
0 |
0 |
T157 |
10520 |
18 |
0 |
0 |
T158 |
13234 |
32 |
0 |
0 |
T159 |
10559 |
14 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2293 |
0 |
0 |
T36 |
34643 |
36 |
0 |
0 |
T39 |
74482 |
500 |
0 |
0 |
T112 |
91275 |
65 |
0 |
0 |
T128 |
14251 |
24 |
0 |
0 |
T139 |
8584 |
13 |
0 |
0 |
T152 |
19617 |
58 |
0 |
0 |
T156 |
72321 |
94 |
0 |
0 |
T157 |
10520 |
7 |
0 |
0 |
T158 |
13234 |
37 |
0 |
0 |
T159 |
10559 |
12 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
3155 |
0 |
0 |
T36 |
34643 |
116 |
0 |
0 |
T39 |
74482 |
535 |
0 |
0 |
T112 |
91275 |
115 |
0 |
0 |
T124 |
11047 |
3 |
0 |
0 |
T128 |
14251 |
38 |
0 |
0 |
T139 |
8584 |
33 |
0 |
0 |
T152 |
19617 |
76 |
0 |
0 |
T154 |
4112 |
2 |
0 |
0 |
T156 |
72321 |
170 |
0 |
0 |
T157 |
10520 |
21 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2235 |
0 |
0 |
T36 |
34643 |
33 |
0 |
0 |
T39 |
74482 |
467 |
0 |
0 |
T112 |
91275 |
76 |
0 |
0 |
T128 |
14251 |
29 |
0 |
0 |
T139 |
8584 |
6 |
0 |
0 |
T152 |
19617 |
42 |
0 |
0 |
T156 |
72321 |
78 |
0 |
0 |
T157 |
10520 |
16 |
0 |
0 |
T158 |
13234 |
24 |
0 |
0 |
T159 |
10559 |
18 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
3418 |
0 |
0 |
T36 |
34643 |
127 |
0 |
0 |
T39 |
74482 |
505 |
0 |
0 |
T112 |
91275 |
233 |
0 |
0 |
T128 |
14251 |
46 |
0 |
0 |
T139 |
8584 |
37 |
0 |
0 |
T152 |
19617 |
70 |
0 |
0 |
T156 |
72321 |
159 |
0 |
0 |
T157 |
10520 |
23 |
0 |
0 |
T158 |
13234 |
68 |
0 |
0 |
T159 |
10559 |
9 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2497 |
0 |
0 |
T36 |
34643 |
50 |
0 |
0 |
T39 |
74482 |
477 |
0 |
0 |
T112 |
91275 |
97 |
0 |
0 |
T128 |
14251 |
25 |
0 |
0 |
T139 |
8584 |
9 |
0 |
0 |
T152 |
19617 |
68 |
0 |
0 |
T154 |
4112 |
13 |
0 |
0 |
T156 |
72321 |
100 |
0 |
0 |
T157 |
10520 |
13 |
0 |
0 |
T158 |
13234 |
65 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2243 |
0 |
0 |
T36 |
34643 |
21 |
0 |
0 |
T39 |
74482 |
486 |
0 |
0 |
T112 |
91275 |
65 |
0 |
0 |
T124 |
11047 |
5 |
0 |
0 |
T128 |
14251 |
24 |
0 |
0 |
T139 |
8584 |
6 |
0 |
0 |
T152 |
19617 |
21 |
0 |
0 |
T156 |
72321 |
46 |
0 |
0 |
T157 |
10520 |
19 |
0 |
0 |
T158 |
13234 |
19 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2284 |
0 |
0 |
T36 |
34643 |
40 |
0 |
0 |
T39 |
74482 |
502 |
0 |
0 |
T112 |
91275 |
42 |
0 |
0 |
T128 |
14251 |
23 |
0 |
0 |
T139 |
8584 |
12 |
0 |
0 |
T152 |
19617 |
35 |
0 |
0 |
T156 |
72321 |
68 |
0 |
0 |
T157 |
10520 |
16 |
0 |
0 |
T158 |
13234 |
71 |
0 |
0 |
T159 |
10559 |
12 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2238 |
0 |
0 |
T36 |
34643 |
53 |
0 |
0 |
T39 |
74482 |
546 |
0 |
0 |
T112 |
91275 |
86 |
0 |
0 |
T128 |
14251 |
36 |
0 |
0 |
T139 |
8584 |
9 |
0 |
0 |
T152 |
19617 |
39 |
0 |
0 |
T154 |
4112 |
5 |
0 |
0 |
T156 |
72321 |
62 |
0 |
0 |
T157 |
10520 |
12 |
0 |
0 |
T158 |
13234 |
19 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2235 |
0 |
0 |
T36 |
34643 |
37 |
0 |
0 |
T39 |
74482 |
519 |
0 |
0 |
T112 |
91275 |
53 |
0 |
0 |
T128 |
14251 |
21 |
0 |
0 |
T139 |
8584 |
2 |
0 |
0 |
T152 |
19617 |
36 |
0 |
0 |
T154 |
4112 |
5 |
0 |
0 |
T156 |
72321 |
68 |
0 |
0 |
T157 |
10520 |
17 |
0 |
0 |
T158 |
13234 |
72 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2076 |
0 |
0 |
T36 |
34643 |
35 |
0 |
0 |
T39 |
74482 |
456 |
0 |
0 |
T112 |
91275 |
52 |
0 |
0 |
T128 |
14251 |
22 |
0 |
0 |
T139 |
8584 |
15 |
0 |
0 |
T152 |
19617 |
54 |
0 |
0 |
T154 |
4112 |
8 |
0 |
0 |
T156 |
72321 |
66 |
0 |
0 |
T157 |
10520 |
11 |
0 |
0 |
T158 |
13234 |
21 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114856851 |
2143 |
0 |
0 |
T36 |
34643 |
52 |
0 |
0 |
T39 |
74482 |
462 |
0 |
0 |
T112 |
91275 |
53 |
0 |
0 |
T128 |
14251 |
30 |
0 |
0 |
T139 |
8584 |
6 |
0 |
0 |
T152 |
19617 |
33 |
0 |
0 |
T154 |
4112 |
2 |
0 |
0 |
T156 |
72321 |
75 |
0 |
0 |
T157 |
10520 |
13 |
0 |
0 |
T158 |
13234 |
25 |
0 |
0 |