Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.03 97.50 92.82 98.61 80.85 95.87 90.96 87.59


Total test records in report: 835
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T149 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.457871591 Apr 21 12:39:18 PM PDT 24 Apr 21 12:39:21 PM PDT 24 65105182 ps
T759 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2450650601 Apr 21 12:38:58 PM PDT 24 Apr 21 12:38:59 PM PDT 24 45173814 ps
T365 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2466749757 Apr 21 12:39:09 PM PDT 24 Apr 21 12:39:18 PM PDT 24 1558368146 ps
T367 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1704621902 Apr 21 12:38:57 PM PDT 24 Apr 21 12:39:10 PM PDT 24 601689867 ps
T760 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.193021857 Apr 21 12:39:00 PM PDT 24 Apr 21 12:39:06 PM PDT 24 612833724 ps
T150 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4100799992 Apr 21 12:38:50 PM PDT 24 Apr 21 12:38:53 PM PDT 24 55430284 ps
T761 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3808548253 Apr 21 12:39:13 PM PDT 24 Apr 21 12:39:15 PM PDT 24 241098464 ps
T762 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2484375595 Apr 21 12:38:42 PM PDT 24 Apr 21 12:38:44 PM PDT 24 123105614 ps
T763 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1814315245 Apr 21 12:38:41 PM PDT 24 Apr 21 12:38:42 PM PDT 24 27875735 ps
T764 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2069087731 Apr 21 12:38:49 PM PDT 24 Apr 21 12:38:52 PM PDT 24 46877761 ps
T765 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.890335799 Apr 21 12:38:38 PM PDT 24 Apr 21 12:38:41 PM PDT 24 139171347 ps
T766 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.714512277 Apr 21 12:38:58 PM PDT 24 Apr 21 12:39:01 PM PDT 24 149887750 ps
T767 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.654694782 Apr 21 12:38:50 PM PDT 24 Apr 21 12:38:55 PM PDT 24 708845387 ps
T768 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3116170694 Apr 21 12:39:05 PM PDT 24 Apr 21 12:39:23 PM PDT 24 872630711 ps
T769 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3111531072 Apr 21 12:38:52 PM PDT 24 Apr 21 12:38:55 PM PDT 24 229967128 ps
T770 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3164689312 Apr 21 12:39:02 PM PDT 24 Apr 21 12:39:05 PM PDT 24 302856492 ps
T771 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2400182575 Apr 21 12:39:12 PM PDT 24 Apr 21 12:39:15 PM PDT 24 174882514 ps
T772 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2613181200 Apr 21 12:39:04 PM PDT 24 Apr 21 12:39:11 PM PDT 24 554185560 ps
T773 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1831463857 Apr 21 12:38:48 PM PDT 24 Apr 21 12:38:50 PM PDT 24 61771136 ps
T774 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3297729780 Apr 21 12:38:56 PM PDT 24 Apr 21 12:38:58 PM PDT 24 45750382 ps
T775 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1837359737 Apr 21 12:39:20 PM PDT 24 Apr 21 12:39:21 PM PDT 24 48178792 ps
T776 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1212975760 Apr 21 12:38:56 PM PDT 24 Apr 21 12:38:59 PM PDT 24 170919665 ps
T777 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3053230910 Apr 21 12:39:37 PM PDT 24 Apr 21 12:39:38 PM PDT 24 13557477 ps
T778 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3515350649 Apr 21 12:39:26 PM PDT 24 Apr 21 12:39:28 PM PDT 24 34515906 ps
T779 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3209550822 Apr 21 12:39:13 PM PDT 24 Apr 21 12:39:18 PM PDT 24 473016257 ps
T780 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4004038355 Apr 21 12:39:00 PM PDT 24 Apr 21 12:39:03 PM PDT 24 56244730 ps
T781 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.236260150 Apr 21 12:38:41 PM PDT 24 Apr 21 12:38:44 PM PDT 24 132774516 ps
T782 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3251889437 Apr 21 12:38:57 PM PDT 24 Apr 21 12:39:00 PM PDT 24 36491911 ps
T783 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2317502637 Apr 21 12:38:46 PM PDT 24 Apr 21 12:38:47 PM PDT 24 21845987 ps
T784 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2986425968 Apr 21 12:38:44 PM PDT 24 Apr 21 12:38:59 PM PDT 24 202838158 ps
T785 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1725659904 Apr 21 12:38:54 PM PDT 24 Apr 21 12:38:56 PM PDT 24 96970882 ps
T786 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2863903157 Apr 21 12:38:59 PM PDT 24 Apr 21 12:39:01 PM PDT 24 298384132 ps
T787 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3605701972 Apr 21 12:39:19 PM PDT 24 Apr 21 12:39:22 PM PDT 24 81923400 ps
T788 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.789443638 Apr 21 12:39:13 PM PDT 24 Apr 21 12:39:15 PM PDT 24 45005643 ps
T789 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2412520368 Apr 21 12:38:48 PM PDT 24 Apr 21 12:39:24 PM PDT 24 1865106003 ps
T790 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3391733104 Apr 21 12:39:18 PM PDT 24 Apr 21 12:39:22 PM PDT 24 653101508 ps
T791 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.346959637 Apr 21 12:38:53 PM PDT 24 Apr 21 12:38:55 PM PDT 24 100131198 ps
T792 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.658462781 Apr 21 12:39:01 PM PDT 24 Apr 21 12:39:03 PM PDT 24 117860889 ps
T793 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3957619405 Apr 21 12:38:49 PM PDT 24 Apr 21 12:38:50 PM PDT 24 12529586 ps
T794 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3974796303 Apr 21 12:39:09 PM PDT 24 Apr 21 12:39:13 PM PDT 24 262126729 ps
T795 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.833276534 Apr 21 12:38:49 PM PDT 24 Apr 21 12:38:52 PM PDT 24 162467690 ps
T796 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4109728984 Apr 21 12:39:14 PM PDT 24 Apr 21 12:39:16 PM PDT 24 44973574 ps
T797 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1840734622 Apr 21 12:39:26 PM PDT 24 Apr 21 12:39:34 PM PDT 24 5213647173 ps
T798 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1612053645 Apr 21 12:39:10 PM PDT 24 Apr 21 12:39:11 PM PDT 24 17093713 ps
T799 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1622964920 Apr 21 12:39:06 PM PDT 24 Apr 21 12:39:09 PM PDT 24 112164381 ps
T800 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1887276259 Apr 21 12:38:49 PM PDT 24 Apr 21 12:38:52 PM PDT 24 70778515 ps
T100 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3648541644 Apr 21 12:38:48 PM PDT 24 Apr 21 12:38:49 PM PDT 24 75484765 ps
T801 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4140492604 Apr 21 12:39:17 PM PDT 24 Apr 21 12:39:20 PM PDT 24 100372319 ps
T802 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3476499068 Apr 21 12:39:34 PM PDT 24 Apr 21 12:39:36 PM PDT 24 39296229 ps
T803 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3463750269 Apr 21 12:39:05 PM PDT 24 Apr 21 12:39:07 PM PDT 24 36854273 ps
T804 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1764115821 Apr 21 12:39:07 PM PDT 24 Apr 21 12:39:18 PM PDT 24 16903108 ps
T805 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1844861374 Apr 21 12:39:11 PM PDT 24 Apr 21 12:39:15 PM PDT 24 208359527 ps
T806 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2683368185 Apr 21 12:39:15 PM PDT 24 Apr 21 12:39:17 PM PDT 24 21650235 ps
T807 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.47225904 Apr 21 12:39:09 PM PDT 24 Apr 21 12:39:11 PM PDT 24 98894225 ps
T808 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3623242125 Apr 21 12:39:07 PM PDT 24 Apr 21 12:39:12 PM PDT 24 618527344 ps
T809 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4244209623 Apr 21 12:39:07 PM PDT 24 Apr 21 12:39:31 PM PDT 24 1055929615 ps
T810 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2383140316 Apr 21 12:39:13 PM PDT 24 Apr 21 12:39:16 PM PDT 24 74984622 ps
T811 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4186955960 Apr 21 12:38:43 PM PDT 24 Apr 21 12:39:03 PM PDT 24 849132052 ps
T812 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2699584176 Apr 21 12:39:04 PM PDT 24 Apr 21 12:39:07 PM PDT 24 210671605 ps
T361 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3196597441 Apr 21 12:38:50 PM PDT 24 Apr 21 12:38:54 PM PDT 24 123520231 ps
T813 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.34926901 Apr 21 12:38:52 PM PDT 24 Apr 21 12:39:01 PM PDT 24 382677585 ps
T814 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4122364068 Apr 21 12:38:46 PM PDT 24 Apr 21 12:38:49 PM PDT 24 171700647 ps
T815 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.954571114 Apr 21 12:38:58 PM PDT 24 Apr 21 12:39:01 PM PDT 24 927454466 ps
T816 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4274733239 Apr 21 12:39:29 PM PDT 24 Apr 21 12:39:31 PM PDT 24 18649042 ps
T817 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1392783720 Apr 21 12:39:08 PM PDT 24 Apr 21 12:39:10 PM PDT 24 53525289 ps
T818 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3209078078 Apr 21 12:38:58 PM PDT 24 Apr 21 12:39:00 PM PDT 24 31740800 ps
T819 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3846357789 Apr 21 12:39:18 PM PDT 24 Apr 21 12:39:20 PM PDT 24 30224893 ps
T820 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2732931427 Apr 21 12:38:54 PM PDT 24 Apr 21 12:38:58 PM PDT 24 105889702 ps
T821 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2773587958 Apr 21 12:39:04 PM PDT 24 Apr 21 12:39:07 PM PDT 24 636139913 ps
T822 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.451322463 Apr 21 12:39:13 PM PDT 24 Apr 21 12:39:15 PM PDT 24 62973792 ps
T823 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.9061573 Apr 21 12:39:00 PM PDT 24 Apr 21 12:39:02 PM PDT 24 20329002 ps
T824 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.774296321 Apr 21 12:39:01 PM PDT 24 Apr 21 12:39:03 PM PDT 24 16062534 ps
T101 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3257072281 Apr 21 12:38:43 PM PDT 24 Apr 21 12:38:45 PM PDT 24 140382065 ps
T825 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1212304294 Apr 21 12:38:47 PM PDT 24 Apr 21 12:38:49 PM PDT 24 46317620 ps
T826 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3615280793 Apr 21 12:39:23 PM PDT 24 Apr 21 12:39:24 PM PDT 24 13412592 ps
T827 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.120220949 Apr 21 12:39:08 PM PDT 24 Apr 21 12:39:10 PM PDT 24 20241597 ps
T828 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3575540053 Apr 21 12:39:00 PM PDT 24 Apr 21 12:39:03 PM PDT 24 33615703 ps
T829 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2384027949 Apr 21 12:39:06 PM PDT 24 Apr 21 12:39:11 PM PDT 24 270379790 ps
T830 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1809957996 Apr 21 12:39:16 PM PDT 24 Apr 21 12:39:17 PM PDT 24 14693547 ps
T831 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3263110505 Apr 21 12:39:12 PM PDT 24 Apr 21 12:39:20 PM PDT 24 1130279982 ps
T832 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3723585687 Apr 21 12:38:49 PM PDT 24 Apr 21 12:38:50 PM PDT 24 69146888 ps
T833 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2331916838 Apr 21 12:39:00 PM PDT 24 Apr 21 12:39:02 PM PDT 24 20679656 ps
T834 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3264264881 Apr 21 12:38:53 PM PDT 24 Apr 21 12:38:56 PM PDT 24 151901684 ps
T835 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3483317375 Apr 21 12:38:52 PM PDT 24 Apr 21 12:38:54 PM PDT 24 49092170 ps
T363 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.69407203 Apr 21 12:38:52 PM PDT 24 Apr 21 12:39:11 PM PDT 24 2376894296 ps

Test location /workspace/coverage/default/36.spi_device_flash_mode.1403028046
Short name T2
Test name
Test status
Simulation time 3479911788 ps
CPU time 62.8 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:57:29 PM PDT 24
Peak memory 251420 kb
Host smart-d19d641b-d9dd-4f6f-b937-4b4b35ca9b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403028046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1403028046
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2271535420
Short name T14
Test name
Test status
Simulation time 2854373432 ps
CPU time 27.44 seconds
Started Apr 21 12:55:54 PM PDT 24
Finished Apr 21 12:56:22 PM PDT 24
Peak memory 216300 kb
Host smart-f3b2f312-361f-46d0-89da-6a8872e2fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271535420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2271535420
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1312210646
Short name T9
Test name
Test status
Simulation time 22696799513 ps
CPU time 17.96 seconds
Started Apr 21 12:56:02 PM PDT 24
Finished Apr 21 12:56:21 PM PDT 24
Peak memory 222912 kb
Host smart-66eb435e-95e3-41c6-8bd2-2d8803dc8679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312210646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1312210646
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3214513890
Short name T51
Test name
Test status
Simulation time 1574944987 ps
CPU time 26.06 seconds
Started Apr 21 12:55:45 PM PDT 24
Finished Apr 21 12:56:11 PM PDT 24
Peak memory 218984 kb
Host smart-be5a6b6f-cdaf-4df9-bc45-9372efefb357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214513890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3214513890
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1060997605
Short name T45
Test name
Test status
Simulation time 527671482 ps
CPU time 8.88 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:58 PM PDT 24
Peak memory 223464 kb
Host smart-5c7f51a8-fdb4-4e33-8488-f55780f16e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060997605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1060997605
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3373405456
Short name T112
Test name
Test status
Simulation time 1126913603 ps
CPU time 20.28 seconds
Started Apr 21 12:39:01 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 215240 kb
Host smart-a53dda0a-3e1a-46e3-9212-8139e69c9304
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373405456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3373405456
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1220923256
Short name T26
Test name
Test status
Simulation time 121466901 ps
CPU time 2.59 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:11 PM PDT 24
Peak memory 222896 kb
Host smart-03d10d12-b525-4f2d-9c92-b8935c2ef28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220923256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1220923256
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3740510800
Short name T352
Test name
Test status
Simulation time 43832676 ps
CPU time 0.93 seconds
Started Apr 21 12:55:28 PM PDT 24
Finished Apr 21 12:55:29 PM PDT 24
Peak memory 206524 kb
Host smart-d3a066f8-6da9-44dd-a04d-91b31072623b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740510800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3740510800
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2175119483
Short name T114
Test name
Test status
Simulation time 2124666017 ps
CPU time 8.27 seconds
Started Apr 21 12:56:53 PM PDT 24
Finished Apr 21 12:57:01 PM PDT 24
Peak memory 218640 kb
Host smart-6dac4471-e1ea-4c88-9689-50f6b9c5e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175119483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2175119483
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4082284695
Short name T370
Test name
Test status
Simulation time 40850894007 ps
CPU time 41.07 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:56:23 PM PDT 24
Peak memory 216288 kb
Host smart-cc6f6d29-034a-4345-9b97-100a2d6fced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082284695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4082284695
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1963305979
Short name T42
Test name
Test status
Simulation time 17037803 ps
CPU time 0.75 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:54:54 PM PDT 24
Peak memory 216144 kb
Host smart-956102df-3799-484b-8faa-5a5e63c4523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963305979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1963305979
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2482675364
Short name T386
Test name
Test status
Simulation time 20088171267 ps
CPU time 53.62 seconds
Started Apr 21 12:55:21 PM PDT 24
Finished Apr 21 12:56:15 PM PDT 24
Peak memory 216116 kb
Host smart-e9bcd71b-2ef7-4611-b2db-b60703219178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482675364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2482675364
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1738771620
Short name T210
Test name
Test status
Simulation time 17758871425 ps
CPU time 16.06 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:55 PM PDT 24
Peak memory 232472 kb
Host smart-a5d789f9-b78c-4250-898f-6cc26b534783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738771620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1738771620
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3881349437
Short name T57
Test name
Test status
Simulation time 12196744405 ps
CPU time 15.05 seconds
Started Apr 21 12:55:59 PM PDT 24
Finished Apr 21 12:56:15 PM PDT 24
Peak memory 228696 kb
Host smart-f33c2156-1295-4e37-96a8-8cf5670f39ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881349437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3881349437
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1270326116
Short name T8
Test name
Test status
Simulation time 11974812879 ps
CPU time 114.95 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:57:54 PM PDT 24
Peak memory 228444 kb
Host smart-781319ba-e4b4-4851-b41a-4422817d0894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270326116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1270326116
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2066864861
Short name T123
Test name
Test status
Simulation time 907739890 ps
CPU time 5.53 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 215500 kb
Host smart-e96a2ad5-7086-4943-bd92-cf38d2198e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066864861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
066864861
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3713191803
Short name T16
Test name
Test status
Simulation time 84585968 ps
CPU time 1.16 seconds
Started Apr 21 12:55:02 PM PDT 24
Finished Apr 21 12:55:03 PM PDT 24
Peak memory 234900 kb
Host smart-e01ac205-41ed-4ada-80f4-390081fb5c6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713191803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3713191803
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1957606276
Short name T11
Test name
Test status
Simulation time 3771704182 ps
CPU time 7.25 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 221712 kb
Host smart-6e14e4da-4d5f-4fc2-8665-d67bc2251a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957606276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1957606276
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2159017873
Short name T242
Test name
Test status
Simulation time 14873615409 ps
CPU time 11.67 seconds
Started Apr 21 12:55:08 PM PDT 24
Finished Apr 21 12:55:20 PM PDT 24
Peak memory 232548 kb
Host smart-65c54cd9-303d-4f17-a00e-28b556c880b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159017873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2159017873
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2797155021
Short name T54
Test name
Test status
Simulation time 3259677868 ps
CPU time 37.18 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:47 PM PDT 24
Peak memory 216348 kb
Host smart-fcb24d08-20bf-4d23-82c3-9b80e507c23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797155021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2797155021
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.53190661
Short name T196
Test name
Test status
Simulation time 1451962372 ps
CPU time 14.22 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:55:25 PM PDT 24
Peak memory 224244 kb
Host smart-55866126-4a95-46f5-8ac9-9cf07f1d8a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53190661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.53190661
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.243171977
Short name T139
Test name
Test status
Simulation time 86728155 ps
CPU time 2.11 seconds
Started Apr 21 12:38:59 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 215064 kb
Host smart-7e4690f4-8623-44ad-9539-1ded956c41b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243171977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.243171977
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.183860476
Short name T381
Test name
Test status
Simulation time 7926186706 ps
CPU time 48.58 seconds
Started Apr 21 12:56:44 PM PDT 24
Finished Apr 21 12:57:33 PM PDT 24
Peak memory 216248 kb
Host smart-4fdfc42f-1c64-465f-aa51-dad042817e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183860476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.183860476
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1341632179
Short name T212
Test name
Test status
Simulation time 5638128908 ps
CPU time 16.59 seconds
Started Apr 21 12:56:33 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 216660 kb
Host smart-7bdc37f4-a0f9-4d19-afff-24eb2c662e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341632179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1341632179
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2446199564
Short name T259
Test name
Test status
Simulation time 73212485703 ps
CPU time 37.24 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 232360 kb
Host smart-a5a38988-78f6-4b3a-a511-aba5ce24640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446199564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2446199564
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1512978926
Short name T319
Test name
Test status
Simulation time 3723654444 ps
CPU time 15.13 seconds
Started Apr 21 12:55:02 PM PDT 24
Finished Apr 21 12:55:18 PM PDT 24
Peak memory 234704 kb
Host smart-db7cff2c-e69c-4e6a-b84b-5aed00607e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512978926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1512978926
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.936863512
Short name T286
Test name
Test status
Simulation time 15961423192 ps
CPU time 109.25 seconds
Started Apr 21 12:56:36 PM PDT 24
Finished Apr 21 12:58:25 PM PDT 24
Peak memory 252948 kb
Host smart-567fae64-f832-41f1-84fc-2786953c153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936863512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.936863512
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2874138998
Short name T346
Test name
Test status
Simulation time 954825541 ps
CPU time 10.94 seconds
Started Apr 21 12:55:24 PM PDT 24
Finished Apr 21 12:55:35 PM PDT 24
Peak memory 222852 kb
Host smart-161f8c18-bace-4625-a118-aa648ecdc3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874138998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2874138998
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.78571358
Short name T67
Test name
Test status
Simulation time 59694697554 ps
CPU time 37.53 seconds
Started Apr 21 12:55:48 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 235012 kb
Host smart-357fc66f-21f8-404f-baf5-431d4f8dd677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78571358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.78571358
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3010717812
Short name T172
Test name
Test status
Simulation time 2726914807 ps
CPU time 28.09 seconds
Started Apr 21 12:54:50 PM PDT 24
Finished Apr 21 12:55:19 PM PDT 24
Peak memory 232580 kb
Host smart-b69bf16e-07dc-494d-87f7-cecb862fa81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010717812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3010717812
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2923662193
Short name T302
Test name
Test status
Simulation time 614994000 ps
CPU time 7.44 seconds
Started Apr 21 12:56:21 PM PDT 24
Finished Apr 21 12:56:29 PM PDT 24
Peak memory 224080 kb
Host smart-7a325991-8984-4e47-a6ae-761d09bfb124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923662193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2923662193
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1322251223
Short name T108
Test name
Test status
Simulation time 101854122324 ps
CPU time 99.25 seconds
Started Apr 21 12:56:43 PM PDT 24
Finished Apr 21 12:58:23 PM PDT 24
Peak memory 232204 kb
Host smart-a6f7c335-0a95-4ff5-81bb-bbe751750f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322251223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1322251223
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1798385187
Short name T332
Test name
Test status
Simulation time 6464331668 ps
CPU time 19.79 seconds
Started Apr 21 12:56:26 PM PDT 24
Finished Apr 21 12:56:47 PM PDT 24
Peak memory 223884 kb
Host smart-a28fe9c0-66e0-4c2b-a6af-5680ca95b89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798385187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1798385187
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.214238150
Short name T104
Test name
Test status
Simulation time 20067663867 ps
CPU time 29.67 seconds
Started Apr 21 12:54:51 PM PDT 24
Finished Apr 21 12:55:22 PM PDT 24
Peak memory 216204 kb
Host smart-127d8f93-ad69-4fdf-b816-c317fac895c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214238150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.214238150
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1374399673
Short name T303
Test name
Test status
Simulation time 9520185908 ps
CPU time 88.92 seconds
Started Apr 21 12:54:59 PM PDT 24
Finished Apr 21 12:56:28 PM PDT 24
Peak memory 230872 kb
Host smart-6b031194-c905-4329-9557-10e3d1bf5036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374399673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1374399673
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.831164560
Short name T343
Test name
Test status
Simulation time 1424078605 ps
CPU time 8.7 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:18 PM PDT 24
Peak memory 221132 kb
Host smart-5c3349db-e304-4342-939b-22e731e8129d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831164560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.831164560
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.85640697
Short name T231
Test name
Test status
Simulation time 10436817599 ps
CPU time 27.4 seconds
Started Apr 21 12:55:01 PM PDT 24
Finished Apr 21 12:55:29 PM PDT 24
Peak memory 224044 kb
Host smart-a51424d3-10cf-4418-b4e2-58f729d30272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85640697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.85640697
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1452833435
Short name T356
Test name
Test status
Simulation time 1109765942 ps
CPU time 8.83 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 218408 kb
Host smart-79f4e8aa-f6ae-4246-badc-1e4b0e2636ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452833435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1452833435
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_upload.1268400104
Short name T224
Test name
Test status
Simulation time 27002864381 ps
CPU time 24.02 seconds
Started Apr 21 12:55:27 PM PDT 24
Finished Apr 21 12:55:52 PM PDT 24
Peak memory 223060 kb
Host smart-dbf26db5-2a91-433e-93f6-9d65e4489e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268400104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1268400104
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_upload.3473941697
Short name T29
Test name
Test status
Simulation time 13165896717 ps
CPU time 39.44 seconds
Started Apr 21 12:55:11 PM PDT 24
Finished Apr 21 12:55:51 PM PDT 24
Peak memory 224376 kb
Host smart-249ca7e3-8004-4017-acf8-4efedb7de8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473941697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3473941697
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_upload.3425938748
Short name T201
Test name
Test status
Simulation time 33167747733 ps
CPU time 51.46 seconds
Started Apr 21 12:55:18 PM PDT 24
Finished Apr 21 12:56:10 PM PDT 24
Peak memory 236448 kb
Host smart-25ec7055-d6a6-47e1-b7de-2b388feecb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425938748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3425938748
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1186878986
Short name T314
Test name
Test status
Simulation time 12286243457 ps
CPU time 98.61 seconds
Started Apr 21 12:56:11 PM PDT 24
Finished Apr 21 12:57:50 PM PDT 24
Peak memory 238556 kb
Host smart-b9574817-7a13-4565-bd2d-6ac441313223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186878986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1186878986
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.707621960
Short name T397
Test name
Test status
Simulation time 6607924375 ps
CPU time 49.17 seconds
Started Apr 21 12:56:11 PM PDT 24
Finished Apr 21 12:57:01 PM PDT 24
Peak memory 216088 kb
Host smart-7793bc5d-2d2d-4e74-bce2-f6ac772ae560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707621960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.707621960
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1320793347
Short name T17
Test name
Test status
Simulation time 172474537 ps
CPU time 0.92 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 206696 kb
Host smart-fa92b306-bc93-464b-9c6c-0eb8ea47509b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320793347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1320793347
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3135272321
Short name T103
Test name
Test status
Simulation time 20439284863 ps
CPU time 37.19 seconds
Started Apr 21 12:55:33 PM PDT 24
Finished Apr 21 12:56:10 PM PDT 24
Peak memory 216268 kb
Host smart-0ef09b17-b3af-4006-b859-acde3c328377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135272321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3135272321
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2330512575
Short name T342
Test name
Test status
Simulation time 1283902203 ps
CPU time 8.8 seconds
Started Apr 21 12:55:45 PM PDT 24
Finished Apr 21 12:55:54 PM PDT 24
Peak memory 222540 kb
Host smart-688d7228-7946-4dc5-a28a-8ea268c4f861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330512575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2330512575
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1143869595
Short name T301
Test name
Test status
Simulation time 3704541505 ps
CPU time 13.94 seconds
Started Apr 21 12:55:44 PM PDT 24
Finished Apr 21 12:55:59 PM PDT 24
Peak memory 232652 kb
Host smart-b1f03cc7-039e-4ba6-a0cd-2bd632384b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143869595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1143869595
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2549278719
Short name T429
Test name
Test status
Simulation time 37140081 ps
CPU time 0.73 seconds
Started Apr 21 12:54:52 PM PDT 24
Finished Apr 21 12:54:53 PM PDT 24
Peak memory 204808 kb
Host smart-11a8dcb6-aab3-49d3-ab15-961c51ed5930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549278719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
549278719
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3370978270
Short name T206
Test name
Test status
Simulation time 781762561 ps
CPU time 3.51 seconds
Started Apr 21 12:55:30 PM PDT 24
Finished Apr 21 12:55:34 PM PDT 24
Peak memory 218596 kb
Host smart-1273363c-d05c-4bb9-8b25-651fcf83b5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370978270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3370978270
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3195060178
Short name T182
Test name
Test status
Simulation time 7295121645 ps
CPU time 7.65 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 223224 kb
Host smart-eae0e65e-f8bf-4041-a636-f6f664ec1b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195060178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3195060178
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2047801225
Short name T219
Test name
Test status
Simulation time 432904778 ps
CPU time 8.63 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 218376 kb
Host smart-698d474d-c3b4-4cdb-b5b9-15e617e272c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047801225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2047801225
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3131751991
Short name T311
Test name
Test status
Simulation time 6703579942 ps
CPU time 89.16 seconds
Started Apr 21 12:56:26 PM PDT 24
Finished Apr 21 12:57:56 PM PDT 24
Peak memory 221448 kb
Host smart-152542da-776d-4235-9ef5-30c5d02428c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131751991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3131751991
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.609388946
Short name T357
Test name
Test status
Simulation time 10378262351 ps
CPU time 28.2 seconds
Started Apr 21 12:55:08 PM PDT 24
Finished Apr 21 12:55:37 PM PDT 24
Peak memory 224280 kb
Host smart-4995b9f2-a662-4e56-bc0c-a57e555738d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609388946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.609388946
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3841321679
Short name T339
Test name
Test status
Simulation time 4610578921 ps
CPU time 17.39 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:25 PM PDT 24
Peak memory 234872 kb
Host smart-de4f6b76-19dd-4a91-a1f2-721e5ce7b54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841321679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3841321679
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3945197063
Short name T236
Test name
Test status
Simulation time 9348010992 ps
CPU time 12.03 seconds
Started Apr 21 12:55:28 PM PDT 24
Finished Apr 21 12:55:40 PM PDT 24
Peak memory 218844 kb
Host smart-3b758e56-5968-4112-b11c-a3a408f1ff5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945197063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3945197063
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3144655997
Short name T78
Test name
Test status
Simulation time 6257085855 ps
CPU time 36.65 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 221980 kb
Host smart-b205ede7-9fd8-45d5-83d9-c82bb2b71df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144655997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3144655997
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2582136000
Short name T277
Test name
Test status
Simulation time 1067468277 ps
CPU time 7.65 seconds
Started Apr 21 12:56:12 PM PDT 24
Finished Apr 21 12:56:20 PM PDT 24
Peak memory 234916 kb
Host smart-5c5ac8df-0996-4f1d-b85d-d47e8d0c1940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582136000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2582136000
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.305786375
Short name T116
Test name
Test status
Simulation time 3038551643 ps
CPU time 38.31 seconds
Started Apr 21 12:56:16 PM PDT 24
Finished Apr 21 12:56:55 PM PDT 24
Peak memory 238936 kb
Host smart-f7fc27f9-cd76-4e82-8396-705ec8743fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305786375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.305786375
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1758755929
Short name T252
Test name
Test status
Simulation time 19397189971 ps
CPU time 16.82 seconds
Started Apr 21 12:56:45 PM PDT 24
Finished Apr 21 12:57:02 PM PDT 24
Peak memory 224448 kb
Host smart-5bbdcaa9-8a7e-4386-8101-abbf1a4991c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758755929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1758755929
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1984228230
Short name T183
Test name
Test status
Simulation time 542303607 ps
CPU time 7.89 seconds
Started Apr 21 12:56:53 PM PDT 24
Finished Apr 21 12:57:02 PM PDT 24
Peak memory 218416 kb
Host smart-6dbdf9fe-e2d8-46ef-9d2f-8b8951f40323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984228230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1984228230
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2229196698
Short name T288
Test name
Test status
Simulation time 2424562483 ps
CPU time 13.56 seconds
Started Apr 21 12:56:46 PM PDT 24
Finished Apr 21 12:57:00 PM PDT 24
Peak memory 249004 kb
Host smart-455bce68-ec31-4393-a5c9-684d3477c9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229196698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2229196698
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.732894818
Short name T71
Test name
Test status
Simulation time 4742335462 ps
CPU time 6.23 seconds
Started Apr 21 12:55:08 PM PDT 24
Finished Apr 21 12:55:15 PM PDT 24
Peak memory 223680 kb
Host smart-ec9d2699-dc96-4034-a949-c78aadb275ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732894818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
732894818
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3719174382
Short name T368
Test name
Test status
Simulation time 677247356 ps
CPU time 15.25 seconds
Started Apr 21 12:38:37 PM PDT 24
Finished Apr 21 12:38:53 PM PDT 24
Peak memory 215184 kb
Host smart-ae2796f6-d013-40b6-bf40-9ff8e4cb9448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719174382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3719174382
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3817613226
Short name T28
Test name
Test status
Simulation time 4988043630 ps
CPU time 17.94 seconds
Started Apr 21 12:54:54 PM PDT 24
Finished Apr 21 12:55:12 PM PDT 24
Peak memory 223532 kb
Host smart-c5ac12d8-28c6-4168-ad04-cf52329f8f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817613226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3817613226
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3207462114
Short name T281
Test name
Test status
Simulation time 1610030308 ps
CPU time 6.18 seconds
Started Apr 21 12:55:09 PM PDT 24
Finished Apr 21 12:55:15 PM PDT 24
Peak memory 224952 kb
Host smart-f3e4c177-f98b-40e4-a7ef-2dd79fc88ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207462114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3207462114
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2210162308
Short name T384
Test name
Test status
Simulation time 10241524564 ps
CPU time 31.33 seconds
Started Apr 21 12:55:12 PM PDT 24
Finished Apr 21 12:55:44 PM PDT 24
Peak memory 220364 kb
Host smart-6ad6c1a7-456d-4d5a-ac78-f5cf8afd9f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210162308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2210162308
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_intercept.586468472
Short name T256
Test name
Test status
Simulation time 6465504958 ps
CPU time 14.83 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:56:04 PM PDT 24
Peak memory 216380 kb
Host smart-327ef4e6-b651-4938-ae56-7177c9822904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586468472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.586468472
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_upload.3505217216
Short name T347
Test name
Test status
Simulation time 492553008 ps
CPU time 3.86 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 232572 kb
Host smart-67e2213a-fa53-44d4-853b-cee47d0892ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505217216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3505217216
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_intercept.668845541
Short name T113
Test name
Test status
Simulation time 3501303710 ps
CPU time 42.36 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:56:47 PM PDT 24
Peak memory 223788 kb
Host smart-49cd5265-ab02-44a6-8992-b84886f5847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668845541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.668845541
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2608475126
Short name T344
Test name
Test status
Simulation time 4097520978 ps
CPU time 7.39 seconds
Started Apr 21 12:55:57 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 222792 kb
Host smart-65ecba2e-47df-46db-8475-eb0b2d754454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608475126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2608475126
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3918380821
Short name T72
Test name
Test status
Simulation time 4624266026 ps
CPU time 7.27 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 240068 kb
Host smart-41dd7ad9-e3f1-4974-a010-947c56bb0aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918380821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3918380821
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1701638558
Short name T69
Test name
Test status
Simulation time 5810964586 ps
CPU time 9.11 seconds
Started Apr 21 12:56:51 PM PDT 24
Finished Apr 21 12:57:00 PM PDT 24
Peak memory 224384 kb
Host smart-c6e46fb0-11e1-434d-b380-765490fde027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701638558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1701638558
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2928149478
Short name T707
Test name
Test status
Simulation time 10674515993 ps
CPU time 34 seconds
Started Apr 21 12:55:09 PM PDT 24
Finished Apr 21 12:55:43 PM PDT 24
Peak memory 216260 kb
Host smart-ea4b1506-aa0f-47ca-af19-4cbfc06d5b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928149478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2928149478
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3602744713
Short name T96
Test name
Test status
Simulation time 179738568 ps
CPU time 5.31 seconds
Started Apr 21 12:54:47 PM PDT 24
Finished Apr 21 12:54:53 PM PDT 24
Peak memory 223052 kb
Host smart-39d68fe4-758e-49f7-9f53-b047ab50786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602744713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3602744713
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2433604030
Short name T117
Test name
Test status
Simulation time 64742535 ps
CPU time 2.29 seconds
Started Apr 21 12:39:04 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 215280 kb
Host smart-1aa077cd-b815-4f81-ae88-0d6f66252210
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433604030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2433604030
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.729603444
Short name T163
Test name
Test status
Simulation time 21869549 ps
CPU time 0.77 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 203588 kb
Host smart-dcf89a35-e3f1-4bdc-85aa-e3021164d4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729603444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.729603444
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1353564130
Short name T336
Test name
Test status
Simulation time 910460452 ps
CPU time 5.88 seconds
Started Apr 21 12:54:46 PM PDT 24
Finished Apr 21 12:54:53 PM PDT 24
Peak memory 220308 kb
Host smart-be178dd3-fdd8-4b6a-b6f3-4c58340d7fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353564130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1353564130
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1574836942
Short name T66
Test name
Test status
Simulation time 3222622360 ps
CPU time 9.22 seconds
Started Apr 21 12:54:49 PM PDT 24
Finished Apr 21 12:54:59 PM PDT 24
Peak memory 230280 kb
Host smart-4af3c3ce-0fba-4466-bf71-30d814e46617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574836942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1574836942
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2177568885
Short name T295
Test name
Test status
Simulation time 9112814912 ps
CPU time 27.06 seconds
Started Apr 21 12:55:20 PM PDT 24
Finished Apr 21 12:55:47 PM PDT 24
Peak memory 251348 kb
Host smart-8fc12d1b-355f-47e5-a746-e37c69c12f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177568885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2177568885
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_upload.3451975428
Short name T55
Test name
Test status
Simulation time 2169632712 ps
CPU time 6.44 seconds
Started Apr 21 12:55:18 PM PDT 24
Finished Apr 21 12:55:24 PM PDT 24
Peak memory 235488 kb
Host smart-35cf8069-41f0-418c-a548-ace3c9c3a16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451975428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3451975428
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3085174298
Short name T221
Test name
Test status
Simulation time 88274329 ps
CPU time 2.87 seconds
Started Apr 21 12:55:19 PM PDT 24
Finished Apr 21 12:55:23 PM PDT 24
Peak memory 222748 kb
Host smart-a08eda96-d561-454e-bba0-a6d030ccd68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085174298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3085174298
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.561414220
Short name T239
Test name
Test status
Simulation time 31302238253 ps
CPU time 14.01 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:58 PM PDT 24
Peak memory 232104 kb
Host smart-091551bf-7207-41d1-a2d7-9b7446a74dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561414220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.561414220
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2026375890
Short name T307
Test name
Test status
Simulation time 10999669027 ps
CPU time 19.12 seconds
Started Apr 21 12:55:22 PM PDT 24
Finished Apr 21 12:55:41 PM PDT 24
Peak memory 235036 kb
Host smart-3e32f9be-ec6b-41e6-b088-6cd62e4c98af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026375890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2026375890
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1301105940
Short name T192
Test name
Test status
Simulation time 616507006 ps
CPU time 3.25 seconds
Started Apr 21 12:55:48 PM PDT 24
Finished Apr 21 12:55:52 PM PDT 24
Peak memory 222432 kb
Host smart-290e0de5-e526-49a1-a6f6-763e301861bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301105940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1301105940
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_upload.502771955
Short name T218
Test name
Test status
Simulation time 2083005583 ps
CPU time 9.71 seconds
Started Apr 21 12:55:34 PM PDT 24
Finished Apr 21 12:55:44 PM PDT 24
Peak memory 238200 kb
Host smart-91ea1aa3-7201-45ee-966e-ffd79495f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502771955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.502771955
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2802355841
Short name T326
Test name
Test status
Simulation time 29824260348 ps
CPU time 35.24 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 233616 kb
Host smart-0321f6c8-dcab-46e8-bcd0-f5b9cb2d20e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802355841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2802355841
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1556902703
Short name T181
Test name
Test status
Simulation time 116680264 ps
CPU time 2.31 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:55:52 PM PDT 24
Peak memory 216744 kb
Host smart-36ebe954-ea30-4654-94a7-e96d1e167d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556902703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1556902703
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1091829244
Short name T179
Test name
Test status
Simulation time 309878576 ps
CPU time 6.39 seconds
Started Apr 21 12:55:55 PM PDT 24
Finished Apr 21 12:56:02 PM PDT 24
Peak memory 223600 kb
Host smart-f2b2cc01-e4cf-414c-a385-61b538b4f9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091829244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1091829244
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_upload.1924328152
Short name T260
Test name
Test status
Simulation time 201278910 ps
CPU time 3.03 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 217540 kb
Host smart-f2344694-0562-4b1a-b691-7586303d7d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924328152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1924328152
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3618816303
Short name T94
Test name
Test status
Simulation time 335674031 ps
CPU time 3.42 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 220892 kb
Host smart-a340a8df-cd9d-4e19-b66e-3c87c406a82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618816303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3618816303
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4018170299
Short name T305
Test name
Test status
Simulation time 20512461646 ps
CPU time 44.16 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 232572 kb
Host smart-55e22de0-ca38-48ac-ab60-2954e62d8edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018170299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4018170299
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3722367634
Short name T293
Test name
Test status
Simulation time 18518604068 ps
CPU time 70.49 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:57:15 PM PDT 24
Peak memory 232676 kb
Host smart-0a927f98-004c-4cf1-bdbc-541373fdaaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722367634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3722367634
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3387222222
Short name T62
Test name
Test status
Simulation time 7765914487 ps
CPU time 22.73 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:33 PM PDT 24
Peak memory 223584 kb
Host smart-ac5b0572-3cfd-4b1d-b4de-142f803f42a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387222222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3387222222
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.894450962
Short name T58
Test name
Test status
Simulation time 903832924 ps
CPU time 11.75 seconds
Started Apr 21 12:56:15 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 240616 kb
Host smart-9cdeb4ec-c655-48be-a95d-7c311c3e68f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894450962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.894450962
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3959206333
Short name T274
Test name
Test status
Simulation time 6710623940 ps
CPU time 28.6 seconds
Started Apr 21 12:56:17 PM PDT 24
Finished Apr 21 12:56:46 PM PDT 24
Peak memory 218580 kb
Host smart-f8454f41-d5a7-416d-ac28-3268d2398591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959206333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3959206333
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_upload.4006947620
Short name T226
Test name
Test status
Simulation time 2135887259 ps
CPU time 2.94 seconds
Started Apr 21 12:56:22 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 223292 kb
Host smart-75f26a79-5f08-44df-aaca-5ec4157bda5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006947620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.4006947620
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_upload.283442013
Short name T190
Test name
Test status
Simulation time 2099100410 ps
CPU time 8.84 seconds
Started Apr 21 12:56:39 PM PDT 24
Finished Apr 21 12:56:48 PM PDT 24
Peak memory 224268 kb
Host smart-e2f30d3b-c2b6-4189-b984-d760ac7b576d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283442013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.283442013
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2653476425
Short name T68
Test name
Test status
Simulation time 3534304359 ps
CPU time 5.18 seconds
Started Apr 21 12:56:36 PM PDT 24
Finished Apr 21 12:56:41 PM PDT 24
Peak memory 223060 kb
Host smart-df56f6c6-189c-4dfa-86cd-a8cc14b33d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653476425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2653476425
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.904600840
Short name T216
Test name
Test status
Simulation time 360657636 ps
CPU time 3.87 seconds
Started Apr 21 12:55:22 PM PDT 24
Finished Apr 21 12:55:26 PM PDT 24
Peak memory 218328 kb
Host smart-46e5df37-cc0c-4c94-b633-81ed0ce521fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904600840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.904600840
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_upload.3555255019
Short name T73
Test name
Test status
Simulation time 1236820795 ps
CPU time 8.46 seconds
Started Apr 21 12:55:22 PM PDT 24
Finished Apr 21 12:55:31 PM PDT 24
Peak memory 221284 kb
Host smart-b165dbf2-a6fb-485a-ab22-cdc895045126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555255019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3555255019
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3196597441
Short name T361
Test name
Test status
Simulation time 123520231 ps
CPU time 3.18 seconds
Started Apr 21 12:38:50 PM PDT 24
Finished Apr 21 12:38:54 PM PDT 24
Peak memory 215300 kb
Host smart-4fad65bd-c588-48f2-8c5b-8212f3bc0952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196597441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3196597441
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1169004093
Short name T86
Test name
Test status
Simulation time 214030352 ps
CPU time 2.67 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:11 PM PDT 24
Peak memory 222880 kb
Host smart-9b6f2994-2f97-4373-876a-97f41d22c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169004093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1169004093
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.440859280
Short name T135
Test name
Test status
Simulation time 104758776 ps
CPU time 6.52 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:13 PM PDT 24
Peak memory 215184 kb
Host smart-2f9eee2a-0af3-4b44-933e-0ba50634adc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440859280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.440859280
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1704621902
Short name T367
Test name
Test status
Simulation time 601689867 ps
CPU time 12.66 seconds
Started Apr 21 12:38:57 PM PDT 24
Finished Apr 21 12:39:10 PM PDT 24
Peak memory 215204 kb
Host smart-90d45107-617d-4e78-b99f-f57b39d1405c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704621902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1704621902
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.69407203
Short name T363
Test name
Test status
Simulation time 2376894296 ps
CPU time 17.75 seconds
Started Apr 21 12:38:52 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 215256 kb
Host smart-d50a04ac-34f7-4988-84f4-c7109ed1c738
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69407203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_
tl_intg_err.69407203
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1490753088
Short name T359
Test name
Test status
Simulation time 15538078718 ps
CPU time 11.83 seconds
Started Apr 21 12:54:54 PM PDT 24
Finished Apr 21 12:55:06 PM PDT 24
Peak memory 221232 kb
Host smart-df6d916d-9849-43c9-a879-f90bb9a320eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490753088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1490753088
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2759183367
Short name T290
Test name
Test status
Simulation time 1587627551 ps
CPU time 13.41 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:55:11 PM PDT 24
Peak memory 250032 kb
Host smart-ebd5a3b1-9ce3-4692-9bb8-54baa321eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759183367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2759183367
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.492395385
Short name T323
Test name
Test status
Simulation time 2009625596 ps
CPU time 10.43 seconds
Started Apr 21 12:55:06 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 222952 kb
Host smart-26b056bd-61d0-44be-a63b-12107319c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492395385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.492395385
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1851291947
Short name T276
Test name
Test status
Simulation time 294795489 ps
CPU time 3.03 seconds
Started Apr 21 12:54:52 PM PDT 24
Finished Apr 21 12:54:56 PM PDT 24
Peak memory 223280 kb
Host smart-9ff269f9-3077-4707-bd19-916b10959346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851291947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1851291947
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_upload.723701591
Short name T59
Test name
Test status
Simulation time 92986446 ps
CPU time 3.02 seconds
Started Apr 21 12:54:52 PM PDT 24
Finished Apr 21 12:54:56 PM PDT 24
Peak memory 222436 kb
Host smart-43aa6af2-eb95-42cf-b173-6044a40fa49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723701591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.723701591
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1068807918
Short name T316
Test name
Test status
Simulation time 1143676623 ps
CPU time 7.53 seconds
Started Apr 21 12:55:09 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 223008 kb
Host smart-cf6f89b6-3a1a-40a5-bae1-132859799d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068807918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1068807918
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3261201230
Short name T251
Test name
Test status
Simulation time 5700500032 ps
CPU time 37.72 seconds
Started Apr 21 12:55:19 PM PDT 24
Finished Apr 21 12:55:57 PM PDT 24
Peak memory 218912 kb
Host smart-a95800ce-2c4d-4067-abfe-b7c1e9a2f15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261201230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3261201230
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3947306041
Short name T229
Test name
Test status
Simulation time 55246686584 ps
CPU time 24.89 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:55:42 PM PDT 24
Peak memory 223264 kb
Host smart-be904796-bcbc-4fae-b79a-24df3360d94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947306041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3947306041
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2772211366
Short name T360
Test name
Test status
Simulation time 21356270445 ps
CPU time 17.06 seconds
Started Apr 21 12:55:31 PM PDT 24
Finished Apr 21 12:55:49 PM PDT 24
Peak memory 234336 kb
Host smart-560aa231-a8f7-4ef9-97bb-b4a72f0cf343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772211366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2772211366
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3033021865
Short name T74
Test name
Test status
Simulation time 41250434 ps
CPU time 1.33 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:14 PM PDT 24
Peak memory 216032 kb
Host smart-7cb9b87d-9c5a-44ac-879e-5134b5f2bd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033021865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3033021865
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2614410616
Short name T6
Test name
Test status
Simulation time 19041466746 ps
CPU time 228.11 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:59:28 PM PDT 24
Peak memory 263548 kb
Host smart-65ffd235-3975-4ebb-af3b-75419e123f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614410616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2614410616
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.569400312
Short name T278
Test name
Test status
Simulation time 2551275795 ps
CPU time 15.42 seconds
Started Apr 21 12:55:28 PM PDT 24
Finished Apr 21 12:55:44 PM PDT 24
Peak memory 223952 kb
Host smart-38af02b6-458c-4d66-97d6-8c06e1a8277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569400312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.569400312
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2543930407
Short name T282
Test name
Test status
Simulation time 6622496602 ps
CPU time 22.25 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:52 PM PDT 24
Peak memory 239356 kb
Host smart-03c2afa2-b53b-4f2b-85b2-498825609f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543930407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2543930407
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_upload.1844557697
Short name T317
Test name
Test status
Simulation time 265774768 ps
CPU time 2.35 seconds
Started Apr 21 12:55:42 PM PDT 24
Finished Apr 21 12:55:45 PM PDT 24
Peak memory 218560 kb
Host smart-608c9ea0-2ca0-4d12-97c3-e54fbac84f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844557697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1844557697
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_upload.1792689981
Short name T185
Test name
Test status
Simulation time 1250068860 ps
CPU time 4.16 seconds
Started Apr 21 12:55:37 PM PDT 24
Finished Apr 21 12:55:42 PM PDT 24
Peak memory 224264 kb
Host smart-eeb6be9e-629a-426c-aa2e-b66fe23dd33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792689981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1792689981
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.779750715
Short name T70
Test name
Test status
Simulation time 37644020525 ps
CPU time 11.16 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:25 PM PDT 24
Peak memory 216636 kb
Host smart-45c99865-02df-4821-81fd-ee6c57058076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779750715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
779750715
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3790042292
Short name T338
Test name
Test status
Simulation time 6431478404 ps
CPU time 7.92 seconds
Started Apr 21 12:55:55 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 222648 kb
Host smart-440c28fb-ecbe-4505-85d8-30a4b422159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790042292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3790042292
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3015765044
Short name T202
Test name
Test status
Simulation time 11564271390 ps
CPU time 14.68 seconds
Started Apr 21 12:55:35 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 234648 kb
Host smart-9099e050-e101-4a50-ab0c-c7d388da300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015765044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3015765044
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_upload.3167180662
Short name T31
Test name
Test status
Simulation time 1555886971 ps
CPU time 5.18 seconds
Started Apr 21 12:55:54 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 220552 kb
Host smart-aecba11a-dfc0-4dcc-9b4f-1507c27c0ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167180662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3167180662
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.216026566
Short name T287
Test name
Test status
Simulation time 1399220065 ps
CPU time 24.53 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:28 PM PDT 24
Peak memory 232468 kb
Host smart-1f0a8976-2c68-4964-9c4f-26bd3fbf8c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216026566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.216026566
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2263862744
Short name T220
Test name
Test status
Simulation time 1691009102 ps
CPU time 22.45 seconds
Started Apr 21 12:55:54 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 216704 kb
Host smart-d1249426-a9c0-4e45-b553-01d60e3f82e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263862744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2263862744
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.142789881
Short name T240
Test name
Test status
Simulation time 143035682 ps
CPU time 2.98 seconds
Started Apr 21 12:56:02 PM PDT 24
Finished Apr 21 12:56:06 PM PDT 24
Peak memory 224036 kb
Host smart-89944b29-aed4-4951-9d29-0978e80e5c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142789881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.142789881
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_upload.1299537299
Short name T315
Test name
Test status
Simulation time 517093435 ps
CPU time 7.82 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 216196 kb
Host smart-1052e7df-9dcd-4303-ae41-a2bf434b340d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299537299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1299537299
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_upload.1084128876
Short name T246
Test name
Test status
Simulation time 645688834 ps
CPU time 4.36 seconds
Started Apr 21 12:55:53 PM PDT 24
Finished Apr 21 12:55:59 PM PDT 24
Peak memory 223208 kb
Host smart-da6ecc91-d958-4788-b9e3-11f958b63024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084128876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1084128876
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3309088884
Short name T330
Test name
Test status
Simulation time 9996629266 ps
CPU time 17.7 seconds
Started Apr 21 12:54:55 PM PDT 24
Finished Apr 21 12:55:13 PM PDT 24
Peak memory 218864 kb
Host smart-c8cc3397-63df-4887-a371-dd67eb703e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309088884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3309088884
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3636848284
Short name T249
Test name
Test status
Simulation time 22649512979 ps
CPU time 26.22 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 240764 kb
Host smart-324489f4-1c0e-44fb-b4d4-b39bd3e822a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636848284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3636848284
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3377992647
Short name T203
Test name
Test status
Simulation time 8314498606 ps
CPU time 15.85 seconds
Started Apr 21 12:56:01 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 218860 kb
Host smart-38654d4b-bbf3-4b28-b8b7-09cc7caad6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377992647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3377992647
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_upload.1589618774
Short name T272
Test name
Test status
Simulation time 3386861183 ps
CPU time 15.65 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:20 PM PDT 24
Peak memory 218744 kb
Host smart-d51712e9-c85b-42cd-b0aa-dd1ed636165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589618774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1589618774
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1280472527
Short name T205
Test name
Test status
Simulation time 9063999026 ps
CPU time 24.77 seconds
Started Apr 21 12:56:05 PM PDT 24
Finished Apr 21 12:56:30 PM PDT 24
Peak memory 234340 kb
Host smart-8998c399-c5a5-483c-83b9-16a322d2a7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280472527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1280472527
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3832000093
Short name T63
Test name
Test status
Simulation time 4738944205 ps
CPU time 11.67 seconds
Started Apr 21 12:56:13 PM PDT 24
Finished Apr 21 12:56:25 PM PDT 24
Peak memory 224440 kb
Host smart-50849637-aa68-4af5-bdfc-9d21b49eb727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832000093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3832000093
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_intercept.314203196
Short name T266
Test name
Test status
Simulation time 693520974 ps
CPU time 4.83 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:13 PM PDT 24
Peak memory 222508 kb
Host smart-33c76ef3-6039-4bd3-9602-5b3d2282131b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314203196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.314203196
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_upload.1844627293
Short name T222
Test name
Test status
Simulation time 493667891 ps
CPU time 2.85 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:13 PM PDT 24
Peak memory 216228 kb
Host smart-9852d390-f978-4f5c-a013-11efd9a4595a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844627293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1844627293
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3593957944
Short name T341
Test name
Test status
Simulation time 689848458 ps
CPU time 3.7 seconds
Started Apr 21 12:56:21 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 218768 kb
Host smart-4c7c6f6d-bb16-424d-a50b-feb90722b03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593957944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3593957944
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3191940035
Short name T227
Test name
Test status
Simulation time 817746218 ps
CPU time 4.22 seconds
Started Apr 21 12:56:17 PM PDT 24
Finished Apr 21 12:56:21 PM PDT 24
Peak memory 223472 kb
Host smart-f9f64587-379e-4a3d-aff8-e40ff94d6048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191940035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3191940035
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1487822130
Short name T337
Test name
Test status
Simulation time 5311325576 ps
CPU time 15.11 seconds
Started Apr 21 12:56:21 PM PDT 24
Finished Apr 21 12:56:37 PM PDT 24
Peak memory 216816 kb
Host smart-d370f546-e7e4-405a-8a42-cce6bcaa925a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487822130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1487822130
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3152577970
Short name T331
Test name
Test status
Simulation time 77957595 ps
CPU time 2.62 seconds
Started Apr 21 12:56:24 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 222776 kb
Host smart-dbe47cae-b53b-4114-afc1-a5f429885d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152577970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3152577970
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.471984993
Short name T187
Test name
Test status
Simulation time 2451308433 ps
CPU time 2.74 seconds
Started Apr 21 12:55:02 PM PDT 24
Finished Apr 21 12:55:06 PM PDT 24
Peak memory 222416 kb
Host smart-bf11b311-3d25-46d3-9550-12c708d12058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471984993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
471984993
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3534966871
Short name T215
Test name
Test status
Simulation time 104392802 ps
CPU time 2.8 seconds
Started Apr 21 12:56:22 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 218628 kb
Host smart-c7bfd3cf-5f2f-4389-81ff-402bec2e6d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534966871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3534966871
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1373069668
Short name T56
Test name
Test status
Simulation time 31832153696 ps
CPU time 20.52 seconds
Started Apr 21 12:56:32 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 229592 kb
Host smart-e2df99d5-0eb3-49ac-8a8f-9d233e32157e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373069668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1373069668
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3712216815
Short name T254
Test name
Test status
Simulation time 230305977 ps
CPU time 2.69 seconds
Started Apr 21 12:56:46 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 223060 kb
Host smart-e5ab5926-55de-41ce-952e-bac901caef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712216815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3712216815
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.468891936
Short name T333
Test name
Test status
Simulation time 5262640331 ps
CPU time 7.73 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:56:57 PM PDT 24
Peak memory 219844 kb
Host smart-964c4e92-99fc-4585-be19-6d1482a2cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468891936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.468891936
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2672768336
Short name T200
Test name
Test status
Simulation time 286666894 ps
CPU time 3.29 seconds
Started Apr 21 12:55:02 PM PDT 24
Finished Apr 21 12:55:06 PM PDT 24
Peak memory 222648 kb
Host smart-faaa5437-aec6-4224-9619-c0ff5b4ac993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672768336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2672768336
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1878203692
Short name T194
Test name
Test status
Simulation time 5561210710 ps
CPU time 7.99 seconds
Started Apr 21 12:55:04 PM PDT 24
Finished Apr 21 12:55:12 PM PDT 24
Peak memory 235236 kb
Host smart-b358d060-1c04-494a-b674-9a68dd7fdbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878203692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1878203692
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3271409170
Short name T334
Test name
Test status
Simulation time 4039209748 ps
CPU time 7.39 seconds
Started Apr 21 12:55:00 PM PDT 24
Finished Apr 21 12:55:08 PM PDT 24
Peak memory 233776 kb
Host smart-cdebaf51-4ffa-4d15-b831-61f5d10a735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271409170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3271409170
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3071164324
Short name T98
Test name
Test status
Simulation time 53206944 ps
CPU time 1.21 seconds
Started Apr 21 12:38:40 PM PDT 24
Finished Apr 21 12:38:41 PM PDT 24
Peak memory 206928 kb
Host smart-eaa4d468-053e-46aa-b383-cc412536148d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071164324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3071164324
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1545336550
Short name T87
Test name
Test status
Simulation time 519853602 ps
CPU time 6.79 seconds
Started Apr 21 12:56:12 PM PDT 24
Finished Apr 21 12:56:19 PM PDT 24
Peak memory 223036 kb
Host smart-d6d1320f-1218-4883-830e-68dbe933fbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545336550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1545336550
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1119113147
Short name T142
Test name
Test status
Simulation time 758693463 ps
CPU time 20.75 seconds
Started Apr 21 12:38:46 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 206912 kb
Host smart-3f3311b3-8b3e-43cc-92c2-e0ab42b90bda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119113147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1119113147
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.84888033
Short name T145
Test name
Test status
Simulation time 9488447322 ps
CPU time 38.42 seconds
Started Apr 21 12:38:36 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 215296 kb
Host smart-e3e5ba7d-97e8-4fc8-b370-0b8ec2a7b44a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84888033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
bit_bash.84888033
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3483317375
Short name T835
Test name
Test status
Simulation time 49092170 ps
CPU time 1.36 seconds
Started Apr 21 12:38:52 PM PDT 24
Finished Apr 21 12:38:54 PM PDT 24
Peak memory 216136 kb
Host smart-0a851afc-2c00-4c50-b7b0-3935a477f866
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483317375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3483317375
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.954571114
Short name T815
Test name
Test status
Simulation time 927454466 ps
CPU time 2.78 seconds
Started Apr 21 12:38:58 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 217948 kb
Host smart-461aee03-5090-46ab-81ab-6de9db39ce9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954571114 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.954571114
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1844861374
Short name T805
Test name
Test status
Simulation time 208359527 ps
CPU time 2.42 seconds
Started Apr 21 12:39:11 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 215096 kb
Host smart-1ccd40e1-195d-4ae9-93af-ed11a335ad19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844861374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
844861374
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1814315245
Short name T763
Test name
Test status
Simulation time 27875735 ps
CPU time 0.73 seconds
Started Apr 21 12:38:41 PM PDT 24
Finished Apr 21 12:38:42 PM PDT 24
Peak memory 203976 kb
Host smart-667e03e0-4b5a-4f2a-836a-5e4c3364d997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814315245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
814315245
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1725659904
Short name T785
Test name
Test status
Simulation time 96970882 ps
CPU time 2.01 seconds
Started Apr 21 12:38:54 PM PDT 24
Finished Apr 21 12:38:56 PM PDT 24
Peak memory 215236 kb
Host smart-ee5e0c7f-7fd3-41d9-9512-0c780cc10bd7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725659904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1725659904
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.658462781
Short name T792
Test name
Test status
Simulation time 117860889 ps
CPU time 0.63 seconds
Started Apr 21 12:39:01 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 203892 kb
Host smart-acc7ec7b-babc-46fa-b326-70b0632c189b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658462781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.658462781
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1887276259
Short name T800
Test name
Test status
Simulation time 70778515 ps
CPU time 1.86 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 215152 kb
Host smart-90277c06-430d-4cab-b722-18cfd5622f11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887276259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1887276259
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3826462592
Short name T755
Test name
Test status
Simulation time 71729116 ps
CPU time 4.06 seconds
Started Apr 21 12:38:57 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 215300 kb
Host smart-aad735c6-f4d7-4d66-8ef2-50336b540f67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826462592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
826462592
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1948882145
Short name T735
Test name
Test status
Simulation time 210065468 ps
CPU time 14.97 seconds
Started Apr 21 12:38:56 PM PDT 24
Finished Apr 21 12:39:12 PM PDT 24
Peak memory 215160 kb
Host smart-ad4c166b-a118-4545-a687-68da2e7b3a7a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948882145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1948882145
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2315768046
Short name T146
Test name
Test status
Simulation time 1813387744 ps
CPU time 13.64 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 206988 kb
Host smart-c3319a83-920d-4d06-aee1-8b020ca13768
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315768046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2315768046
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2069087731
Short name T764
Test name
Test status
Simulation time 46877761 ps
CPU time 1.9 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 215216 kb
Host smart-4bd4dc06-2611-4483-9ad2-9c2c4d9741a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069087731 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2069087731
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.890335799
Short name T765
Test name
Test status
Simulation time 139171347 ps
CPU time 2.39 seconds
Started Apr 21 12:38:38 PM PDT 24
Finished Apr 21 12:38:41 PM PDT 24
Peak memory 215144 kb
Host smart-50cfd2fa-e3a9-4e08-b0d2-2574c8917817
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890335799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.890335799
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2057159960
Short name T758
Test name
Test status
Simulation time 16146217 ps
CPU time 0.78 seconds
Started Apr 21 12:39:16 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 203688 kb
Host smart-29297520-7b00-4ca7-ac65-aa74d2aba0a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057159960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
057159960
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3476499068
Short name T802
Test name
Test status
Simulation time 39296229 ps
CPU time 1.36 seconds
Started Apr 21 12:39:34 PM PDT 24
Finished Apr 21 12:39:36 PM PDT 24
Peak memory 215248 kb
Host smart-39f9e2fd-34fe-4ca0-bfb4-985b2243479a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476499068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3476499068
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.284710776
Short name T732
Test name
Test status
Simulation time 18347068 ps
CPU time 0.71 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:54 PM PDT 24
Peak memory 203512 kb
Host smart-ca68d598-eadf-4e12-82d3-5a9f08721948
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284710776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.284710776
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1009713302
Short name T153
Test name
Test status
Simulation time 49293715 ps
CPU time 1.81 seconds
Started Apr 21 12:39:03 PM PDT 24
Finished Apr 21 12:39:05 PM PDT 24
Peak memory 215048 kb
Host smart-b5ea8669-3b35-4d0c-a13e-5d73a17efca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009713302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1009713302
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.236260150
Short name T781
Test name
Test status
Simulation time 132774516 ps
CPU time 1.87 seconds
Started Apr 21 12:38:41 PM PDT 24
Finished Apr 21 12:38:44 PM PDT 24
Peak memory 215300 kb
Host smart-8fe22ad9-2145-42b2-a3ba-e7ab56cccac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236260150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.236260150
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1205346641
Short name T742
Test name
Test status
Simulation time 800012659 ps
CPU time 14.04 seconds
Started Apr 21 12:38:59 PM PDT 24
Finished Apr 21 12:39:14 PM PDT 24
Peak memory 215512 kb
Host smart-f023d766-a8d0-434f-a7ab-d984e9515ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205346641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1205346641
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.342078715
Short name T157
Test name
Test status
Simulation time 420895158 ps
CPU time 2.71 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 217488 kb
Host smart-d988d86b-1b53-48bc-9477-5c8074ec48bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342078715 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.342078715
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.457871591
Short name T149
Test name
Test status
Simulation time 65105182 ps
CPU time 2.55 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:21 PM PDT 24
Peak memory 215136 kb
Host smart-c6537719-99cc-4dbd-8a75-507a5952c918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457871591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.457871591
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1764115821
Short name T804
Test name
Test status
Simulation time 16903108 ps
CPU time 0.74 seconds
Started Apr 21 12:39:07 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 203904 kb
Host smart-d63eab2b-478f-4f1f-ae83-7a4713a0d0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764115821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1764115821
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3745385777
Short name T744
Test name
Test status
Simulation time 94860772 ps
CPU time 1.64 seconds
Started Apr 21 12:39:16 PM PDT 24
Finished Apr 21 12:39:19 PM PDT 24
Peak memory 215128 kb
Host smart-d95f5cd5-dba6-4cf4-b21a-b2067d0b2595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745385777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3745385777
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4019092041
Short name T756
Test name
Test status
Simulation time 264534060 ps
CPU time 3.5 seconds
Started Apr 21 12:39:08 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 215420 kb
Host smart-c1cb8665-46d7-4e1e-9f34-1f44f0c0b44d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019092041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4019092041
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3378614524
Short name T136
Test name
Test status
Simulation time 785367363 ps
CPU time 12.23 seconds
Started Apr 21 12:38:47 PM PDT 24
Finished Apr 21 12:39:00 PM PDT 24
Peak memory 215120 kb
Host smart-bae6ed17-43fc-451a-a1c4-6980f977095c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378614524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3378614524
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3189528792
Short name T37
Test name
Test status
Simulation time 78568531 ps
CPU time 2.7 seconds
Started Apr 21 12:38:58 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 216336 kb
Host smart-12e7cc72-f1fc-4a15-b24b-8a3216cd404c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189528792 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3189528792
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1212304294
Short name T825
Test name
Test status
Simulation time 46317620 ps
CPU time 1.42 seconds
Started Apr 21 12:38:47 PM PDT 24
Finished Apr 21 12:38:49 PM PDT 24
Peak memory 215188 kb
Host smart-81282b86-0a61-45fb-a7fd-ce4e04c3317c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212304294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1212304294
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4004038355
Short name T780
Test name
Test status
Simulation time 56244730 ps
CPU time 0.72 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 203660 kb
Host smart-8459627e-ac8b-4ded-90f8-0034b8b183c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004038355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4004038355
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.714512277
Short name T766
Test name
Test status
Simulation time 149887750 ps
CPU time 2.71 seconds
Started Apr 21 12:38:58 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 215132 kb
Host smart-b84e76bf-0fb0-4b5c-89d5-6fc90f3c6961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714512277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.714512277
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3824196969
Short name T132
Test name
Test status
Simulation time 53381086 ps
CPU time 2.19 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 216236 kb
Host smart-d64f5a1b-f848-4bd2-b272-725f9f00c157
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824196969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3824196969
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2384027949
Short name T829
Test name
Test status
Simulation time 270379790 ps
CPU time 3.88 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 218116 kb
Host smart-125ada38-27a1-4ed1-974c-9efcfbc9977a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384027949 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2384027949
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3209078078
Short name T818
Test name
Test status
Simulation time 31740800 ps
CPU time 1.93 seconds
Started Apr 21 12:38:58 PM PDT 24
Finished Apr 21 12:39:00 PM PDT 24
Peak memory 215228 kb
Host smart-20d5c01b-c282-4fbe-ae7b-cf077c5a677e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209078078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3209078078
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2157751053
Short name T731
Test name
Test status
Simulation time 29847703 ps
CPU time 0.72 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 203580 kb
Host smart-8ec46065-cc6c-4342-82a1-9774dc7166d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157751053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2157751053
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2699584176
Short name T812
Test name
Test status
Simulation time 210671605 ps
CPU time 2.89 seconds
Started Apr 21 12:39:04 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 215136 kb
Host smart-3f24c087-4f4a-45de-8f5f-d9c2a5c8192b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699584176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2699584176
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.374892024
Short name T129
Test name
Test status
Simulation time 105547049 ps
CPU time 2.65 seconds
Started Apr 21 12:38:50 PM PDT 24
Finished Apr 21 12:38:53 PM PDT 24
Peak memory 215280 kb
Host smart-e078f1a4-6774-41e1-8b0c-f6069e2b6ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374892024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.374892024
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3391733104
Short name T790
Test name
Test status
Simulation time 653101508 ps
CPU time 3.48 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 217032 kb
Host smart-8af049e0-35bb-4b7f-8588-359800777a09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391733104 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3391733104
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3417091408
Short name T144
Test name
Test status
Simulation time 39973181 ps
CPU time 2.49 seconds
Started Apr 21 12:39:03 PM PDT 24
Finished Apr 21 12:39:06 PM PDT 24
Peak memory 206948 kb
Host smart-d22b50ae-be5d-4340-b6ed-eea314c81943
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417091408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3417091408
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1365444521
Short name T729
Test name
Test status
Simulation time 15596441 ps
CPU time 0.72 seconds
Started Apr 21 12:38:59 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 203568 kb
Host smart-8be3460b-c3cd-4baa-af3b-e7007913affe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365444521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1365444521
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.487181715
Short name T155
Test name
Test status
Simulation time 96532098 ps
CPU time 1.77 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:16 PM PDT 24
Peak memory 215100 kb
Host smart-480f29db-fa7f-4cec-9a05-4a10605d4430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487181715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.487181715
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4244209623
Short name T809
Test name
Test status
Simulation time 1055929615 ps
CPU time 23.5 seconds
Started Apr 21 12:39:07 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 215172 kb
Host smart-45f76d2e-e678-4321-80bf-4838d3148535
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244209623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4244209623
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4140492604
Short name T801
Test name
Test status
Simulation time 100372319 ps
CPU time 2.09 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 216144 kb
Host smart-af5ce378-0d10-4507-925f-105b217547e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140492604 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4140492604
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2773587958
Short name T821
Test name
Test status
Simulation time 636139913 ps
CPU time 1.66 seconds
Started Apr 21 12:39:04 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 206916 kb
Host smart-9f599bbc-93ae-4e7f-aa43-8590d52a42f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773587958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2773587958
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2996389052
Short name T726
Test name
Test status
Simulation time 16886593 ps
CPU time 0.75 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 203896 kb
Host smart-6f0a56a4-2299-4dd9-a0cf-565f17953cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996389052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2996389052
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3605701972
Short name T787
Test name
Test status
Simulation time 81923400 ps
CPU time 2.02 seconds
Started Apr 21 12:39:19 PM PDT 24
Finished Apr 21 12:39:22 PM PDT 24
Peak memory 215072 kb
Host smart-e4bb0ae9-06ff-4b1f-a2d1-0b82f8f27cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605701972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3605701972
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.864233526
Short name T727
Test name
Test status
Simulation time 1225475851 ps
CPU time 2.69 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:04 PM PDT 24
Peak memory 217148 kb
Host smart-bee7e2c0-3f69-4d55-8a14-adcfccb8d6ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864233526 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.864233526
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3367802001
Short name T154
Test name
Test status
Simulation time 41152060 ps
CPU time 1.23 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 207016 kb
Host smart-d7bdde54-b616-4957-b2ce-82d36c02df2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367802001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3367802001
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2331916838
Short name T833
Test name
Test status
Simulation time 20679656 ps
CPU time 0.72 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:02 PM PDT 24
Peak memory 203668 kb
Host smart-90891dfb-dce9-44f4-abc6-5008d0ef6dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331916838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2331916838
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1622964920
Short name T799
Test name
Test status
Simulation time 112164381 ps
CPU time 2.86 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:09 PM PDT 24
Peak memory 215036 kb
Host smart-fae429c7-3e0d-482b-a6ff-101eb303ba6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622964920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1622964920
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.833276534
Short name T795
Test name
Test status
Simulation time 162467690 ps
CPU time 2.45 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 215324 kb
Host smart-28d00999-eed7-4341-ad45-6256212b8d06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833276534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.833276534
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.305313085
Short name T36
Test name
Test status
Simulation time 2309664786 ps
CPU time 7.98 seconds
Started Apr 21 12:39:16 PM PDT 24
Finished Apr 21 12:39:25 PM PDT 24
Peak memory 215232 kb
Host smart-1f1177d1-68ea-4a81-a22d-93192406a0ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305313085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.305313085
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1817926484
Short name T128
Test name
Test status
Simulation time 268925975 ps
CPU time 3.49 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:10 PM PDT 24
Peak memory 216852 kb
Host smart-6a7b2ad5-da38-470f-88e5-ab4e69cd6e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817926484 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1817926484
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2400182575
Short name T771
Test name
Test status
Simulation time 174882514 ps
CPU time 2.29 seconds
Started Apr 21 12:39:12 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 215108 kb
Host smart-c3562002-6d1b-4350-ab9e-61d7c8d91c7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400182575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2400182575
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2837710548
Short name T749
Test name
Test status
Simulation time 13517101 ps
CPU time 0.75 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 203668 kb
Host smart-3f591856-6e23-4d20-8125-e020967d840b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837710548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2837710548
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.654694782
Short name T767
Test name
Test status
Simulation time 708845387 ps
CPU time 3.69 seconds
Started Apr 21 12:38:50 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 215124 kb
Host smart-3193df7d-30a5-4bd1-af90-c9db821b1f76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654694782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.654694782
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2626146619
Short name T127
Test name
Test status
Simulation time 68201506 ps
CPU time 1.9 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:16 PM PDT 24
Peak memory 215316 kb
Host smart-3f7b2d82-6651-4ac3-822a-5c62059c6a16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626146619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2626146619
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1840734622
Short name T797
Test name
Test status
Simulation time 5213647173 ps
CPU time 7.56 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 215288 kb
Host smart-9821bcb0-1edf-4d4f-870f-a2b8b315be5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840734622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1840734622
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4024057951
Short name T159
Test name
Test status
Simulation time 422461241 ps
CPU time 2.8 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 217364 kb
Host smart-1963c7ef-c9ac-4635-946f-fd89565935c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024057951 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4024057951
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3575540053
Short name T828
Test name
Test status
Simulation time 33615703 ps
CPU time 1.22 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 206952 kb
Host smart-ed68adac-b0a1-48b9-925a-5ffa5e09a16d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575540053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3575540053
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2703672032
Short name T741
Test name
Test status
Simulation time 14206373 ps
CPU time 0.71 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:25 PM PDT 24
Peak memory 203504 kb
Host smart-36db6f63-20c5-4bb7-ab20-7fc10eed7bd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703672032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2703672032
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.47225904
Short name T807
Test name
Test status
Simulation time 98894225 ps
CPU time 1.92 seconds
Started Apr 21 12:39:09 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 215164 kb
Host smart-2d36835e-ca36-45d8-befe-d685e0337c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47225904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sp
i_device_same_csr_outstanding.47225904
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.998579746
Short name T748
Test name
Test status
Simulation time 917411680 ps
CPU time 4.84 seconds
Started Apr 21 12:38:56 PM PDT 24
Finished Apr 21 12:39:02 PM PDT 24
Peak memory 216276 kb
Host smart-5a301d75-66bc-44f0-ad0d-ae49f26f1cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998579746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.998579746
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1639850235
Short name T366
Test name
Test status
Simulation time 536507910 ps
CPU time 7.31 seconds
Started Apr 21 12:38:43 PM PDT 24
Finished Apr 21 12:38:51 PM PDT 24
Peak memory 215120 kb
Host smart-24a9d1ab-36ad-49b9-94ee-fa0748ebd820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639850235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1639850235
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.346959637
Short name T791
Test name
Test status
Simulation time 100131198 ps
CPU time 1.57 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 215220 kb
Host smart-54f3d7e1-ad37-4cd6-90da-3e912df99746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346959637 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.346959637
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3135652726
Short name T140
Test name
Test status
Simulation time 141572982 ps
CPU time 2.29 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:56 PM PDT 24
Peak memory 215232 kb
Host smart-a50775e4-0580-4a6d-a1b0-ea989baf68d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135652726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3135652726
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1218582988
Short name T722
Test name
Test status
Simulation time 22395074 ps
CPU time 0.73 seconds
Started Apr 21 12:39:32 PM PDT 24
Finished Apr 21 12:39:34 PM PDT 24
Peak memory 203624 kb
Host smart-7310951d-c1a8-415d-be01-59489bc82a86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218582988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1218582988
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3164689312
Short name T770
Test name
Test status
Simulation time 302856492 ps
CPU time 1.9 seconds
Started Apr 21 12:39:02 PM PDT 24
Finished Apr 21 12:39:05 PM PDT 24
Peak memory 215224 kb
Host smart-cc3afe9a-de28-48b3-9858-a7ad5b5875d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164689312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3164689312
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1436076671
Short name T118
Test name
Test status
Simulation time 29864145 ps
CPU time 1.87 seconds
Started Apr 21 12:39:24 PM PDT 24
Finished Apr 21 12:39:27 PM PDT 24
Peak memory 215312 kb
Host smart-2b2e79da-e89c-4c56-b277-f8953222d9ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436076671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1436076671
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2466749757
Short name T365
Test name
Test status
Simulation time 1558368146 ps
CPU time 8.87 seconds
Started Apr 21 12:39:09 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 215300 kb
Host smart-0fe589e1-1b3b-4f57-a128-f10b3e5461c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466749757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2466749757
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3314847720
Short name T134
Test name
Test status
Simulation time 105118737 ps
CPU time 1.71 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:13 PM PDT 24
Peak memory 216272 kb
Host smart-9f3d15ae-d847-434e-b822-cb567fbedcbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314847720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3314847720
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3242447293
Short name T141
Test name
Test status
Simulation time 64478849 ps
CPU time 2.01 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 215216 kb
Host smart-e006a7c8-66d0-4d40-9cac-3ee1809d18a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242447293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3242447293
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4274733239
Short name T816
Test name
Test status
Simulation time 18649042 ps
CPU time 0.77 seconds
Started Apr 21 12:39:29 PM PDT 24
Finished Apr 21 12:39:31 PM PDT 24
Peak memory 203628 kb
Host smart-75d12dec-4f63-4406-a6b6-d0749cfb4b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274733239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4274733239
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3974796303
Short name T794
Test name
Test status
Simulation time 262126729 ps
CPU time 3.62 seconds
Started Apr 21 12:39:09 PM PDT 24
Finished Apr 21 12:39:13 PM PDT 24
Peak memory 215184 kb
Host smart-7d22e125-855d-477b-82d1-eeaec850550f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974796303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3974796303
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3792519895
Short name T126
Test name
Test status
Simulation time 470306548 ps
CPU time 3.79 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 215480 kb
Host smart-27bfa247-acff-4b47-aeb2-50f6f0d24936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792519895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3792519895
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2613181200
Short name T772
Test name
Test status
Simulation time 554185560 ps
CPU time 7.23 seconds
Started Apr 21 12:39:04 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 215112 kb
Host smart-43cf5f98-b78b-41ae-9a9b-43d83848b856
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613181200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2613181200
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3309653526
Short name T39
Test name
Test status
Simulation time 3103493549 ps
CPU time 15.39 seconds
Started Apr 21 12:38:45 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 207008 kb
Host smart-e5175ecc-5708-4b8e-97d0-b43ff3c6db91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309653526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3309653526
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.632827430
Short name T747
Test name
Test status
Simulation time 3619593776 ps
CPU time 37.3 seconds
Started Apr 21 12:39:09 PM PDT 24
Finished Apr 21 12:39:47 PM PDT 24
Peak memory 215248 kb
Host smart-744cd642-669f-4857-8c89-20768529aaa7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632827430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.632827430
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3257072281
Short name T101
Test name
Test status
Simulation time 140382065 ps
CPU time 1.13 seconds
Started Apr 21 12:38:43 PM PDT 24
Finished Apr 21 12:38:45 PM PDT 24
Peak memory 216156 kb
Host smart-02f3a422-e47e-4db0-b0e1-3c2a90143ecc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257072281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3257072281
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3251889437
Short name T782
Test name
Test status
Simulation time 36491911 ps
CPU time 2.55 seconds
Started Apr 21 12:38:57 PM PDT 24
Finished Apr 21 12:39:00 PM PDT 24
Peak memory 216968 kb
Host smart-d2214e4f-d02a-48e1-b690-3f1504b56a8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251889437 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3251889437
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1812529549
Short name T148
Test name
Test status
Simulation time 253086785 ps
CPU time 2.63 seconds
Started Apr 21 12:38:51 PM PDT 24
Finished Apr 21 12:38:54 PM PDT 24
Peak memory 206988 kb
Host smart-dd809b4c-241e-4431-b3fc-f3fa21741d6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812529549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
812529549
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3723585687
Short name T832
Test name
Test status
Simulation time 69146888 ps
CPU time 0.71 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:50 PM PDT 24
Peak memory 203668 kb
Host smart-56464955-27b6-4953-a3d3-a1579969db5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723585687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
723585687
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.120220949
Short name T827
Test name
Test status
Simulation time 20241597 ps
CPU time 1.21 seconds
Started Apr 21 12:39:08 PM PDT 24
Finished Apr 21 12:39:10 PM PDT 24
Peak memory 215212 kb
Host smart-00584149-b957-479b-97fd-236c8193606a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120220949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.120220949
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4290810277
Short name T738
Test name
Test status
Simulation time 12683183 ps
CPU time 0.66 seconds
Started Apr 21 12:39:12 PM PDT 24
Finished Apr 21 12:39:14 PM PDT 24
Peak memory 203560 kb
Host smart-b298e937-d15c-48c1-a24e-098af0de68a1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290810277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4290810277
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3111531072
Short name T769
Test name
Test status
Simulation time 229967128 ps
CPU time 1.85 seconds
Started Apr 21 12:38:52 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 215220 kb
Host smart-74718647-136e-45d7-a12a-5b50e6c79cfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111531072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3111531072
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2484375595
Short name T762
Test name
Test status
Simulation time 123105614 ps
CPU time 1.79 seconds
Started Apr 21 12:38:42 PM PDT 24
Finished Apr 21 12:38:44 PM PDT 24
Peak memory 215372 kb
Host smart-63fc54e5-2464-4dfd-978a-f5d9f0b6d222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484375595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
484375595
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1455594415
Short name T35
Test name
Test status
Simulation time 1207763072 ps
CPU time 18.13 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:36 PM PDT 24
Peak memory 216984 kb
Host smart-5b162136-f46a-45c0-9893-d2dce9c546ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455594415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1455594415
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1612053645
Short name T798
Test name
Test status
Simulation time 17093713 ps
CPU time 0.66 seconds
Started Apr 21 12:39:10 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 203584 kb
Host smart-ea3f487e-e10a-4fdf-8a74-33bcef017854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612053645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1612053645
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4109728984
Short name T796
Test name
Test status
Simulation time 44973574 ps
CPU time 0.77 seconds
Started Apr 21 12:39:14 PM PDT 24
Finished Apr 21 12:39:16 PM PDT 24
Peak memory 203652 kb
Host smart-bc22e79d-f2b2-45e3-9e1e-385957df76c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109728984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4109728984
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3615280793
Short name T826
Test name
Test status
Simulation time 13412592 ps
CPU time 0.74 seconds
Started Apr 21 12:39:23 PM PDT 24
Finished Apr 21 12:39:24 PM PDT 24
Peak memory 203580 kb
Host smart-f52fbee2-4522-40a4-9936-a658670a9b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615280793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3615280793
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3808548253
Short name T761
Test name
Test status
Simulation time 241098464 ps
CPU time 0.73 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 203616 kb
Host smart-f5c9b512-11ca-4b77-b22d-d550d3467f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808548253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3808548253
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4209934423
Short name T724
Test name
Test status
Simulation time 20364205 ps
CPU time 0.69 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 203652 kb
Host smart-7c16b0a4-e3de-4165-9b9b-a3c93d223a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209934423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4209934423
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3349451446
Short name T745
Test name
Test status
Simulation time 29999183 ps
CPU time 0.76 seconds
Started Apr 21 12:39:32 PM PDT 24
Finished Apr 21 12:39:39 PM PDT 24
Peak memory 203604 kb
Host smart-c11d31f7-5b69-42f1-9347-aeeee1d58f5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349451446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3349451446
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.451322463
Short name T822
Test name
Test status
Simulation time 62973792 ps
CPU time 0.74 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 203872 kb
Host smart-17a807f4-c934-42f1-a123-a862492c763a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451322463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.451322463
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.789443638
Short name T788
Test name
Test status
Simulation time 45005643 ps
CPU time 0.73 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 203876 kb
Host smart-066b0a96-4c73-479a-93e0-bb92b684b124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789443638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.789443638
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1122154521
Short name T736
Test name
Test status
Simulation time 11956253 ps
CPU time 0.72 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 203656 kb
Host smart-be8792e7-2748-4095-97bd-8129cbb1021e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122154521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1122154521
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2986425968
Short name T784
Test name
Test status
Simulation time 202838158 ps
CPU time 14.56 seconds
Started Apr 21 12:38:44 PM PDT 24
Finished Apr 21 12:38:59 PM PDT 24
Peak memory 206968 kb
Host smart-97284aa0-0240-4fcd-af53-430d5d9622b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986425968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2986425968
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2927815895
Short name T751
Test name
Test status
Simulation time 936300075 ps
CPU time 13.9 seconds
Started Apr 21 12:38:57 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 206924 kb
Host smart-3ca33f4e-4d5a-42d6-8c94-23f6807eb4a6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927815895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2927815895
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3648541644
Short name T100
Test name
Test status
Simulation time 75484765 ps
CPU time 0.95 seconds
Started Apr 21 12:38:48 PM PDT 24
Finished Apr 21 12:38:49 PM PDT 24
Peak memory 206744 kb
Host smart-6089c2c2-4c44-42a7-9f80-ae79cfd4787c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648541644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3648541644
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3209550822
Short name T779
Test name
Test status
Simulation time 473016257 ps
CPU time 3.65 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:18 PM PDT 24
Peak memory 216936 kb
Host smart-e3c63d46-78b5-4e4b-a39d-5c2be1924691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209550822 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3209550822
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1392783720
Short name T817
Test name
Test status
Simulation time 53525289 ps
CPU time 0.74 seconds
Started Apr 21 12:39:08 PM PDT 24
Finished Apr 21 12:39:10 PM PDT 24
Peak memory 203800 kb
Host smart-8558a362-e13a-4a9f-bd1a-05b5633f5627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392783720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
392783720
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3054435895
Short name T143
Test name
Test status
Simulation time 76296083 ps
CPU time 2.36 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:55 PM PDT 24
Peak memory 215176 kb
Host smart-5558680d-5915-47cb-844c-9b942acd558e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054435895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3054435895
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3264450410
Short name T737
Test name
Test status
Simulation time 41649631 ps
CPU time 0.66 seconds
Started Apr 21 12:38:43 PM PDT 24
Finished Apr 21 12:38:44 PM PDT 24
Peak memory 203824 kb
Host smart-b4dbf87f-e418-46b3-b5c8-ee40fe15b89d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264450410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3264450410
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.193021857
Short name T760
Test name
Test status
Simulation time 612833724 ps
CPU time 4.08 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:06 PM PDT 24
Peak memory 215016 kb
Host smart-6d00f01d-a0f0-400f-b9d0-a53a59152200
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193021857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.193021857
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1212975760
Short name T776
Test name
Test status
Simulation time 170919665 ps
CPU time 3 seconds
Started Apr 21 12:38:56 PM PDT 24
Finished Apr 21 12:38:59 PM PDT 24
Peak memory 215312 kb
Host smart-8e571e27-f429-407a-ba3c-c139b2c8a112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212975760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
212975760
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.34926901
Short name T813
Test name
Test status
Simulation time 382677585 ps
CPU time 8.24 seconds
Started Apr 21 12:38:52 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 215664 kb
Host smart-f68ecc8c-9c3e-49e9-962a-f5049d33f79f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34926901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_t
l_intg_err.34926901
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3053230910
Short name T777
Test name
Test status
Simulation time 13557477 ps
CPU time 0.74 seconds
Started Apr 21 12:39:37 PM PDT 24
Finished Apr 21 12:39:38 PM PDT 24
Peak memory 203644 kb
Host smart-81b01047-ed98-4a70-9cd9-f53d4104a331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053230910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3053230910
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1658402249
Short name T740
Test name
Test status
Simulation time 26405786 ps
CPU time 0.69 seconds
Started Apr 21 12:39:16 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 203572 kb
Host smart-951cb9b6-8ed5-48f8-b82d-eec40ae23699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658402249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1658402249
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.9061573
Short name T823
Test name
Test status
Simulation time 20329002 ps
CPU time 0.73 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:02 PM PDT 24
Peak memory 203644 kb
Host smart-fd3e5955-a4bc-4024-9cdb-2d1744c68389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9061573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.9061573
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.774296321
Short name T824
Test name
Test status
Simulation time 16062534 ps
CPU time 0.71 seconds
Started Apr 21 12:39:01 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 203616 kb
Host smart-86fbe385-a466-4618-a2cb-a84db4e94444
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774296321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.774296321
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3846357789
Short name T819
Test name
Test status
Simulation time 30224893 ps
CPU time 0.7 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 203596 kb
Host smart-a7756ef2-ed78-4aa2-984e-fd1035aff096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846357789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3846357789
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2683368185
Short name T806
Test name
Test status
Simulation time 21650235 ps
CPU time 0.7 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 203580 kb
Host smart-47a37c46-7884-420f-93ce-6e9b59723ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683368185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2683368185
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1839588115
Short name T728
Test name
Test status
Simulation time 14744109 ps
CPU time 0.78 seconds
Started Apr 21 12:39:17 PM PDT 24
Finished Apr 21 12:39:19 PM PDT 24
Peak memory 203680 kb
Host smart-fa879b1b-f1a5-46d5-9ab1-c14f4b6c13a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839588115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1839588115
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3295378629
Short name T746
Test name
Test status
Simulation time 15221673 ps
CPU time 0.73 seconds
Started Apr 21 12:39:15 PM PDT 24
Finished Apr 21 12:39:16 PM PDT 24
Peak memory 203868 kb
Host smart-37fd0f6e-f9a3-4f99-b227-e1798981c160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295378629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3295378629
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1518825211
Short name T739
Test name
Test status
Simulation time 14675713 ps
CPU time 0.73 seconds
Started Apr 21 12:39:14 PM PDT 24
Finished Apr 21 12:39:16 PM PDT 24
Peak memory 203536 kb
Host smart-ed7c6643-abe3-4e02-9e97-9f1d030f360a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518825211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1518825211
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1837359737
Short name T775
Test name
Test status
Simulation time 48178792 ps
CPU time 0.77 seconds
Started Apr 21 12:39:20 PM PDT 24
Finished Apr 21 12:39:21 PM PDT 24
Peak memory 203460 kb
Host smart-b8b49738-1fae-4b9b-bd79-5904cb679773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837359737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1837359737
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3116170694
Short name T768
Test name
Test status
Simulation time 872630711 ps
CPU time 17.41 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:23 PM PDT 24
Peak memory 215096 kb
Host smart-d29b89a4-d8fd-413a-a1bd-4dca9d7cc459
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116170694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3116170694
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2412520368
Short name T789
Test name
Test status
Simulation time 1865106003 ps
CPU time 35.96 seconds
Started Apr 21 12:38:48 PM PDT 24
Finished Apr 21 12:39:24 PM PDT 24
Peak memory 206828 kb
Host smart-084d4da4-a897-4666-b566-41012bb1961d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412520368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2412520368
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3322576197
Short name T99
Test name
Test status
Simulation time 41759767 ps
CPU time 1.37 seconds
Started Apr 21 12:39:07 PM PDT 24
Finished Apr 21 12:39:09 PM PDT 24
Peak memory 216132 kb
Host smart-b8b05add-6ebc-47c9-880c-62d74d9632f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322576197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3322576197
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1764478947
Short name T133
Test name
Test status
Simulation time 199317911 ps
CPU time 3.62 seconds
Started Apr 21 12:39:07 PM PDT 24
Finished Apr 21 12:39:11 PM PDT 24
Peak memory 217052 kb
Host smart-9d9f86aa-d8f7-4f83-8141-72bdb2a97d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764478947 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1764478947
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2173604243
Short name T752
Test name
Test status
Simulation time 18736269 ps
CPU time 1.14 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:08 PM PDT 24
Peak memory 206960 kb
Host smart-30994557-4a4c-4f33-ab1c-31d391b02b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173604243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
173604243
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2317502637
Short name T783
Test name
Test status
Simulation time 21845987 ps
CPU time 0.7 seconds
Started Apr 21 12:38:46 PM PDT 24
Finished Apr 21 12:38:47 PM PDT 24
Peak memory 203604 kb
Host smart-dce4d624-d98b-43f4-a508-ccc336dac503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317502637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
317502637
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4100799992
Short name T150
Test name
Test status
Simulation time 55430284 ps
CPU time 1.77 seconds
Started Apr 21 12:38:50 PM PDT 24
Finished Apr 21 12:38:53 PM PDT 24
Peak memory 215208 kb
Host smart-1a5375c1-f6ef-4ed3-9ded-576cae36292d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100799992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4100799992
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3675186845
Short name T743
Test name
Test status
Simulation time 30058823 ps
CPU time 0.64 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:50 PM PDT 24
Peak memory 203536 kb
Host smart-cb915a49-c815-46f9-9a73-d43a53a2c69a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675186845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3675186845
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.894591212
Short name T38
Test name
Test status
Simulation time 63067758 ps
CPU time 3.54 seconds
Started Apr 21 12:39:02 PM PDT 24
Finished Apr 21 12:39:06 PM PDT 24
Peak memory 215052 kb
Host smart-14613d1d-a549-464c-932e-0e010bd1af24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894591212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.894591212
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2666235423
Short name T111
Test name
Test status
Simulation time 160901870 ps
CPU time 2.63 seconds
Started Apr 21 12:39:04 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 216332 kb
Host smart-a66d23be-ee90-4c26-8aa6-989dfb1268f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666235423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
666235423
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2034164529
Short name T362
Test name
Test status
Simulation time 1114664341 ps
CPU time 7.11 seconds
Started Apr 21 12:39:12 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 215392 kb
Host smart-cc5177f6-da07-4d94-8386-c2f5ec03490f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034164529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2034164529
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2874044748
Short name T753
Test name
Test status
Simulation time 39365171 ps
CPU time 0.7 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:15 PM PDT 24
Peak memory 203964 kb
Host smart-55f1fffd-4221-416f-9fe1-84e1933c76ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874044748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2874044748
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3515350649
Short name T778
Test name
Test status
Simulation time 34515906 ps
CPU time 0.7 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 203584 kb
Host smart-5ab35ae1-2a88-4f60-b764-92d2920757fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515350649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3515350649
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1809957996
Short name T830
Test name
Test status
Simulation time 14693547 ps
CPU time 0.75 seconds
Started Apr 21 12:39:16 PM PDT 24
Finished Apr 21 12:39:17 PM PDT 24
Peak memory 203928 kb
Host smart-e21e4fb0-8bf7-4acf-b737-a55ba591235a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809957996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1809957996
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3822923316
Short name T725
Test name
Test status
Simulation time 12268776 ps
CPU time 0.71 seconds
Started Apr 21 12:39:04 PM PDT 24
Finished Apr 21 12:39:05 PM PDT 24
Peak memory 203676 kb
Host smart-4ade5242-0ec5-4594-a6fd-d29fd385ee60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822923316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3822923316
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2576914547
Short name T720
Test name
Test status
Simulation time 12595334 ps
CPU time 0.7 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:19 PM PDT 24
Peak memory 203872 kb
Host smart-050509fe-0c77-4a2b-83df-2dad3574665b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576914547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2576914547
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1528191370
Short name T733
Test name
Test status
Simulation time 15059622 ps
CPU time 0.72 seconds
Started Apr 21 12:39:36 PM PDT 24
Finished Apr 21 12:39:38 PM PDT 24
Peak memory 203608 kb
Host smart-eb579ff5-207a-4dff-992e-fbd29b39c6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528191370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1528191370
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2872140787
Short name T730
Test name
Test status
Simulation time 13862355 ps
CPU time 0.69 seconds
Started Apr 21 12:39:26 PM PDT 24
Finished Apr 21 12:39:32 PM PDT 24
Peak memory 203524 kb
Host smart-c964cbfa-57cd-4c97-a523-df9b782d24b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872140787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2872140787
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.180143569
Short name T723
Test name
Test status
Simulation time 53274060 ps
CPU time 0.71 seconds
Started Apr 21 12:39:12 PM PDT 24
Finished Apr 21 12:39:14 PM PDT 24
Peak memory 203664 kb
Host smart-1c36880b-74e9-4d01-bc8f-1ba96f3f451d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180143569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.180143569
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.72519217
Short name T721
Test name
Test status
Simulation time 15859543 ps
CPU time 0.69 seconds
Started Apr 21 12:39:18 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 203868 kb
Host smart-041f7668-0986-42e2-b38e-8c887838e955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72519217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.72519217
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4015864186
Short name T734
Test name
Test status
Simulation time 47581122 ps
CPU time 0.75 seconds
Started Apr 21 12:39:00 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 203852 kb
Host smart-61a2089d-b18a-417c-9782-6fd94ebbf123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015864186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4015864186
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2732931427
Short name T820
Test name
Test status
Simulation time 105889702 ps
CPU time 2.69 seconds
Started Apr 21 12:38:54 PM PDT 24
Finished Apr 21 12:38:58 PM PDT 24
Peak memory 216676 kb
Host smart-bb1d6616-4bdc-4efb-beb0-08ddcc86ea8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732931427 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2732931427
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.732973293
Short name T151
Test name
Test status
Simulation time 57817943 ps
CPU time 2.35 seconds
Started Apr 21 12:38:45 PM PDT 24
Finished Apr 21 12:38:58 PM PDT 24
Peak memory 215148 kb
Host smart-4a0264bc-4cc1-4c29-bf0b-80c83d635376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732973293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.732973293
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3957619405
Short name T793
Test name
Test status
Simulation time 12529586 ps
CPU time 0.68 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:50 PM PDT 24
Peak memory 203604 kb
Host smart-00844826-25c5-46f3-b99a-fc06d078ba28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957619405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
957619405
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1831463857
Short name T773
Test name
Test status
Simulation time 61771136 ps
CPU time 1.73 seconds
Started Apr 21 12:38:48 PM PDT 24
Finished Apr 21 12:38:50 PM PDT 24
Peak memory 215056 kb
Host smart-9c69eb86-1e18-4ae3-9f7b-30b3a2b27d9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831463857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1831463857
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1652211163
Short name T130
Test name
Test status
Simulation time 71749277 ps
CPU time 2 seconds
Started Apr 21 12:38:49 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 215288 kb
Host smart-017cf01d-040e-42df-ab96-514a94ce48e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652211163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
652211163
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4186955960
Short name T811
Test name
Test status
Simulation time 849132052 ps
CPU time 19.84 seconds
Started Apr 21 12:38:43 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 215276 kb
Host smart-551cc7ce-2ed7-4e63-ae5b-e74fe74f3adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186955960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4186955960
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3264264881
Short name T834
Test name
Test status
Simulation time 151901684 ps
CPU time 2.7 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:56 PM PDT 24
Peak memory 216728 kb
Host smart-663ce08b-4c5b-4601-af24-56b5b2bd216b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264264881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3264264881
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.160593219
Short name T138
Test name
Test status
Simulation time 21519356 ps
CPU time 1.18 seconds
Started Apr 21 12:38:50 PM PDT 24
Finished Apr 21 12:38:52 PM PDT 24
Peak memory 206968 kb
Host smart-2ef1ad7d-1b74-43ab-9961-e462e47dbfe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160593219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.160593219
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1394196806
Short name T754
Test name
Test status
Simulation time 11372304 ps
CPU time 0.71 seconds
Started Apr 21 12:39:01 PM PDT 24
Finished Apr 21 12:39:03 PM PDT 24
Peak memory 203584 kb
Host smart-fbfbb35e-fa67-4228-82aa-a1c1b33b03d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394196806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
394196806
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2956197587
Short name T158
Test name
Test status
Simulation time 132373510 ps
CPU time 2.82 seconds
Started Apr 21 12:39:06 PM PDT 24
Finished Apr 21 12:39:09 PM PDT 24
Peak memory 215176 kb
Host smart-f8a8c94e-020f-4b68-8a37-790bf707d907
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956197587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2956197587
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.568835390
Short name T364
Test name
Test status
Simulation time 869951814 ps
CPU time 21.92 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:28 PM PDT 24
Peak memory 223320 kb
Host smart-a2b84297-9dd7-4a4a-96fd-0b3eb5356444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568835390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.568835390
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2091797838
Short name T110
Test name
Test status
Simulation time 179682418 ps
CPU time 2.49 seconds
Started Apr 21 12:38:53 PM PDT 24
Finished Apr 21 12:38:56 PM PDT 24
Peak memory 216320 kb
Host smart-8d8404ed-818a-4d66-a269-295331d02a3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091797838 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2091797838
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4122364068
Short name T814
Test name
Test status
Simulation time 171700647 ps
CPU time 1.33 seconds
Started Apr 21 12:38:46 PM PDT 24
Finished Apr 21 12:38:49 PM PDT 24
Peak memory 206960 kb
Host smart-305a6e66-34fd-4be3-8951-16e0995a18ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122364068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
122364068
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3463750269
Short name T803
Test name
Test status
Simulation time 36854273 ps
CPU time 0.71 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:07 PM PDT 24
Peak memory 203648 kb
Host smart-365a3076-3082-404c-880e-ec470adac80c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463750269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
463750269
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2593690799
Short name T757
Test name
Test status
Simulation time 60917749 ps
CPU time 1.81 seconds
Started Apr 21 12:39:08 PM PDT 24
Finished Apr 21 12:39:10 PM PDT 24
Peak memory 215180 kb
Host smart-8bf32ca1-7ee3-483e-9c06-b92006c234a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593690799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2593690799
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3623242125
Short name T808
Test name
Test status
Simulation time 618527344 ps
CPU time 4.58 seconds
Started Apr 21 12:39:07 PM PDT 24
Finished Apr 21 12:39:12 PM PDT 24
Peak memory 215280 kb
Host smart-b8086afc-cf27-4697-ae25-f93be19b4fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623242125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
623242125
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2084763510
Short name T156
Test name
Test status
Simulation time 761268675 ps
CPU time 16.31 seconds
Started Apr 21 12:39:09 PM PDT 24
Finished Apr 21 12:39:26 PM PDT 24
Peak memory 215176 kb
Host smart-dba7a636-cd36-41e3-ba55-2cc00d4af309
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084763510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2084763510
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.585803766
Short name T131
Test name
Test status
Simulation time 412655605 ps
CPU time 2.81 seconds
Started Apr 21 12:39:12 PM PDT 24
Finished Apr 21 12:39:16 PM PDT 24
Peak memory 217460 kb
Host smart-1a72fecc-3d57-4abd-a02a-0e27a909882f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585803766 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.585803766
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2863903157
Short name T786
Test name
Test status
Simulation time 298384132 ps
CPU time 1.83 seconds
Started Apr 21 12:38:59 PM PDT 24
Finished Apr 21 12:39:01 PM PDT 24
Peak memory 206896 kb
Host smart-233f8b79-5ba1-4f0e-81d4-4d7f104b2df6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863903157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
863903157
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2450650601
Short name T759
Test name
Test status
Simulation time 45173814 ps
CPU time 0.74 seconds
Started Apr 21 12:38:58 PM PDT 24
Finished Apr 21 12:38:59 PM PDT 24
Peak memory 203608 kb
Host smart-839ead25-8d70-434f-986d-80d0cb89cbc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450650601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
450650601
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3589237525
Short name T152
Test name
Test status
Simulation time 676550438 ps
CPU time 4.08 seconds
Started Apr 21 12:39:30 PM PDT 24
Finished Apr 21 12:39:35 PM PDT 24
Peak memory 215084 kb
Host smart-52e2fc09-d5c6-401c-b9fc-e75c6cc17261
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589237525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3589237525
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3718362907
Short name T124
Test name
Test status
Simulation time 116299188 ps
CPU time 2.74 seconds
Started Apr 21 12:38:41 PM PDT 24
Finished Apr 21 12:38:44 PM PDT 24
Peak memory 215880 kb
Host smart-0695b74f-72d5-4a47-a497-5d90e13347ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718362907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
718362907
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2383140316
Short name T810
Test name
Test status
Simulation time 74984622 ps
CPU time 1.79 seconds
Started Apr 21 12:39:13 PM PDT 24
Finished Apr 21 12:39:16 PM PDT 24
Peak memory 215452 kb
Host smart-f4aa37dc-2637-442c-b94d-11329ef7ca13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383140316 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2383140316
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1603776377
Short name T147
Test name
Test status
Simulation time 91824753 ps
CPU time 2.55 seconds
Started Apr 21 12:38:56 PM PDT 24
Finished Apr 21 12:38:59 PM PDT 24
Peak memory 215112 kb
Host smart-ae1942c6-f167-48ea-98d4-d88c456fe684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603776377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
603776377
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3297729780
Short name T774
Test name
Test status
Simulation time 45750382 ps
CPU time 0.73 seconds
Started Apr 21 12:38:56 PM PDT 24
Finished Apr 21 12:38:58 PM PDT 24
Peak memory 203696 kb
Host smart-9f22d107-46ba-4901-9315-8afda3cb56e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297729780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
297729780
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.392103070
Short name T750
Test name
Test status
Simulation time 127150880 ps
CPU time 1.67 seconds
Started Apr 21 12:39:05 PM PDT 24
Finished Apr 21 12:39:12 PM PDT 24
Peak memory 206672 kb
Host smart-76e4eef0-ba21-4a42-9b03-97a31c354ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392103070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.392103070
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3987914453
Short name T125
Test name
Test status
Simulation time 121176622 ps
CPU time 1.83 seconds
Started Apr 21 12:39:11 PM PDT 24
Finished Apr 21 12:39:14 PM PDT 24
Peak memory 215484 kb
Host smart-9e29a753-7e72-4545-9975-9322207a28bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987914453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
987914453
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3263110505
Short name T831
Test name
Test status
Simulation time 1130279982 ps
CPU time 7.13 seconds
Started Apr 21 12:39:12 PM PDT 24
Finished Apr 21 12:39:20 PM PDT 24
Peak memory 215176 kb
Host smart-7216d380-2f6a-4b3a-9db0-d185c1bfd649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263110505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3263110505
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3882209059
Short name T600
Test name
Test status
Simulation time 48531379 ps
CPU time 0.78 seconds
Started Apr 21 12:54:55 PM PDT 24
Finished Apr 21 12:54:56 PM PDT 24
Peak memory 206084 kb
Host smart-33c80e53-b32f-4d86-88d5-13fb5dde8577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882209059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3882209059
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.195824621
Short name T646
Test name
Test status
Simulation time 5359937891 ps
CPU time 75.29 seconds
Started Apr 21 12:55:00 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 233704 kb
Host smart-a85435a6-06d6-423d-8a68-498f670e1b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195824621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.195824621
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2441222726
Short name T180
Test name
Test status
Simulation time 75971373 ps
CPU time 3.52 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:55:02 PM PDT 24
Peak memory 221624 kb
Host smart-25628f61-f177-435c-80c2-873c23c1a276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441222726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2441222726
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2455245965
Short name T543
Test name
Test status
Simulation time 4201127793 ps
CPU time 9.39 seconds
Started Apr 21 12:54:55 PM PDT 24
Finished Apr 21 12:55:05 PM PDT 24
Peak memory 221392 kb
Host smart-c5d74e34-c99d-4935-8685-59834eb2e417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455245965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2455245965
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.965937870
Short name T637
Test name
Test status
Simulation time 7172502934 ps
CPU time 14.1 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:55:08 PM PDT 24
Peak memory 219168 kb
Host smart-29f03a78-84e2-4be9-85f5-4c0dea8ebeef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=965937870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.965937870
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2793436068
Short name T46
Test name
Test status
Simulation time 229379469 ps
CPU time 1.12 seconds
Started Apr 21 12:54:42 PM PDT 24
Finished Apr 21 12:54:43 PM PDT 24
Peak memory 234900 kb
Host smart-135febe8-b21b-418c-874a-947022d9bf3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793436068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2793436068
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2495518413
Short name T711
Test name
Test status
Simulation time 135869836 ps
CPU time 0.93 seconds
Started Apr 21 12:54:51 PM PDT 24
Finished Apr 21 12:54:53 PM PDT 24
Peak memory 205736 kb
Host smart-8d161fbf-07b2-4e0a-b50f-087ac5844240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495518413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2495518413
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2041792033
Short name T398
Test name
Test status
Simulation time 302140046 ps
CPU time 4.96 seconds
Started Apr 21 12:54:50 PM PDT 24
Finished Apr 21 12:54:56 PM PDT 24
Peak memory 216264 kb
Host smart-52783529-3bbb-4b4b-b042-97b6e979ce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041792033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2041792033
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.282650085
Short name T513
Test name
Test status
Simulation time 29602612 ps
CPU time 0.85 seconds
Started Apr 21 12:54:38 PM PDT 24
Finished Apr 21 12:54:40 PM PDT 24
Peak memory 206524 kb
Host smart-18131706-2341-4e85-8e39-0612e31074af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282650085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.282650085
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1795073217
Short name T525
Test name
Test status
Simulation time 73734983 ps
CPU time 0.93 seconds
Started Apr 21 12:54:45 PM PDT 24
Finished Apr 21 12:54:46 PM PDT 24
Peak memory 205652 kb
Host smart-ed3cd7de-1dc0-4a65-bca5-8a9a751ed047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795073217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1795073217
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2166578836
Short name T230
Test name
Test status
Simulation time 3650845369 ps
CPU time 17.21 seconds
Started Apr 21 12:54:47 PM PDT 24
Finished Apr 21 12:55:05 PM PDT 24
Peak memory 235072 kb
Host smart-9ae32ce2-024a-4db6-a198-0fbe2775ba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166578836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2166578836
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4249005527
Short name T575
Test name
Test status
Simulation time 17503848 ps
CPU time 0.69 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:54:58 PM PDT 24
Peak memory 204776 kb
Host smart-48c2a441-1d2c-41ac-9342-05bc82358343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249005527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
249005527
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4119623782
Short name T565
Test name
Test status
Simulation time 35011399 ps
CPU time 0.74 seconds
Started Apr 21 12:54:49 PM PDT 24
Finished Apr 21 12:54:52 PM PDT 24
Peak memory 205764 kb
Host smart-b4177cc1-1b05-42b7-b7eb-5e542509f700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119623782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4119623782
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2325282167
Short name T340
Test name
Test status
Simulation time 1078906186 ps
CPU time 5.39 seconds
Started Apr 21 12:54:50 PM PDT 24
Finished Apr 21 12:54:56 PM PDT 24
Peak memory 222012 kb
Host smart-35b0ec91-3d3b-4e9c-9964-b026503fc7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325282167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2325282167
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1571956077
Short name T573
Test name
Test status
Simulation time 4347477664 ps
CPU time 20.1 seconds
Started Apr 21 12:54:44 PM PDT 24
Finished Apr 21 12:55:04 PM PDT 24
Peak memory 221736 kb
Host smart-433c036b-3a3e-462e-b8f1-b37ea74508f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1571956077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1571956077
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1677902404
Short name T387
Test name
Test status
Simulation time 740422610 ps
CPU time 8.36 seconds
Started Apr 21 12:54:55 PM PDT 24
Finished Apr 21 12:55:04 PM PDT 24
Peak memory 216012 kb
Host smart-bbe1d07b-8f46-4221-81d5-854c8b3d87d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677902404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1677902404
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.835209280
Short name T564
Test name
Test status
Simulation time 4263558792 ps
CPU time 9.55 seconds
Started Apr 21 12:54:49 PM PDT 24
Finished Apr 21 12:54:58 PM PDT 24
Peak memory 216304 kb
Host smart-f417fa1e-ff91-4c28-a183-1af614c4b4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835209280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.835209280
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1396447515
Short name T53
Test name
Test status
Simulation time 349387863 ps
CPU time 2.65 seconds
Started Apr 21 12:54:48 PM PDT 24
Finished Apr 21 12:54:51 PM PDT 24
Peak memory 216140 kb
Host smart-5a492f97-0c8a-4864-ae5a-f546ca9bf35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396447515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1396447515
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1562926423
Short name T170
Test name
Test status
Simulation time 48208933 ps
CPU time 0.88 seconds
Started Apr 21 12:54:39 PM PDT 24
Finished Apr 21 12:54:40 PM PDT 24
Peak memory 205656 kb
Host smart-8a45b492-22a4-4067-85bd-cdac1f6f62f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562926423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1562926423
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3379000871
Short name T15
Test name
Test status
Simulation time 91666518 ps
CPU time 0.7 seconds
Started Apr 21 12:55:11 PM PDT 24
Finished Apr 21 12:55:13 PM PDT 24
Peak memory 205660 kb
Host smart-cde65621-d18d-4a30-b090-9d06bcbac471
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379000871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3379000871
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.470988327
Short name T588
Test name
Test status
Simulation time 15404878 ps
CPU time 0.79 seconds
Started Apr 21 12:55:15 PM PDT 24
Finished Apr 21 12:55:16 PM PDT 24
Peak memory 206984 kb
Host smart-2a7d658b-d45c-4c19-9f18-9477a8525902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470988327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.470988327
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.286049768
Short name T122
Test name
Test status
Simulation time 750795006 ps
CPU time 19.56 seconds
Started Apr 21 12:55:38 PM PDT 24
Finished Apr 21 12:55:58 PM PDT 24
Peak memory 240692 kb
Host smart-28ebfcce-cc53-4073-8108-ec711306ef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286049768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.286049768
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1876891364
Short name T169
Test name
Test status
Simulation time 175676536 ps
CPU time 3.01 seconds
Started Apr 21 12:55:19 PM PDT 24
Finished Apr 21 12:55:23 PM PDT 24
Peak memory 218172 kb
Host smart-cc7c9a88-470a-4f93-a56e-7eddaac18d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876891364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1876891364
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3829643143
Short name T345
Test name
Test status
Simulation time 3182441666 ps
CPU time 11.86 seconds
Started Apr 21 12:55:25 PM PDT 24
Finished Apr 21 12:55:37 PM PDT 24
Peak memory 220784 kb
Host smart-14b902ca-4bd2-4b2b-90cc-f72c370e862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829643143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3829643143
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1778127084
Short name T433
Test name
Test status
Simulation time 413716968 ps
CPU time 3.4 seconds
Started Apr 21 12:55:11 PM PDT 24
Finished Apr 21 12:55:15 PM PDT 24
Peak memory 234916 kb
Host smart-159fca6f-3083-46b2-a1d5-41c2647cba3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778127084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1778127084
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.643603947
Short name T716
Test name
Test status
Simulation time 183884822 ps
CPU time 3.81 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:55:14 PM PDT 24
Peak memory 219660 kb
Host smart-7fb89802-75a7-44aa-b8ec-67c547fb66e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=643603947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.643603947
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1160123359
Short name T488
Test name
Test status
Simulation time 1061395551 ps
CPU time 4.44 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 216188 kb
Host smart-68ef7b60-6833-4a77-92b1-7f56c76c84c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160123359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1160123359
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1170925300
Short name T424
Test name
Test status
Simulation time 4333646528 ps
CPU time 8.7 seconds
Started Apr 21 12:55:30 PM PDT 24
Finished Apr 21 12:55:39 PM PDT 24
Peak memory 216176 kb
Host smart-b41319d4-058a-4c9a-9006-2c70367acaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170925300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1170925300
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1105799881
Short name T474
Test name
Test status
Simulation time 116113743 ps
CPU time 1.5 seconds
Started Apr 21 12:55:07 PM PDT 24
Finished Apr 21 12:55:09 PM PDT 24
Peak memory 216212 kb
Host smart-5fd4096b-5a63-4d31-b741-c6e8b2374d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105799881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1105799881
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2136209890
Short name T493
Test name
Test status
Simulation time 70506872 ps
CPU time 0.73 seconds
Started Apr 21 12:55:12 PM PDT 24
Finished Apr 21 12:55:13 PM PDT 24
Peak memory 205648 kb
Host smart-b458d84b-ba83-46b2-8b09-686470f8d712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136209890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2136209890
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2283107587
Short name T611
Test name
Test status
Simulation time 46720956 ps
CPU time 0.71 seconds
Started Apr 21 12:55:15 PM PDT 24
Finished Apr 21 12:55:16 PM PDT 24
Peak memory 205384 kb
Host smart-3b96ca21-58b8-46c6-ad6f-f41048c2e05c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283107587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2283107587
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.739885371
Short name T558
Test name
Test status
Simulation time 33732987 ps
CPU time 0.83 seconds
Started Apr 21 12:55:25 PM PDT 24
Finished Apr 21 12:55:26 PM PDT 24
Peak memory 206416 kb
Host smart-adf9a976-b854-4a90-823a-cdb7c1be840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739885371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.739885371
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2467191404
Short name T5
Test name
Test status
Simulation time 20026028873 ps
CPU time 68.99 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:56:23 PM PDT 24
Peak memory 256856 kb
Host smart-e1def72b-75b8-4876-8b18-dd1756ae1ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467191404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2467191404
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3768001064
Short name T267
Test name
Test status
Simulation time 4579067019 ps
CPU time 13.77 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 238056 kb
Host smart-c50d9e52-977c-485f-a62b-43bb719837ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768001064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3768001064
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2825573605
Short name T510
Test name
Test status
Simulation time 1555258097 ps
CPU time 11.3 seconds
Started Apr 21 12:55:28 PM PDT 24
Finished Apr 21 12:55:40 PM PDT 24
Peak memory 219016 kb
Host smart-6d79ffe1-7f02-4fb2-93d7-5030400d8204
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2825573605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2825573605
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.892968249
Short name T400
Test name
Test status
Simulation time 276276386 ps
CPU time 2.13 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:55:13 PM PDT 24
Peak memory 216108 kb
Host smart-e576ac17-15d7-4f32-bbd8-9ff3e2d04fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892968249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.892968249
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1051582838
Short name T22
Test name
Test status
Simulation time 51813597259 ps
CPU time 13.9 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:55:24 PM PDT 24
Peak memory 216100 kb
Host smart-cc760599-f101-41b4-92ac-0c6b2104f338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051582838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1051582838
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2138688339
Short name T476
Test name
Test status
Simulation time 88195439 ps
CPU time 3.23 seconds
Started Apr 21 12:55:08 PM PDT 24
Finished Apr 21 12:55:12 PM PDT 24
Peak memory 216228 kb
Host smart-839f0efa-89f2-4938-b9b2-61b7108b320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138688339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2138688339
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3671279215
Short name T674
Test name
Test status
Simulation time 30677542 ps
CPU time 0.84 seconds
Started Apr 21 12:55:01 PM PDT 24
Finished Apr 21 12:55:03 PM PDT 24
Peak memory 205644 kb
Host smart-69845419-d1e2-45df-8f0f-33b12ef1bd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671279215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3671279215
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1030110078
Short name T656
Test name
Test status
Simulation time 18960616 ps
CPU time 0.72 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:55:12 PM PDT 24
Peak memory 204740 kb
Host smart-7185421e-ace3-4ca8-b3c1-911567583b99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030110078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1030110078
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3314907868
Short name T616
Test name
Test status
Simulation time 25817347 ps
CPU time 0.78 seconds
Started Apr 21 12:55:40 PM PDT 24
Finished Apr 21 12:55:51 PM PDT 24
Peak memory 206500 kb
Host smart-ec9d2674-455c-47e4-96f3-eed9264dae5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314907868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3314907868
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3166526405
Short name T93
Test name
Test status
Simulation time 6423139404 ps
CPU time 12.14 seconds
Started Apr 21 12:55:26 PM PDT 24
Finished Apr 21 12:55:39 PM PDT 24
Peak memory 223328 kb
Host smart-4d04e654-ea2e-4d14-b277-8186a5a7a96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166526405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3166526405
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.937141700
Short name T685
Test name
Test status
Simulation time 186470827 ps
CPU time 5 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:55:21 PM PDT 24
Peak memory 220196 kb
Host smart-3e7eeff9-e71e-40c2-96f0-437af5c1837c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937141700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.937141700
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.203771970
Short name T531
Test name
Test status
Simulation time 3930595929 ps
CPU time 4.46 seconds
Started Apr 21 12:55:30 PM PDT 24
Finished Apr 21 12:55:35 PM PDT 24
Peak memory 216276 kb
Host smart-802b4cbb-0fca-4ef3-8d55-58050de5c973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203771970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.203771970
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1531785142
Short name T490
Test name
Test status
Simulation time 88109202 ps
CPU time 3.71 seconds
Started Apr 21 12:55:26 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 216216 kb
Host smart-07923e8b-ac92-4e93-a1e7-e0310974f916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531785142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1531785142
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4102437481
Short name T562
Test name
Test status
Simulation time 171350720 ps
CPU time 1.24 seconds
Started Apr 21 12:55:33 PM PDT 24
Finished Apr 21 12:55:34 PM PDT 24
Peak memory 206756 kb
Host smart-ec46d0dc-45f9-4789-abb5-bfae2838cce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102437481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4102437481
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.349456030
Short name T612
Test name
Test status
Simulation time 22453405 ps
CPU time 0.71 seconds
Started Apr 21 12:55:14 PM PDT 24
Finished Apr 21 12:55:16 PM PDT 24
Peak memory 204744 kb
Host smart-62c19737-c696-4e84-b5a6-053521d92265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349456030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.349456030
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1377416084
Short name T30
Test name
Test status
Simulation time 113017860 ps
CPU time 2.16 seconds
Started Apr 21 12:55:14 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 216748 kb
Host smart-9a2683df-a5d3-4693-9cc5-f728a6a8a16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377416084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1377416084
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.807332857
Short name T475
Test name
Test status
Simulation time 74438933 ps
CPU time 0.72 seconds
Started Apr 21 12:55:19 PM PDT 24
Finished Apr 21 12:55:20 PM PDT 24
Peak memory 205784 kb
Host smart-bf8ea8e2-dafd-489b-b0da-04f6415e8024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807332857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.807332857
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2242834516
Short name T587
Test name
Test status
Simulation time 827815520 ps
CPU time 17.64 seconds
Started Apr 21 12:55:36 PM PDT 24
Finished Apr 21 12:55:54 PM PDT 24
Peak memory 232668 kb
Host smart-fcf02a9c-afc8-44d2-8087-0dd23a461e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242834516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2242834516
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1440598714
Short name T321
Test name
Test status
Simulation time 4066939544 ps
CPU time 38.2 seconds
Started Apr 21 12:55:20 PM PDT 24
Finished Apr 21 12:55:59 PM PDT 24
Peak memory 239504 kb
Host smart-d50df8fd-2a0e-4302-9da1-bafc32f964a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440598714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1440598714
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2315628339
Short name T591
Test name
Test status
Simulation time 6411107345 ps
CPU time 10.76 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:40 PM PDT 24
Peak memory 221896 kb
Host smart-3ca9b877-d380-4197-bf57-ef7a90cf35c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2315628339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2315628339
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1896772722
Short name T584
Test name
Test status
Simulation time 83148061274 ps
CPU time 30.23 seconds
Started Apr 21 12:55:19 PM PDT 24
Finished Apr 21 12:55:49 PM PDT 24
Peak memory 216264 kb
Host smart-75f0186f-3ac8-4c01-822b-10b65f113daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896772722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1896772722
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.650722086
Short name T572
Test name
Test status
Simulation time 175121608 ps
CPU time 4.34 seconds
Started Apr 21 12:55:51 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 216152 kb
Host smart-f055a749-a6de-42c8-a50f-f267808a1ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650722086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.650722086
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1565339008
Short name T580
Test name
Test status
Simulation time 149600080 ps
CPU time 0.93 seconds
Started Apr 21 12:55:25 PM PDT 24
Finished Apr 21 12:55:26 PM PDT 24
Peak memory 205700 kb
Host smart-0a783300-47bd-42af-95e6-18a8e0d9e522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565339008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1565339008
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2977105212
Short name T512
Test name
Test status
Simulation time 64974608 ps
CPU time 0.72 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 205364 kb
Host smart-ebf0ad66-10cc-4e38-97ad-2d7f0b37b6fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977105212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2977105212
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3050155231
Short name T310
Test name
Test status
Simulation time 5181196197 ps
CPU time 15.85 seconds
Started Apr 21 12:55:20 PM PDT 24
Finished Apr 21 12:55:36 PM PDT 24
Peak memory 218484 kb
Host smart-6d8db979-3efd-424a-8a46-421dc157eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050155231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3050155231
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1155195530
Short name T625
Test name
Test status
Simulation time 16676905 ps
CPU time 0.76 seconds
Started Apr 21 12:55:31 PM PDT 24
Finished Apr 21 12:55:32 PM PDT 24
Peak memory 205492 kb
Host smart-baba1ca1-f7e5-49b6-be84-dad4d94da37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155195530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1155195530
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2722732911
Short name T349
Test name
Test status
Simulation time 3578070019 ps
CPU time 23.23 seconds
Started Apr 21 12:55:38 PM PDT 24
Finished Apr 21 12:56:02 PM PDT 24
Peak memory 240616 kb
Host smart-9857d842-10eb-4c36-b82d-8060a5e63c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722732911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2722732911
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1870845336
Short name T253
Test name
Test status
Simulation time 39862810 ps
CPU time 2.28 seconds
Started Apr 21 12:55:22 PM PDT 24
Finished Apr 21 12:55:25 PM PDT 24
Peak memory 219880 kb
Host smart-f7708cd0-9b49-4fbc-a19e-1f65ec365407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870845336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1870845336
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4075198464
Short name T225
Test name
Test status
Simulation time 16982437084 ps
CPU time 16.54 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 222908 kb
Host smart-7d5a3b0a-4751-4e97-94e7-f4190e3d3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075198464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4075198464
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2471456587
Short name T237
Test name
Test status
Simulation time 26170691932 ps
CPU time 11.87 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:25 PM PDT 24
Peak memory 235016 kb
Host smart-6573f4a0-0dd4-4d45-93e5-b92f93bb632e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471456587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2471456587
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1947727300
Short name T658
Test name
Test status
Simulation time 3500010152 ps
CPU time 13.38 seconds
Started Apr 21 12:55:14 PM PDT 24
Finished Apr 21 12:55:28 PM PDT 24
Peak memory 221868 kb
Host smart-3ae3895e-708e-4dda-948d-40a6a5f4dc15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947727300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1947727300
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2879222793
Short name T20
Test name
Test status
Simulation time 8129780858 ps
CPU time 10.06 seconds
Started Apr 21 12:55:25 PM PDT 24
Finished Apr 21 12:55:35 PM PDT 24
Peak memory 216188 kb
Host smart-49996476-e5c9-49ce-bc41-24e3c6b1056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879222793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2879222793
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1126190189
Short name T671
Test name
Test status
Simulation time 2246657396 ps
CPU time 10.3 seconds
Started Apr 21 12:55:25 PM PDT 24
Finished Apr 21 12:55:36 PM PDT 24
Peak memory 216156 kb
Host smart-7912d3d9-744f-452d-ba63-46e5b83640d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126190189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1126190189
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2987312742
Short name T606
Test name
Test status
Simulation time 96556969 ps
CPU time 1.34 seconds
Started Apr 21 12:55:18 PM PDT 24
Finished Apr 21 12:55:19 PM PDT 24
Peak memory 216232 kb
Host smart-61feadee-a2a3-4f13-8c4c-1633a5bf8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987312742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2987312742
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4037845379
Short name T447
Test name
Test status
Simulation time 391580866 ps
CPU time 1.02 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:15 PM PDT 24
Peak memory 206676 kb
Host smart-978bbd5f-c842-4277-8236-e8e22f388c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037845379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4037845379
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2252022045
Short name T164
Test name
Test status
Simulation time 20229719 ps
CPU time 0.73 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:31 PM PDT 24
Peak memory 204692 kb
Host smart-0510c822-787c-4f38-bca6-03a6567e52e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252022045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2252022045
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1258864893
Short name T638
Test name
Test status
Simulation time 1205307861 ps
CPU time 13.69 seconds
Started Apr 21 12:55:27 PM PDT 24
Finished Apr 21 12:55:41 PM PDT 24
Peak memory 217208 kb
Host smart-9026824b-5905-4d03-8581-2d8e7f20e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258864893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1258864893
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1592809977
Short name T712
Test name
Test status
Simulation time 14406971 ps
CPU time 0.81 seconds
Started Apr 21 12:55:34 PM PDT 24
Finished Apr 21 12:55:35 PM PDT 24
Peak memory 206400 kb
Host smart-1e467186-dd83-4632-b2b5-4031c67b6371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592809977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1592809977
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.907259862
Short name T289
Test name
Test status
Simulation time 29874650418 ps
CPU time 80.86 seconds
Started Apr 21 12:55:36 PM PDT 24
Finished Apr 21 12:56:57 PM PDT 24
Peak memory 250468 kb
Host smart-4db99d10-bc78-4ef0-8971-7da6a84554d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907259862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.907259862
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.4290158153
Short name T44
Test name
Test status
Simulation time 208487077 ps
CPU time 3.81 seconds
Started Apr 21 12:55:18 PM PDT 24
Finished Apr 21 12:55:23 PM PDT 24
Peak memory 222112 kb
Host smart-5d35488d-abe7-47fe-9d1b-29f2318b7125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290158153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.4290158153
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.897812170
Short name T243
Test name
Test status
Simulation time 1887065463 ps
CPU time 10.81 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 222996 kb
Host smart-31add2ac-7a51-44ac-91d5-f9ba276bb460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897812170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.897812170
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1880147716
Short name T97
Test name
Test status
Simulation time 11335483190 ps
CPU time 6.68 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:20 PM PDT 24
Peak memory 219292 kb
Host smart-1df763d8-ff14-4807-b270-8fb3b94d4254
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1880147716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1880147716
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2207984040
Short name T609
Test name
Test status
Simulation time 2747117840 ps
CPU time 7.21 seconds
Started Apr 21 12:55:30 PM PDT 24
Finished Apr 21 12:55:37 PM PDT 24
Peak memory 216244 kb
Host smart-fefc5dde-e75a-40b3-867c-3cbaa3be4e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207984040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2207984040
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2213016393
Short name T528
Test name
Test status
Simulation time 15353911715 ps
CPU time 12.76 seconds
Started Apr 21 12:55:28 PM PDT 24
Finished Apr 21 12:55:41 PM PDT 24
Peak memory 216208 kb
Host smart-d66f1790-a58f-4654-acac-d05c7c14132f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213016393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2213016393
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3849153007
Short name T481
Test name
Test status
Simulation time 18522569 ps
CPU time 0.76 seconds
Started Apr 21 12:55:21 PM PDT 24
Finished Apr 21 12:55:22 PM PDT 24
Peak memory 205632 kb
Host smart-6b1d6452-4430-4ba1-b1bf-aa00dbd31dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849153007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3849153007
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1565577174
Short name T619
Test name
Test status
Simulation time 19393881 ps
CPU time 0.73 seconds
Started Apr 21 12:55:33 PM PDT 24
Finished Apr 21 12:55:35 PM PDT 24
Peak memory 205600 kb
Host smart-cc69299a-8dfe-4512-a49f-d79383eb9b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565577174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1565577174
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.759204968
Short name T542
Test name
Test status
Simulation time 242382312 ps
CPU time 0.8 seconds
Started Apr 21 12:55:25 PM PDT 24
Finished Apr 21 12:55:26 PM PDT 24
Peak memory 206480 kb
Host smart-0457583c-2e24-4ce5-b94b-6929fa91cc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759204968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.759204968
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1218389009
Short name T692
Test name
Test status
Simulation time 12128539132 ps
CPU time 90.61 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:57:00 PM PDT 24
Peak memory 253952 kb
Host smart-1b8b7112-1049-4e86-8f00-8d5197e81cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218389009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1218389009
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3329301148
Short name T560
Test name
Test status
Simulation time 1238214348 ps
CPU time 10.23 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 221980 kb
Host smart-199b3ac1-8c83-41df-9a60-9a6ed1ef1c1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3329301148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3329301148
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.631005419
Short name T647
Test name
Test status
Simulation time 7423643615 ps
CPU time 22.74 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 216244 kb
Host smart-fd857266-add7-44a1-8d1b-8543b34293a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631005419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.631005419
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3124517360
Short name T539
Test name
Test status
Simulation time 556186474 ps
CPU time 13.71 seconds
Started Apr 21 12:55:26 PM PDT 24
Finished Apr 21 12:55:40 PM PDT 24
Peak memory 216244 kb
Host smart-438591f2-70bd-41ca-ab96-10c65fc71984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124517360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3124517360
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.773466676
Short name T462
Test name
Test status
Simulation time 102705942 ps
CPU time 1.06 seconds
Started Apr 21 12:55:28 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 206608 kb
Host smart-f086b1a7-fe0c-47c0-a65b-80ef7df1bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773466676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.773466676
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.216977058
Short name T706
Test name
Test status
Simulation time 12814798 ps
CPU time 0.73 seconds
Started Apr 21 12:55:44 PM PDT 24
Finished Apr 21 12:55:45 PM PDT 24
Peak memory 205324 kb
Host smart-b6e58945-e827-4c05-95c5-88fec444810a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216977058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.216977058
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3557214757
Short name T25
Test name
Test status
Simulation time 25285020 ps
CPU time 0.77 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 205812 kb
Host smart-6274cd49-61f8-4acb-b942-b6d1e62a2ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557214757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3557214757
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2005274405
Short name T292
Test name
Test status
Simulation time 37152219983 ps
CPU time 149.61 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:58:11 PM PDT 24
Peak memory 240796 kb
Host smart-f4c3fbbb-91a1-4329-9f94-3398a7657f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005274405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2005274405
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.44486680
Short name T64
Test name
Test status
Simulation time 7677674542 ps
CPU time 6.35 seconds
Started Apr 21 12:55:33 PM PDT 24
Finished Apr 21 12:55:39 PM PDT 24
Peak memory 222812 kb
Host smart-5a0169fd-de7a-4f2e-870a-6c639ea4ee8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44486680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.44486680
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3331687004
Short name T431
Test name
Test status
Simulation time 1075286877 ps
CPU time 6.05 seconds
Started Apr 21 12:55:42 PM PDT 24
Finished Apr 21 12:55:48 PM PDT 24
Peak memory 222740 kb
Host smart-8c7f2f5e-3421-4bd6-ab34-be932de7de94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3331687004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3331687004
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3413114586
Short name T635
Test name
Test status
Simulation time 28277719720 ps
CPU time 45.98 seconds
Started Apr 21 12:55:21 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 216256 kb
Host smart-c32278f5-13c2-4766-8450-75809ac5921e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413114586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3413114586
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3871547217
Short name T21
Test name
Test status
Simulation time 2967210630 ps
CPU time 4.54 seconds
Started Apr 21 12:55:23 PM PDT 24
Finished Apr 21 12:55:28 PM PDT 24
Peak memory 216228 kb
Host smart-ea25d65c-1c47-4681-9f35-13e4cee18e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871547217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3871547217
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3217708080
Short name T502
Test name
Test status
Simulation time 269209487 ps
CPU time 1.36 seconds
Started Apr 21 12:55:36 PM PDT 24
Finished Apr 21 12:55:37 PM PDT 24
Peak memory 216256 kb
Host smart-cced1de0-4738-45ec-9f38-1b4ff87740bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217708080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3217708080
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1763374294
Short name T561
Test name
Test status
Simulation time 66063989 ps
CPU time 0.91 seconds
Started Apr 21 12:55:22 PM PDT 24
Finished Apr 21 12:55:23 PM PDT 24
Peak memory 206112 kb
Host smart-d79e4e6d-9e6e-4bf8-9abe-5d3aa8d1d8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763374294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1763374294
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3208215161
Short name T432
Test name
Test status
Simulation time 13287314 ps
CPU time 0.78 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:40 PM PDT 24
Peak memory 205364 kb
Host smart-d914c373-d5d4-471e-9dbd-19ac1f21d053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208215161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3208215161
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2006562181
Short name T443
Test name
Test status
Simulation time 82633588 ps
CPU time 0.77 seconds
Started Apr 21 12:55:42 PM PDT 24
Finished Apr 21 12:55:43 PM PDT 24
Peak memory 206452 kb
Host smart-b1ad2b9b-ffa4-4ae3-bc65-2e8c84d95186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006562181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2006562181
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3978338374
Short name T688
Test name
Test status
Simulation time 496135122 ps
CPU time 2.62 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:47 PM PDT 24
Peak memory 220076 kb
Host smart-244befa2-3eef-49c1-9b49-fd7fbcd8afb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978338374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3978338374
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3217502582
Short name T530
Test name
Test status
Simulation time 170367273 ps
CPU time 4.08 seconds
Started Apr 21 12:55:31 PM PDT 24
Finished Apr 21 12:55:36 PM PDT 24
Peak memory 222720 kb
Host smart-6bd7e659-8268-47c5-b0a7-67c6e5d149ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3217502582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3217502582
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.384704931
Short name T422
Test name
Test status
Simulation time 4127439279 ps
CPU time 2.35 seconds
Started Apr 21 12:55:45 PM PDT 24
Finished Apr 21 12:55:48 PM PDT 24
Peak memory 216052 kb
Host smart-cea7cbba-250d-47f9-97bb-b5481028e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384704931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.384704931
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1783468765
Short name T645
Test name
Test status
Simulation time 838005291 ps
CPU time 3.58 seconds
Started Apr 21 12:55:36 PM PDT 24
Finished Apr 21 12:55:40 PM PDT 24
Peak memory 216152 kb
Host smart-98bc8f06-2296-4ff5-a462-4c222d0b76a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783468765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1783468765
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1623805201
Short name T449
Test name
Test status
Simulation time 70877642 ps
CPU time 0.93 seconds
Started Apr 21 12:55:33 PM PDT 24
Finished Apr 21 12:55:34 PM PDT 24
Peak memory 206704 kb
Host smart-753b065d-6d47-4555-84b4-887e64f4702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623805201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1623805201
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2358069927
Short name T715
Test name
Test status
Simulation time 22058145 ps
CPU time 0.71 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 205380 kb
Host smart-bdefe5da-80d6-4749-be63-4c3a31362d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358069927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2358069927
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.124903380
Short name T268
Test name
Test status
Simulation time 1344455708 ps
CPU time 6.76 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:51 PM PDT 24
Peak memory 232572 kb
Host smart-a3087525-c62f-4242-9358-5306cd107f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124903380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.124903380
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.306502261
Short name T421
Test name
Test status
Simulation time 59359450 ps
CPU time 0.79 seconds
Started Apr 21 12:55:32 PM PDT 24
Finished Apr 21 12:55:33 PM PDT 24
Peak memory 206520 kb
Host smart-3970022a-4e11-4203-8f90-89875f9f7703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306502261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.306502261
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3766770598
Short name T602
Test name
Test status
Simulation time 45131002371 ps
CPU time 131.54 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:58:01 PM PDT 24
Peak memory 235932 kb
Host smart-3576260b-2530-4703-aa40-1a40b0135667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766770598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3766770598
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3072179428
Short name T43
Test name
Test status
Simulation time 10809691245 ps
CPU time 28.76 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:56:13 PM PDT 24
Peak memory 232336 kb
Host smart-60e43ff7-e68b-49f0-b476-817c68356050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072179428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3072179428
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3243363896
Short name T667
Test name
Test status
Simulation time 8783333323 ps
CPU time 22.21 seconds
Started Apr 21 12:55:31 PM PDT 24
Finished Apr 21 12:55:54 PM PDT 24
Peak memory 220852 kb
Host smart-f9f83605-0005-4538-ab60-822f9e17db12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243363896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3243363896
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.333851231
Short name T248
Test name
Test status
Simulation time 1259206319 ps
CPU time 7.91 seconds
Started Apr 21 12:55:38 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 217292 kb
Host smart-527f217d-eff0-4f81-b559-19ab1a43efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333851231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.333851231
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1922063701
Short name T195
Test name
Test status
Simulation time 1587212219 ps
CPU time 11.66 seconds
Started Apr 21 12:55:44 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 223004 kb
Host smart-9aa8f60b-c43f-4414-a724-b1abf0e0aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922063701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1922063701
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4131019255
Short name T657
Test name
Test status
Simulation time 348339188 ps
CPU time 5.09 seconds
Started Apr 21 12:55:44 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 222768 kb
Host smart-455c6211-5a65-4b9d-9fe5-3dde601f83e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131019255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4131019255
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2641557062
Short name T41
Test name
Test status
Simulation time 186569805 ps
CPU time 0.95 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:55:43 PM PDT 24
Peak memory 206704 kb
Host smart-1463c96c-66db-4f20-82ed-ace0ecc59ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641557062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2641557062
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2729203229
Short name T102
Test name
Test status
Simulation time 3234406668 ps
CPU time 9.95 seconds
Started Apr 21 12:55:40 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 216268 kb
Host smart-08d51f2c-cc6b-4c64-9016-7eaadaa11dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729203229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2729203229
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1625509458
Short name T581
Test name
Test status
Simulation time 1868704944 ps
CPU time 4.36 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:34 PM PDT 24
Peak memory 216048 kb
Host smart-b4592d97-0704-48a3-a640-739a317c96e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625509458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1625509458
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.290275962
Short name T534
Test name
Test status
Simulation time 145565255 ps
CPU time 1.06 seconds
Started Apr 21 12:55:24 PM PDT 24
Finished Apr 21 12:55:26 PM PDT 24
Peak memory 207492 kb
Host smart-345158f9-3d11-4f28-8f70-531493cb2a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290275962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.290275962
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3185013708
Short name T427
Test name
Test status
Simulation time 70682205 ps
CPU time 0.77 seconds
Started Apr 21 12:55:24 PM PDT 24
Finished Apr 21 12:55:25 PM PDT 24
Peak memory 205584 kb
Host smart-1cd1c9be-3c14-433c-aa2f-9290a996f1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185013708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3185013708
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1590884603
Short name T550
Test name
Test status
Simulation time 17526595 ps
CPU time 0.72 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:54:58 PM PDT 24
Peak memory 205328 kb
Host smart-7ecda097-eaa5-45f5-9034-cc783b50ae4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590884603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
590884603
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1762068825
Short name T261
Test name
Test status
Simulation time 13697592411 ps
CPU time 26.82 seconds
Started Apr 21 12:55:09 PM PDT 24
Finished Apr 21 12:55:37 PM PDT 24
Peak memory 218616 kb
Host smart-9874034b-d43b-404f-a430-33b73d8916e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762068825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1762068825
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1436869464
Short name T670
Test name
Test status
Simulation time 214640628 ps
CPU time 0.81 seconds
Started Apr 21 12:55:04 PM PDT 24
Finished Apr 21 12:55:05 PM PDT 24
Peak memory 206468 kb
Host smart-2b0a8a96-1498-425f-ae65-4fa88706d32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436869464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1436869464
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3429713108
Short name T451
Test name
Test status
Simulation time 162766774 ps
CPU time 4.44 seconds
Started Apr 21 12:55:00 PM PDT 24
Finished Apr 21 12:55:05 PM PDT 24
Peak memory 222712 kb
Host smart-536d2d1d-eceb-42fd-a376-0ce2543973c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3429713108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3429713108
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1821555213
Short name T47
Test name
Test status
Simulation time 302794629 ps
CPU time 1.18 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:54:55 PM PDT 24
Peak memory 234928 kb
Host smart-65557117-e0c7-4ab1-8820-ccffd1fe6c3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821555213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1821555213
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2031074854
Short name T665
Test name
Test status
Simulation time 276476535 ps
CPU time 1.21 seconds
Started Apr 21 12:54:59 PM PDT 24
Finished Apr 21 12:55:01 PM PDT 24
Peak memory 206912 kb
Host smart-4cf9875d-8d18-4a19-9c80-ce170ba2653b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031074854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2031074854
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3808912431
Short name T389
Test name
Test status
Simulation time 7895775119 ps
CPU time 16.88 seconds
Started Apr 21 12:54:49 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 216216 kb
Host smart-d61042b1-674b-4588-925f-49714f4c121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808912431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3808912431
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3175464665
Short name T717
Test name
Test status
Simulation time 2579668569 ps
CPU time 12.99 seconds
Started Apr 21 12:54:54 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 216260 kb
Host smart-ddf492e9-65ac-4abe-8713-06998afad703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175464665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3175464665
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2501260879
Short name T623
Test name
Test status
Simulation time 165370774 ps
CPU time 2.3 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:55:00 PM PDT 24
Peak memory 216256 kb
Host smart-527a739d-9a32-4476-959a-11bfee15889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501260879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2501260879
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1866592009
Short name T541
Test name
Test status
Simulation time 125610677 ps
CPU time 1.02 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:54:55 PM PDT 24
Peak memory 206080 kb
Host smart-e9e4fd8c-32fd-44e8-96f9-eaeee74af4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866592009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1866592009
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2739824138
Short name T65
Test name
Test status
Simulation time 6740258221 ps
CPU time 22.38 seconds
Started Apr 21 12:54:48 PM PDT 24
Finished Apr 21 12:55:11 PM PDT 24
Peak memory 224344 kb
Host smart-f01c0c71-3065-4725-ab9e-b3fd0f9eb5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739824138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2739824138
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.548104195
Short name T32
Test name
Test status
Simulation time 11298589 ps
CPU time 0.69 seconds
Started Apr 21 12:55:45 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 205348 kb
Host smart-65628fe4-d5d7-4a20-8315-662bcd4e47d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548104195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.548104195
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3172552689
Short name T464
Test name
Test status
Simulation time 325322007 ps
CPU time 2.93 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:47 PM PDT 24
Peak memory 222456 kb
Host smart-7f3f7331-8484-43e6-b007-47d92f74b878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172552689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3172552689
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2620722698
Short name T500
Test name
Test status
Simulation time 14657654 ps
CPU time 0.76 seconds
Started Apr 21 12:55:45 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 206512 kb
Host smart-c30a9e10-2d0b-423b-866f-c05ff1cba556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620722698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2620722698
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2213970104
Short name T91
Test name
Test status
Simulation time 2365125278 ps
CPU time 25.46 seconds
Started Apr 21 12:55:50 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 218812 kb
Host smart-c95d1cc1-ce7c-4b19-befd-54160a9c6b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213970104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2213970104
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3743060178
Short name T280
Test name
Test status
Simulation time 10770850607 ps
CPU time 84.74 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:57:04 PM PDT 24
Peak memory 227256 kb
Host smart-90cdcf52-048c-4c66-bc70-39b2e7fc259c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743060178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3743060178
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2594703110
Short name T217
Test name
Test status
Simulation time 34219036835 ps
CPU time 27.32 seconds
Started Apr 21 12:55:29 PM PDT 24
Finished Apr 21 12:55:57 PM PDT 24
Peak memory 235752 kb
Host smart-d27f77af-5665-47ce-a590-14124525e1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594703110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2594703110
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3909674407
Short name T436
Test name
Test status
Simulation time 107466317 ps
CPU time 3.77 seconds
Started Apr 21 12:55:48 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 218748 kb
Host smart-f0514e37-a45c-48ad-995a-42a5c3012998
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3909674407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3909674407
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1432751899
Short name T425
Test name
Test status
Simulation time 71372269 ps
CPU time 1.09 seconds
Started Apr 21 12:55:52 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 206828 kb
Host smart-c4705605-6636-404a-930f-4227b266227a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432751899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1432751899
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.819519507
Short name T19
Test name
Test status
Simulation time 3861591009 ps
CPU time 6.09 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 216288 kb
Host smart-dde21d65-90fd-48c4-b255-ed93890e25df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819519507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.819519507
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3911668060
Short name T518
Test name
Test status
Simulation time 1186642130 ps
CPU time 9.16 seconds
Started Apr 21 12:55:50 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 216168 kb
Host smart-05fed937-9fb3-457f-9483-b3d55aa0875a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911668060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3911668060
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3098558299
Short name T473
Test name
Test status
Simulation time 415490504 ps
CPU time 3.5 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:55:45 PM PDT 24
Peak memory 216156 kb
Host smart-e4505ed3-4115-4e0e-89ab-caaaedf367d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098558299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3098558299
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3997700788
Short name T454
Test name
Test status
Simulation time 60007865 ps
CPU time 0.78 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:55:48 PM PDT 24
Peak memory 205696 kb
Host smart-e0f35328-516b-4fca-84e8-4ca519e55cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997700788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3997700788
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.240933893
Short name T509
Test name
Test status
Simulation time 1065433913 ps
CPU time 5.13 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 217628 kb
Host smart-e7ff6e4a-4248-4bdc-9ca3-72f7fc9b69b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240933893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.240933893
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1130220223
Short name T640
Test name
Test status
Simulation time 28893968 ps
CPU time 0.72 seconds
Started Apr 21 12:55:52 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 203876 kb
Host smart-a4623706-7bce-4816-b0a9-e1f00498ba5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130220223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1130220223
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.471421900
Short name T327
Test name
Test status
Simulation time 2152128014 ps
CPU time 16.15 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 223548 kb
Host smart-a656861f-ea74-4624-9819-6c2c6b63807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471421900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.471421900
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.358651091
Short name T659
Test name
Test status
Simulation time 103679636 ps
CPU time 0.76 seconds
Started Apr 21 12:55:46 PM PDT 24
Finished Apr 21 12:55:47 PM PDT 24
Peak memory 205364 kb
Host smart-cf522811-517e-4fa9-a9b5-2a4a2c0ab2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358651091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.358651091
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4193001325
Short name T77
Test name
Test status
Simulation time 3217271216 ps
CPU time 36.82 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 233768 kb
Host smart-ac68b7bb-38f6-4e12-b14c-7e2ef1d37ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193001325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4193001325
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2462349811
Short name T198
Test name
Test status
Simulation time 92298309 ps
CPU time 3.04 seconds
Started Apr 21 12:55:44 PM PDT 24
Finished Apr 21 12:55:48 PM PDT 24
Peak memory 222712 kb
Host smart-e2589fb9-c9d4-44f8-ba9b-45e09c64398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462349811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2462349811
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.665148452
Short name T209
Test name
Test status
Simulation time 7570944000 ps
CPU time 86.52 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:57:14 PM PDT 24
Peak memory 240504 kb
Host smart-a95ac07c-11c1-4390-b883-0108341dde1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665148452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.665148452
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3621630263
Short name T325
Test name
Test status
Simulation time 948125366 ps
CPU time 7.06 seconds
Started Apr 21 12:55:38 PM PDT 24
Finished Apr 21 12:55:45 PM PDT 24
Peak memory 222772 kb
Host smart-2d7d7969-a1c2-4169-abdc-77fe595ea2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621630263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3621630263
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1223441532
Short name T79
Test name
Test status
Simulation time 2183042399 ps
CPU time 19.3 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 221852 kb
Host smart-5212c06b-1c63-45fb-9e3c-f4f78a582b29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1223441532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1223441532
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.314453779
Short name T23
Test name
Test status
Simulation time 3609779413 ps
CPU time 7.05 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:55:55 PM PDT 24
Peak memory 216128 kb
Host smart-8d517ce4-8ba9-402a-b1b7-0a7dbed06c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314453779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.314453779
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2920425933
Short name T171
Test name
Test status
Simulation time 1787959676 ps
CPU time 4.95 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:44 PM PDT 24
Peak memory 216220 kb
Host smart-f4ad5445-b54b-492f-a09f-ef1f01bfcb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920425933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2920425933
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4076317537
Short name T471
Test name
Test status
Simulation time 83258359 ps
CPU time 0.74 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:45 PM PDT 24
Peak memory 205680 kb
Host smart-e2d19321-1b7a-40a7-8966-c6ac34b422ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076317537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4076317537
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.338726771
Short name T472
Test name
Test status
Simulation time 48618732 ps
CPU time 0.67 seconds
Started Apr 21 12:56:00 PM PDT 24
Finished Apr 21 12:56:01 PM PDT 24
Peak memory 205228 kb
Host smart-94a76110-a2eb-4bb7-920e-fc5daf02344e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338726771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.338726771
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4190619957
Short name T523
Test name
Test status
Simulation time 24633163 ps
CPU time 0.79 seconds
Started Apr 21 12:55:35 PM PDT 24
Finished Apr 21 12:55:36 PM PDT 24
Peak memory 205476 kb
Host smart-b7f7fb04-e103-48ff-803e-375a91cdfcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190619957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4190619957
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3886347428
Short name T285
Test name
Test status
Simulation time 20641342205 ps
CPU time 81.64 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:57:09 PM PDT 24
Peak memory 247912 kb
Host smart-14152c05-1195-492c-ba8c-c0482fbaf774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886347428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3886347428
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2407203416
Short name T174
Test name
Test status
Simulation time 508353272 ps
CPU time 7.79 seconds
Started Apr 21 12:55:39 PM PDT 24
Finished Apr 21 12:55:47 PM PDT 24
Peak memory 220120 kb
Host smart-6d9bf3f8-699f-47d4-885e-436db9493b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407203416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2407203416
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1154775754
Short name T193
Test name
Test status
Simulation time 252915954 ps
CPU time 2.7 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:47 PM PDT 24
Peak memory 222248 kb
Host smart-f3286396-9dc4-4639-a9a7-62eec61f43a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154775754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1154775754
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4092644289
Short name T644
Test name
Test status
Simulation time 475644953 ps
CPU time 4.09 seconds
Started Apr 21 12:55:51 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 222052 kb
Host smart-d233c183-8ae3-4c27-90a4-0b38d9bfa588
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4092644289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4092644289
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.823610628
Short name T521
Test name
Test status
Simulation time 1449683104 ps
CPU time 13.26 seconds
Started Apr 21 12:55:50 PM PDT 24
Finished Apr 21 12:56:04 PM PDT 24
Peak memory 216168 kb
Host smart-81cf5acc-91a0-4e5b-9996-5dd209a0cab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823610628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.823610628
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2514349467
Short name T412
Test name
Test status
Simulation time 14065076955 ps
CPU time 18.95 seconds
Started Apr 21 12:55:42 PM PDT 24
Finished Apr 21 12:56:01 PM PDT 24
Peak memory 216216 kb
Host smart-25ce0b43-b01b-4dc7-85e8-d47fcc240ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514349467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2514349467
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1618482344
Short name T698
Test name
Test status
Simulation time 161658303 ps
CPU time 6.26 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 216168 kb
Host smart-2e7f3f6f-012f-4d55-9325-1087c2b5aff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618482344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1618482344
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3082387784
Short name T641
Test name
Test status
Simulation time 70582668 ps
CPU time 0.81 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 205652 kb
Host smart-f5109310-fa7d-4be0-b188-f7fb7e22f9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082387784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3082387784
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2528633565
Short name T566
Test name
Test status
Simulation time 23460048 ps
CPU time 0.67 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:55:48 PM PDT 24
Peak memory 205356 kb
Host smart-e5a69752-bc38-4090-a6bd-960397b34963
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528633565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2528633565
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3385834516
Short name T27
Test name
Test status
Simulation time 505347494 ps
CPU time 2.61 seconds
Started Apr 21 12:55:56 PM PDT 24
Finished Apr 21 12:55:59 PM PDT 24
Peak memory 218712 kb
Host smart-3ac72437-8599-49c3-91a8-9d284f9f3420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385834516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3385834516
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2923221165
Short name T466
Test name
Test status
Simulation time 35409780 ps
CPU time 0.81 seconds
Started Apr 21 12:55:42 PM PDT 24
Finished Apr 21 12:55:43 PM PDT 24
Peak memory 206496 kb
Host smart-bdb8d5c0-a05e-4855-b590-f20b8b3b6448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923221165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2923221165
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.274707184
Short name T348
Test name
Test status
Simulation time 206737006 ps
CPU time 9.37 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 238324 kb
Host smart-d04975e4-d569-4b8d-b95c-e16b72ce6bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274707184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.274707184
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2767070349
Short name T264
Test name
Test status
Simulation time 1601109192 ps
CPU time 13.55 seconds
Started Apr 21 12:55:53 PM PDT 24
Finished Apr 21 12:56:08 PM PDT 24
Peak memory 222188 kb
Host smart-fc3b2b1e-f255-4ec1-a6a3-1435d0e2b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767070349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2767070349
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2771979537
Short name T211
Test name
Test status
Simulation time 7420947445 ps
CPU time 47.02 seconds
Started Apr 21 12:55:41 PM PDT 24
Finished Apr 21 12:56:28 PM PDT 24
Peak memory 234988 kb
Host smart-2e557a0d-1ec9-4b3c-868b-40d050763f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771979537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2771979537
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.823306850
Short name T284
Test name
Test status
Simulation time 17962583573 ps
CPU time 27.67 seconds
Started Apr 21 12:55:43 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 240456 kb
Host smart-da54a87b-8a89-4dbf-8e83-31aa4747ba90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823306850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.823306850
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3146531470
Short name T257
Test name
Test status
Simulation time 12818134460 ps
CPU time 10.37 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:55:58 PM PDT 24
Peak memory 216668 kb
Host smart-a990676d-8679-4d00-8691-1720985bdb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146531470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3146531470
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3867529881
Short name T693
Test name
Test status
Simulation time 355728147 ps
CPU time 4.61 seconds
Started Apr 21 12:55:50 PM PDT 24
Finished Apr 21 12:55:55 PM PDT 24
Peak memory 219864 kb
Host smart-130ba964-a1d8-4f54-91e7-29698ee8d086
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3867529881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3867529881
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1930246554
Short name T160
Test name
Test status
Simulation time 57241545 ps
CPU time 0.99 seconds
Started Apr 21 12:55:45 PM PDT 24
Finished Apr 21 12:55:47 PM PDT 24
Peak memory 206728 kb
Host smart-980de9f4-19d6-42a0-9153-adf57b86cc7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930246554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1930246554
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.55302614
Short name T654
Test name
Test status
Simulation time 3647305833 ps
CPU time 35.33 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:56:25 PM PDT 24
Peak memory 216212 kb
Host smart-afbc7197-938b-450b-86a1-cb74f4d7d50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55302614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.55302614
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.733506109
Short name T601
Test name
Test status
Simulation time 1261454397 ps
CPU time 6.84 seconds
Started Apr 21 12:55:50 PM PDT 24
Finished Apr 21 12:55:57 PM PDT 24
Peak memory 216072 kb
Host smart-e30391ed-9d62-4fb0-86fd-714fd01f48cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733506109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.733506109
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.37271249
Short name T434
Test name
Test status
Simulation time 162367544 ps
CPU time 0.97 seconds
Started Apr 21 12:55:45 PM PDT 24
Finished Apr 21 12:55:46 PM PDT 24
Peak memory 207236 kb
Host smart-dc2234b9-b37f-43da-9f79-577a541e2280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37271249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.37271249
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4290860294
Short name T465
Test name
Test status
Simulation time 36195626 ps
CPU time 0.77 seconds
Started Apr 21 12:55:44 PM PDT 24
Finished Apr 21 12:55:45 PM PDT 24
Peak memory 205624 kb
Host smart-2e37d4c2-24ff-4590-8034-ea12a2cd2708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290860294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4290860294
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2894013806
Short name T626
Test name
Test status
Simulation time 15555265 ps
CPU time 0.67 seconds
Started Apr 21 12:55:57 PM PDT 24
Finished Apr 21 12:55:59 PM PDT 24
Peak memory 205308 kb
Host smart-1ec875aa-147a-4d34-aabf-9352e049076c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894013806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2894013806
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.201231092
Short name T719
Test name
Test status
Simulation time 61769922 ps
CPU time 0.8 seconds
Started Apr 21 12:55:53 PM PDT 24
Finished Apr 21 12:55:55 PM PDT 24
Peak memory 206444 kb
Host smart-696130c4-2cb5-432f-b6bc-8f78bff00eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201231092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.201231092
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.694064980
Short name T503
Test name
Test status
Simulation time 12278343522 ps
CPU time 28.71 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 232708 kb
Host smart-d6fa05e9-301b-4bc7-a4a1-265ed6f83962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694064980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.694064980
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2980323503
Short name T228
Test name
Test status
Simulation time 3789934058 ps
CPU time 6.13 seconds
Started Apr 21 12:55:53 PM PDT 24
Finished Apr 21 12:55:59 PM PDT 24
Peak memory 218844 kb
Host smart-41c7c950-9897-4f88-80e0-1bb56ae00cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980323503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2980323503
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2814022042
Short name T675
Test name
Test status
Simulation time 38291710335 ps
CPU time 18.47 seconds
Started Apr 21 12:55:53 PM PDT 24
Finished Apr 21 12:56:13 PM PDT 24
Peak memory 222120 kb
Host smart-c1e1b27c-cbc5-429d-845e-ad5fecfe4ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814022042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2814022042
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2561075641
Short name T613
Test name
Test status
Simulation time 245694633 ps
CPU time 3.79 seconds
Started Apr 21 12:56:02 PM PDT 24
Finished Apr 21 12:56:06 PM PDT 24
Peak memory 222796 kb
Host smart-4113c1bf-fd76-4d2e-920e-a767063845ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2561075641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2561075641
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1368101596
Short name T655
Test name
Test status
Simulation time 85905884 ps
CPU time 0.99 seconds
Started Apr 21 12:56:01 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 205700 kb
Host smart-3342ac5a-94a9-4985-b8b5-79e07aa38582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368101596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1368101596
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4221626665
Short name T390
Test name
Test status
Simulation time 3209932252 ps
CPU time 43.11 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:56:33 PM PDT 24
Peak memory 216388 kb
Host smart-b14a3826-8829-4740-864d-cc1ccca3a9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221626665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4221626665
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2707878954
Short name T668
Test name
Test status
Simulation time 4015804877 ps
CPU time 4.26 seconds
Started Apr 21 12:56:00 PM PDT 24
Finished Apr 21 12:56:04 PM PDT 24
Peak memory 216120 kb
Host smart-618de85a-4899-4b70-b3ab-b767f0c998b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707878954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2707878954
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3160016355
Short name T395
Test name
Test status
Simulation time 49057196 ps
CPU time 1.45 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 216268 kb
Host smart-1f0a92a1-6d7d-4554-8e18-af6462641439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160016355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3160016355
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2265081149
Short name T687
Test name
Test status
Simulation time 494174701 ps
CPU time 0.97 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:55:50 PM PDT 24
Peak memory 206688 kb
Host smart-8a248cd4-a536-4c49-9acc-1898cfc6a4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265081149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2265081149
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1154885831
Short name T417
Test name
Test status
Simulation time 40813668 ps
CPU time 0.72 seconds
Started Apr 21 12:55:54 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 204808 kb
Host smart-82a56e09-1ee7-40be-94af-87260c742de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154885831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1154885831
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2665062535
Short name T440
Test name
Test status
Simulation time 53514021 ps
CPU time 0.78 seconds
Started Apr 21 12:55:51 PM PDT 24
Finished Apr 21 12:55:52 PM PDT 24
Peak memory 205440 kb
Host smart-ca0e999e-7f6c-4621-8fbe-cc1986857450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665062535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2665062535
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.13479084
Short name T76
Test name
Test status
Simulation time 640417278 ps
CPU time 14.23 seconds
Started Apr 21 12:55:46 PM PDT 24
Finished Apr 21 12:56:01 PM PDT 24
Peak memory 248692 kb
Host smart-db000d24-9fb9-4a95-9619-be33d76a0414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13479084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.13479084
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2731559361
Short name T186
Test name
Test status
Simulation time 220721581 ps
CPU time 2.51 seconds
Started Apr 21 12:55:52 PM PDT 24
Finished Apr 21 12:55:55 PM PDT 24
Peak memory 218324 kb
Host smart-5a0178a2-f7d3-45aa-a82f-8669093b499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731559361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2731559361
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4158690873
Short name T408
Test name
Test status
Simulation time 706212899 ps
CPU time 10.03 seconds
Started Apr 21 12:55:51 PM PDT 24
Finished Apr 21 12:56:02 PM PDT 24
Peak memory 219080 kb
Host smart-f378212c-4b10-4d8a-bada-e0f20516206a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4158690873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4158690873
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1527573584
Short name T369
Test name
Test status
Simulation time 19456905638 ps
CPU time 23.89 seconds
Started Apr 21 12:56:00 PM PDT 24
Finished Apr 21 12:56:24 PM PDT 24
Peak memory 216260 kb
Host smart-01ada4da-483a-443b-911a-be46b740c903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527573584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1527573584
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2322312168
Short name T684
Test name
Test status
Simulation time 690876842 ps
CPU time 3.04 seconds
Started Apr 21 12:55:53 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 216208 kb
Host smart-d174d747-b90f-4e59-8299-6805ee5c163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322312168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2322312168
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3079782125
Short name T552
Test name
Test status
Simulation time 149328405 ps
CPU time 1.2 seconds
Started Apr 21 12:55:52 PM PDT 24
Finished Apr 21 12:55:54 PM PDT 24
Peak memory 216144 kb
Host smart-4045f157-f9f1-473a-853f-5b134970bd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079782125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3079782125
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.239292700
Short name T633
Test name
Test status
Simulation time 119588701 ps
CPU time 0.78 seconds
Started Apr 21 12:55:59 PM PDT 24
Finished Apr 21 12:56:01 PM PDT 24
Peak memory 205684 kb
Host smart-03a2f03b-09b4-47d9-9401-fcbe01a7d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239292700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.239292700
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4189004979
Short name T358
Test name
Test status
Simulation time 989461967 ps
CPU time 2.8 seconds
Started Apr 21 12:55:49 PM PDT 24
Finished Apr 21 12:55:53 PM PDT 24
Peak memory 216276 kb
Host smart-c1302028-e0ce-44ab-8adf-2abf07e4d5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189004979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4189004979
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1725484618
Short name T498
Test name
Test status
Simulation time 52328730 ps
CPU time 0.75 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 205396 kb
Host smart-cc5c2c89-7a74-44cb-bdc2-c7616f8e9826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725484618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1725484618
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4009984407
Short name T540
Test name
Test status
Simulation time 16075771 ps
CPU time 0.8 seconds
Started Apr 21 12:55:56 PM PDT 24
Finished Apr 21 12:55:57 PM PDT 24
Peak memory 206716 kb
Host smart-11675c93-eab2-45f0-b1e0-e843ff6fab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009984407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4009984407
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1573218957
Short name T514
Test name
Test status
Simulation time 24814261865 ps
CPU time 115.99 seconds
Started Apr 21 12:56:00 PM PDT 24
Finished Apr 21 12:57:57 PM PDT 24
Peak memory 249032 kb
Host smart-6530de51-c502-408f-9a3e-a129512c7318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573218957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1573218957
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.438628934
Short name T273
Test name
Test status
Simulation time 1104017738 ps
CPU time 8.44 seconds
Started Apr 21 12:55:56 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 219980 kb
Host smart-8485374d-b6f4-4618-8011-92df64062e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438628934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.438628934
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4278485990
Short name T583
Test name
Test status
Simulation time 3556066001 ps
CPU time 13.63 seconds
Started Apr 21 12:55:50 PM PDT 24
Finished Apr 21 12:56:04 PM PDT 24
Peak memory 231952 kb
Host smart-37c40f6f-9ac3-447d-98a3-b5569929518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278485990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4278485990
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.915558457
Short name T438
Test name
Test status
Simulation time 315215138 ps
CPU time 3.5 seconds
Started Apr 21 12:55:51 PM PDT 24
Finished Apr 21 12:55:55 PM PDT 24
Peak memory 220124 kb
Host smart-da7a6b8c-be19-41c3-bbdc-c777074db274
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=915558457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.915558457
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2026524553
Short name T379
Test name
Test status
Simulation time 38339713765 ps
CPU time 16.75 seconds
Started Apr 21 12:55:48 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 216140 kb
Host smart-87fb6699-6763-4897-a346-82ceaf0eebb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026524553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2026524553
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2353712599
Short name T107
Test name
Test status
Simulation time 39658984812 ps
CPU time 27.03 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 216200 kb
Host smart-94bda982-8907-4426-80e4-e9a21df34bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353712599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2353712599
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2474224827
Short name T457
Test name
Test status
Simulation time 38229120 ps
CPU time 0.76 seconds
Started Apr 21 12:55:59 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 205600 kb
Host smart-80a6288e-244d-4d6c-9ba2-534d8779c84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474224827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2474224827
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1957324952
Short name T696
Test name
Test status
Simulation time 73577126 ps
CPU time 0.77 seconds
Started Apr 21 12:55:59 PM PDT 24
Finished Apr 21 12:56:01 PM PDT 24
Peak memory 205600 kb
Host smart-5b8078a1-75da-4e04-b2c6-3927a66fe48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957324952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1957324952
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4258379017
Short name T271
Test name
Test status
Simulation time 3169816647 ps
CPU time 10.21 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:14 PM PDT 24
Peak memory 216264 kb
Host smart-6906b1d6-70d7-4c9a-9a76-c4c294a81c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258379017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4258379017
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.997889171
Short name T524
Test name
Test status
Simulation time 20430116 ps
CPU time 0.72 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:06 PM PDT 24
Peak memory 205216 kb
Host smart-09c71f76-10b8-4686-b547-3454cd041905
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997889171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.997889171
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2301077216
Short name T631
Test name
Test status
Simulation time 25723113 ps
CPU time 0.76 seconds
Started Apr 21 12:56:02 PM PDT 24
Finished Apr 21 12:56:04 PM PDT 24
Peak memory 206788 kb
Host smart-37747599-00ee-4f83-b77e-e32f31e54a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301077216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2301077216
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.499498620
Short name T328
Test name
Test status
Simulation time 837944283 ps
CPU time 4.54 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 222728 kb
Host smart-479bd5f2-fa58-4281-a829-c52a6932745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499498620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.499498620
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3925856646
Short name T663
Test name
Test status
Simulation time 1533424242 ps
CPU time 13.27 seconds
Started Apr 21 12:56:01 PM PDT 24
Finished Apr 21 12:56:15 PM PDT 24
Peak memory 219884 kb
Host smart-da1c279d-c759-4662-acc3-fbc43c51ab19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3925856646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3925856646
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1830531161
Short name T686
Test name
Test status
Simulation time 28446371 ps
CPU time 0.99 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 205828 kb
Host smart-dffef885-a123-4af2-bc36-a2d118bc5afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830531161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1830531161
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2074912609
Short name T636
Test name
Test status
Simulation time 155157915 ps
CPU time 0.91 seconds
Started Apr 21 12:56:02 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 206372 kb
Host smart-32db5c44-221c-4b02-8ce1-2244d6785afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074912609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2074912609
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1265077904
Short name T569
Test name
Test status
Simulation time 175632058 ps
CPU time 0.87 seconds
Started Apr 21 12:55:57 PM PDT 24
Finished Apr 21 12:55:58 PM PDT 24
Peak memory 206620 kb
Host smart-94d672ca-3784-4d3f-8661-94afa6dc542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265077904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1265077904
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3286651425
Short name T416
Test name
Test status
Simulation time 72198707 ps
CPU time 0.73 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 204908 kb
Host smart-29378615-7116-4ad6-8503-21c6ba33f3c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286651425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3286651425
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.390478436
Short name T409
Test name
Test status
Simulation time 31197158 ps
CPU time 0.79 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:56:06 PM PDT 24
Peak memory 206480 kb
Host smart-e68eec91-d728-4933-82f9-f9205b4f18b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390478436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.390478436
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1378449457
Short name T175
Test name
Test status
Simulation time 530294238 ps
CPU time 8.59 seconds
Started Apr 21 12:56:05 PM PDT 24
Finished Apr 21 12:56:14 PM PDT 24
Peak memory 218072 kb
Host smart-48f9b87e-168e-43ee-b2bb-883f0fba86dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378449457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1378449457
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2327674614
Short name T258
Test name
Test status
Simulation time 6829730491 ps
CPU time 12.25 seconds
Started Apr 21 12:55:52 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 224180 kb
Host smart-fe93c46a-5c78-415b-a607-f25a7c86a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327674614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2327674614
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3961076055
Short name T713
Test name
Test status
Simulation time 142130524 ps
CPU time 3.89 seconds
Started Apr 21 12:55:52 PM PDT 24
Finished Apr 21 12:55:57 PM PDT 24
Peak memory 219188 kb
Host smart-65571027-c9d2-4c20-aaab-5589fadd1a59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3961076055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3961076055
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1356495800
Short name T380
Test name
Test status
Simulation time 548559986 ps
CPU time 7.59 seconds
Started Apr 21 12:55:47 PM PDT 24
Finished Apr 21 12:55:55 PM PDT 24
Peak memory 216388 kb
Host smart-76b97536-b5b5-414e-bb03-1798a52f6206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356495800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1356495800
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.844519292
Short name T470
Test name
Test status
Simulation time 639967153 ps
CPU time 2.32 seconds
Started Apr 21 12:56:00 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 207500 kb
Host smart-68be3da8-5814-4449-a23e-274d1eccc2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844519292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.844519292
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3771799806
Short name T515
Test name
Test status
Simulation time 48583798 ps
CPU time 0.78 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 205540 kb
Host smart-18fb5377-117d-4ff2-b79e-daac9465941c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771799806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3771799806
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1342970873
Short name T486
Test name
Test status
Simulation time 60670066 ps
CPU time 0.85 seconds
Started Apr 21 12:55:54 PM PDT 24
Finished Apr 21 12:55:56 PM PDT 24
Peak memory 205600 kb
Host smart-4703b3e1-fa68-4248-b91e-cb11f0d03881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342970873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1342970873
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.82011448
Short name T508
Test name
Test status
Simulation time 22880943 ps
CPU time 0.74 seconds
Started Apr 21 12:56:01 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 204752 kb
Host smart-04828fba-1749-4a63-ad24-4730ac117cbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82011448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.82011448
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.896628909
Short name T593
Test name
Test status
Simulation time 63047776 ps
CPU time 0.77 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 206080 kb
Host smart-5478ab90-8056-4af0-8c84-034a916427c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896628909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.896628909
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.185470659
Short name T351
Test name
Test status
Simulation time 1563733438 ps
CPU time 32.47 seconds
Started Apr 21 12:56:05 PM PDT 24
Finished Apr 21 12:56:38 PM PDT 24
Peak memory 252216 kb
Host smart-6eb1d7a8-c973-4ffb-8577-df7d2b4c8a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185470659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.185470659
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2070441161
Short name T413
Test name
Test status
Simulation time 6117139741 ps
CPU time 19.42 seconds
Started Apr 21 12:55:51 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 234368 kb
Host smart-9453f630-3e74-4838-a4c2-a0f6f5d271ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070441161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2070441161
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.499530164
Short name T478
Test name
Test status
Simulation time 1314712166 ps
CPU time 9.28 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 221988 kb
Host smart-17063461-3bf4-4068-835e-88a562a688a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=499530164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.499530164
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1810019580
Short name T40
Test name
Test status
Simulation time 48307700 ps
CPU time 0.99 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 205692 kb
Host smart-c101f963-efa8-4226-92aa-560fa355a54f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810019580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1810019580
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2077973495
Short name T373
Test name
Test status
Simulation time 2179006247 ps
CPU time 19.74 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:56:24 PM PDT 24
Peak memory 216272 kb
Host smart-c9c17131-5805-487e-b391-5316164cca94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077973495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2077973495
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.639549475
Short name T459
Test name
Test status
Simulation time 1049365781 ps
CPU time 3.54 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:11 PM PDT 24
Peak memory 216244 kb
Host smart-6bf580d8-70f6-4f41-8ec2-4513c0fdd96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639549475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.639549475
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.520517167
Short name T662
Test name
Test status
Simulation time 156921300 ps
CPU time 0.94 seconds
Started Apr 21 12:55:59 PM PDT 24
Finished Apr 21 12:56:01 PM PDT 24
Peak memory 206784 kb
Host smart-53ec40da-8ede-4f55-a938-72a3e565b463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520517167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.520517167
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.697434259
Short name T629
Test name
Test status
Simulation time 197851257 ps
CPU time 0.87 seconds
Started Apr 21 12:56:11 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 205572 kb
Host smart-9f0025f2-5737-4dfb-856c-eb961cbb59e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697434259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.697434259
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.87627691
Short name T520
Test name
Test status
Simulation time 28476052 ps
CPU time 0.69 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:54:55 PM PDT 24
Peak memory 205736 kb
Host smart-edbd226b-c9d4-4802-92d5-caadf3b3bac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87627691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.87627691
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3701712788
Short name T628
Test name
Test status
Simulation time 22465016 ps
CPU time 0.8 seconds
Started Apr 21 12:55:20 PM PDT 24
Finished Apr 21 12:55:21 PM PDT 24
Peak memory 206832 kb
Host smart-870b0d31-798a-4c67-bc00-a948ac23ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701712788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3701712788
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.484251765
Short name T570
Test name
Test status
Simulation time 10280529630 ps
CPU time 40.6 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:55:39 PM PDT 24
Peak memory 232668 kb
Host smart-4183a01f-350d-4e2e-ae7c-bbc3f19ccda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484251765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.484251765
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3674354770
Short name T95
Test name
Test status
Simulation time 2845625908 ps
CPU time 25.11 seconds
Started Apr 21 12:54:49 PM PDT 24
Finished Apr 21 12:55:15 PM PDT 24
Peak memory 224240 kb
Host smart-12d3bbd2-0d2f-42f9-b857-90f4472a232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674354770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3674354770
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.974353075
Short name T199
Test name
Test status
Simulation time 134445800 ps
CPU time 3.05 seconds
Started Apr 21 12:54:50 PM PDT 24
Finished Apr 21 12:54:54 PM PDT 24
Peak memory 219004 kb
Host smart-fa18cc0c-5c56-4f69-a9b6-2f54b3266c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974353075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
974353075
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2306461398
Short name T10
Test name
Test status
Simulation time 1035366512 ps
CPU time 14.1 seconds
Started Apr 21 12:55:02 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 219892 kb
Host smart-df3feb07-aef0-420b-89fd-dffcbba84f71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2306461398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2306461398
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2338481827
Short name T48
Test name
Test status
Simulation time 228322621 ps
CPU time 0.98 seconds
Started Apr 21 12:54:55 PM PDT 24
Finished Apr 21 12:54:56 PM PDT 24
Peak memory 234840 kb
Host smart-a37e5422-d34b-429b-a81f-528ba7798f67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338481827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2338481827
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1247742190
Short name T399
Test name
Test status
Simulation time 1491612947 ps
CPU time 9.11 seconds
Started Apr 21 12:54:47 PM PDT 24
Finished Apr 21 12:54:57 PM PDT 24
Peak memory 216216 kb
Host smart-54dadc5b-62d0-406e-8565-d02967cb79a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247742190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1247742190
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2422092335
Short name T428
Test name
Test status
Simulation time 3803981613 ps
CPU time 15.54 seconds
Started Apr 21 12:54:52 PM PDT 24
Finished Apr 21 12:55:08 PM PDT 24
Peak memory 216184 kb
Host smart-31477482-aa6a-4f86-8be0-ddcace793f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422092335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2422092335
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3304987502
Short name T403
Test name
Test status
Simulation time 1311499719 ps
CPU time 1.45 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:54:59 PM PDT 24
Peak memory 216192 kb
Host smart-4f8ce531-3d1e-4e43-a79e-78f1d25ce53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304987502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3304987502
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1085312374
Short name T527
Test name
Test status
Simulation time 196982132 ps
CPU time 1.11 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:54:55 PM PDT 24
Peak memory 206640 kb
Host smart-e7c9fe77-fb7d-48ce-a4d7-0f4dde5c9ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085312374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1085312374
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.715707056
Short name T651
Test name
Test status
Simulation time 12204004 ps
CPU time 0.76 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 205360 kb
Host smart-fec6f4fb-0a7c-418c-a673-4eb50ee934db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715707056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.715707056
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.329820271
Short name T559
Test name
Test status
Simulation time 33955036 ps
CPU time 0.82 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:00 PM PDT 24
Peak memory 206464 kb
Host smart-a7cb75b9-b628-498a-9e41-07a23ad259ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329820271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.329820271
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2510107169
Short name T298
Test name
Test status
Simulation time 10212079834 ps
CPU time 41.7 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 232576 kb
Host smart-e69498b4-3946-4e4b-a1d1-37df24c12130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510107169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2510107169
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3629104575
Short name T308
Test name
Test status
Simulation time 10157925009 ps
CPU time 32.92 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:43 PM PDT 24
Peak memory 223492 kb
Host smart-4fa57980-7c4e-4c64-8a72-7371ba6a2a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629104575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3629104575
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1090123495
Short name T304
Test name
Test status
Simulation time 6974080921 ps
CPU time 11.36 seconds
Started Apr 21 12:56:02 PM PDT 24
Finished Apr 21 12:56:14 PM PDT 24
Peak memory 227100 kb
Host smart-f0a962a8-5abb-489a-9aad-92268b8abedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090123495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1090123495
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2982973456
Short name T624
Test name
Test status
Simulation time 1174574506 ps
CPU time 15.63 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:22 PM PDT 24
Peak memory 218736 kb
Host smart-7824a4c2-7b49-48dc-a8a5-b216e51820ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2982973456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2982973456
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3812256457
Short name T355
Test name
Test status
Simulation time 167013684 ps
CPU time 0.99 seconds
Started Apr 21 12:55:57 PM PDT 24
Finished Apr 21 12:55:58 PM PDT 24
Peak memory 206968 kb
Host smart-bab6ba20-130f-4265-86c2-02dad5184eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812256457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3812256457
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1363704529
Short name T388
Test name
Test status
Simulation time 14025479273 ps
CPU time 40.34 seconds
Started Apr 21 12:56:01 PM PDT 24
Finished Apr 21 12:56:42 PM PDT 24
Peak memory 216252 kb
Host smart-137de7e6-3ddc-4030-bcb3-a82ce6e380ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363704529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1363704529
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.861436338
Short name T682
Test name
Test status
Simulation time 28298392476 ps
CPU time 15.89 seconds
Started Apr 21 12:55:56 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 216252 kb
Host smart-2019fa1d-7513-4695-bb38-5ba8e81f4935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861436338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.861436338
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2720873008
Short name T480
Test name
Test status
Simulation time 451737029 ps
CPU time 2 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 216196 kb
Host smart-0b631422-dfb0-4880-b28c-e2d076fdd33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720873008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2720873008
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1021820678
Short name T489
Test name
Test status
Simulation time 196258209 ps
CPU time 0.82 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:04 PM PDT 24
Peak memory 205508 kb
Host smart-e78abd47-2e22-4be9-a03c-6b7ca20ae92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021820678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1021820678
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3372451456
Short name T324
Test name
Test status
Simulation time 4898251254 ps
CPU time 6 seconds
Started Apr 21 12:55:58 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 223420 kb
Host smart-c2773eb1-85e0-453b-88d7-559fa9ee3e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372451456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3372451456
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3875380670
Short name T557
Test name
Test status
Simulation time 19424182 ps
CPU time 0.7 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 204756 kb
Host smart-40616108-6589-4e63-a294-1c63bd3ebfe7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875380670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3875380670
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.974336912
Short name T483
Test name
Test status
Simulation time 42583167 ps
CPU time 0.8 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 206420 kb
Host smart-e15cb458-f8a2-40bb-8859-f8cd9175d696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974336912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.974336912
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3665953970
Short name T291
Test name
Test status
Simulation time 8201159884 ps
CPU time 23.43 seconds
Started Apr 21 12:56:11 PM PDT 24
Finished Apr 21 12:56:34 PM PDT 24
Peak memory 248956 kb
Host smart-9d79e66d-9e1b-4ded-bc36-cfb7bd6983a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665953970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3665953970
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1456690586
Short name T223
Test name
Test status
Simulation time 104827070 ps
CPU time 3.94 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 216392 kb
Host smart-b8ea2467-c14f-4445-a9ad-933a85f86715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456690586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1456690586
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4240355825
Short name T232
Test name
Test status
Simulation time 3465190604 ps
CPU time 5.31 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:13 PM PDT 24
Peak memory 221524 kb
Host smart-f3ae9cdb-0285-46a3-9610-171a44e2fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240355825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4240355825
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3175162675
Short name T673
Test name
Test status
Simulation time 832663508 ps
CPU time 8.6 seconds
Started Apr 21 12:56:10 PM PDT 24
Finished Apr 21 12:56:19 PM PDT 24
Peak memory 219056 kb
Host smart-55247b3a-8b18-4960-885a-c1f5f77adbd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3175162675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3175162675
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.701795985
Short name T404
Test name
Test status
Simulation time 985879540 ps
CPU time 7.84 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:14 PM PDT 24
Peak memory 216092 kb
Host smart-2f4e694a-ddfe-4d71-ab34-ce3c1678b8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701795985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.701795985
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3974384775
Short name T452
Test name
Test status
Simulation time 20240842481 ps
CPU time 16.95 seconds
Started Apr 21 12:56:05 PM PDT 24
Finished Apr 21 12:56:22 PM PDT 24
Peak memory 216172 kb
Host smart-eafc23c0-79a6-4e0f-a25d-a6620b8bd35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974384775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3974384775
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.943478794
Short name T594
Test name
Test status
Simulation time 161978667 ps
CPU time 2.72 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:10 PM PDT 24
Peak memory 216232 kb
Host smart-6af5f14c-1156-4630-ba1d-a9ffccc9aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943478794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.943478794
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.247166580
Short name T598
Test name
Test status
Simulation time 314861546 ps
CPU time 1.11 seconds
Started Apr 21 12:56:06 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 206676 kb
Host smart-e75aa6de-ef90-41a7-87ac-be5814e7f0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247166580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.247166580
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.791713906
Short name T492
Test name
Test status
Simulation time 12171844 ps
CPU time 0.69 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 205296 kb
Host smart-88db8e3d-8123-4789-87a3-00b446242ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791713906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.791713906
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3744311596
Short name T24
Test name
Test status
Simulation time 68371430 ps
CPU time 0.81 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 205400 kb
Host smart-4051b4d7-08a5-4c9e-96cb-e2612d77dc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744311596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3744311596
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3983729847
Short name T617
Test name
Test status
Simulation time 7656647717 ps
CPU time 14.19 seconds
Started Apr 21 12:56:10 PM PDT 24
Finished Apr 21 12:56:24 PM PDT 24
Peak memory 220328 kb
Host smart-fdfe3f8f-6393-467b-9d7c-7128828d94c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3983729847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3983729847
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2091004209
Short name T353
Test name
Test status
Simulation time 42974403 ps
CPU time 0.96 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 206408 kb
Host smart-1d53849b-5582-4351-9c49-cb02e330c2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091004209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2091004209
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2123962001
Short name T378
Test name
Test status
Simulation time 1420912902 ps
CPU time 22.72 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 216468 kb
Host smart-6e1ce939-5ced-4aad-979b-b23b42bfb595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123962001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2123962001
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1492649326
Short name T578
Test name
Test status
Simulation time 391219416 ps
CPU time 1.62 seconds
Started Apr 21 12:56:11 PM PDT 24
Finished Apr 21 12:56:13 PM PDT 24
Peak memory 206672 kb
Host smart-d1f936c3-3760-4dda-a297-44723e886322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492649326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1492649326
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2670362452
Short name T690
Test name
Test status
Simulation time 161801461 ps
CPU time 0.99 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:56:06 PM PDT 24
Peak memory 206684 kb
Host smart-8adfd5f0-e173-4bca-9a79-862d54397c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670362452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2670362452
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2711488695
Short name T703
Test name
Test status
Simulation time 572104380 ps
CPU time 1.2 seconds
Started Apr 21 12:56:02 PM PDT 24
Finished Apr 21 12:56:03 PM PDT 24
Peak memory 206688 kb
Host smart-563c6dde-553a-4b24-a3ed-353dcedb78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711488695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2711488695
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.910332765
Short name T320
Test name
Test status
Simulation time 1159415631 ps
CPU time 3.71 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 217300 kb
Host smart-dba73b59-ffa5-4f2b-87e3-9ff5fc373a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910332765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.910332765
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1096482757
Short name T592
Test name
Test status
Simulation time 25184690 ps
CPU time 0.72 seconds
Started Apr 21 12:56:03 PM PDT 24
Finished Apr 21 12:56:06 PM PDT 24
Peak memory 204784 kb
Host smart-416c8d85-1907-4a16-b7af-9bdbcee11531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096482757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1096482757
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3886776979
Short name T537
Test name
Test status
Simulation time 50689189 ps
CPU time 0.76 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 205468 kb
Host smart-e499242a-f18a-4dff-a49c-5b01af1e8729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886776979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3886776979
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2060259729
Short name T549
Test name
Test status
Simulation time 1539988188 ps
CPU time 15.65 seconds
Started Apr 21 12:56:14 PM PDT 24
Finished Apr 21 12:56:30 PM PDT 24
Peak memory 248896 kb
Host smart-3fd9c4fe-1286-463e-aae8-5e63ab87cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060259729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2060259729
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3424038917
Short name T247
Test name
Test status
Simulation time 407378247 ps
CPU time 5.76 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:14 PM PDT 24
Peak memory 218876 kb
Host smart-988b54df-6df1-4148-bbb8-9e88f7b986b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424038917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3424038917
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.786363305
Short name T714
Test name
Test status
Simulation time 68110657 ps
CPU time 2.64 seconds
Started Apr 21 12:56:15 PM PDT 24
Finished Apr 21 12:56:18 PM PDT 24
Peak memory 222332 kb
Host smart-e5cee72d-05c6-4eaa-82a5-f678c2eb2a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786363305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.786363305
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1623951409
Short name T504
Test name
Test status
Simulation time 4370301078 ps
CPU time 5.92 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:14 PM PDT 24
Peak memory 222384 kb
Host smart-8583c01c-6c71-4a1b-8a20-d51f70dcb942
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1623951409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1623951409
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.148199177
Short name T393
Test name
Test status
Simulation time 3459590184 ps
CPU time 11.04 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:21 PM PDT 24
Peak memory 216268 kb
Host smart-deeb0e58-9aae-42fd-831b-3959f79a719b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148199177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.148199177
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3300429907
Short name T533
Test name
Test status
Simulation time 2389821166 ps
CPU time 5.35 seconds
Started Apr 21 12:56:13 PM PDT 24
Finished Apr 21 12:56:19 PM PDT 24
Peak memory 216176 kb
Host smart-8fb483b0-e930-4cc7-9cf8-5134b76b8d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300429907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3300429907
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3584315310
Short name T621
Test name
Test status
Simulation time 182971060 ps
CPU time 2.65 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:10 PM PDT 24
Peak memory 216164 kb
Host smart-c37d5303-148c-44a2-a334-886d330ce89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584315310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3584315310
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.129537143
Short name T106
Test name
Test status
Simulation time 216820712 ps
CPU time 0.93 seconds
Started Apr 21 12:56:10 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 206696 kb
Host smart-7599c91a-fe0b-4145-8df1-29d69d2681f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129537143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.129537143
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3244178481
Short name T548
Test name
Test status
Simulation time 13351362 ps
CPU time 0.75 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:10 PM PDT 24
Peak memory 205300 kb
Host smart-ff5a3a2a-6462-4818-94b9-bd4bccfdc2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244178481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3244178481
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1388168116
Short name T441
Test name
Test status
Simulation time 28167100 ps
CPU time 0.75 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:09 PM PDT 24
Peak memory 205792 kb
Host smart-7866e3af-e9b1-46e4-8c4e-38c1755a3f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388168116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1388168116
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1763248815
Short name T632
Test name
Test status
Simulation time 787875677 ps
CPU time 16.07 seconds
Started Apr 21 12:56:14 PM PDT 24
Finished Apr 21 12:56:30 PM PDT 24
Peak memory 232520 kb
Host smart-0ed90fae-1a1b-45d4-a358-03f171123110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763248815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1763248815
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3302991693
Short name T214
Test name
Test status
Simulation time 49319889 ps
CPU time 2.44 seconds
Started Apr 21 12:56:15 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 221704 kb
Host smart-f5cc387f-7f14-449f-88a2-1107cf078ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302991693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3302991693
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1613026085
Short name T60
Test name
Test status
Simulation time 1718456272 ps
CPU time 7.35 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 216872 kb
Host smart-051bb926-75b4-4853-9185-00732ec25c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613026085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1613026085
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.131292586
Short name T538
Test name
Test status
Simulation time 800744650 ps
CPU time 4.08 seconds
Started Apr 21 12:56:07 PM PDT 24
Finished Apr 21 12:56:11 PM PDT 24
Peak memory 218700 kb
Host smart-02f5c6af-89db-490a-9714-de8918f3c8e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=131292586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.131292586
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1360427883
Short name T494
Test name
Test status
Simulation time 494852104 ps
CPU time 3.25 seconds
Started Apr 21 12:56:08 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 216204 kb
Host smart-e06c2b4f-6313-467c-aa47-7084300d7b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360427883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1360427883
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.335238405
Short name T610
Test name
Test status
Simulation time 207475222 ps
CPU time 1.56 seconds
Started Apr 21 12:56:04 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 216152 kb
Host smart-e3059a6c-b8cd-4438-b642-f56d347b1094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335238405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.335238405
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1400847082
Short name T467
Test name
Test status
Simulation time 249633027 ps
CPU time 0.94 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:10 PM PDT 24
Peak memory 206640 kb
Host smart-25abcae9-d78d-4a96-bb64-232da1c4490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400847082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1400847082
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3223576505
Short name T270
Test name
Test status
Simulation time 1478632538 ps
CPU time 6.9 seconds
Started Apr 21 12:56:10 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 218404 kb
Host smart-30e23ed3-9b02-4680-afb7-4f5d50df9d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223576505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3223576505
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1965856270
Short name T463
Test name
Test status
Simulation time 12781714 ps
CPU time 0.72 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:10 PM PDT 24
Peak memory 204784 kb
Host smart-1c421f97-c763-4b9e-8cb9-382f7d131f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965856270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1965856270
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3847948940
Short name T88
Test name
Test status
Simulation time 1043145509 ps
CPU time 8.09 seconds
Started Apr 21 12:56:09 PM PDT 24
Finished Apr 21 12:56:18 PM PDT 24
Peak memory 232608 kb
Host smart-cc6399bc-633b-4b59-8ba3-ab868be5bfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847948940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3847948940
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2945676953
Short name T435
Test name
Test status
Simulation time 20376790 ps
CPU time 0.8 seconds
Started Apr 21 12:56:13 PM PDT 24
Finished Apr 21 12:56:14 PM PDT 24
Peak memory 206560 kb
Host smart-483eb03d-7231-4009-8aa9-76d9cacaa9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945676953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2945676953
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2606774965
Short name T83
Test name
Test status
Simulation time 2137655148 ps
CPU time 37.26 seconds
Started Apr 21 12:56:16 PM PDT 24
Finished Apr 21 12:56:54 PM PDT 24
Peak memory 240796 kb
Host smart-cf85d4f5-573d-4f77-bc44-eb38ecf4f91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606774965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2606774965
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1596444269
Short name T263
Test name
Test status
Simulation time 1426472524 ps
CPU time 11.87 seconds
Started Apr 21 12:56:10 PM PDT 24
Finished Apr 21 12:56:23 PM PDT 24
Peak memory 224384 kb
Host smart-e4f71b2f-c03d-439c-a719-e695534472f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596444269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1596444269
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1493329560
Short name T595
Test name
Test status
Simulation time 420036265 ps
CPU time 4.33 seconds
Started Apr 21 12:56:10 PM PDT 24
Finished Apr 21 12:56:15 PM PDT 24
Peak memory 220088 kb
Host smart-fd1220ec-3a17-465b-881a-6dab7fdfe83f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1493329560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1493329560
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.291030484
Short name T382
Test name
Test status
Simulation time 1614584011 ps
CPU time 25.66 seconds
Started Apr 21 12:56:05 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 216288 kb
Host smart-49798b62-c1df-483f-bfe1-864b3a578e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291030484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.291030484
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2815107911
Short name T708
Test name
Test status
Simulation time 8117848311 ps
CPU time 23.09 seconds
Started Apr 21 12:56:14 PM PDT 24
Finished Apr 21 12:56:38 PM PDT 24
Peak memory 216180 kb
Host smart-95a0e57c-bd2c-4346-b9e6-c14d5208d529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815107911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2815107911
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4234470724
Short name T577
Test name
Test status
Simulation time 76012545 ps
CPU time 1.84 seconds
Started Apr 21 12:56:14 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 216212 kb
Host smart-2b7aeaca-9f64-4e5b-aa9d-e1e57f40d15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234470724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4234470724
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.659015923
Short name T661
Test name
Test status
Simulation time 129243717 ps
CPU time 0.89 seconds
Started Apr 21 12:56:18 PM PDT 24
Finished Apr 21 12:56:19 PM PDT 24
Peak memory 205672 kb
Host smart-4ad90f15-482a-4fa3-a784-82fff1f56653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659015923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.659015923
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1566481925
Short name T18
Test name
Test status
Simulation time 33011350 ps
CPU time 0.71 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:24 PM PDT 24
Peak memory 204776 kb
Host smart-bc65ddcd-9c8a-4fac-a98a-8aa021e565c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566481925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1566481925
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3881899568
Short name T579
Test name
Test status
Simulation time 17374556 ps
CPU time 0.78 seconds
Started Apr 21 12:56:11 PM PDT 24
Finished Apr 21 12:56:12 PM PDT 24
Peak memory 205540 kb
Host smart-a866480e-7b5d-43cf-822f-f99726809e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881899568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3881899568
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2586214805
Short name T165
Test name
Test status
Simulation time 4401479876 ps
CPU time 14.21 seconds
Started Apr 21 12:56:13 PM PDT 24
Finished Apr 21 12:56:28 PM PDT 24
Peak memory 234012 kb
Host smart-420d8970-a163-41cc-95c0-770d676b9f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586214805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2586214805
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4182887036
Short name T652
Test name
Test status
Simulation time 1098680430 ps
CPU time 4.65 seconds
Started Apr 21 12:56:21 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 222556 kb
Host smart-38d7525a-b8d8-4b45-9ca0-2b3c6dfd05b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4182887036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4182887036
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3786900235
Short name T618
Test name
Test status
Simulation time 12141861512 ps
CPU time 29.21 seconds
Started Apr 21 12:56:14 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 216220 kb
Host smart-477d5574-b878-4738-b319-1a5651ee0f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786900235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3786900235
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1786567443
Short name T664
Test name
Test status
Simulation time 4799525172 ps
CPU time 5.02 seconds
Started Apr 21 12:56:15 PM PDT 24
Finished Apr 21 12:56:21 PM PDT 24
Peak memory 216292 kb
Host smart-05c916e9-d728-4d4a-a953-90197c13f555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786567443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1786567443
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3754525356
Short name T620
Test name
Test status
Simulation time 280070803 ps
CPU time 0.79 seconds
Started Apr 21 12:56:19 PM PDT 24
Finished Apr 21 12:56:20 PM PDT 24
Peak memory 205684 kb
Host smart-a5c2b13f-ae0e-4906-9399-feaf58c4ecdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754525356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3754525356
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2079385135
Short name T448
Test name
Test status
Simulation time 13971054 ps
CPU time 0.67 seconds
Started Apr 21 12:56:16 PM PDT 24
Finished Apr 21 12:56:17 PM PDT 24
Peak memory 204724 kb
Host smart-a37e3ce9-4174-434d-a29d-a78fb1599897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079385135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2079385135
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.162019400
Short name T450
Test name
Test status
Simulation time 55563904 ps
CPU time 0.77 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:25 PM PDT 24
Peak memory 206432 kb
Host smart-ca895b27-1500-46c6-b0fe-b77000692706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162019400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.162019400
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4050992376
Short name T312
Test name
Test status
Simulation time 2122486610 ps
CPU time 14.07 seconds
Started Apr 21 12:56:24 PM PDT 24
Finished Apr 21 12:56:39 PM PDT 24
Peak memory 223176 kb
Host smart-ac119d0b-30fb-47ad-bcc6-91186d8ef95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050992376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4050992376
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.643129697
Short name T233
Test name
Test status
Simulation time 8465006546 ps
CPU time 6.56 seconds
Started Apr 21 12:56:16 PM PDT 24
Finished Apr 21 12:56:23 PM PDT 24
Peak memory 223284 kb
Host smart-7f6bd6b0-10c4-432a-b19f-2e746a816048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643129697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.643129697
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1889958829
Short name T607
Test name
Test status
Simulation time 739542718 ps
CPU time 9.53 seconds
Started Apr 21 12:56:28 PM PDT 24
Finished Apr 21 12:56:38 PM PDT 24
Peak memory 219816 kb
Host smart-430da65f-a569-4ff6-8add-0ae3d59daca1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1889958829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1889958829
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1666349394
Short name T375
Test name
Test status
Simulation time 6840054635 ps
CPU time 41.22 seconds
Started Apr 21 12:56:17 PM PDT 24
Finished Apr 21 12:56:59 PM PDT 24
Peak memory 216300 kb
Host smart-be8d899a-8e1c-46ec-9c05-a18f76036d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666349394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1666349394
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1793807528
Short name T608
Test name
Test status
Simulation time 19475944039 ps
CPU time 19.07 seconds
Started Apr 21 12:56:20 PM PDT 24
Finished Apr 21 12:56:39 PM PDT 24
Peak memory 216136 kb
Host smart-70d3463e-9e23-4962-abc1-fe9a04774710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793807528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1793807528
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2515368326
Short name T401
Test name
Test status
Simulation time 189483184 ps
CPU time 1.76 seconds
Started Apr 21 12:56:17 PM PDT 24
Finished Apr 21 12:56:19 PM PDT 24
Peak memory 216092 kb
Host smart-bbec4a2c-d3e1-4a21-914a-fdc42acd066a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515368326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2515368326
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3592541304
Short name T554
Test name
Test status
Simulation time 1244354033 ps
CPU time 0.97 seconds
Started Apr 21 12:56:19 PM PDT 24
Finished Apr 21 12:56:20 PM PDT 24
Peak memory 206628 kb
Host smart-84eda38d-5ab0-414e-b634-acfcde3ead9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592541304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3592541304
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.705987764
Short name T718
Test name
Test status
Simulation time 60028895 ps
CPU time 0.72 seconds
Started Apr 21 12:56:21 PM PDT 24
Finished Apr 21 12:56:23 PM PDT 24
Peak memory 204780 kb
Host smart-c1dab22c-75b1-4af9-97b9-1e2ce99b7326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705987764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.705987764
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1696242097
Short name T419
Test name
Test status
Simulation time 16537596 ps
CPU time 0.82 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 206536 kb
Host smart-8250f3ad-56d4-4033-ae41-b66f08faa9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696242097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1696242097
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3435972703
Short name T545
Test name
Test status
Simulation time 48461120618 ps
CPU time 81.07 seconds
Started Apr 21 12:56:32 PM PDT 24
Finished Apr 21 12:57:54 PM PDT 24
Peak memory 234552 kb
Host smart-1b934efa-6f08-4603-8865-09da017118c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435972703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3435972703
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3016660377
Short name T235
Test name
Test status
Simulation time 308872239 ps
CPU time 5.39 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:31 PM PDT 24
Peak memory 216748 kb
Host smart-dc358276-9864-4e26-9897-c87f3f139b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016660377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3016660377
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1514123952
Short name T173
Test name
Test status
Simulation time 1288867898 ps
CPU time 8.14 seconds
Started Apr 21 12:56:33 PM PDT 24
Finished Apr 21 12:56:41 PM PDT 24
Peak memory 233772 kb
Host smart-5149eb43-d291-4020-b0e8-2dd6847cdfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514123952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1514123952
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4004915219
Short name T238
Test name
Test status
Simulation time 9207655193 ps
CPU time 25.3 seconds
Started Apr 21 12:56:19 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 218648 kb
Host smart-2332ef48-f0c4-424e-b62d-b81063e5a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004915219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4004915219
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2481638008
Short name T121
Test name
Test status
Simulation time 4121266284 ps
CPU time 10.56 seconds
Started Apr 21 12:56:21 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 218800 kb
Host smart-8964f51f-771d-4c15-9287-3bdcd156e4ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2481638008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2481638008
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2274845954
Short name T385
Test name
Test status
Simulation time 3013948605 ps
CPU time 39.02 seconds
Started Apr 21 12:56:22 PM PDT 24
Finished Apr 21 12:57:02 PM PDT 24
Peak memory 216160 kb
Host smart-c6914307-5813-4760-bf80-ccc051b03c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274845954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2274845954
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.977580738
Short name T484
Test name
Test status
Simulation time 9808256029 ps
CPU time 6.64 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:31 PM PDT 24
Peak memory 216236 kb
Host smart-31e384e9-21fc-4937-9360-216d6e9626c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977580738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.977580738
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2559597590
Short name T50
Test name
Test status
Simulation time 239944974 ps
CPU time 3.53 seconds
Started Apr 21 12:56:22 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 216112 kb
Host smart-58e6e521-1a66-4151-8388-8dac4f0acb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559597590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2559597590
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4169664360
Short name T168
Test name
Test status
Simulation time 150143738 ps
CPU time 0.77 seconds
Started Apr 21 12:56:17 PM PDT 24
Finished Apr 21 12:56:18 PM PDT 24
Peak memory 205672 kb
Host smart-809dc8ce-fc4b-4c78-9a04-1314dbfe239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169664360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4169664360
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2228479301
Short name T234
Test name
Test status
Simulation time 623953273 ps
CPU time 6.9 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:31 PM PDT 24
Peak memory 223752 kb
Host smart-d3975384-2f40-4b02-8775-99672565d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228479301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2228479301
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3261365670
Short name T506
Test name
Test status
Simulation time 44242616 ps
CPU time 0.7 seconds
Started Apr 21 12:56:24 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 205308 kb
Host smart-40d6669c-67d4-49c3-a3ce-fb4383a1ded5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261365670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3261365670
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3847824525
Short name T109
Test name
Test status
Simulation time 1857742229 ps
CPU time 15.93 seconds
Started Apr 21 12:56:27 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 223308 kb
Host smart-e88e9c42-0c27-4fac-87d6-5c5bac683b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847824525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3847824525
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.909514534
Short name T639
Test name
Test status
Simulation time 73056749 ps
CPU time 0.77 seconds
Started Apr 21 12:56:19 PM PDT 24
Finished Apr 21 12:56:20 PM PDT 24
Peak memory 206460 kb
Host smart-da885c71-4703-45c6-bdb0-1f52b086e943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909514534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.909514534
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2182062704
Short name T299
Test name
Test status
Simulation time 1495999310 ps
CPU time 25.83 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:51 PM PDT 24
Peak memory 248980 kb
Host smart-12ec4260-c7bb-456b-ba99-aa09d4fa47d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182062704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2182062704
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1417930733
Short name T92
Test name
Test status
Simulation time 1650145069 ps
CPU time 21.39 seconds
Started Apr 21 12:56:29 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 216632 kb
Host smart-9dab8caf-e33a-4f38-adec-4943a079693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417930733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1417930733
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1531194988
Short name T574
Test name
Test status
Simulation time 266472544 ps
CPU time 3.52 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 222312 kb
Host smart-c3e58869-8d80-4a9d-94af-237150c68425
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1531194988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1531194988
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.798211409
Short name T372
Test name
Test status
Simulation time 1013321228 ps
CPU time 10.5 seconds
Started Apr 21 12:56:20 PM PDT 24
Finished Apr 21 12:56:31 PM PDT 24
Peak memory 216308 kb
Host smart-196b36f1-f9e3-43d1-a1e7-4a20c3402dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798211409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.798211409
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2558752898
Short name T497
Test name
Test status
Simulation time 770649054 ps
CPU time 4.71 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:29 PM PDT 24
Peak memory 215916 kb
Host smart-43482f5b-6101-469d-82dc-a9bc2c2b1383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558752898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2558752898
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.261113203
Short name T634
Test name
Test status
Simulation time 53868732 ps
CPU time 1.29 seconds
Started Apr 21 12:56:28 PM PDT 24
Finished Apr 21 12:56:30 PM PDT 24
Peak memory 215940 kb
Host smart-e196939d-1a01-4054-9e45-07fc419b7b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261113203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.261113203
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2367971319
Short name T603
Test name
Test status
Simulation time 57664625 ps
CPU time 0.79 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 205608 kb
Host smart-ce501fcb-7fe2-43f6-8497-a188e0fcc753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367971319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2367971319
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1955625680
Short name T322
Test name
Test status
Simulation time 1840457470 ps
CPU time 7.05 seconds
Started Apr 21 12:56:30 PM PDT 24
Finished Apr 21 12:56:37 PM PDT 24
Peak memory 236776 kb
Host smart-c76de5c0-ffbd-4045-88a8-d19563c4e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955625680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1955625680
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1514363389
Short name T414
Test name
Test status
Simulation time 13246183 ps
CPU time 0.72 seconds
Started Apr 21 12:55:00 PM PDT 24
Finished Apr 21 12:55:01 PM PDT 24
Peak memory 204772 kb
Host smart-0f18e57d-4df9-41f5-a8f5-f2249af9f307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514363389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
514363389
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.970369973
Short name T437
Test name
Test status
Simulation time 47031797 ps
CPU time 0.74 seconds
Started Apr 21 12:55:05 PM PDT 24
Finished Apr 21 12:55:06 PM PDT 24
Peak memory 205444 kb
Host smart-ae2a42a1-9652-49af-b030-8396fb94cb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970369973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.970369973
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4076865056
Short name T643
Test name
Test status
Simulation time 592154297 ps
CPU time 18.33 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:55:29 PM PDT 24
Peak memory 254912 kb
Host smart-9857ae52-9b4e-4b7a-9306-ac391dd038e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076865056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4076865056
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.230872117
Short name T80
Test name
Test status
Simulation time 1383010463 ps
CPU time 15.06 seconds
Started Apr 21 12:55:03 PM PDT 24
Finished Apr 21 12:55:19 PM PDT 24
Peak memory 223076 kb
Host smart-28085896-3eba-498e-83b6-8aea9039a3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230872117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.230872117
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1134505441
Short name T7
Test name
Test status
Simulation time 46139738385 ps
CPU time 106.24 seconds
Started Apr 21 12:55:01 PM PDT 24
Finished Apr 21 12:56:48 PM PDT 24
Peak memory 233676 kb
Host smart-e8dc6b7a-dce6-4ffa-9e40-5e20a49346ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134505441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1134505441
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.867184070
Short name T329
Test name
Test status
Simulation time 1041411173 ps
CPU time 6.85 seconds
Started Apr 21 12:55:05 PM PDT 24
Finished Apr 21 12:55:12 PM PDT 24
Peak memory 222556 kb
Host smart-914554d1-4d14-4b7c-85e2-33f3e39068f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867184070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.867184070
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3338224206
Short name T585
Test name
Test status
Simulation time 2081892987 ps
CPU time 4.41 seconds
Started Apr 21 12:54:54 PM PDT 24
Finished Apr 21 12:54:59 PM PDT 24
Peak memory 218960 kb
Host smart-08ae9a6d-bd0b-438a-b786-a66c54531a5e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3338224206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3338224206
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2647553810
Short name T34
Test name
Test status
Simulation time 206912051 ps
CPU time 1.05 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:54:54 PM PDT 24
Peak memory 234976 kb
Host smart-095d935f-aa13-46c0-99e8-df96213164e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647553810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2647553810
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3281464171
Short name T162
Test name
Test status
Simulation time 79923988 ps
CPU time 1.32 seconds
Started Apr 21 12:55:00 PM PDT 24
Finished Apr 21 12:55:02 PM PDT 24
Peak memory 207092 kb
Host smart-bfd0765a-5333-4aa6-b095-a1bd8f318772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281464171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3281464171
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.190698986
Short name T371
Test name
Test status
Simulation time 3258689291 ps
CPU time 13.58 seconds
Started Apr 21 12:54:55 PM PDT 24
Finished Apr 21 12:55:09 PM PDT 24
Peak memory 216224 kb
Host smart-af5b4868-a299-4fb1-9bd6-5bbfa5d85727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190698986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.190698986
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3230412915
Short name T586
Test name
Test status
Simulation time 32200954730 ps
CPU time 24.25 seconds
Started Apr 21 12:55:05 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 216300 kb
Host smart-160dcf65-d3c8-4084-ab80-ec894270f6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230412915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3230412915
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1182735043
Short name T597
Test name
Test status
Simulation time 384444283 ps
CPU time 1.96 seconds
Started Apr 21 12:55:01 PM PDT 24
Finished Apr 21 12:55:03 PM PDT 24
Peak memory 216108 kb
Host smart-5af4c692-db03-4dd0-83f8-57047bdbb63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182735043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1182735043
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.719741460
Short name T604
Test name
Test status
Simulation time 45068683 ps
CPU time 0.91 seconds
Started Apr 21 12:54:54 PM PDT 24
Finished Apr 21 12:54:55 PM PDT 24
Peak memory 205696 kb
Host smart-c35a1dfa-5704-431e-9fa0-f4600a50eaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719741460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.719741460
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2344036430
Short name T318
Test name
Test status
Simulation time 304046171 ps
CPU time 2.96 seconds
Started Apr 21 12:55:03 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 222956 kb
Host smart-5fdd7756-4fcf-4f1a-bb3e-7039935bbfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344036430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2344036430
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2239927577
Short name T622
Test name
Test status
Simulation time 14154366 ps
CPU time 0.72 seconds
Started Apr 21 12:56:32 PM PDT 24
Finished Apr 21 12:56:33 PM PDT 24
Peak memory 204804 kb
Host smart-8e95aae8-5a9a-489a-a8b6-0e624a4f18cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239927577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2239927577
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2414011043
Short name T406
Test name
Test status
Simulation time 71133924 ps
CPU time 0.8 seconds
Started Apr 21 12:56:22 PM PDT 24
Finished Apr 21 12:56:24 PM PDT 24
Peak memory 206468 kb
Host smart-4f5244e3-11e7-4df3-88d3-758430438dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414011043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2414011043
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2194034590
Short name T297
Test name
Test status
Simulation time 404036918 ps
CPU time 15.31 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:41 PM PDT 24
Peak memory 233616 kb
Host smart-e72cc924-c02e-4413-b0ee-51c93f3e1dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194034590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2194034590
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3693598186
Short name T90
Test name
Test status
Simulation time 8085844747 ps
CPU time 29.29 seconds
Started Apr 21 12:56:27 PM PDT 24
Finished Apr 21 12:56:57 PM PDT 24
Peak memory 222396 kb
Host smart-2a138ab1-e539-4c7f-92bd-9dbc3103ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693598186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3693598186
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4158053750
Short name T250
Test name
Test status
Simulation time 41290182822 ps
CPU time 30.91 seconds
Started Apr 21 12:56:35 PM PDT 24
Finished Apr 21 12:57:06 PM PDT 24
Peak memory 232612 kb
Host smart-7a76e0e0-6863-4838-9673-8d23bda7ee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158053750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4158053750
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.175773166
Short name T477
Test name
Test status
Simulation time 674478216 ps
CPU time 5.35 seconds
Started Apr 21 12:56:26 PM PDT 24
Finished Apr 21 12:56:33 PM PDT 24
Peak memory 222292 kb
Host smart-510f3d10-9a87-4cc0-9264-3d50f734b378
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=175773166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.175773166
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1085299638
Short name T52
Test name
Test status
Simulation time 2323336611 ps
CPU time 10.5 seconds
Started Apr 21 12:56:23 PM PDT 24
Finished Apr 21 12:56:34 PM PDT 24
Peak memory 216272 kb
Host smart-7b7e05fc-16af-4494-8141-6b7eb2576f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085299638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1085299638
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2020205387
Short name T683
Test name
Test status
Simulation time 2025530004 ps
CPU time 5.42 seconds
Started Apr 21 12:56:20 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 216204 kb
Host smart-58aca79f-2c2d-4a3b-8d55-84d0ed98d64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020205387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2020205387
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4029415162
Short name T627
Test name
Test status
Simulation time 53824690 ps
CPU time 1.57 seconds
Started Apr 21 12:56:30 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 216232 kb
Host smart-69576e34-6928-4ae9-808b-fa855311e87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029415162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4029415162
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3831737041
Short name T553
Test name
Test status
Simulation time 166070110 ps
CPU time 0.98 seconds
Started Apr 21 12:56:31 PM PDT 24
Finished Apr 21 12:56:33 PM PDT 24
Peak memory 205632 kb
Host smart-3a60ace0-e9cb-4469-8d16-57c82b8da712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831737041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3831737041
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3272503305
Short name T596
Test name
Test status
Simulation time 83353477743 ps
CPU time 55.17 seconds
Started Apr 21 12:56:27 PM PDT 24
Finished Apr 21 12:57:23 PM PDT 24
Peak memory 235992 kb
Host smart-28cfb124-e068-4e86-a4e7-db05146925ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272503305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3272503305
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.696721343
Short name T460
Test name
Test status
Simulation time 12354379 ps
CPU time 0.7 seconds
Started Apr 21 12:56:28 PM PDT 24
Finished Apr 21 12:56:29 PM PDT 24
Peak memory 205300 kb
Host smart-08138359-ed77-454c-a9cd-d6b135800f85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696721343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.696721343
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2867707103
Short name T697
Test name
Test status
Simulation time 19118797 ps
CPU time 0.77 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:26 PM PDT 24
Peak memory 206832 kb
Host smart-8a08d04c-b921-4188-b7df-63927fe3160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867707103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2867707103
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2276351044
Short name T300
Test name
Test status
Simulation time 5360701704 ps
CPU time 79.48 seconds
Started Apr 21 12:56:26 PM PDT 24
Finished Apr 21 12:57:47 PM PDT 24
Peak memory 250776 kb
Host smart-c4f6e117-274e-44c0-8c3c-2946d2b0063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276351044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2276351044
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2562557243
Short name T4
Test name
Test status
Simulation time 6334320810 ps
CPU time 11.54 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:38 PM PDT 24
Peak memory 224396 kb
Host smart-356fea75-aa17-4516-9303-37416502b350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562557243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2562557243
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3704982896
Short name T207
Test name
Test status
Simulation time 1511000850 ps
CPU time 5.86 seconds
Started Apr 21 12:56:27 PM PDT 24
Finished Apr 21 12:56:34 PM PDT 24
Peak memory 218636 kb
Host smart-c1147072-6eb0-459e-97aa-e008291cec07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704982896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3704982896
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2252089714
Short name T453
Test name
Test status
Simulation time 410152586 ps
CPU time 4.12 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:46 PM PDT 24
Peak memory 222980 kb
Host smart-bec1eebd-6102-478b-b285-c03966b15e90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2252089714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2252089714
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3155682151
Short name T377
Test name
Test status
Simulation time 14597410490 ps
CPU time 27.82 seconds
Started Apr 21 12:56:26 PM PDT 24
Finished Apr 21 12:56:55 PM PDT 24
Peak memory 216208 kb
Host smart-677126ca-ac73-4b30-8733-034d96339243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155682151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3155682151
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.313250424
Short name T555
Test name
Test status
Simulation time 518955287 ps
CPU time 3.98 seconds
Started Apr 21 12:56:38 PM PDT 24
Finished Apr 21 12:56:42 PM PDT 24
Peak memory 216184 kb
Host smart-b3416d44-1135-4816-a7ce-47930d4ee10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313250424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.313250424
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3113609567
Short name T516
Test name
Test status
Simulation time 484961814 ps
CPU time 2.92 seconds
Started Apr 21 12:56:28 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 216204 kb
Host smart-c9a7612a-5c74-4234-81f5-f048b1c377cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113609567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3113609567
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2810758306
Short name T479
Test name
Test status
Simulation time 41902119 ps
CPU time 0.83 seconds
Started Apr 21 12:56:25 PM PDT 24
Finished Apr 21 12:56:27 PM PDT 24
Peak memory 205680 kb
Host smart-435e3650-8542-4720-bf3d-86a77cb8a5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810758306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2810758306
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4172529780
Short name T191
Test name
Test status
Simulation time 913244573 ps
CPU time 9.24 seconds
Started Apr 21 12:56:27 PM PDT 24
Finished Apr 21 12:56:37 PM PDT 24
Peak memory 235212 kb
Host smart-bcff71cf-bf4d-4057-bffb-76023c7bfbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172529780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4172529780
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.137826209
Short name T517
Test name
Test status
Simulation time 44205117 ps
CPU time 0.71 seconds
Started Apr 21 12:56:38 PM PDT 24
Finished Apr 21 12:56:39 PM PDT 24
Peak memory 204776 kb
Host smart-a94ce1f2-43c4-40ef-931a-7a4639aba47a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137826209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.137826209
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.7150922
Short name T84
Test name
Test status
Simulation time 1495145855 ps
CPU time 16.61 seconds
Started Apr 21 12:56:43 PM PDT 24
Finished Apr 21 12:57:00 PM PDT 24
Peak memory 218640 kb
Host smart-54fb8f67-bc12-4df1-b869-acec307b87c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7150922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.7150922
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3129525195
Short name T407
Test name
Test status
Simulation time 95063263 ps
CPU time 0.82 seconds
Started Apr 21 12:56:37 PM PDT 24
Finished Apr 21 12:56:38 PM PDT 24
Peak memory 206476 kb
Host smart-51229988-6dd9-4efe-83fc-0531b40c6fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129525195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3129525195
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_intercept.876384139
Short name T255
Test name
Test status
Simulation time 1103946425 ps
CPU time 4.66 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:46 PM PDT 24
Peak memory 221364 kb
Host smart-00947c25-23af-400d-9486-f8b86a5bc942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876384139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.876384139
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2799180335
Short name T529
Test name
Test status
Simulation time 191478614 ps
CPU time 4.08 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 222648 kb
Host smart-cddd8dd3-e1da-4ebe-9560-760068d3c285
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2799180335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2799180335
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4206576272
Short name T374
Test name
Test status
Simulation time 20931331985 ps
CPU time 24.92 seconds
Started Apr 21 12:56:29 PM PDT 24
Finished Apr 21 12:56:54 PM PDT 24
Peak memory 216212 kb
Host smart-44bf00c5-4ee3-448f-b235-3048fe0b7313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206576272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4206576272
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.635160922
Short name T532
Test name
Test status
Simulation time 6069312881 ps
CPU time 18.48 seconds
Started Apr 21 12:56:34 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 216264 kb
Host smart-0b82f495-0ce9-4cac-90df-67a286489958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635160922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.635160922
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1926794226
Short name T13
Test name
Test status
Simulation time 229195558 ps
CPU time 1.76 seconds
Started Apr 21 12:56:40 PM PDT 24
Finished Apr 21 12:56:42 PM PDT 24
Peak memory 216196 kb
Host smart-5cd110d8-9d01-4419-badb-664d47e9fcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926794226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1926794226
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1492979716
Short name T567
Test name
Test status
Simulation time 206904416 ps
CPU time 1.02 seconds
Started Apr 21 12:56:35 PM PDT 24
Finished Apr 21 12:56:37 PM PDT 24
Peak memory 206656 kb
Host smart-d82ad46d-4004-40d6-80cc-31c6c142249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492979716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1492979716
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3871333919
Short name T571
Test name
Test status
Simulation time 39370758 ps
CPU time 0.7 seconds
Started Apr 21 12:56:38 PM PDT 24
Finished Apr 21 12:56:39 PM PDT 24
Peak memory 204756 kb
Host smart-4996a2a8-33b4-4e23-8dd3-9d0f091a3ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871333919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3871333919
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2386396386
Short name T456
Test name
Test status
Simulation time 49288479 ps
CPU time 0.76 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 206804 kb
Host smart-d4ecd0af-6cf8-45c2-9768-1583b3fc9504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386396386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2386396386
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3859993137
Short name T485
Test name
Test status
Simulation time 19913005963 ps
CPU time 120.69 seconds
Started Apr 21 12:56:34 PM PDT 24
Finished Apr 21 12:58:35 PM PDT 24
Peak memory 249052 kb
Host smart-7186e987-d263-4aa5-8117-f71a6fb4b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859993137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3859993137
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1823572104
Short name T197
Test name
Test status
Simulation time 8288016867 ps
CPU time 23.85 seconds
Started Apr 21 12:56:39 PM PDT 24
Finished Apr 21 12:57:03 PM PDT 24
Peak memory 216436 kb
Host smart-19a5f37a-7c30-40b3-ae29-d23da2e5d239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823572104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1823572104
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3954475529
Short name T115
Test name
Test status
Simulation time 186308868 ps
CPU time 5.57 seconds
Started Apr 21 12:56:38 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 232204 kb
Host smart-025f0639-142e-40d1-a42e-7db09ec46b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954475529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3954475529
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2160355618
Short name T672
Test name
Test status
Simulation time 2547532718 ps
CPU time 7.87 seconds
Started Apr 21 12:56:44 PM PDT 24
Finished Apr 21 12:56:52 PM PDT 24
Peak memory 223052 kb
Host smart-5030c848-276d-4635-8e25-1bdf157a35ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2160355618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2160355618
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.522635337
Short name T354
Test name
Test status
Simulation time 224476725 ps
CPU time 1.02 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:43 PM PDT 24
Peak memory 207120 kb
Host smart-eb77c84a-26a9-4d7b-861f-f02af6f971bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522635337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.522635337
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3758566111
Short name T701
Test name
Test status
Simulation time 8995011167 ps
CPU time 31.57 seconds
Started Apr 21 12:56:31 PM PDT 24
Finished Apr 21 12:57:03 PM PDT 24
Peak memory 216300 kb
Host smart-253e617d-2110-4a19-974d-6a0e1c64a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758566111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3758566111
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2282146252
Short name T650
Test name
Test status
Simulation time 6345200174 ps
CPU time 14.16 seconds
Started Apr 21 12:56:40 PM PDT 24
Finished Apr 21 12:56:55 PM PDT 24
Peak memory 216152 kb
Host smart-394ad649-d364-4146-89d1-837577896366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282146252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2282146252
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1503291656
Short name T49
Test name
Test status
Simulation time 137919578 ps
CPU time 2.2 seconds
Started Apr 21 12:56:38 PM PDT 24
Finished Apr 21 12:56:40 PM PDT 24
Peak memory 216164 kb
Host smart-2972a93e-d623-4d18-a482-531e63bd744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503291656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1503291656
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3434729765
Short name T710
Test name
Test status
Simulation time 17132935 ps
CPU time 0.74 seconds
Started Apr 21 12:56:39 PM PDT 24
Finished Apr 21 12:56:40 PM PDT 24
Peak memory 205648 kb
Host smart-6ac137ea-ac89-432a-99b2-2c8b4b0b528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434729765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3434729765
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.154541776
Short name T653
Test name
Test status
Simulation time 14442343 ps
CPU time 0.73 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:43 PM PDT 24
Peak memory 205364 kb
Host smart-9e95d4c2-eb07-415d-9f7e-e41930707397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154541776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.154541776
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.713803564
Short name T681
Test name
Test status
Simulation time 90661427 ps
CPU time 0.79 seconds
Started Apr 21 12:56:40 PM PDT 24
Finished Apr 21 12:56:41 PM PDT 24
Peak memory 206872 kb
Host smart-9d605b44-3ea1-4b70-be0e-241f90f30e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713803564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.713803564
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3076709969
Short name T544
Test name
Test status
Simulation time 6556376111 ps
CPU time 32.94 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:57:15 PM PDT 24
Peak memory 248956 kb
Host smart-472a1ba8-787b-4691-b033-c52749738e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076709969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3076709969
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3612331582
Short name T699
Test name
Test status
Simulation time 67996162 ps
CPU time 2.5 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 216540 kb
Host smart-8cd6fe20-fe8b-4a03-a3ea-e697778b1c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612331582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3612331582
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2255344732
Short name T507
Test name
Test status
Simulation time 314371614 ps
CPU time 3.75 seconds
Started Apr 21 12:56:37 PM PDT 24
Finished Apr 21 12:56:41 PM PDT 24
Peak memory 220108 kb
Host smart-6a31cfad-f135-4e32-8e33-64b16ef9222b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2255344732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2255344732
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1225144716
Short name T551
Test name
Test status
Simulation time 1491172238 ps
CPU time 8.43 seconds
Started Apr 21 12:56:32 PM PDT 24
Finished Apr 21 12:56:41 PM PDT 24
Peak memory 216120 kb
Host smart-fe49755e-e97a-4367-8aca-aed922c0cf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225144716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1225144716
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3992129895
Short name T546
Test name
Test status
Simulation time 35170513 ps
CPU time 1.36 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 216152 kb
Host smart-6b7e4ad1-55f0-4a6d-8cd3-6e3b4c50f02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992129895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3992129895
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.643758508
Short name T599
Test name
Test status
Simulation time 275717655 ps
CPU time 0.96 seconds
Started Apr 21 12:56:45 PM PDT 24
Finished Apr 21 12:56:47 PM PDT 24
Peak memory 205696 kb
Host smart-6fb94cf3-9e61-4795-ac18-210d2ea69543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643758508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.643758508
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.180569087
Short name T241
Test name
Test status
Simulation time 434891649 ps
CPU time 4.35 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:47 PM PDT 24
Peak memory 223152 kb
Host smart-00c39a21-a3ce-4078-b046-8e8350e8cba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180569087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.180569087
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2565393526
Short name T33
Test name
Test status
Simulation time 37317843 ps
CPU time 0.71 seconds
Started Apr 21 12:56:44 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 205344 kb
Host smart-dbf6b812-fe7e-4475-bfee-47af5b261ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565393526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2565393526
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3199803699
Short name T547
Test name
Test status
Simulation time 37114519 ps
CPU time 0.77 seconds
Started Apr 21 12:56:38 PM PDT 24
Finished Apr 21 12:56:39 PM PDT 24
Peak memory 206516 kb
Host smart-0eb92a27-108d-4e71-b002-3f7da1635048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199803699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3199803699
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3466327505
Short name T582
Test name
Test status
Simulation time 7639259067 ps
CPU time 29.81 seconds
Started Apr 21 12:56:40 PM PDT 24
Finished Apr 21 12:57:10 PM PDT 24
Peak memory 240472 kb
Host smart-728f8110-5571-425e-8414-7364a61ca85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466327505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3466327505
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3053275713
Short name T188
Test name
Test status
Simulation time 1410291197 ps
CPU time 10.27 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 218292 kb
Host smart-d270b3ef-5660-4148-8039-1a80a96a5fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053275713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3053275713
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1003817571
Short name T120
Test name
Test status
Simulation time 38723188140 ps
CPU time 77.88 seconds
Started Apr 21 12:56:36 PM PDT 24
Finished Apr 21 12:57:54 PM PDT 24
Peak memory 232420 kb
Host smart-ae381a9b-db3e-473c-b94d-434fec361827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003817571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1003817571
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.871345087
Short name T335
Test name
Test status
Simulation time 1238148562 ps
CPU time 5.84 seconds
Started Apr 21 12:56:40 PM PDT 24
Finished Apr 21 12:56:47 PM PDT 24
Peak memory 234004 kb
Host smart-1c49e42b-5d22-4aa4-a2c9-615596f31fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871345087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.871345087
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2337307518
Short name T676
Test name
Test status
Simulation time 3892518798 ps
CPU time 5.3 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:48 PM PDT 24
Peak memory 216608 kb
Host smart-c8bb23c7-4b4a-4723-83e8-f831b77b9300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337307518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2337307518
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2806756708
Short name T648
Test name
Test status
Simulation time 1833098014 ps
CPU time 10.74 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 221160 kb
Host smart-8607dd00-da88-4aeb-8753-1b1766513e2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2806756708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2806756708
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4114675548
Short name T376
Test name
Test status
Simulation time 5062686186 ps
CPU time 33.04 seconds
Started Apr 21 12:56:40 PM PDT 24
Finished Apr 21 12:57:14 PM PDT 24
Peak memory 216192 kb
Host smart-2e07f657-f545-4d1a-8401-c518346a7f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114675548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4114675548
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3637825995
Short name T430
Test name
Test status
Simulation time 536821834 ps
CPU time 2.26 seconds
Started Apr 21 12:56:38 PM PDT 24
Finished Apr 21 12:56:41 PM PDT 24
Peak memory 206844 kb
Host smart-d93ecf99-41a7-41b5-bfaa-955c038527ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637825995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3637825995
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4130981878
Short name T1
Test name
Test status
Simulation time 399968904 ps
CPU time 6.67 seconds
Started Apr 21 12:56:42 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 216304 kb
Host smart-3fb5643f-15c1-4afa-bef9-4c0d3ad0e5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130981878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4130981878
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3889495426
Short name T702
Test name
Test status
Simulation time 36568158 ps
CPU time 0.72 seconds
Started Apr 21 12:56:46 PM PDT 24
Finished Apr 21 12:56:47 PM PDT 24
Peak memory 205640 kb
Host smart-c3739495-853f-4c23-9079-9045a0d2487a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889495426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3889495426
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1686666152
Short name T660
Test name
Test status
Simulation time 26183409 ps
CPU time 0.72 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 205356 kb
Host smart-21818d3f-e559-41d9-bab6-cbfe9094c61a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686666152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1686666152
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1866301379
Short name T445
Test name
Test status
Simulation time 71731682 ps
CPU time 0.8 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:56:51 PM PDT 24
Peak memory 206500 kb
Host smart-b1e66e5d-7522-43ca-aa25-caaf893c1b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866301379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1866301379
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2750090700
Short name T522
Test name
Test status
Simulation time 2818694053 ps
CPU time 42.48 seconds
Started Apr 21 12:56:50 PM PDT 24
Finished Apr 21 12:57:33 PM PDT 24
Peak memory 240824 kb
Host smart-bf019fae-e7db-41b7-802a-97e81032735c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750090700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2750090700
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1261641794
Short name T309
Test name
Test status
Simulation time 269656897 ps
CPU time 6.18 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:48 PM PDT 24
Peak memory 223780 kb
Host smart-b37577aa-d298-4d1f-a8e2-7c79e0c342de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261641794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1261641794
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4542055
Short name T491
Test name
Test status
Simulation time 200793525 ps
CPU time 3.65 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 222948 kb
Host smart-9f4165e0-1fe9-48cf-9ac4-c0ba587a1616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4542055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4542055
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3817671285
Short name T244
Test name
Test status
Simulation time 507845728 ps
CPU time 2.82 seconds
Started Apr 21 12:56:47 PM PDT 24
Finished Apr 21 12:56:51 PM PDT 24
Peak memory 218776 kb
Host smart-038c98b7-fa1e-43f2-a930-b9de41a269a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817671285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3817671285
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1253029020
Short name T313
Test name
Test status
Simulation time 2157570295 ps
CPU time 6.42 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:56:56 PM PDT 24
Peak memory 218328 kb
Host smart-24887d06-e112-4e3f-83db-3bbc1ba00e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253029020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1253029020
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.735473959
Short name T423
Test name
Test status
Simulation time 1734736511 ps
CPU time 8.37 seconds
Started Apr 21 12:56:46 PM PDT 24
Finished Apr 21 12:56:55 PM PDT 24
Peak memory 218688 kb
Host smart-f7b16095-153b-4438-9339-c520edc1ba47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=735473959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.735473959
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1534783809
Short name T396
Test name
Test status
Simulation time 895292640 ps
CPU time 2.05 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 216140 kb
Host smart-f1492300-e121-47cb-b5e8-00ac3c9d8036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534783809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1534783809
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2290745085
Short name T590
Test name
Test status
Simulation time 11262124950 ps
CPU time 7.47 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 216124 kb
Host smart-af484b65-4577-4083-bcdd-a0e17457cd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290745085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2290745085
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.668824131
Short name T700
Test name
Test status
Simulation time 126785552 ps
CPU time 2.75 seconds
Started Apr 21 12:56:41 PM PDT 24
Finished Apr 21 12:56:44 PM PDT 24
Peak memory 216204 kb
Host smart-be8b498e-eefe-4a66-96dc-ddd3f430e0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668824131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.668824131
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.577426258
Short name T556
Test name
Test status
Simulation time 201714392 ps
CPU time 0.9 seconds
Started Apr 21 12:56:50 PM PDT 24
Finished Apr 21 12:56:51 PM PDT 24
Peak memory 206676 kb
Host smart-ba0c2a8a-7aa2-4429-9cd7-42fba4ea9bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577426258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.577426258
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1313717899
Short name T208
Test name
Test status
Simulation time 957609431 ps
CPU time 4.51 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 223260 kb
Host smart-1fe5a7c2-85f4-4f58-b917-2f2dc6a53a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313717899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1313717899
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1360579240
Short name T415
Test name
Test status
Simulation time 15210188 ps
CPU time 0.73 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 204740 kb
Host smart-87ad4e08-8741-4c41-a9f6-f49d110635d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360579240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1360579240
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2790580542
Short name T468
Test name
Test status
Simulation time 86797047 ps
CPU time 0.76 seconds
Started Apr 21 12:56:44 PM PDT 24
Finished Apr 21 12:56:45 PM PDT 24
Peak memory 205688 kb
Host smart-96ccdeea-c7c8-4e51-bd4a-08e3816357ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790580542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2790580542
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2794101341
Short name T137
Test name
Test status
Simulation time 5719468869 ps
CPU time 93.72 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:58:23 PM PDT 24
Peak memory 238820 kb
Host smart-614b6e4b-c7a1-4fb4-a6ea-3601939f7565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794101341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2794101341
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2969275729
Short name T167
Test name
Test status
Simulation time 37243419572 ps
CPU time 131.51 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:59:00 PM PDT 24
Peak memory 237920 kb
Host smart-e54e41c5-72f3-44b0-abda-777947cebf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969275729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2969275729
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2928626028
Short name T245
Test name
Test status
Simulation time 1908921505 ps
CPU time 13.1 seconds
Started Apr 21 12:56:54 PM PDT 24
Finished Apr 21 12:57:08 PM PDT 24
Peak memory 230280 kb
Host smart-1d610566-3b6b-4d54-9923-558aee37d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928626028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2928626028
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.100998382
Short name T204
Test name
Test status
Simulation time 4050899877 ps
CPU time 6.18 seconds
Started Apr 21 12:56:52 PM PDT 24
Finished Apr 21 12:56:58 PM PDT 24
Peak memory 222940 kb
Host smart-11397d3d-34f5-488b-b7a2-4c991d632b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100998382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.100998382
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2503346068
Short name T519
Test name
Test status
Simulation time 2436239948 ps
CPU time 7.03 seconds
Started Apr 21 12:56:45 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 219884 kb
Host smart-4368ec29-9e8a-4e19-94e9-39497432b106
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2503346068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2503346068
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3769045063
Short name T402
Test name
Test status
Simulation time 12603347861 ps
CPU time 69.13 seconds
Started Apr 21 12:56:43 PM PDT 24
Finished Apr 21 12:57:52 PM PDT 24
Peak memory 216164 kb
Host smart-68dd6772-62a4-4fe0-9fa9-f87ce396470b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769045063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3769045063
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2503794024
Short name T3
Test name
Test status
Simulation time 12308431759 ps
CPU time 14.12 seconds
Started Apr 21 12:56:47 PM PDT 24
Finished Apr 21 12:57:01 PM PDT 24
Peak memory 216252 kb
Host smart-0c5ea364-18ad-47a4-858a-e4aed98c99f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503794024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2503794024
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1161663447
Short name T405
Test name
Test status
Simulation time 388549571 ps
CPU time 2.24 seconds
Started Apr 21 12:56:43 PM PDT 24
Finished Apr 21 12:56:46 PM PDT 24
Peak memory 216212 kb
Host smart-55e71adb-71b9-47ef-9192-4b21353fa0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161663447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1161663447
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3053854229
Short name T677
Test name
Test status
Simulation time 83418247 ps
CPU time 0.82 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 205648 kb
Host smart-70aa26bf-c71e-4474-8b62-60c977cc1e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053854229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3053854229
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3385749389
Short name T487
Test name
Test status
Simulation time 6641273646 ps
CPU time 22.11 seconds
Started Apr 21 12:56:51 PM PDT 24
Finished Apr 21 12:57:14 PM PDT 24
Peak memory 238404 kb
Host smart-a6b75c90-a364-4a3f-a36e-f8d120340a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385749389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3385749389
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4066871830
Short name T482
Test name
Test status
Simulation time 14121423 ps
CPU time 0.7 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 205304 kb
Host smart-4440fee2-2562-4524-b1f1-38a6f06c61d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066871830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4066871830
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4272015412
Short name T275
Test name
Test status
Simulation time 234861166 ps
CPU time 2.45 seconds
Started Apr 21 12:56:50 PM PDT 24
Finished Apr 21 12:56:53 PM PDT 24
Peak memory 218328 kb
Host smart-6ea7ab29-c9f4-4f3d-8fc6-ea91f3ad4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272015412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4272015412
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2823662923
Short name T410
Test name
Test status
Simulation time 37474945 ps
CPU time 0.73 seconds
Started Apr 21 12:56:59 PM PDT 24
Finished Apr 21 12:57:00 PM PDT 24
Peak memory 205408 kb
Host smart-0155324e-7ad1-497d-bc5b-7004d78095a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823662923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2823662923
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4245311057
Short name T75
Test name
Test status
Simulation time 64536916939 ps
CPU time 126.77 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:58:57 PM PDT 24
Peak memory 229200 kb
Host smart-768b49e2-deab-4a94-b597-540e3b95de9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245311057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4245311057
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4188908221
Short name T61
Test name
Test status
Simulation time 9367996031 ps
CPU time 17.89 seconds
Started Apr 21 12:56:58 PM PDT 24
Finished Apr 21 12:57:17 PM PDT 24
Peak memory 248824 kb
Host smart-bd828a73-de6c-4262-8bcc-7623e9b2eb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188908221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4188908221
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.547350451
Short name T442
Test name
Test status
Simulation time 7527148814 ps
CPU time 22.02 seconds
Started Apr 21 12:56:51 PM PDT 24
Finished Apr 21 12:57:14 PM PDT 24
Peak memory 221344 kb
Host smart-403f7741-6667-4cde-9f9d-4b62365768a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=547350451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.547350451
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3327043123
Short name T392
Test name
Test status
Simulation time 2031421771 ps
CPU time 27.34 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:57:17 PM PDT 24
Peak memory 216312 kb
Host smart-8c46e8de-7dcd-4379-8377-44c0bb9f00aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327043123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3327043123
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.764541996
Short name T709
Test name
Test status
Simulation time 22010107060 ps
CPU time 11.03 seconds
Started Apr 21 12:56:47 PM PDT 24
Finished Apr 21 12:56:58 PM PDT 24
Peak memory 216100 kb
Host smart-68ee34fa-b3d8-4365-a546-20d0411d3fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764541996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.764541996
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2734495839
Short name T426
Test name
Test status
Simulation time 471589770 ps
CPU time 0.93 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 206488 kb
Host smart-6152821e-fed9-4a46-9715-304ccad715f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734495839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2734495839
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3382009541
Short name T678
Test name
Test status
Simulation time 35330156 ps
CPU time 0.86 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:50 PM PDT 24
Peak memory 205632 kb
Host smart-ccc46d2c-3e01-4a51-bbea-61a8e3094d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382009541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3382009541
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1931349832
Short name T505
Test name
Test status
Simulation time 24521162 ps
CPU time 0.75 seconds
Started Apr 21 12:56:50 PM PDT 24
Finished Apr 21 12:56:51 PM PDT 24
Peak memory 205360 kb
Host smart-ddaab8db-3997-433a-9c40-68901b7ffc19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931349832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1931349832
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1999991312
Short name T649
Test name
Test status
Simulation time 398158456 ps
CPU time 4.04 seconds
Started Apr 21 12:56:50 PM PDT 24
Finished Apr 21 12:56:55 PM PDT 24
Peak memory 218616 kb
Host smart-c72b301d-b7f8-46b2-bfdc-6d2a584a40af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999991312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1999991312
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1317711529
Short name T526
Test name
Test status
Simulation time 19998015 ps
CPU time 0.75 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 205376 kb
Host smart-3d6cf182-4d7d-47b8-b3fe-b5429650ae8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317711529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1317711529
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.908447761
Short name T694
Test name
Test status
Simulation time 42908727855 ps
CPU time 93.87 seconds
Started Apr 21 12:56:57 PM PDT 24
Finished Apr 21 12:58:31 PM PDT 24
Peak memory 235376 kb
Host smart-01660e91-4669-4436-b3bb-bf983001916e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908447761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.908447761
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3897935309
Short name T189
Test name
Test status
Simulation time 3706579087 ps
CPU time 34.54 seconds
Started Apr 21 12:56:54 PM PDT 24
Finished Apr 21 12:57:29 PM PDT 24
Peak memory 235504 kb
Host smart-9cde3503-d52b-49ae-a8c4-add7e210fa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897935309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3897935309
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2485399965
Short name T178
Test name
Test status
Simulation time 278296593 ps
CPU time 2.95 seconds
Started Apr 21 12:56:53 PM PDT 24
Finished Apr 21 12:56:56 PM PDT 24
Peak memory 222324 kb
Host smart-0a3c56be-ab7c-43c6-b217-a64abf23f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485399965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2485399965
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4075835102
Short name T691
Test name
Test status
Simulation time 1642009092 ps
CPU time 12.12 seconds
Started Apr 21 12:56:52 PM PDT 24
Finished Apr 21 12:57:04 PM PDT 24
Peak memory 218648 kb
Host smart-3c3c70cb-1cd1-4070-b8e9-3982b20f49d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4075835102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4075835102
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2224035375
Short name T383
Test name
Test status
Simulation time 6613365602 ps
CPU time 20 seconds
Started Apr 21 12:56:50 PM PDT 24
Finished Apr 21 12:57:11 PM PDT 24
Peak memory 216268 kb
Host smart-d27cb84b-401c-43f6-b075-4c9729083aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224035375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2224035375
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.322407751
Short name T535
Test name
Test status
Simulation time 1631792078 ps
CPU time 2.55 seconds
Started Apr 21 12:56:52 PM PDT 24
Finished Apr 21 12:56:55 PM PDT 24
Peak memory 216140 kb
Host smart-9a3b3e71-e74b-428c-984e-a8ff8328b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322407751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.322407751
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1398112727
Short name T615
Test name
Test status
Simulation time 23776213 ps
CPU time 0.93 seconds
Started Apr 21 12:56:49 PM PDT 24
Finished Apr 21 12:56:51 PM PDT 24
Peak memory 207140 kb
Host smart-063d6031-08cb-4906-8664-b61096c7cbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398112727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1398112727
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2303202047
Short name T458
Test name
Test status
Simulation time 243915535 ps
CPU time 0.87 seconds
Started Apr 21 12:56:48 PM PDT 24
Finished Apr 21 12:56:49 PM PDT 24
Peak memory 206124 kb
Host smart-87d65279-fc8d-4e30-9bb5-13615d5a16f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303202047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2303202047
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2652255816
Short name T184
Test name
Test status
Simulation time 7918147696 ps
CPU time 6.22 seconds
Started Apr 21 12:56:51 PM PDT 24
Finished Apr 21 12:56:58 PM PDT 24
Peak memory 221644 kb
Host smart-3acf3ee3-5fb1-49de-ac39-c4b6a283ddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652255816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2652255816
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2415902324
Short name T469
Test name
Test status
Simulation time 65887082 ps
CPU time 0.73 seconds
Started Apr 21 12:55:06 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 205392 kb
Host smart-8b1a75be-38b1-42fe-ae73-14d7769136c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415902324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
415902324
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.460898763
Short name T446
Test name
Test status
Simulation time 84412129 ps
CPU time 0.76 seconds
Started Apr 21 12:54:53 PM PDT 24
Finished Apr 21 12:54:54 PM PDT 24
Peak memory 206400 kb
Host smart-80301123-fdef-4a89-bfb8-3aad89f11df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460898763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.460898763
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2317382016
Short name T82
Test name
Test status
Simulation time 5567462777 ps
CPU time 76.12 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:56:33 PM PDT 24
Peak memory 233700 kb
Host smart-05a45c42-2422-4926-971e-82aa0eab1281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317382016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2317382016
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4153146981
Short name T119
Test name
Test status
Simulation time 5523744353 ps
CPU time 6.31 seconds
Started Apr 21 12:55:20 PM PDT 24
Finished Apr 21 12:55:26 PM PDT 24
Peak memory 218828 kb
Host smart-55ed8f67-51e7-4008-938c-61411f7fd64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153146981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4153146981
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3609057325
Short name T89
Test name
Test status
Simulation time 39227623456 ps
CPU time 66.74 seconds
Started Apr 21 12:55:01 PM PDT 24
Finished Apr 21 12:56:08 PM PDT 24
Peak memory 234308 kb
Host smart-b3c85cb4-a058-4be8-9eab-388a84c8d050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609057325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3609057325
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.69087852
Short name T496
Test name
Test status
Simulation time 3743849117 ps
CPU time 14.34 seconds
Started Apr 21 12:55:11 PM PDT 24
Finished Apr 21 12:55:26 PM PDT 24
Peak memory 220248 kb
Host smart-69faff9b-9655-42d0-bd67-8d1ab554a512
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=69087852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.69087852
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2200698046
Short name T642
Test name
Test status
Simulation time 576459336 ps
CPU time 3.33 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:55:01 PM PDT 24
Peak memory 216144 kb
Host smart-83fd8a92-efb4-4419-b29c-ecce128521f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200698046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2200698046
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1716964429
Short name T455
Test name
Test status
Simulation time 4793697539 ps
CPU time 15.88 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:30 PM PDT 24
Peak memory 216156 kb
Host smart-64eb20fc-65fe-41a9-8f35-ab20c07f0fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716964429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1716964429
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1235429551
Short name T418
Test name
Test status
Simulation time 20481156 ps
CPU time 0.86 seconds
Started Apr 21 12:54:55 PM PDT 24
Finished Apr 21 12:54:56 PM PDT 24
Peak memory 205732 kb
Host smart-fd324612-91f9-4802-8987-4e59ce376999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235429551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1235429551
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1440959833
Short name T495
Test name
Test status
Simulation time 188041890 ps
CPU time 0.93 seconds
Started Apr 21 12:55:03 PM PDT 24
Finished Apr 21 12:55:04 PM PDT 24
Peak memory 205680 kb
Host smart-1b71178a-48b8-4430-b8a7-b0cd7b4415c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440959833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1440959833
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2234793009
Short name T536
Test name
Test status
Simulation time 54501937 ps
CPU time 0.71 seconds
Started Apr 21 12:55:06 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 205672 kb
Host smart-1d37520d-55f1-4443-aac5-16d7adaad191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234793009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
234793009
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3230235136
Short name T85
Test name
Test status
Simulation time 75626677 ps
CPU time 2.28 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:55:18 PM PDT 24
Peak memory 219896 kb
Host smart-c03f522b-72c5-4c9a-a89c-f83c6737a621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230235136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3230235136
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3684814068
Short name T563
Test name
Test status
Simulation time 63228229 ps
CPU time 0.8 seconds
Started Apr 21 12:55:08 PM PDT 24
Finished Apr 21 12:55:09 PM PDT 24
Peak memory 206500 kb
Host smart-912ce660-c907-4588-8494-7856e67c5eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684814068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3684814068
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2474163772
Short name T350
Test name
Test status
Simulation time 5628771554 ps
CPU time 19.04 seconds
Started Apr 21 12:55:06 PM PDT 24
Finished Apr 21 12:55:25 PM PDT 24
Peak memory 232600 kb
Host smart-02f31f0d-ae80-40b4-87a1-81eb3fc2acf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474163772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2474163772
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3313460963
Short name T177
Test name
Test status
Simulation time 1082107064 ps
CPU time 12.22 seconds
Started Apr 21 12:55:11 PM PDT 24
Finished Apr 21 12:55:24 PM PDT 24
Peak memory 222924 kb
Host smart-30dbf2f4-8a22-436e-9088-5c738b7b4da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313460963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3313460963
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3506275173
Short name T279
Test name
Test status
Simulation time 1028738232 ps
CPU time 8.82 seconds
Started Apr 21 12:55:07 PM PDT 24
Finished Apr 21 12:55:16 PM PDT 24
Peak memory 218476 kb
Host smart-851e7892-2b76-457c-9e13-3b02540295be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506275173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3506275173
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1315722937
Short name T81
Test name
Test status
Simulation time 332089651 ps
CPU time 4.04 seconds
Started Apr 21 12:55:11 PM PDT 24
Finished Apr 21 12:55:16 PM PDT 24
Peak memory 222836 kb
Host smart-dd36a28f-6f95-436c-b407-02b5fff2b3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315722937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1315722937
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.4085920295
Short name T265
Test name
Test status
Simulation time 8871732875 ps
CPU time 7.61 seconds
Started Apr 21 12:55:06 PM PDT 24
Finished Apr 21 12:55:14 PM PDT 24
Peak memory 224472 kb
Host smart-9d4b7630-8c42-4ab3-bb50-59f7def16d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085920295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.4085920295
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2616988745
Short name T444
Test name
Test status
Simulation time 3121113084 ps
CPU time 10.71 seconds
Started Apr 21 12:55:03 PM PDT 24
Finished Apr 21 12:55:14 PM PDT 24
Peak memory 221396 kb
Host smart-a8984037-bd4b-49e5-91a9-2abea6f73fc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2616988745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2616988745
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3487422924
Short name T394
Test name
Test status
Simulation time 1342766137 ps
CPU time 18.24 seconds
Started Apr 21 12:55:09 PM PDT 24
Finished Apr 21 12:55:28 PM PDT 24
Peak memory 216440 kb
Host smart-f3b78e49-5c7b-48a9-9ebc-e928f9b39700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487422924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3487422924
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2134056250
Short name T499
Test name
Test status
Simulation time 1786106971 ps
CPU time 4.55 seconds
Started Apr 21 12:54:59 PM PDT 24
Finished Apr 21 12:55:04 PM PDT 24
Peak memory 216236 kb
Host smart-df955069-cc58-454b-95ee-d86f57f2a2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134056250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2134056250
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2817811731
Short name T695
Test name
Test status
Simulation time 28467007 ps
CPU time 0.82 seconds
Started Apr 21 12:55:06 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 206068 kb
Host smart-8d17a67b-fac4-4683-b7cc-04827dd0f4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817811731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2817811731
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2477869437
Short name T166
Test name
Test status
Simulation time 49774034 ps
CPU time 0.82 seconds
Started Apr 21 12:54:57 PM PDT 24
Finished Apr 21 12:54:59 PM PDT 24
Peak memory 205624 kb
Host smart-75e4e2b4-9e19-417c-ab50-b6593ebdfdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477869437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2477869437
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2859609425
Short name T12
Test name
Test status
Simulation time 930172289 ps
CPU time 5.93 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:55:22 PM PDT 24
Peak memory 234604 kb
Host smart-18009e12-cb32-4b90-b3e5-536dd68b9741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859609425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2859609425
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1473031550
Short name T605
Test name
Test status
Simulation time 13620735 ps
CPU time 0.74 seconds
Started Apr 21 12:55:22 PM PDT 24
Finished Apr 21 12:55:23 PM PDT 24
Peak memory 205120 kb
Host smart-316ffaa1-265d-4499-add4-ffa17efdc1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473031550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
473031550
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2497958129
Short name T176
Test name
Test status
Simulation time 10368263907 ps
CPU time 7.79 seconds
Started Apr 21 12:55:08 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 218552 kb
Host smart-3236f534-4375-42d4-8d06-77a600d5a62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497958129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2497958129
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4023782808
Short name T420
Test name
Test status
Simulation time 120936433 ps
CPU time 0.74 seconds
Started Apr 21 12:55:04 PM PDT 24
Finished Apr 21 12:55:05 PM PDT 24
Peak memory 206468 kb
Host smart-ef8383ac-cb7b-4d02-b332-d4f234bec2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023782808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4023782808
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3062376281
Short name T666
Test name
Test status
Simulation time 1379202540 ps
CPU time 14.82 seconds
Started Apr 21 12:55:03 PM PDT 24
Finished Apr 21 12:55:18 PM PDT 24
Peak memory 232520 kb
Host smart-66b5d20c-cfb1-40d2-8e1c-e93c1260595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062376281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3062376281
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1011132119
Short name T213
Test name
Test status
Simulation time 8521684225 ps
CPU time 18.3 seconds
Started Apr 21 12:55:15 PM PDT 24
Finished Apr 21 12:55:33 PM PDT 24
Peak memory 232684 kb
Host smart-9151bbf9-8c16-4d40-9fbe-94f33e8c4ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011132119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1011132119
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.666233535
Short name T283
Test name
Test status
Simulation time 388411025 ps
CPU time 9.51 seconds
Started Apr 21 12:55:07 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 226880 kb
Host smart-bed3357a-3be1-4073-9b6a-359475d9ad01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666233535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.666233535
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3332674961
Short name T669
Test name
Test status
Simulation time 1686634685 ps
CPU time 11.11 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:55:21 PM PDT 24
Peak memory 221732 kb
Host smart-db1efee7-0e60-4926-9845-6b8a896dcf0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3332674961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3332674961
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2093345449
Short name T391
Test name
Test status
Simulation time 1180579714 ps
CPU time 7.73 seconds
Started Apr 21 12:54:59 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 216200 kb
Host smart-9fb436a1-d845-4085-b898-28c3c1b87015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093345449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2093345449
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2824272886
Short name T576
Test name
Test status
Simulation time 11888190338 ps
CPU time 14.98 seconds
Started Apr 21 12:55:13 PM PDT 24
Finished Apr 21 12:55:28 PM PDT 24
Peak memory 216300 kb
Host smart-8999bd29-4980-40d6-8d30-22d6960bcf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824272886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2824272886
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4023854391
Short name T705
Test name
Test status
Simulation time 790842916 ps
CPU time 8.88 seconds
Started Apr 21 12:55:08 PM PDT 24
Finished Apr 21 12:55:18 PM PDT 24
Peak memory 216164 kb
Host smart-cd3cb144-0061-49fd-a673-2c9cc3209065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023854391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4023854391
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1784598523
Short name T689
Test name
Test status
Simulation time 22017102 ps
CPU time 0.78 seconds
Started Apr 21 12:54:59 PM PDT 24
Finished Apr 21 12:55:00 PM PDT 24
Peak memory 205704 kb
Host smart-58620d37-e04f-44bc-9546-d6b9016c998e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784598523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1784598523
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2155243554
Short name T679
Test name
Test status
Simulation time 13428037 ps
CPU time 0.71 seconds
Started Apr 21 12:55:19 PM PDT 24
Finished Apr 21 12:55:21 PM PDT 24
Peak memory 205384 kb
Host smart-6793bfb6-da02-4bc5-914a-29f9374212a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155243554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
155243554
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2777518318
Short name T411
Test name
Test status
Simulation time 50145168 ps
CPU time 0.8 seconds
Started Apr 21 12:55:15 PM PDT 24
Finished Apr 21 12:55:16 PM PDT 24
Peak memory 206836 kb
Host smart-53e4d79f-516e-430a-b4e4-9cb9914d19a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777518318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2777518318
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.122967798
Short name T294
Test name
Test status
Simulation time 3260973504 ps
CPU time 51.16 seconds
Started Apr 21 12:55:10 PM PDT 24
Finished Apr 21 12:56:02 PM PDT 24
Peak memory 240060 kb
Host smart-5f62ac2e-a6f8-4eac-a63f-41bc21c36095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122967798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.122967798
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.838513448
Short name T262
Test name
Test status
Simulation time 2252845776 ps
CPU time 20.02 seconds
Started Apr 21 12:55:24 PM PDT 24
Finished Apr 21 12:55:44 PM PDT 24
Peak memory 223840 kb
Host smart-2c2d0a5f-54ec-4217-8281-9f34ea6c8d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838513448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.838513448
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2189416656
Short name T306
Test name
Test status
Simulation time 78037781179 ps
CPU time 51.27 seconds
Started Apr 21 12:55:24 PM PDT 24
Finished Apr 21 12:56:16 PM PDT 24
Peak memory 239416 kb
Host smart-6b4a431f-e826-4915-8b48-04604ee9f6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189416656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2189416656
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1095547881
Short name T501
Test name
Test status
Simulation time 2815787328 ps
CPU time 10.09 seconds
Started Apr 21 12:55:12 PM PDT 24
Finished Apr 21 12:55:22 PM PDT 24
Peak memory 219104 kb
Host smart-6f083c4a-48b1-4d6f-8852-8f69b9229926
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1095547881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1095547881
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1515653734
Short name T614
Test name
Test status
Simulation time 844908064 ps
CPU time 2.42 seconds
Started Apr 21 12:55:07 PM PDT 24
Finished Apr 21 12:55:10 PM PDT 24
Peak memory 216124 kb
Host smart-137ab8b2-0682-41a5-b715-4f4dbe29cdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515653734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1515653734
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3680745805
Short name T439
Test name
Test status
Simulation time 50924631 ps
CPU time 1.12 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 207820 kb
Host smart-013c9164-7af2-4d63-a193-9c03099954d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680745805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3680745805
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3403816633
Short name T680
Test name
Test status
Simulation time 197740794 ps
CPU time 0.86 seconds
Started Apr 21 12:55:14 PM PDT 24
Finished Apr 21 12:55:15 PM PDT 24
Peak memory 205696 kb
Host smart-f5263412-9249-456e-8110-3f38a8ad9394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403816633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3403816633
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2295598958
Short name T461
Test name
Test status
Simulation time 128991135 ps
CPU time 0.72 seconds
Started Apr 21 12:55:11 PM PDT 24
Finished Apr 21 12:55:12 PM PDT 24
Peak memory 205364 kb
Host smart-e611281f-b086-4e13-9d5c-c4cbe97574cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295598958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
295598958
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4010635383
Short name T589
Test name
Test status
Simulation time 24747344 ps
CPU time 0.75 seconds
Started Apr 21 12:55:16 PM PDT 24
Finished Apr 21 12:55:17 PM PDT 24
Peak memory 205504 kb
Host smart-6ce8bcc3-3749-41a7-9cd1-42b9d3469485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010635383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4010635383
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3902987393
Short name T296
Test name
Test status
Simulation time 605176937 ps
CPU time 21.22 seconds
Started Apr 21 12:55:21 PM PDT 24
Finished Apr 21 12:55:42 PM PDT 24
Peak memory 240020 kb
Host smart-9d9d39f1-8482-4762-88df-b8168eaf7daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902987393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3902987393
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3307710291
Short name T269
Test name
Test status
Simulation time 2706625190 ps
CPU time 10.57 seconds
Started Apr 21 12:55:20 PM PDT 24
Finished Apr 21 12:55:31 PM PDT 24
Peak memory 223704 kb
Host smart-e8c82b6f-9123-4d8f-bd8e-8930669e2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307710291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3307710291
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3367912799
Short name T630
Test name
Test status
Simulation time 4689111250 ps
CPU time 23.24 seconds
Started Apr 21 12:55:04 PM PDT 24
Finished Apr 21 12:55:28 PM PDT 24
Peak memory 219196 kb
Host smart-9a9ff12e-3fde-43f4-862e-ac2769b812c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3367912799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3367912799
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.272881754
Short name T161
Test name
Test status
Simulation time 345320660 ps
CPU time 1.18 seconds
Started Apr 21 12:55:14 PM PDT 24
Finished Apr 21 12:55:16 PM PDT 24
Peak memory 207056 kb
Host smart-de013fd0-49c6-4a88-b277-361ce5e4a6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272881754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.272881754
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3119483293
Short name T704
Test name
Test status
Simulation time 6174412367 ps
CPU time 18.67 seconds
Started Apr 21 12:55:05 PM PDT 24
Finished Apr 21 12:55:24 PM PDT 24
Peak memory 216124 kb
Host smart-e8eee3e5-7b45-4244-9435-5822f5010075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119483293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3119483293
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3953941325
Short name T105
Test name
Test status
Simulation time 1335077462 ps
CPU time 5.36 seconds
Started Apr 21 12:55:02 PM PDT 24
Finished Apr 21 12:55:07 PM PDT 24
Peak memory 216136 kb
Host smart-06d52995-71d1-4363-acc1-87e2719f822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953941325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3953941325
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3345289405
Short name T511
Test name
Test status
Simulation time 408517919 ps
CPU time 2 seconds
Started Apr 21 12:55:23 PM PDT 24
Finished Apr 21 12:55:25 PM PDT 24
Peak memory 216224 kb
Host smart-a3ac3365-700b-49c0-840a-178b57e722e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345289405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3345289405
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.938992681
Short name T568
Test name
Test status
Simulation time 79280220 ps
CPU time 0.84 seconds
Started Apr 21 12:55:19 PM PDT 24
Finished Apr 21 12:55:20 PM PDT 24
Peak memory 205644 kb
Host smart-815be0af-3a68-4248-803a-e9857909da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938992681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.938992681
Directory /workspace/9.spi_device_tpm_sts_read/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%