Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1156334	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1309831

1

T1

1731

T2

145

T3

351

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1779520	1			T1	1677		T2	1233		T3	1
values[0x0]	342556	1			T1	461		T2	62		T3	213
values[0x1]	344089	1			T1	446		T2	68		T3	202

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	862979	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1603186

1

T1

1899

T2

531

T3

367

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9846	1			T1	15		T2	10		T13	15
valid_sources[0x01]	8160	1			T1	4		T2	7		T13	18
valid_sources[0x02]	7950	1			T1	5		T13	11		T4	6
valid_sources[0x03]	10753	1			T1	7		T2	1		T13	24
valid_sources[0x04]	9426	1			T1	11		T2	3		T13	17
valid_sources[0x05]	9775	1			T1	6		T2	2		T13	13
valid_sources[0x06]	8486	1			T1	7		T13	22		T4	2
valid_sources[0x07]	9061	1			T1	13		T2	3		T13	17
valid_sources[0x08]	9452	1			T1	21		T2	1		T13	19
valid_sources[0x09]	7836	1			T1	11		T13	13		T4	3
valid_sources[0x0a]	8091	1			T1	13		T2	4		T13	18
valid_sources[0x0b]	9440	1			T1	20		T13	17		T4	6
valid_sources[0x0c]	8425	1			T1	4		T2	2		T13	23
valid_sources[0x0d]	14130	1			T1	7		T2	1		T13	14
valid_sources[0x0e]	8270	1			T1	6		T13	12		T4	7
valid_sources[0x0f]	10305	1			T1	14		T2	10		T13	14
valid_sources[0x10]	10146	1			T1	7		T2	19		T13	15
valid_sources[0x11]	8006	1			T1	12		T2	6		T13	14
valid_sources[0x12]	8655	1			T1	10		T2	2		T13	20
valid_sources[0x13]	8946	1			T1	16		T2	1		T13	14
valid_sources[0x14]	7935	1			T1	9		T2	14		T13	15
valid_sources[0x15]	8029	1			T1	8		T13	20		T4	8
valid_sources[0x16]	15571	1			T1	5		T2	1		T13	28
valid_sources[0x17]	8879	1			T1	11		T2	6		T13	13
valid_sources[0x18]	8437	1			T1	8		T2	5		T13	20
valid_sources[0x19]	7526	1			T1	17		T13	24		T4	8
valid_sources[0x1a]	9265	1			T1	14		T2	1		T13	17
valid_sources[0x1b]	11540	1			T1	5		T2	7		T13	23
valid_sources[0x1c]	11962	1			T1	15		T13	20		T4	4
valid_sources[0x1d]	9822	1			T1	3		T2	7		T13	10
valid_sources[0x1e]	9302	1			T1	15		T13	20		T4	4
valid_sources[0x1f]	8313	1			T1	12		T2	1		T13	14
valid_sources[0x20]	7773	1			T1	2		T13	17		T4	6
valid_sources[0x21]	10413	1			T1	13		T2	2		T13	16
valid_sources[0x22]	9458	1			T1	11		T2	8		T13	16
valid_sources[0x23]	9307	1			T1	8		T2	4		T13	18
valid_sources[0x24]	8761	1			T1	8		T2	3		T13	18
valid_sources[0x25]	7657	1			T1	4		T2	3		T13	23
valid_sources[0x26]	9755	1			T1	11		T13	14		T4	6
valid_sources[0x27]	7890	1			T1	5		T2	1		T13	21
valid_sources[0x28]	7588	1			T1	8		T2	1		T13	14
valid_sources[0x29]	8891	1			T1	5		T13	15		T4	4
valid_sources[0x2a]	10595	1			T1	8		T13	19		T4	3
valid_sources[0x2b]	8040	1			T1	11		T2	30		T13	13
valid_sources[0x2c]	9172	1			T1	5		T13	15		T4	3
valid_sources[0x2d]	8136	1			T1	13		T2	10		T13	19
valid_sources[0x2e]	8579	1			T1	14		T13	11		T4	3
valid_sources[0x2f]	9190	1			T1	11		T13	15		T4	6
valid_sources[0x30]	12625	1			T1	9		T13	12		T4	9
valid_sources[0x31]	8322	1			T1	6		T2	11		T13	8
valid_sources[0x32]	7492	1			T1	5		T2	19		T13	17
valid_sources[0x33]	9776	1			T1	11		T13	15		T4	1
valid_sources[0x34]	9586	1			T1	10		T2	3		T13	20
valid_sources[0x35]	7990	1			T1	10		T2	8		T13	18
valid_sources[0x36]	8454	1			T1	16		T13	18		T4	5
valid_sources[0x37]	9216	1			T1	10		T2	5		T13	17
valid_sources[0x38]	15973	1			T1	9		T2	19		T13	18
valid_sources[0x39]	8805	1			T1	10		T13	18		T4	3
valid_sources[0x3a]	10801	1			T1	9		T2	10		T13	13
valid_sources[0x3b]	8420	1			T1	8		T13	19		T15	1
valid_sources[0x3c]	9210	1			T1	10		T2	5		T13	7
valid_sources[0x3d]	8463	1			T1	6		T2	14		T13	19
valid_sources[0x3e]	8368	1			T1	13		T2	5		T13	14
valid_sources[0x3f]	8884	1			T1	6		T2	5		T13	10
valid_sources[0x40]	9593	1			T1	6		T2	9		T13	28
valid_sources[0x41]	9108	1			T1	14		T13	21		T4	7
valid_sources[0x42]	8959	1			T1	11		T2	1		T13	10
valid_sources[0x43]	8797	1			T1	16		T2	4		T13	15
valid_sources[0x44]	10639	1			T1	9		T13	16		T4	5
valid_sources[0x45]	9675	1			T1	8		T2	4		T13	15
valid_sources[0x46]	10122	1			T1	13		T2	1		T13	24
valid_sources[0x47]	8948	1			T1	3		T2	7		T13	18
valid_sources[0x48]	8081	1			T1	10		T2	1		T13	8
valid_sources[0x49]	11078	1			T1	12		T13	15		T4	1
valid_sources[0x4a]	8075	1			T1	9		T2	7		T13	13
valid_sources[0x4b]	9115	1			T1	19		T2	9		T13	12
valid_sources[0x4c]	7564	1			T1	9		T2	11		T13	8
valid_sources[0x4d]	9582	1			T1	9		T2	9		T13	16
valid_sources[0x4e]	9058	1			T1	12		T2	7		T13	17
valid_sources[0x4f]	10162	1			T1	9		T13	18		T4	7
valid_sources[0x50]	8648	1			T1	16		T13	8		T4	3
valid_sources[0x51]	9569	1			T1	10		T2	8		T13	17
valid_sources[0x52]	9650	1			T1	9		T2	2		T13	17
valid_sources[0x53]	10006	1			T1	14		T13	13		T4	3
valid_sources[0x54]	9926	1			T1	8		T13	16		T4	4
valid_sources[0x55]	9021	1			T1	11		T2	15		T13	15
valid_sources[0x56]	7680	1			T1	7		T2	26		T13	14
valid_sources[0x57]	9215	1			T1	13		T13	12		T4	4
valid_sources[0x58]	11999	1			T1	9		T13	11		T4	1
valid_sources[0x59]	10044	1			T1	6		T13	19		T4	4
valid_sources[0x5a]	12058	1			T1	10		T13	12		T4	5
valid_sources[0x5b]	9205	1			T1	13		T13	17		T4	5
valid_sources[0x5c]	7711	1			T1	11		T2	4		T13	23
valid_sources[0x5d]	7513	1			T1	6		T13	19		T4	2
valid_sources[0x5e]	9834	1			T1	8		T2	8		T13	20
valid_sources[0x5f]	9074	1			T1	3		T2	1		T13	16
valid_sources[0x60]	7845	1			T1	7		T13	23		T4	9
valid_sources[0x61]	11869	1			T1	15		T2	5		T13	16
valid_sources[0x62]	15262	1			T1	6		T13	14		T4	3
valid_sources[0x63]	13838	1			T1	18		T2	1		T13	24
valid_sources[0x64]	8651	1			T1	19		T13	20		T4	6
valid_sources[0x65]	9388	1			T1	11		T2	17		T13	24
valid_sources[0x66]	9123	1			T1	10		T2	3		T13	11
valid_sources[0x67]	12304	1			T1	8		T13	11		T4	6
valid_sources[0x68]	8573	1			T1	13		T2	4		T13	14
valid_sources[0x69]	14751	1			T1	15		T2	6		T13	17
valid_sources[0x6a]	8263	1			T1	6		T13	14		T4	5
valid_sources[0x6b]	8642	1			T1	7		T13	10		T4	3
valid_sources[0x6c]	7944	1			T1	8		T13	12		T4	4
valid_sources[0x6d]	7479	1			T1	11		T2	7		T13	14
valid_sources[0x6e]	8263	1			T1	2		T13	16		T4	7
valid_sources[0x6f]	10218	1			T1	14		T2	11		T13	15
valid_sources[0x70]	9479	1			T1	7		T13	16		T4	4
valid_sources[0x71]	8123	1			T1	8		T2	5		T13	12
valid_sources[0x72]	8212	1			T1	10		T13	21		T4	8
valid_sources[0x73]	8364	1			T1	14		T2	6		T13	21
valid_sources[0x74]	9724	1			T1	4		T2	16		T13	15
valid_sources[0x75]	8616	1			T1	15		T13	13		T4	5
valid_sources[0x76]	9577	1			T1	13		T2	5		T13	21
valid_sources[0x77]	14681	1			T1	6		T13	18		T4	2
valid_sources[0x78]	9060	1			T1	11		T2	9		T13	9
valid_sources[0x79]	9166	1			T1	10		T2	16		T13	12
valid_sources[0x7a]	10344	1			T1	11		T2	19		T13	16
valid_sources[0x7b]	8810	1			T1	10		T2	17		T13	20
valid_sources[0x7c]	8537	1			T1	8		T13	17		T4	4
valid_sources[0x7d]	8295	1			T1	8		T2	24		T13	8
valid_sources[0x7e]	9848	1			T1	12		T2	6		T13	15
valid_sources[0x7f]	8262	1			T1	12		T2	2		T13	24
valid_sources[0x80]	8552	1			T1	16		T2	16		T13	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

690412

1

T1

828

T2

62

T13

27

values[0x0]

all_enables

biggest_size

312480

1

T1

460

T2

44

T3

178

values[0x1]

all_enables

biggest_size

306939

1

T1

443

T2

39

T3

173