Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1177820

1

T1

853

T2

1218

T3

65

full_word

1311089

1

T1

1731

T2

145

T3

351

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2488509	1			T1	2584		T2	1363		T3	416
auto[TlIntgErrCmd]	131	1			T33	10		T34	8		T35	6
auto[TlIntgErrData]	139	1			T33	12		T34	11		T35	8
auto[TlIntgErrBoth]	130	1			T33	8		T34	11		T35	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1783129

1

T1

1677

T2

1233

T3

1

auto[1]

705780

1

T1

907

T2

130

T3

415

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1092247	1			T1	849		T2	1171		T3	1
auto[TlIntgErrNone]	partial	auto[1]	85204	1			T1	4		T2	47		T3	64
auto[TlIntgErrNone]	full_word	auto[0]	690702	1			T1	828		T2	62		T13	27
auto[TlIntgErrNone]	full_word	auto[1]	620356	1			T1	903		T2	83		T3	351
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T33	4		T34	2		T35	1
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T33	4		T34	5		T35	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T33	1		T35	1		T372	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T33	1		T34	1		T35	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T33	5		T34	4		T35	3
auto[TlIntgErrData]	partial	auto[1]	67	1			T33	7		T34	6		T35	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T132	1		T373	1		T372	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T34	1		T35	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T33	4		T34	5		T35	3
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T33	4		T34	6		T35	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T132	1		T368	1		T369	2
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T132	1		T134	1		T369	1