Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3728 |
0 |
0 |
T33 |
29582 |
2 |
0 |
0 |
T34 |
91540 |
4 |
0 |
0 |
T35 |
20266 |
3 |
0 |
0 |
T110 |
8853 |
5 |
0 |
0 |
T112 |
5259 |
2 |
0 |
0 |
T116 |
16419 |
300 |
0 |
0 |
T117 |
8939 |
121 |
0 |
0 |
T132 |
28494 |
5 |
0 |
0 |
T133 |
9781 |
3 |
0 |
0 |
T134 |
35617 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1621 |
0 |
0 |
T34 |
91540 |
55 |
0 |
0 |
T37 |
12805 |
42 |
0 |
0 |
T129 |
15280 |
20 |
0 |
0 |
T131 |
94853 |
66 |
0 |
0 |
T134 |
35617 |
41 |
0 |
0 |
T163 |
8200 |
14 |
0 |
0 |
T164 |
7056 |
10 |
0 |
0 |
T165 |
78586 |
133 |
0 |
0 |
T166 |
12049 |
45 |
0 |
0 |
T167 |
5378 |
12 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1600 |
0 |
0 |
T34 |
91540 |
64 |
0 |
0 |
T37 |
12805 |
40 |
0 |
0 |
T92 |
3152 |
2 |
0 |
0 |
T129 |
15280 |
28 |
0 |
0 |
T131 |
94853 |
70 |
0 |
0 |
T134 |
35617 |
36 |
0 |
0 |
T163 |
8200 |
1 |
0 |
0 |
T164 |
7056 |
6 |
0 |
0 |
T165 |
78586 |
129 |
0 |
0 |
T166 |
12049 |
29 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1778 |
0 |
0 |
T34 |
91540 |
100 |
0 |
0 |
T37 |
12805 |
20 |
0 |
0 |
T129 |
15280 |
12 |
0 |
0 |
T131 |
94853 |
123 |
0 |
0 |
T134 |
35617 |
97 |
0 |
0 |
T163 |
8200 |
17 |
0 |
0 |
T164 |
7056 |
3 |
0 |
0 |
T165 |
78586 |
116 |
0 |
0 |
T166 |
12049 |
58 |
0 |
0 |
T167 |
5378 |
14 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
6252 |
0 |
0 |
T34 |
91540 |
978 |
0 |
0 |
T92 |
3152 |
12 |
0 |
0 |
T129 |
15280 |
224 |
0 |
0 |
T131 |
94853 |
841 |
0 |
0 |
T134 |
35617 |
456 |
0 |
0 |
T163 |
8200 |
4 |
0 |
0 |
T164 |
7056 |
117 |
0 |
0 |
T165 |
78586 |
146 |
0 |
0 |
T166 |
12049 |
56 |
0 |
0 |
T167 |
5378 |
132 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
6872 |
0 |
0 |
T34 |
91540 |
775 |
0 |
0 |
T37 |
12805 |
15 |
0 |
0 |
T92 |
3152 |
4 |
0 |
0 |
T129 |
15280 |
274 |
0 |
0 |
T131 |
94853 |
1136 |
0 |
0 |
T134 |
35617 |
881 |
0 |
0 |
T163 |
8200 |
154 |
0 |
0 |
T164 |
7056 |
110 |
0 |
0 |
T165 |
78586 |
156 |
0 |
0 |
T167 |
5378 |
103 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
7014 |
0 |
0 |
T34 |
91540 |
903 |
0 |
0 |
T37 |
12805 |
26 |
0 |
0 |
T92 |
3152 |
4 |
0 |
0 |
T129 |
15280 |
263 |
0 |
0 |
T131 |
94853 |
1339 |
0 |
0 |
T134 |
35617 |
695 |
0 |
0 |
T163 |
8200 |
133 |
0 |
0 |
T164 |
7056 |
3 |
0 |
0 |
T165 |
78586 |
108 |
0 |
0 |
T166 |
12049 |
32 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
6564 |
0 |
0 |
T34 |
91540 |
1367 |
0 |
0 |
T37 |
12805 |
19 |
0 |
0 |
T92 |
3152 |
7 |
0 |
0 |
T129 |
15280 |
125 |
0 |
0 |
T131 |
94853 |
828 |
0 |
0 |
T134 |
35617 |
498 |
0 |
0 |
T163 |
8200 |
143 |
0 |
0 |
T164 |
7056 |
3 |
0 |
0 |
T165 |
78586 |
162 |
0 |
0 |
T166 |
12049 |
23 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
6691 |
0 |
0 |
T34 |
91540 |
838 |
0 |
0 |
T37 |
12805 |
28 |
0 |
0 |
T92 |
3152 |
2 |
0 |
0 |
T129 |
15280 |
131 |
0 |
0 |
T131 |
94853 |
960 |
0 |
0 |
T134 |
35617 |
710 |
0 |
0 |
T163 |
8200 |
10 |
0 |
0 |
T164 |
7056 |
138 |
0 |
0 |
T165 |
78586 |
126 |
0 |
0 |
T166 |
12049 |
34 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
6463 |
0 |
0 |
T34 |
91540 |
895 |
0 |
0 |
T37 |
12805 |
54 |
0 |
0 |
T129 |
15280 |
342 |
0 |
0 |
T131 |
94853 |
1112 |
0 |
0 |
T134 |
35617 |
272 |
0 |
0 |
T163 |
8200 |
259 |
0 |
0 |
T164 |
7056 |
9 |
0 |
0 |
T165 |
78586 |
105 |
0 |
0 |
T166 |
12049 |
27 |
0 |
0 |
T167 |
5378 |
9 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
6140 |
0 |
0 |
T34 |
91540 |
844 |
0 |
0 |
T37 |
12805 |
45 |
0 |
0 |
T92 |
3152 |
2 |
0 |
0 |
T129 |
15280 |
12 |
0 |
0 |
T131 |
94853 |
744 |
0 |
0 |
T134 |
35617 |
587 |
0 |
0 |
T163 |
8200 |
208 |
0 |
0 |
T164 |
7056 |
7 |
0 |
0 |
T165 |
78586 |
130 |
0 |
0 |
T166 |
12049 |
15 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
6345 |
0 |
0 |
T34 |
91540 |
855 |
0 |
0 |
T37 |
12805 |
49 |
0 |
0 |
T92 |
3152 |
17 |
0 |
0 |
T129 |
15280 |
261 |
0 |
0 |
T131 |
94853 |
940 |
0 |
0 |
T134 |
35617 |
772 |
0 |
0 |
T163 |
8200 |
235 |
0 |
0 |
T164 |
7056 |
6 |
0 |
0 |
T165 |
78586 |
97 |
0 |
0 |
T166 |
12049 |
18 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3250 |
0 |
0 |
T34 |
91540 |
374 |
0 |
0 |
T37 |
12805 |
19 |
0 |
0 |
T92 |
3152 |
2 |
0 |
0 |
T129 |
15280 |
26 |
0 |
0 |
T131 |
94853 |
297 |
0 |
0 |
T134 |
35617 |
207 |
0 |
0 |
T163 |
8200 |
56 |
0 |
0 |
T164 |
7056 |
68 |
0 |
0 |
T165 |
78586 |
172 |
0 |
0 |
T166 |
12049 |
9 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3851 |
0 |
0 |
T34 |
91540 |
503 |
0 |
0 |
T37 |
12805 |
49 |
0 |
0 |
T92 |
3152 |
4 |
0 |
0 |
T129 |
15280 |
53 |
0 |
0 |
T131 |
94853 |
443 |
0 |
0 |
T134 |
35617 |
237 |
0 |
0 |
T163 |
8200 |
54 |
0 |
0 |
T164 |
7056 |
98 |
0 |
0 |
T165 |
78586 |
143 |
0 |
0 |
T166 |
12049 |
35 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3807 |
0 |
0 |
T34 |
91540 |
459 |
0 |
0 |
T37 |
12805 |
15 |
0 |
0 |
T92 |
3152 |
15 |
0 |
0 |
T129 |
15280 |
113 |
0 |
0 |
T131 |
94853 |
501 |
0 |
0 |
T134 |
35617 |
277 |
0 |
0 |
T163 |
8200 |
33 |
0 |
0 |
T164 |
7056 |
60 |
0 |
0 |
T165 |
78586 |
132 |
0 |
0 |
T166 |
12049 |
22 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3750 |
0 |
0 |
T34 |
91540 |
415 |
0 |
0 |
T37 |
12805 |
30 |
0 |
0 |
T129 |
15280 |
86 |
0 |
0 |
T131 |
94853 |
391 |
0 |
0 |
T134 |
35617 |
352 |
0 |
0 |
T163 |
8200 |
66 |
0 |
0 |
T164 |
7056 |
42 |
0 |
0 |
T165 |
78586 |
160 |
0 |
0 |
T166 |
12049 |
8 |
0 |
0 |
T167 |
5378 |
62 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3471 |
0 |
0 |
T34 |
91540 |
341 |
0 |
0 |
T37 |
12805 |
35 |
0 |
0 |
T129 |
15280 |
117 |
0 |
0 |
T131 |
94853 |
350 |
0 |
0 |
T134 |
35617 |
186 |
0 |
0 |
T163 |
8200 |
106 |
0 |
0 |
T164 |
7056 |
98 |
0 |
0 |
T165 |
78586 |
142 |
0 |
0 |
T166 |
12049 |
33 |
0 |
0 |
T167 |
5378 |
50 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3955 |
0 |
0 |
T34 |
91540 |
407 |
0 |
0 |
T37 |
12805 |
43 |
0 |
0 |
T129 |
15280 |
159 |
0 |
0 |
T131 |
94853 |
388 |
0 |
0 |
T134 |
35617 |
340 |
0 |
0 |
T163 |
8200 |
68 |
0 |
0 |
T164 |
7056 |
85 |
0 |
0 |
T165 |
78586 |
127 |
0 |
0 |
T166 |
12049 |
28 |
0 |
0 |
T167 |
5378 |
49 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3698 |
0 |
0 |
T34 |
91540 |
449 |
0 |
0 |
T37 |
12805 |
35 |
0 |
0 |
T129 |
15280 |
122 |
0 |
0 |
T131 |
94853 |
461 |
0 |
0 |
T134 |
35617 |
200 |
0 |
0 |
T163 |
8200 |
124 |
0 |
0 |
T164 |
7056 |
55 |
0 |
0 |
T165 |
78586 |
148 |
0 |
0 |
T166 |
12049 |
37 |
0 |
0 |
T167 |
5378 |
13 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3431 |
0 |
0 |
T34 |
91540 |
451 |
0 |
0 |
T37 |
12805 |
25 |
0 |
0 |
T92 |
3152 |
1 |
0 |
0 |
T129 |
15280 |
113 |
0 |
0 |
T131 |
94853 |
309 |
0 |
0 |
T134 |
35617 |
261 |
0 |
0 |
T163 |
8200 |
9 |
0 |
0 |
T164 |
7056 |
106 |
0 |
0 |
T165 |
78586 |
150 |
0 |
0 |
T166 |
12049 |
9 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3489 |
0 |
0 |
T34 |
91540 |
404 |
0 |
0 |
T37 |
12805 |
73 |
0 |
0 |
T129 |
15280 |
51 |
0 |
0 |
T131 |
94853 |
460 |
0 |
0 |
T134 |
35617 |
272 |
0 |
0 |
T163 |
8200 |
71 |
0 |
0 |
T164 |
7056 |
107 |
0 |
0 |
T165 |
78586 |
166 |
0 |
0 |
T166 |
12049 |
21 |
0 |
0 |
T167 |
5378 |
44 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3621 |
0 |
0 |
T34 |
91540 |
496 |
0 |
0 |
T37 |
12805 |
38 |
0 |
0 |
T92 |
3152 |
2 |
0 |
0 |
T129 |
15280 |
72 |
0 |
0 |
T131 |
94853 |
470 |
0 |
0 |
T134 |
35617 |
273 |
0 |
0 |
T163 |
8200 |
39 |
0 |
0 |
T164 |
7056 |
50 |
0 |
0 |
T165 |
78586 |
110 |
0 |
0 |
T166 |
12049 |
18 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3473 |
0 |
0 |
T34 |
91540 |
472 |
0 |
0 |
T37 |
12805 |
43 |
0 |
0 |
T129 |
15280 |
150 |
0 |
0 |
T131 |
94853 |
487 |
0 |
0 |
T134 |
35617 |
176 |
0 |
0 |
T163 |
8200 |
55 |
0 |
0 |
T164 |
7056 |
72 |
0 |
0 |
T165 |
78586 |
129 |
0 |
0 |
T166 |
12049 |
27 |
0 |
0 |
T167 |
5378 |
8 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3788 |
0 |
0 |
T34 |
91540 |
368 |
0 |
0 |
T37 |
12805 |
23 |
0 |
0 |
T92 |
3152 |
2 |
0 |
0 |
T129 |
15280 |
59 |
0 |
0 |
T131 |
94853 |
347 |
0 |
0 |
T134 |
35617 |
334 |
0 |
0 |
T163 |
8200 |
49 |
0 |
0 |
T164 |
7056 |
103 |
0 |
0 |
T165 |
78586 |
150 |
0 |
0 |
T166 |
12049 |
8 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3612 |
0 |
0 |
T34 |
91540 |
428 |
0 |
0 |
T37 |
12805 |
76 |
0 |
0 |
T92 |
3152 |
8 |
0 |
0 |
T129 |
15280 |
73 |
0 |
0 |
T131 |
94853 |
416 |
0 |
0 |
T134 |
35617 |
344 |
0 |
0 |
T163 |
8200 |
43 |
0 |
0 |
T164 |
7056 |
14 |
0 |
0 |
T165 |
78586 |
113 |
0 |
0 |
T166 |
12049 |
24 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3260 |
0 |
0 |
T34 |
91540 |
376 |
0 |
0 |
T37 |
12805 |
43 |
0 |
0 |
T129 |
15280 |
84 |
0 |
0 |
T131 |
94853 |
375 |
0 |
0 |
T134 |
35617 |
291 |
0 |
0 |
T163 |
8200 |
62 |
0 |
0 |
T164 |
7056 |
6 |
0 |
0 |
T165 |
78586 |
125 |
0 |
0 |
T166 |
12049 |
8 |
0 |
0 |
T167 |
5378 |
45 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3691 |
0 |
0 |
T34 |
91540 |
421 |
0 |
0 |
T37 |
12805 |
38 |
0 |
0 |
T92 |
3152 |
8 |
0 |
0 |
T129 |
15280 |
164 |
0 |
0 |
T131 |
94853 |
456 |
0 |
0 |
T134 |
35617 |
344 |
0 |
0 |
T163 |
8200 |
54 |
0 |
0 |
T164 |
7056 |
61 |
0 |
0 |
T165 |
78586 |
136 |
0 |
0 |
T166 |
12049 |
25 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3785 |
0 |
0 |
T34 |
91540 |
429 |
0 |
0 |
T37 |
12805 |
36 |
0 |
0 |
T116 |
16419 |
2 |
0 |
0 |
T129 |
15280 |
51 |
0 |
0 |
T131 |
94853 |
547 |
0 |
0 |
T134 |
35617 |
437 |
0 |
0 |
T163 |
8200 |
49 |
0 |
0 |
T164 |
7056 |
57 |
0 |
0 |
T165 |
78586 |
119 |
0 |
0 |
T166 |
12049 |
24 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3238 |
0 |
0 |
T34 |
91540 |
308 |
0 |
0 |
T37 |
12805 |
12 |
0 |
0 |
T129 |
15280 |
67 |
0 |
0 |
T131 |
94853 |
420 |
0 |
0 |
T134 |
35617 |
287 |
0 |
0 |
T163 |
8200 |
49 |
0 |
0 |
T164 |
7056 |
11 |
0 |
0 |
T165 |
78586 |
130 |
0 |
0 |
T166 |
12049 |
46 |
0 |
0 |
T167 |
5378 |
51 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3361 |
0 |
0 |
T34 |
91540 |
320 |
0 |
0 |
T37 |
12805 |
6 |
0 |
0 |
T129 |
15280 |
85 |
0 |
0 |
T131 |
94853 |
409 |
0 |
0 |
T134 |
35617 |
159 |
0 |
0 |
T163 |
8200 |
70 |
0 |
0 |
T164 |
7056 |
112 |
0 |
0 |
T165 |
78586 |
152 |
0 |
0 |
T166 |
12049 |
32 |
0 |
0 |
T167 |
5378 |
9 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3593 |
0 |
0 |
T34 |
91540 |
410 |
0 |
0 |
T37 |
12805 |
48 |
0 |
0 |
T92 |
3152 |
8 |
0 |
0 |
T129 |
15280 |
118 |
0 |
0 |
T131 |
94853 |
536 |
0 |
0 |
T134 |
35617 |
124 |
0 |
0 |
T163 |
8200 |
39 |
0 |
0 |
T164 |
7056 |
45 |
0 |
0 |
T165 |
78586 |
128 |
0 |
0 |
T167 |
5378 |
59 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3586 |
0 |
0 |
T34 |
91540 |
357 |
0 |
0 |
T37 |
12805 |
56 |
0 |
0 |
T92 |
3152 |
5 |
0 |
0 |
T129 |
15280 |
109 |
0 |
0 |
T131 |
94853 |
306 |
0 |
0 |
T134 |
35617 |
417 |
0 |
0 |
T163 |
8200 |
103 |
0 |
0 |
T164 |
7056 |
114 |
0 |
0 |
T165 |
78586 |
78 |
0 |
0 |
T166 |
12049 |
12 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3656 |
0 |
0 |
T34 |
91540 |
323 |
0 |
0 |
T37 |
12805 |
74 |
0 |
0 |
T92 |
3152 |
7 |
0 |
0 |
T129 |
15280 |
131 |
0 |
0 |
T131 |
94853 |
438 |
0 |
0 |
T134 |
35617 |
221 |
0 |
0 |
T163 |
8200 |
40 |
0 |
0 |
T164 |
7056 |
50 |
0 |
0 |
T165 |
78586 |
163 |
0 |
0 |
T166 |
12049 |
24 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3851 |
0 |
0 |
T34 |
91540 |
448 |
0 |
0 |
T37 |
12805 |
46 |
0 |
0 |
T92 |
3152 |
12 |
0 |
0 |
T129 |
15280 |
156 |
0 |
0 |
T131 |
94853 |
443 |
0 |
0 |
T134 |
35617 |
210 |
0 |
0 |
T163 |
8200 |
7 |
0 |
0 |
T164 |
7056 |
60 |
0 |
0 |
T165 |
78586 |
178 |
0 |
0 |
T166 |
12049 |
28 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3721 |
0 |
0 |
T34 |
91540 |
525 |
0 |
0 |
T37 |
12805 |
24 |
0 |
0 |
T92 |
3152 |
10 |
0 |
0 |
T129 |
15280 |
67 |
0 |
0 |
T131 |
94853 |
529 |
0 |
0 |
T134 |
35617 |
284 |
0 |
0 |
T163 |
8200 |
45 |
0 |
0 |
T164 |
7056 |
8 |
0 |
0 |
T165 |
78586 |
147 |
0 |
0 |
T166 |
12049 |
30 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3471 |
0 |
0 |
T34 |
91540 |
363 |
0 |
0 |
T37 |
12805 |
49 |
0 |
0 |
T129 |
15280 |
96 |
0 |
0 |
T131 |
94853 |
463 |
0 |
0 |
T134 |
35617 |
254 |
0 |
0 |
T163 |
8200 |
51 |
0 |
0 |
T164 |
7056 |
52 |
0 |
0 |
T165 |
78586 |
99 |
0 |
0 |
T166 |
12049 |
22 |
0 |
0 |
T167 |
5378 |
58 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1809 |
0 |
0 |
T34 |
91540 |
87 |
0 |
0 |
T37 |
12805 |
19 |
0 |
0 |
T92 |
3152 |
10 |
0 |
0 |
T129 |
15280 |
28 |
0 |
0 |
T131 |
94853 |
85 |
0 |
0 |
T134 |
35617 |
49 |
0 |
0 |
T163 |
8200 |
7 |
0 |
0 |
T164 |
7056 |
13 |
0 |
0 |
T165 |
78586 |
116 |
0 |
0 |
T166 |
12049 |
39 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1725 |
0 |
0 |
T34 |
91540 |
71 |
0 |
0 |
T37 |
12805 |
11 |
0 |
0 |
T92 |
3152 |
7 |
0 |
0 |
T129 |
15280 |
34 |
0 |
0 |
T131 |
94853 |
90 |
0 |
0 |
T134 |
35617 |
34 |
0 |
0 |
T163 |
8200 |
14 |
0 |
0 |
T164 |
7056 |
12 |
0 |
0 |
T165 |
78586 |
133 |
0 |
0 |
T166 |
12049 |
27 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1920 |
0 |
0 |
T34 |
91540 |
119 |
0 |
0 |
T37 |
12805 |
54 |
0 |
0 |
T92 |
3152 |
10 |
0 |
0 |
T129 |
15280 |
32 |
0 |
0 |
T131 |
94853 |
108 |
0 |
0 |
T134 |
35617 |
65 |
0 |
0 |
T163 |
8200 |
9 |
0 |
0 |
T164 |
7056 |
22 |
0 |
0 |
T165 |
78586 |
148 |
0 |
0 |
T166 |
12049 |
36 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1832 |
0 |
0 |
T34 |
91540 |
122 |
0 |
0 |
T37 |
12805 |
49 |
0 |
0 |
T92 |
3152 |
9 |
0 |
0 |
T129 |
15280 |
26 |
0 |
0 |
T131 |
94853 |
122 |
0 |
0 |
T134 |
35617 |
60 |
0 |
0 |
T163 |
8200 |
11 |
0 |
0 |
T164 |
7056 |
21 |
0 |
0 |
T165 |
78586 |
134 |
0 |
0 |
T166 |
12049 |
13 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
2101 |
0 |
0 |
T34 |
91540 |
127 |
0 |
0 |
T37 |
12805 |
68 |
0 |
0 |
T129 |
15280 |
38 |
0 |
0 |
T131 |
94853 |
135 |
0 |
0 |
T134 |
35617 |
92 |
0 |
0 |
T163 |
8200 |
23 |
0 |
0 |
T164 |
7056 |
9 |
0 |
0 |
T165 |
78586 |
148 |
0 |
0 |
T167 |
5378 |
8 |
0 |
0 |
T168 |
19804 |
50 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
3191 |
0 |
0 |
T34 |
0 |
227 |
0 |
0 |
T37 |
0 |
38 |
0 |
0 |
T92 |
0 |
4 |
0 |
0 |
T116 |
0 |
13 |
0 |
0 |
T134 |
0 |
138 |
0 |
0 |
T163 |
0 |
26 |
0 |
0 |
T169 |
6150 |
11 |
0 |
0 |
T170 |
0 |
19 |
0 |
0 |
T171 |
0 |
16 |
0 |
0 |
T172 |
0 |
38 |
0 |
0 |
T173 |
266318 |
0 |
0 |
0 |
T174 |
128463 |
0 |
0 |
0 |
T175 |
372049 |
0 |
0 |
0 |
T176 |
277416 |
0 |
0 |
0 |
T177 |
60076 |
0 |
0 |
0 |
T178 |
118755 |
0 |
0 |
0 |
T179 |
739 |
0 |
0 |
0 |
T180 |
7507 |
0 |
0 |
0 |
T181 |
157391 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1719 |
0 |
0 |
T34 |
91540 |
73 |
0 |
0 |
T37 |
12805 |
56 |
0 |
0 |
T92 |
3152 |
4 |
0 |
0 |
T129 |
15280 |
31 |
0 |
0 |
T131 |
94853 |
102 |
0 |
0 |
T134 |
35617 |
51 |
0 |
0 |
T163 |
8200 |
8 |
0 |
0 |
T164 |
7056 |
10 |
0 |
0 |
T165 |
78586 |
159 |
0 |
0 |
T166 |
12049 |
32 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1737 |
0 |
0 |
T34 |
91540 |
86 |
0 |
0 |
T37 |
12805 |
25 |
0 |
0 |
T129 |
15280 |
50 |
0 |
0 |
T131 |
94853 |
63 |
0 |
0 |
T134 |
35617 |
36 |
0 |
0 |
T163 |
8200 |
2 |
0 |
0 |
T164 |
7056 |
1 |
0 |
0 |
T165 |
78586 |
162 |
0 |
0 |
T166 |
12049 |
8 |
0 |
0 |
T167 |
5378 |
7 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1468 |
0 |
0 |
T34 |
91540 |
56 |
0 |
0 |
T37 |
12805 |
27 |
0 |
0 |
T92 |
3152 |
17 |
0 |
0 |
T129 |
15280 |
22 |
0 |
0 |
T131 |
94853 |
56 |
0 |
0 |
T134 |
35617 |
33 |
0 |
0 |
T163 |
8200 |
2 |
0 |
0 |
T164 |
7056 |
6 |
0 |
0 |
T165 |
78586 |
143 |
0 |
0 |
T166 |
12049 |
39 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1675 |
0 |
0 |
T34 |
91540 |
52 |
0 |
0 |
T37 |
12805 |
35 |
0 |
0 |
T92 |
3152 |
1 |
0 |
0 |
T129 |
15280 |
36 |
0 |
0 |
T131 |
94853 |
64 |
0 |
0 |
T134 |
35617 |
32 |
0 |
0 |
T163 |
8200 |
9 |
0 |
0 |
T164 |
7056 |
7 |
0 |
0 |
T165 |
78586 |
164 |
0 |
0 |
T166 |
12049 |
28 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1611 |
0 |
0 |
T34 |
91540 |
47 |
0 |
0 |
T37 |
12805 |
41 |
0 |
0 |
T129 |
15280 |
26 |
0 |
0 |
T131 |
94853 |
56 |
0 |
0 |
T134 |
35617 |
29 |
0 |
0 |
T163 |
8200 |
11 |
0 |
0 |
T164 |
7056 |
15 |
0 |
0 |
T165 |
78586 |
135 |
0 |
0 |
T166 |
12049 |
16 |
0 |
0 |
T167 |
5378 |
10 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1733 |
0 |
0 |
T34 |
91540 |
75 |
0 |
0 |
T37 |
12805 |
98 |
0 |
0 |
T92 |
3152 |
6 |
0 |
0 |
T129 |
15280 |
25 |
0 |
0 |
T131 |
94853 |
78 |
0 |
0 |
T134 |
35617 |
52 |
0 |
0 |
T164 |
7056 |
10 |
0 |
0 |
T165 |
78586 |
151 |
0 |
0 |
T166 |
12049 |
20 |
0 |
0 |
T167 |
5378 |
5 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1920 |
0 |
0 |
T34 |
91540 |
125 |
0 |
0 |
T37 |
12805 |
18 |
0 |
0 |
T92 |
3152 |
7 |
0 |
0 |
T129 |
15280 |
33 |
0 |
0 |
T131 |
94853 |
149 |
0 |
0 |
T134 |
35617 |
54 |
0 |
0 |
T163 |
8200 |
16 |
0 |
0 |
T164 |
7056 |
28 |
0 |
0 |
T165 |
78586 |
108 |
0 |
0 |
T166 |
12049 |
29 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1601 |
0 |
0 |
T34 |
91540 |
48 |
0 |
0 |
T37 |
12805 |
23 |
0 |
0 |
T92 |
3152 |
6 |
0 |
0 |
T129 |
15280 |
15 |
0 |
0 |
T131 |
94853 |
87 |
0 |
0 |
T134 |
35617 |
27 |
0 |
0 |
T163 |
8200 |
10 |
0 |
0 |
T164 |
7056 |
13 |
0 |
0 |
T165 |
78586 |
151 |
0 |
0 |
T166 |
12049 |
31 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
2197 |
0 |
0 |
T34 |
91540 |
193 |
0 |
0 |
T37 |
12805 |
52 |
0 |
0 |
T92 |
3152 |
1 |
0 |
0 |
T129 |
15280 |
21 |
0 |
0 |
T131 |
94853 |
167 |
0 |
0 |
T134 |
35617 |
63 |
0 |
0 |
T163 |
8200 |
20 |
0 |
0 |
T164 |
7056 |
17 |
0 |
0 |
T165 |
78586 |
99 |
0 |
0 |
T166 |
12049 |
6 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1797 |
0 |
0 |
T34 |
91540 |
95 |
0 |
0 |
T37 |
12805 |
2 |
0 |
0 |
T92 |
3152 |
3 |
0 |
0 |
T129 |
15280 |
37 |
0 |
0 |
T131 |
94853 |
96 |
0 |
0 |
T134 |
35617 |
47 |
0 |
0 |
T163 |
8200 |
12 |
0 |
0 |
T164 |
7056 |
14 |
0 |
0 |
T165 |
78586 |
139 |
0 |
0 |
T166 |
12049 |
61 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1537 |
0 |
0 |
T34 |
91540 |
63 |
0 |
0 |
T37 |
12805 |
18 |
0 |
0 |
T92 |
3152 |
4 |
0 |
0 |
T129 |
15280 |
19 |
0 |
0 |
T131 |
94853 |
46 |
0 |
0 |
T134 |
35617 |
31 |
0 |
0 |
T163 |
8200 |
3 |
0 |
0 |
T164 |
7056 |
7 |
0 |
0 |
T165 |
78586 |
131 |
0 |
0 |
T166 |
12049 |
29 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1698 |
0 |
0 |
T34 |
91540 |
65 |
0 |
0 |
T37 |
12805 |
46 |
0 |
0 |
T92 |
3152 |
9 |
0 |
0 |
T116 |
16419 |
3 |
0 |
0 |
T131 |
94853 |
36 |
0 |
0 |
T134 |
35617 |
34 |
0 |
0 |
T163 |
8200 |
7 |
0 |
0 |
T164 |
7056 |
11 |
0 |
0 |
T165 |
78586 |
155 |
0 |
0 |
T166 |
12049 |
17 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1685 |
0 |
0 |
T34 |
91540 |
54 |
0 |
0 |
T37 |
12805 |
71 |
0 |
0 |
T129 |
15280 |
22 |
0 |
0 |
T131 |
94853 |
54 |
0 |
0 |
T134 |
35617 |
46 |
0 |
0 |
T163 |
8200 |
6 |
0 |
0 |
T164 |
7056 |
10 |
0 |
0 |
T165 |
78586 |
155 |
0 |
0 |
T166 |
12049 |
31 |
0 |
0 |
T167 |
5378 |
3 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1529 |
0 |
0 |
T34 |
91540 |
30 |
0 |
0 |
T37 |
12805 |
49 |
0 |
0 |
T92 |
3152 |
5 |
0 |
0 |
T129 |
15280 |
22 |
0 |
0 |
T131 |
94853 |
62 |
0 |
0 |
T134 |
35617 |
22 |
0 |
0 |
T163 |
8200 |
6 |
0 |
0 |
T164 |
7056 |
4 |
0 |
0 |
T165 |
78586 |
135 |
0 |
0 |
T166 |
12049 |
6 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1613 |
0 |
0 |
T34 |
91540 |
46 |
0 |
0 |
T37 |
12805 |
34 |
0 |
0 |
T129 |
15280 |
12 |
0 |
0 |
T131 |
94853 |
62 |
0 |
0 |
T134 |
35617 |
38 |
0 |
0 |
T163 |
8200 |
12 |
0 |
0 |
T164 |
7056 |
3 |
0 |
0 |
T165 |
78586 |
143 |
0 |
0 |
T166 |
12049 |
47 |
0 |
0 |
T167 |
5378 |
16 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112586037 |
1523 |
0 |
0 |
T34 |
91540 |
68 |
0 |
0 |
T37 |
12805 |
53 |
0 |
0 |
T129 |
15280 |
17 |
0 |
0 |
T131 |
94853 |
34 |
0 |
0 |
T134 |
35617 |
46 |
0 |
0 |
T163 |
8200 |
3 |
0 |
0 |
T164 |
7056 |
4 |
0 |
0 |
T165 |
78586 |
132 |
0 |
0 |
T166 |
12049 |
25 |
0 |
0 |
T167 |
5378 |
5 |
0 |
0 |