Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1386782	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1546512

1

T1

901

T2

907

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2230562	1			T1	5		T2	6		T3	79
values[0x0]	351412	1			T1	471		T2	450		T16	5
values[0x1]	351320	1			T1	429		T2	456		T16	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1046787	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1886507

1

T1

902

T2

908

T3

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9627	1			T1	1		T2	5		T5	14
valid_sources[0x01]	10060	1			T1	6		T2	4		T4	4
valid_sources[0x02]	10803	1			T1	5		T4	4		T5	7
valid_sources[0x03]	17049	1			T1	2		T4	3		T5	2
valid_sources[0x04]	18464	1			T4	3		T5	7		T12	15
valid_sources[0x05]	10193	1			T1	3		T2	2		T4	5
valid_sources[0x06]	10491	1			T1	1		T4	5		T5	4
valid_sources[0x07]	11313	1			T1	13		T16	3		T4	5
valid_sources[0x08]	11422	1			T1	1		T2	7		T4	1
valid_sources[0x09]	12234	1			T2	2		T4	6		T5	10
valid_sources[0x0a]	11631	1			T1	9		T2	7		T4	8
valid_sources[0x0b]	10121	1			T2	3		T4	3		T5	1
valid_sources[0x0c]	9410	1			T2	5		T4	2		T5	17
valid_sources[0x0d]	13101	1			T1	6		T4	2		T5	5
valid_sources[0x0e]	11124	1			T1	5		T2	1		T4	1
valid_sources[0x0f]	11627	1			T1	1		T4	1		T5	3
valid_sources[0x10]	10809	1			T1	11		T2	1		T4	4
valid_sources[0x11]	10193	1			T1	4		T2	7		T4	5
valid_sources[0x12]	15311	1			T2	2		T4	2		T5	7
valid_sources[0x13]	10490	1			T1	3		T4	2		T5	5
valid_sources[0x14]	9755	1			T1	10		T2	5		T4	3
valid_sources[0x15]	11820	1			T1	3		T2	7		T4	4
valid_sources[0x16]	20970	1			T2	3		T4	2		T5	2
valid_sources[0x17]	13605	1			T2	4		T4	2		T5	8
valid_sources[0x18]	11008	1			T1	6		T2	9		T4	2
valid_sources[0x19]	14500	1			T1	6		T2	4		T4	2
valid_sources[0x1a]	15597	1			T1	3		T2	3		T3	2
valid_sources[0x1b]	10664	1			T1	1		T2	3		T4	2
valid_sources[0x1c]	11063	1			T1	5		T2	8		T4	5
valid_sources[0x1d]	11160	1			T1	5		T2	2		T4	2
valid_sources[0x1e]	11719	1			T2	2		T4	2		T5	7
valid_sources[0x1f]	12131	1			T2	6		T16	5		T4	3
valid_sources[0x20]	9286	1			T1	4		T2	8		T4	4
valid_sources[0x21]	10875	1			T2	1		T4	2		T5	10
valid_sources[0x22]	11252	1			T1	2		T2	4		T4	5
valid_sources[0x23]	10124	1			T1	8		T2	2		T4	4
valid_sources[0x24]	14564	1			T2	2		T5	5		T12	18
valid_sources[0x25]	9733	1			T1	10		T2	2		T4	3
valid_sources[0x26]	10893	1			T2	1		T4	1		T5	2
valid_sources[0x27]	15913	1			T1	6		T2	1		T4	2
valid_sources[0x28]	22457	1			T1	1		T2	2		T4	3
valid_sources[0x29]	11375	1			T2	1		T4	2		T5	6
valid_sources[0x2a]	14388	1			T2	3		T4	3		T5	12
valid_sources[0x2b]	9295	1			T1	3		T2	2		T4	1
valid_sources[0x2c]	11021	1			T2	3		T4	10		T5	9
valid_sources[0x2d]	11124	1			T1	4		T2	3		T4	9
valid_sources[0x2e]	10369	1			T2	1		T4	3		T5	11
valid_sources[0x2f]	20707	1			T2	6		T4	5		T5	15
valid_sources[0x30]	10335	1			T1	1		T2	2		T3	5
valid_sources[0x31]	11646	1			T1	6		T2	6		T4	3
valid_sources[0x32]	9807	1			T1	5		T2	7		T3	2
valid_sources[0x33]	14240	1			T1	3		T2	1		T4	6
valid_sources[0x34]	11489	1			T1	13		T2	3		T4	1
valid_sources[0x35]	21648	1			T1	4		T2	4		T4	2
valid_sources[0x36]	10767	1			T1	3		T2	9		T4	5
valid_sources[0x37]	9093	1			T1	1		T2	6		T4	7
valid_sources[0x38]	9525	1			T1	1		T4	2		T5	5
valid_sources[0x39]	10227	1			T1	5		T4	3		T5	6
valid_sources[0x3a]	9555	1			T1	1		T2	2		T4	4
valid_sources[0x3b]	10953	1			T1	8		T2	2		T4	9
valid_sources[0x3c]	9517	1			T1	5		T2	3		T4	1
valid_sources[0x3d]	9568	1			T2	8		T4	5		T5	7
valid_sources[0x3e]	13621	1			T1	4		T2	5		T4	5
valid_sources[0x3f]	10676	1			T1	9		T2	6		T4	1
valid_sources[0x40]	10698	1			T2	1		T3	10		T4	2
valid_sources[0x41]	9564	1			T1	14		T2	4		T4	3
valid_sources[0x42]	11063	1			T1	2		T2	1		T4	5
valid_sources[0x43]	9991	1			T1	11		T4	6		T5	5
valid_sources[0x44]	10740	1			T1	2		T2	8		T4	1
valid_sources[0x45]	9383	1			T1	8		T2	13		T3	10
valid_sources[0x46]	10064	1			T1	6		T2	4		T4	5
valid_sources[0x47]	11221	1			T1	2		T2	2		T4	1
valid_sources[0x48]	10297	1			T1	5		T5	3		T12	14
valid_sources[0x49]	9432	1			T2	6		T4	4		T5	9
valid_sources[0x4a]	14865	1			T2	9		T4	4		T5	10
valid_sources[0x4b]	9095	1			T2	3		T4	1		T5	8
valid_sources[0x4c]	12574	1			T1	1		T2	3		T4	4
valid_sources[0x4d]	9754	1			T2	1		T4	2		T12	8
valid_sources[0x4e]	9921	1			T1	1		T2	7		T4	3
valid_sources[0x4f]	9589	1			T1	2		T2	6		T4	8
valid_sources[0x50]	13097	1			T1	6		T2	13		T4	3
valid_sources[0x51]	10944	1			T1	4		T2	4		T4	1
valid_sources[0x52]	15960	1			T1	7		T2	6		T4	4
valid_sources[0x53]	10305	1			T3	2		T4	9		T5	2
valid_sources[0x54]	10666	1			T1	5		T5	7		T12	15
valid_sources[0x55]	10159	1			T1	1		T2	5		T4	6
valid_sources[0x56]	10237	1			T1	8		T2	1		T4	3
valid_sources[0x57]	10826	1			T1	1		T2	1		T4	2
valid_sources[0x58]	9672	1			T1	6		T2	2		T4	4
valid_sources[0x59]	35019	1			T1	8		T2	11		T4	2
valid_sources[0x5a]	11476	1			T1	1		T2	4		T5	9
valid_sources[0x5b]	9242	1			T1	6		T16	1		T4	9
valid_sources[0x5c]	9940	1			T1	5		T2	8		T4	5
valid_sources[0x5d]	10256	1			T1	3		T2	9		T4	1
valid_sources[0x5e]	11254	1			T2	4		T4	1		T5	6
valid_sources[0x5f]	11149	1			T1	4		T4	4		T5	9
valid_sources[0x60]	10396	1			T1	11		T2	10		T3	7
valid_sources[0x61]	11613	1			T1	2		T2	1		T3	2
valid_sources[0x62]	9916	1			T1	1		T2	2		T4	3
valid_sources[0x63]	19181	1			T1	3		T2	9		T4	7
valid_sources[0x64]	9873	1			T2	1		T4	3		T5	4
valid_sources[0x65]	9390	1			T1	2		T2	9		T4	4
valid_sources[0x66]	10866	1			T2	1		T4	6		T5	3
valid_sources[0x67]	16580	1			T1	9		T2	12		T4	3
valid_sources[0x68]	10205	1			T2	5		T4	2		T5	8
valid_sources[0x69]	9990	1			T1	4		T4	4		T5	2
valid_sources[0x6a]	11069	1			T4	1		T5	8		T12	10
valid_sources[0x6b]	9832	1			T1	1		T2	4		T4	3
valid_sources[0x6c]	11546	1			T1	7		T2	5		T4	9
valid_sources[0x6d]	16293	1			T1	1		T2	1		T4	5
valid_sources[0x6e]	10468	1			T1	2		T2	6		T4	5
valid_sources[0x6f]	9667	1			T1	1		T4	2		T5	4
valid_sources[0x70]	9485	1			T1	3		T2	5		T4	1
valid_sources[0x71]	10969	1			T1	3		T2	2		T4	8
valid_sources[0x72]	11420	1			T1	9		T2	3		T4	3
valid_sources[0x73]	11837	1			T1	15		T2	2		T4	7
valid_sources[0x74]	10232	1			T1	6		T2	8		T4	2
valid_sources[0x75]	12447	1			T1	4		T2	1		T4	5
valid_sources[0x76]	11221	1			T1	4		T2	4		T4	1
valid_sources[0x77]	10852	1			T1	6		T2	3		T4	3
valid_sources[0x78]	9513	1			T1	2		T2	6		T4	4
valid_sources[0x79]	9557	1			T1	15		T2	6		T4	2
valid_sources[0x7a]	10239	1			T1	4		T2	1		T4	5
valid_sources[0x7b]	9377	1			T1	3		T2	4		T4	2
valid_sources[0x7c]	9999	1			T1	9		T2	4		T4	5
valid_sources[0x7d]	11400	1			T4	3		T5	8		T12	15
valid_sources[0x7e]	10528	1			T4	3		T5	9		T12	13
valid_sources[0x7f]	10727	1			T1	7		T2	3		T4	3
valid_sources[0x80]	13327	1			T2	1		T4	2		T5	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

914576

1

T1

3

T2

3

T3

1

values[0x0]

all_enables

biggest_size

319850

1

T1

471

T2

449

T16

1

values[0x1]

all_enables

biggest_size

312086

1

T1

427

T2

455

T16

1