Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1405865

1

T1

4

T2

5

T3

78

full_word

1547690

1

T1

901

T2

907

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2953105	1			T1	905		T2	912		T3	79
auto[TlIntgErrCmd]	156	1			T35	10		T36	8		T114	5
auto[TlIntgErrData]	161	1			T35	7		T36	6		T114	7
auto[TlIntgErrBoth]	133	1			T35	13		T36	6		T114	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2233821

1

T1

5

T2

6

T3

79

auto[1]

719734

1

T1

900

T2

906

T16

8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1318801	1			T1	2		T2	3		T3	78
auto[TlIntgErrNone]	partial	auto[1]	86654	1			T1	2		T2	2		T16	6
auto[TlIntgErrNone]	full_word	auto[0]	914827	1			T1	3		T2	3		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	632823	1			T1	898		T2	904		T16	2
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T35	3		T36	3		T114	1
auto[TlIntgErrCmd]	partial	auto[1]	91	1			T35	7		T36	4		T114	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T36	1		T358	1		T360	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T128	2		T362	2		-	-
auto[TlIntgErrData]	partial	auto[0]	62	1			T35	4		T36	2		T114	4
auto[TlIntgErrData]	partial	auto[1]	85	1			T35	3		T36	4		T114	3
auto[TlIntgErrData]	full_word	auto[0]	11	1			T358	1		T128	1		T359	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T127	1		T363	1		T364	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T35	6		T36	2		T114	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T35	5		T36	3		T114	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T36	1		T362	1		T365	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T35	2		T127	3		T358	1