Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.36	85.00	45.45			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.83	94.37	68.33			84.62	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	39756030	5881382	0	0
DepthKnown_A	39756030	23751490	0	0
RvalidKnown_A	39756030	23751490	0	0
WreadyKnown_A	39756030	23751490	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	39756030	5881382	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	5881382	0	0
T1	87441	26042	0	0
T2	186989	27854	0	0
T4	112026	2048	0	0
T5	59571	6945	0	0
T6	87886	41876	0	0
T7	52785	10078	0	0
T8	0	96	0	0
T10	0	3258	0	0
T11	0	23333	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T87	0	39894	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	5881382	0	0
T1	87441	26042	0	0
T2	186989	27854	0	0
T4	112026	2048	0	0
T5	59571	6945	0	0
T6	87886	41876	0	0
T7	52785	10078	0	0
T8	0	96	0	0
T10	0	3258	0	0
T11	0	23333	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T87	0	39894	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	39756030	6195193	0	0
DepthKnown_A	39756030	23751490	0	0
RvalidKnown_A	39756030	23751490	0	0
WreadyKnown_A	39756030	23751490	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	39756030	6195193	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	6195193	0	0
T1	87441	27624	0	0
T2	186989	28736	0	0
T4	112026	2168	0	0
T5	59571	7248	0	0
T6	87886	43350	0	0
T7	52785	11200	0	0
T8	0	92	0	0
T10	0	3360	0	0
T11	0	24204	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T87	0	41785	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	6195193	0	0
T1	87441	27624	0	0
T2	186989	28736	0	0
T4	112026	2168	0	0
T5	59571	7248	0	0
T6	87886	43350	0	0
T7	52785	11200	0	0
T8	0	92	0	0
T10	0	3360	0	0
T11	0	24204	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T87	0	41785	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	39756030	0	0	0
DepthKnown_A	39756030	23751490	0	0
RvalidKnown_A	39756030	23751490	0	0
WreadyKnown_A	39756030	23751490	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	39756030	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	23751490	0	0
T1	87441	86616	0	0
T2	186989	186584	0	0
T4	112026	111336	0	0
T5	59571	59328	0	0
T6	87886	87886	0	0
T7	52785	52672	0	0
T8	0	48236	0	0
T9	0	141348	0	0
T10	0	55142	0	0
T11	0	24500	0	0
T12	130783	0	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T14

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Not Covered
1	1	Covered	T12,T18,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T18,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T18,T19
1	0	1	Covered	T12,T18,T19
1	1	0	Not Covered
1	1	1	Covered	T12,T18,T19

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T18,T19

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T18,T19

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T12,T18,T19
1	0	Covered	T12,T18,T19
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T18,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T12,T18,T19
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	39756030	2319968	0	0
DepthKnown_A	39756030	15414828	0	0
RvalidKnown_A	39756030	15414828	0	0
WreadyKnown_A	39756030	15414828	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	39756030	2319968	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	2319968	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	19676	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T18	0	68285	0	0
T19	0	634	0	0
T58	0	66827	0	0
T60	0	21891	0	0
T61	0	60544	0	0
T62	0	91210	0	0
T63	0	928	0	0
T64	0	27734	0	0
T65	0	1624	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	15414828	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	127528	0	0
T13	1368	1368	0	0
T14	67007	63856	0	0
T15	1224	1224	0	0
T18	0	536736	0	0
T19	0	2288	0	0
T23	0	504	0	0
T58	0	642752	0	0
T59	0	130688	0	0
T60	0	48200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	15414828	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	127528	0	0
T13	1368	1368	0	0
T14	67007	63856	0	0
T15	1224	1224	0	0
T18	0	536736	0	0
T19	0	2288	0	0
T23	0	504	0	0
T58	0	642752	0	0
T59	0	130688	0	0
T60	0	48200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	15414828	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	127528	0	0
T13	1368	1368	0	0
T14	67007	63856	0	0
T15	1224	1224	0	0
T18	0	536736	0	0
T19	0	2288	0	0
T23	0	504	0	0
T58	0	642752	0	0
T59	0	130688	0	0
T60	0	48200	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	2319968	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	19676	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T18	0	68285	0	0
T19	0	634	0	0
T58	0	66827	0	0
T60	0	21891	0	0
T61	0	60544	0	0
T62	0	91210	0	0
T63	0	928	0	0
T64	0	27734	0	0
T65	0	1624	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T12,T13,T14

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T14
1	0	Not Covered
1	1	Covered	T12,T18,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T13,T14
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T18,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T18,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T12,T18,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T18,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
0	0	Covered	T12,T13,T14

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T12,T18,T19
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	39756030	74580	0	0
DepthKnown_A	39756030	15414828	0	0
RvalidKnown_A	39756030	15414828	0	0
WreadyKnown_A	39756030	15414828	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	39756030	74580	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	74580	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	632	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T18	0	2199	0	0
T19	0	22	0	0
T58	0	2146	0	0
T60	0	706	0	0
T61	0	1949	0	0
T62	0	2931	0	0
T63	0	30	0	0
T64	0	885	0	0
T65	0	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	15414828	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	127528	0	0
T13	1368	1368	0	0
T14	67007	63856	0	0
T15	1224	1224	0	0
T18	0	536736	0	0
T19	0	2288	0	0
T23	0	504	0	0
T58	0	642752	0	0
T59	0	130688	0	0
T60	0	48200	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	15414828	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	127528	0	0
T13	1368	1368	0	0
T14	67007	63856	0	0
T15	1224	1224	0	0
T18	0	536736	0	0
T19	0	2288	0	0
T23	0	504	0	0
T58	0	642752	0	0
T59	0	130688	0	0
T60	0	48200	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	15414828	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	127528	0	0
T13	1368	1368	0	0
T14	67007	63856	0	0
T15	1224	1224	0	0
T18	0	536736	0	0
T19	0	2288	0	0
T23	0	504	0	0
T58	0	642752	0	0
T59	0	130688	0	0
T60	0	48200	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	39756030	74580	0	0
T6	87886	0	0	0
T7	52785	0	0	0
T8	48388	0	0	0
T9	141348	0	0	0
T10	55210	0	0	0
T11	24500	0	0	0
T12	130783	632	0	0
T13	1368	0	0	0
T14	67007	0	0	0
T15	1224	0	0	0
T18	0	2199	0	0
T19	0	22	0	0
T58	0	2146	0	0
T60	0	706	0	0
T61	0	1949	0	0
T62	0	2931	0	0
T63	0	30	0	0
T64	0	885	0	0
T65	0	52	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T5,T7
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	113744254	465345	0	0
DepthKnown_A	113744254	113685586	0	0
RvalidKnown_A	113744254	113685586	0	0
WreadyKnown_A	113744254	113685586	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	113744254	465345	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	465345	0	0
T1	34015	3607	0	0
T2	758407	832	0	0
T3	1861	0	0	0
T4	905554	832	0	0
T5	30531	832	0	0
T6	534240	832	0	0
T7	0	3931	0	0
T8	0	832	0	0
T9	0	835	0	0
T10	0	832	0	0
T11	0	832	0	0
T12	76052	0	0	0
T13	8805	0	0	0
T16	994	0	0	0
T17	711	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	465345	0	0
T1	34015	3607	0	0
T2	758407	832	0	0
T3	1861	0	0	0
T4	905554	832	0	0
T5	30531	832	0	0
T6	534240	832	0	0
T7	0	3931	0	0
T8	0	832	0	0
T9	0	835	0	0
T10	0	832	0	0
T11	0	832	0	0
T12	76052	0	0	0
T13	8805	0	0	0
T16	994	0	0	0
T17	711	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	113744254	0	0	0
DepthKnown_A	113744254	113685586	0	0
RvalidKnown_A	113744254	113685586	0	0
WreadyKnown_A	113744254	113685586	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	113744254	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	113744254	0	0	0
DepthKnown_A	113744254	113685586	0	0
RvalidKnown_A	113744254	113685586	0	0
WreadyKnown_A	113744254	113685586	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	113744254	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T18,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T12,T18,T19

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T18,T19

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T18,T58,T60
1	1	0	Not Covered
1	1	1	Covered	T12,T18,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T12,T18,T19
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T12,T18,T19

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T12,T18,T19
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	113744254	98708	0	0
DepthKnown_A	113744254	113685586	0	0
RvalidKnown_A	113744254	113685586	0	0
WreadyKnown_A	113744254	113685586	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	113744254	98708	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	98708	0	0
T6	534240	0	0	0
T7	38306	0	0	0
T8	101192	0	0	0
T9	148545	0	0	0
T12	76052	414	0	0
T13	8805	0	0	0
T14	51829	0	0	0
T15	5904	0	0	0
T18	0	977	0	0
T19	0	36	0	0
T20	2031	0	0	0
T32	1244	0	0	0
T58	0	7706	0	0
T60	0	1686	0	0
T61	0	861	0	0
T62	0	6189	0	0
T63	0	17	0	0
T64	0	477	0	0
T65	0	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	113685586	0	0
T1	34015	33959	0	0
T2	758407	758333	0	0
T3	1861	1777	0	0
T4	905554	905486	0	0
T5	30531	30476	0	0
T6	534240	534166	0	0
T12	76052	75971	0	0
T13	8805	8734	0	0
T16	994	910	0	0
T17	711	645	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	113744254	98708	0	0
T6	534240	0	0	0
T7	38306	0	0	0
T8	101192	0	0	0
T9	148545	0	0	0
T12	76052	414	0	0
T13	8805	0	0	0
T14	51829	0	0	0
T15	5904	0	0	0
T18	0	977	0	0
T19	0	36	0	0
T20	2031	0	0	0
T32	1244	0	0	0
T58	0	7706	0	0
T60	0	1686	0	0
T61	0	861	0	0
T62	0	6189	0	0
T63	0	17	0	0
T64	0	477	0	0
T65	0	10	0	0