Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.09 97.50 92.83 98.61 80.85 95.89 90.94 88.03


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T761 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2227021983 Apr 25 12:39:08 PM PDT 24 Apr 25 12:39:11 PM PDT 24 40076062 ps
T123 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1890811746 Apr 25 12:39:29 PM PDT 24 Apr 25 12:39:35 PM PDT 24 86208837 ps
T361 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3977099438 Apr 25 12:39:11 PM PDT 24 Apr 25 12:39:21 PM PDT 24 217885199 ps
T762 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1075906052 Apr 25 12:39:35 PM PDT 24 Apr 25 12:39:38 PM PDT 24 23446164 ps
T98 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4152946262 Apr 25 12:39:15 PM PDT 24 Apr 25 12:39:22 PM PDT 24 43528049 ps
T357 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3869583539 Apr 25 12:39:33 PM PDT 24 Apr 25 12:39:40 PM PDT 24 123148965 ps
T763 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3735603700 Apr 25 12:39:35 PM PDT 24 Apr 25 12:39:39 PM PDT 24 51515794 ps
T362 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3105965300 Apr 25 12:39:30 PM PDT 24 Apr 25 12:39:40 PM PDT 24 110967461 ps
T764 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.224597162 Apr 25 12:39:27 PM PDT 24 Apr 25 12:39:33 PM PDT 24 469092453 ps
T765 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2347395352 Apr 25 12:39:30 PM PDT 24 Apr 25 12:39:42 PM PDT 24 1901801936 ps
T766 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1694390880 Apr 25 12:39:05 PM PDT 24 Apr 25 12:39:09 PM PDT 24 392611854 ps
T767 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1149226403 Apr 25 12:39:11 PM PDT 24 Apr 25 12:39:35 PM PDT 24 1348206673 ps
T768 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4214224012 Apr 25 12:39:26 PM PDT 24 Apr 25 12:39:29 PM PDT 24 51774445 ps
T769 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.488034949 Apr 25 12:39:12 PM PDT 24 Apr 25 12:39:19 PM PDT 24 28275438 ps
T770 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.332022260 Apr 25 12:39:50 PM PDT 24 Apr 25 12:39:52 PM PDT 24 49449720 ps
T771 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.950920238 Apr 25 12:39:20 PM PDT 24 Apr 25 12:39:25 PM PDT 24 16391606 ps
T99 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2979723856 Apr 25 12:39:15 PM PDT 24 Apr 25 12:39:22 PM PDT 24 25428181 ps
T772 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.211477514 Apr 25 12:39:26 PM PDT 24 Apr 25 12:39:29 PM PDT 24 34170345 ps
T773 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.986797909 Apr 25 12:39:10 PM PDT 24 Apr 25 12:39:15 PM PDT 24 103473055 ps
T774 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1969671835 Apr 25 12:39:13 PM PDT 24 Apr 25 12:39:21 PM PDT 24 157186291 ps
T775 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2128719876 Apr 25 12:39:27 PM PDT 24 Apr 25 12:39:31 PM PDT 24 48476174 ps
T363 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1613062734 Apr 25 12:39:18 PM PDT 24 Apr 25 12:39:38 PM PDT 24 1126507121 ps
T776 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2637923639 Apr 25 12:39:26 PM PDT 24 Apr 25 12:39:30 PM PDT 24 45028630 ps
T365 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.463992718 Apr 25 12:39:17 PM PDT 24 Apr 25 12:39:41 PM PDT 24 287772765 ps
T777 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1622909401 Apr 25 12:39:31 PM PDT 24 Apr 25 12:39:35 PM PDT 24 55905414 ps
T778 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2074850012 Apr 25 12:39:35 PM PDT 24 Apr 25 12:39:38 PM PDT 24 63156752 ps
T779 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1937649211 Apr 25 12:39:30 PM PDT 24 Apr 25 12:39:36 PM PDT 24 87464932 ps
T780 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1537706828 Apr 25 12:39:13 PM PDT 24 Apr 25 12:39:23 PM PDT 24 63633387 ps
T781 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1004047723 Apr 25 12:39:35 PM PDT 24 Apr 25 12:39:38 PM PDT 24 15932396 ps
T782 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2469957357 Apr 25 12:39:28 PM PDT 24 Apr 25 12:39:35 PM PDT 24 131013686 ps
T783 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.753757560 Apr 25 12:39:13 PM PDT 24 Apr 25 12:39:20 PM PDT 24 92900727 ps
T784 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4120658896 Apr 25 12:39:26 PM PDT 24 Apr 25 12:39:31 PM PDT 24 75153192 ps
T785 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1762417049 Apr 25 12:39:40 PM PDT 24 Apr 25 12:39:42 PM PDT 24 39915878 ps
T364 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3641108118 Apr 25 12:39:28 PM PDT 24 Apr 25 12:39:52 PM PDT 24 15752376770 ps
T786 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.580818217 Apr 25 12:39:10 PM PDT 24 Apr 25 12:39:14 PM PDT 24 54849303 ps
T787 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.627180361 Apr 25 12:39:26 PM PDT 24 Apr 25 12:39:30 PM PDT 24 146809348 ps
T788 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3869617673 Apr 25 12:39:28 PM PDT 24 Apr 25 12:39:49 PM PDT 24 548873866 ps
T789 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4249090970 Apr 25 12:39:17 PM PDT 24 Apr 25 12:39:23 PM PDT 24 10749114 ps
T790 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.877830436 Apr 25 12:39:29 PM PDT 24 Apr 25 12:39:34 PM PDT 24 67586705 ps
T791 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2412650396 Apr 25 12:39:36 PM PDT 24 Apr 25 12:39:39 PM PDT 24 34873915 ps
T792 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.108679760 Apr 25 12:39:46 PM PDT 24 Apr 25 12:39:49 PM PDT 24 43196579 ps
T793 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1230114668 Apr 25 12:39:10 PM PDT 24 Apr 25 12:39:14 PM PDT 24 135809323 ps
T794 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2169134618 Apr 25 12:39:30 PM PDT 24 Apr 25 12:39:37 PM PDT 24 178961109 ps
T795 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1506903171 Apr 25 12:39:06 PM PDT 24 Apr 25 12:39:10 PM PDT 24 154422214 ps
T796 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3397751775 Apr 25 12:39:33 PM PDT 24 Apr 25 12:39:41 PM PDT 24 1894005459 ps
T797 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.268421052 Apr 25 12:39:14 PM PDT 24 Apr 25 12:39:21 PM PDT 24 41154992 ps
T798 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.582110379 Apr 25 12:39:09 PM PDT 24 Apr 25 12:39:12 PM PDT 24 16595996 ps
T799 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2311687998 Apr 25 12:39:30 PM PDT 24 Apr 25 12:39:36 PM PDT 24 111587269 ps
T800 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1968202899 Apr 25 12:39:39 PM PDT 24 Apr 25 12:39:41 PM PDT 24 16198768 ps
T801 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1274551741 Apr 25 12:39:12 PM PDT 24 Apr 25 12:39:19 PM PDT 24 199315691 ps
T802 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.664807205 Apr 25 12:39:27 PM PDT 24 Apr 25 12:39:32 PM PDT 24 22957186 ps
T803 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3805591268 Apr 25 12:39:19 PM PDT 24 Apr 25 12:39:28 PM PDT 24 964065265 ps
T804 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3665514665 Apr 25 12:39:41 PM PDT 24 Apr 25 12:39:49 PM PDT 24 269406910 ps
T805 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1909023947 Apr 25 12:39:37 PM PDT 24 Apr 25 12:39:42 PM PDT 24 1504799098 ps
T806 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1558850196 Apr 25 12:39:17 PM PDT 24 Apr 25 12:39:37 PM PDT 24 912602861 ps
T807 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2884043705 Apr 25 12:39:42 PM PDT 24 Apr 25 12:39:44 PM PDT 24 14103669 ps
T808 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3971206279 Apr 25 12:39:41 PM PDT 24 Apr 25 12:39:44 PM PDT 24 13368739 ps
T809 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1346277331 Apr 25 12:39:40 PM PDT 24 Apr 25 12:39:42 PM PDT 24 27913200 ps
T810 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.648569325 Apr 25 12:39:22 PM PDT 24 Apr 25 12:39:28 PM PDT 24 30516700 ps
T811 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3737516614 Apr 25 12:39:48 PM PDT 24 Apr 25 12:39:51 PM PDT 24 37073109 ps
T812 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2536478706 Apr 25 12:39:07 PM PDT 24 Apr 25 12:39:49 PM PDT 24 2821201957 ps
T813 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2394739000 Apr 25 12:39:15 PM PDT 24 Apr 25 12:39:36 PM PDT 24 8237123764 ps
T100 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2745528371 Apr 25 12:39:11 PM PDT 24 Apr 25 12:39:16 PM PDT 24 23658522 ps
T814 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2555879625 Apr 25 12:39:22 PM PDT 24 Apr 25 12:39:27 PM PDT 24 15911324 ps
T815 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2306061789 Apr 25 12:39:42 PM PDT 24 Apr 25 12:39:44 PM PDT 24 19387581 ps
T816 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3504618186 Apr 25 12:39:07 PM PDT 24 Apr 25 12:39:10 PM PDT 24 11602149 ps
T817 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1251698945 Apr 25 12:39:43 PM PDT 24 Apr 25 12:39:44 PM PDT 24 13188414 ps
T818 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.953183128 Apr 25 12:39:28 PM PDT 24 Apr 25 12:39:34 PM PDT 24 65690766 ps
T819 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1197414842 Apr 25 12:39:22 PM PDT 24 Apr 25 12:39:28 PM PDT 24 47912135 ps
T820 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3789679107 Apr 25 12:39:48 PM PDT 24 Apr 25 12:39:51 PM PDT 24 11564867 ps
T821 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2990078352 Apr 25 12:39:22 PM PDT 24 Apr 25 12:39:26 PM PDT 24 17214212 ps
T822 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2347551805 Apr 25 12:39:12 PM PDT 24 Apr 25 12:39:23 PM PDT 24 1330223967 ps
T823 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3724646000 Apr 25 12:39:27 PM PDT 24 Apr 25 12:39:34 PM PDT 24 129581209 ps
T824 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3630509321 Apr 25 12:39:27 PM PDT 24 Apr 25 12:39:33 PM PDT 24 119848364 ps
T825 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.539262073 Apr 25 12:39:13 PM PDT 24 Apr 25 12:39:21 PM PDT 24 376416137 ps
T826 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1966092777 Apr 25 12:39:13 PM PDT 24 Apr 25 12:39:22 PM PDT 24 153577158 ps
T827 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.220525594 Apr 25 12:39:29 PM PDT 24 Apr 25 12:39:35 PM PDT 24 30371310 ps
T828 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1880972863 Apr 25 12:39:08 PM PDT 24 Apr 25 12:39:12 PM PDT 24 71569751 ps
T829 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2458739373 Apr 25 12:39:25 PM PDT 24 Apr 25 12:39:30 PM PDT 24 127072673 ps
T830 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2516930677 Apr 25 12:39:39 PM PDT 24 Apr 25 12:39:40 PM PDT 24 14842978 ps
T831 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2629381735 Apr 25 12:39:39 PM PDT 24 Apr 25 12:39:42 PM PDT 24 117694795 ps

Test location /workspace/coverage/default/0.spi_device_intercept.3376406375
Short name T5
Test name
Test status
Simulation time 308411177 ps
CPU time 6.84 seconds
Started Apr 25 01:09:34 PM PDT 24
Finished Apr 25 01:09:44 PM PDT 24
Peak memory 220300 kb
Host smart-295c3d83-1d5c-4f71-acaf-2a693f2d8725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376406375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3376406375
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1907994246
Short name T58
Test name
Test status
Simulation time 5272708641 ps
CPU time 43.69 seconds
Started Apr 25 01:11:16 PM PDT 24
Finished Apr 25 01:12:01 PM PDT 24
Peak memory 216360 kb
Host smart-45956613-e5c4-43e4-a1f6-9d33eee5fe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907994246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1907994246
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.211266657
Short name T35
Test name
Test status
Simulation time 1962083101 ps
CPU time 21.91 seconds
Started Apr 25 12:39:31 PM PDT 24
Finished Apr 25 12:39:56 PM PDT 24
Peak memory 216724 kb
Host smart-029d56bc-6223-4882-97a5-203d3b1ec0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211266657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.211266657
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1209554715
Short name T21
Test name
Test status
Simulation time 81215083 ps
CPU time 1.07 seconds
Started Apr 25 01:12:17 PM PDT 24
Finished Apr 25 01:12:19 PM PDT 24
Peak memory 207136 kb
Host smart-4a829bd3-209d-46c6-a52c-8149dfe52405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209554715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1209554715
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_upload.1832271891
Short name T28
Test name
Test status
Simulation time 892674044 ps
CPU time 9.87 seconds
Started Apr 25 01:11:50 PM PDT 24
Finished Apr 25 01:12:01 PM PDT 24
Peak memory 234932 kb
Host smart-3bc4282e-bb3f-4aac-bd5f-a33196adc957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832271891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1832271891
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3115223512
Short name T376
Test name
Test status
Simulation time 16890338577 ps
CPU time 42.62 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:48 PM PDT 24
Peak memory 222096 kb
Host smart-89b68bca-d3a8-4825-8b5b-73ebc53fcc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115223512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3115223512
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1044893541
Short name T87
Test name
Test status
Simulation time 4518458616 ps
CPU time 25.24 seconds
Started Apr 25 01:11:30 PM PDT 24
Finished Apr 25 01:11:56 PM PDT 24
Peak memory 250352 kb
Host smart-984850a9-44c9-4466-8716-53bfbe79841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044893541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1044893541
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_upload.850279748
Short name T68
Test name
Test status
Simulation time 18443807579 ps
CPU time 28.02 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:12:13 PM PDT 24
Peak memory 235404 kb
Host smart-98b10639-3619-4322-a8d8-8d2d25cf838d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850279748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.850279748
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.457189928
Short name T41
Test name
Test status
Simulation time 40265060 ps
CPU time 0.75 seconds
Started Apr 25 01:09:34 PM PDT 24
Finished Apr 25 01:09:37 PM PDT 24
Peak memory 216188 kb
Host smart-549fae67-c3fc-4fb6-80e5-9234536279cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457189928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.457189928
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1160141377
Short name T26
Test name
Test status
Simulation time 817919721 ps
CPU time 12.08 seconds
Started Apr 25 01:09:33 PM PDT 24
Finished Apr 25 01:09:49 PM PDT 24
Peak memory 218520 kb
Host smart-56582a87-b3db-476b-9907-dffd80bd9163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160141377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1160141377
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2189148712
Short name T479
Test name
Test status
Simulation time 28980276517 ps
CPU time 70.89 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:12:22 PM PDT 24
Peak memory 216264 kb
Host smart-e999e75a-19db-4730-9420-a0789867ad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189148712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2189148712
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3905983181
Short name T113
Test name
Test status
Simulation time 7385411219 ps
CPU time 29.06 seconds
Started Apr 25 01:12:18 PM PDT 24
Finished Apr 25 01:12:49 PM PDT 24
Peak memory 232580 kb
Host smart-c9bb16ae-a5b9-46cf-bac7-0866e2d27528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905983181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3905983181
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3176152461
Short name T67
Test name
Test status
Simulation time 707610742 ps
CPU time 11.49 seconds
Started Apr 25 01:09:43 PM PDT 24
Finished Apr 25 01:09:56 PM PDT 24
Peak memory 237204 kb
Host smart-c7bb0c7d-3b52-4d9e-b33e-840db7fd34c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176152461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3176152461
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3552091739
Short name T379
Test name
Test status
Simulation time 2827734924 ps
CPU time 35.44 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:34 PM PDT 24
Peak memory 216296 kb
Host smart-f87e1167-c6af-4c60-8caa-f1530a66fe32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552091739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3552091739
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2935486735
Short name T17
Test name
Test status
Simulation time 142574127 ps
CPU time 0.72 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:10:10 PM PDT 24
Peak memory 205372 kb
Host smart-e1cf40d2-8832-487e-9ad1-6bb0b5a109a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935486735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
935486735
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3880755911
Short name T307
Test name
Test status
Simulation time 2930425719 ps
CPU time 35.06 seconds
Started Apr 25 01:12:29 PM PDT 24
Finished Apr 25 01:13:05 PM PDT 24
Peak memory 223232 kb
Host smart-16a04f2e-3a61-4aa3-a0a5-5e41d7c9aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880755911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3880755911
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.358115559
Short name T115
Test name
Test status
Simulation time 70114017 ps
CPU time 4.69 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 215140 kb
Host smart-882246da-3b7a-4ec3-aa09-40627da33ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358115559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.358115559
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.93738348
Short name T168
Test name
Test status
Simulation time 6517440534 ps
CPU time 18.24 seconds
Started Apr 25 01:11:50 PM PDT 24
Finished Apr 25 01:12:09 PM PDT 24
Peak memory 223592 kb
Host smart-b24b40f0-89c2-4a98-9d36-0fab45d3abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93738348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.93738348
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1466810238
Short name T116
Test name
Test status
Simulation time 38750879184 ps
CPU time 80.16 seconds
Started Apr 25 01:10:37 PM PDT 24
Finished Apr 25 01:11:57 PM PDT 24
Peak memory 239992 kb
Host smart-c73ae9ec-7a57-40d0-94ce-2012858c4d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466810238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1466810238
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_upload.2214987658
Short name T238
Test name
Test status
Simulation time 14107132235 ps
CPU time 18.58 seconds
Started Apr 25 01:11:27 PM PDT 24
Finished Apr 25 01:11:46 PM PDT 24
Peak memory 224544 kb
Host smart-eb49a0f3-a731-4830-8696-423b3152246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214987658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2214987658
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_upload.2226921160
Short name T262
Test name
Test status
Simulation time 8762795564 ps
CPU time 25.44 seconds
Started Apr 25 01:12:39 PM PDT 24
Finished Apr 25 01:13:06 PM PDT 24
Peak memory 219708 kb
Host smart-2c31c595-b164-4a7c-9b38-1de86668ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226921160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2226921160
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.58220383
Short name T135
Test name
Test status
Simulation time 762001005 ps
CPU time 8.43 seconds
Started Apr 25 12:39:17 PM PDT 24
Finished Apr 25 12:39:31 PM PDT 24
Peak memory 215104 kb
Host smart-36c5cae4-3f36-444b-995b-a312750fd593
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58220383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
aliasing.58220383
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2443788145
Short name T80
Test name
Test status
Simulation time 692568282 ps
CPU time 13.61 seconds
Started Apr 25 01:12:15 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 239964 kb
Host smart-0b5248e1-45ea-4e98-80ec-0f6756cd47a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443788145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2443788145
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3293177322
Short name T69
Test name
Test status
Simulation time 5641213453 ps
CPU time 17.82 seconds
Started Apr 25 01:11:00 PM PDT 24
Finished Apr 25 01:11:19 PM PDT 24
Peak memory 226964 kb
Host smart-5fc10329-f6cd-40e2-afca-f28888405e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293177322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3293177322
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3503853883
Short name T337
Test name
Test status
Simulation time 9681349263 ps
CPU time 15.62 seconds
Started Apr 25 01:09:35 PM PDT 24
Finished Apr 25 01:09:53 PM PDT 24
Peak memory 216768 kb
Host smart-eb4adfda-542b-4615-8690-196b7b60567a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503853883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3503853883
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1132694814
Short name T54
Test name
Test status
Simulation time 7937778933 ps
CPU time 8.24 seconds
Started Apr 25 01:10:18 PM PDT 24
Finished Apr 25 01:10:28 PM PDT 24
Peak memory 217424 kb
Host smart-99afc3b0-4da1-4282-9cc1-0d58f92b779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132694814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1132694814
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2530520251
Short name T301
Test name
Test status
Simulation time 350921461 ps
CPU time 4.43 seconds
Started Apr 25 01:12:18 PM PDT 24
Finished Apr 25 01:12:25 PM PDT 24
Peak memory 216808 kb
Host smart-360606d3-fbb7-4110-8cfa-c37199e84f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530520251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2530520251
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1828343368
Short name T61
Test name
Test status
Simulation time 6380821690 ps
CPU time 42.56 seconds
Started Apr 25 01:10:05 PM PDT 24
Finished Apr 25 01:10:49 PM PDT 24
Peak memory 216360 kb
Host smart-d923c494-b705-4b30-8e07-a7f2dbb51579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828343368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1828343368
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_upload.3017541614
Short name T252
Test name
Test status
Simulation time 1484377112 ps
CPU time 9.42 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:12:39 PM PDT 24
Peak memory 232564 kb
Host smart-4d631235-b934-480c-8c53-87e52dfddd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017541614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3017541614
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.285579688
Short name T94
Test name
Test status
Simulation time 11383349896 ps
CPU time 18.8 seconds
Started Apr 25 01:12:31 PM PDT 24
Finished Apr 25 01:12:51 PM PDT 24
Peak memory 218680 kb
Host smart-e52953c6-9a84-4720-bef8-122fc0b0b0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285579688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.285579688
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.503036231
Short name T49
Test name
Test status
Simulation time 185220427 ps
CPU time 1.03 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:10:49 PM PDT 24
Peak memory 206260 kb
Host smart-3cc9e77f-120e-4cce-b5f4-a7ccf6112861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503036231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.503036231
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2496955452
Short name T14
Test name
Test status
Simulation time 518323788 ps
CPU time 4.32 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:11 PM PDT 24
Peak memory 216276 kb
Host smart-d2f86eec-6a01-49d2-a322-a8f3b4f5e27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496955452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2496955452
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.949640146
Short name T324
Test name
Test status
Simulation time 24207635162 ps
CPU time 49.52 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:10:36 PM PDT 24
Peak memory 224284 kb
Host smart-959c2582-151d-4c16-a657-8e4f55cfbc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949640146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.949640146
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1353531151
Short name T290
Test name
Test status
Simulation time 2525461525 ps
CPU time 53.97 seconds
Started Apr 25 01:10:06 PM PDT 24
Finished Apr 25 01:11:02 PM PDT 24
Peak memory 232692 kb
Host smart-6893afdf-3cea-4411-8bb6-7887ac9e6f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353531151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1353531151
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3068734191
Short name T105
Test name
Test status
Simulation time 5712470120 ps
CPU time 58.8 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:10:57 PM PDT 24
Peak memory 221344 kb
Host smart-67801762-ee88-4fcf-9875-e8049fb46a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068734191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3068734191
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.354344754
Short name T48
Test name
Test status
Simulation time 85146713 ps
CPU time 1.2 seconds
Started Apr 25 01:09:30 PM PDT 24
Finished Apr 25 01:09:32 PM PDT 24
Peak memory 235324 kb
Host smart-4887cc8e-3dd5-4a3e-a4b4-5df6ffadd881
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354344754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.354344754
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3762464283
Short name T208
Test name
Test status
Simulation time 1433575116 ps
CPU time 7.09 seconds
Started Apr 25 01:11:03 PM PDT 24
Finished Apr 25 01:11:11 PM PDT 24
Peak memory 224112 kb
Host smart-e3359d0f-d38c-4a88-98cf-1d3ca87d73b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762464283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3762464283
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1616484278
Short name T175
Test name
Test status
Simulation time 51461995052 ps
CPU time 36.36 seconds
Started Apr 25 01:12:19 PM PDT 24
Finished Apr 25 01:12:57 PM PDT 24
Peak memory 239988 kb
Host smart-de3d1238-16fd-4c3f-acae-ff71f5e75365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616484278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1616484278
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4109799392
Short name T233
Test name
Test status
Simulation time 3045155807 ps
CPU time 31.37 seconds
Started Apr 25 01:09:59 PM PDT 24
Finished Apr 25 01:10:33 PM PDT 24
Peak memory 219164 kb
Host smart-8efe2277-17dd-4204-86f3-6119ced8287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109799392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4109799392
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.771237078
Short name T338
Test name
Test status
Simulation time 751236454 ps
CPU time 7.41 seconds
Started Apr 25 01:10:37 PM PDT 24
Finished Apr 25 01:10:46 PM PDT 24
Peak memory 221472 kb
Host smart-e4d6fc86-c226-4445-9162-efefddafc8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771237078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.771237078
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.738491848
Short name T312
Test name
Test status
Simulation time 14760493925 ps
CPU time 120.24 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:12:00 PM PDT 24
Peak memory 223872 kb
Host smart-48ab97c9-1b33-4b9c-9a8e-c782ab8a23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738491848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.738491848
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3126533041
Short name T314
Test name
Test status
Simulation time 2930106341 ps
CPU time 11.73 seconds
Started Apr 25 01:11:45 PM PDT 24
Finished Apr 25 01:11:58 PM PDT 24
Peak memory 223440 kb
Host smart-9e3b4d2d-946b-4e0c-84c6-39b846f60cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126533041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3126533041
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_upload.2680564608
Short name T346
Test name
Test status
Simulation time 66303410953 ps
CPU time 33.36 seconds
Started Apr 25 01:12:21 PM PDT 24
Finished Apr 25 01:12:55 PM PDT 24
Peak memory 219300 kb
Host smart-9fe7af1f-0a6b-4246-9ff5-8c2c2d1714ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680564608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2680564608
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4189877227
Short name T230
Test name
Test status
Simulation time 212654351 ps
CPU time 4.45 seconds
Started Apr 25 01:11:56 PM PDT 24
Finished Apr 25 01:12:01 PM PDT 24
Peak memory 218660 kb
Host smart-c8c50501-8887-4690-96e2-110e3ded91d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189877227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4189877227
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2204602492
Short name T223
Test name
Test status
Simulation time 3434175534 ps
CPU time 13.06 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 232844 kb
Host smart-b7512d0b-94af-46d2-8ada-79daabf8ad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204602492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2204602492
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3967924796
Short name T197
Test name
Test status
Simulation time 11438599820 ps
CPU time 72.61 seconds
Started Apr 25 01:09:44 PM PDT 24
Finished Apr 25 01:10:58 PM PDT 24
Peak memory 224400 kb
Host smart-969cc6bd-d6cc-46d9-81d4-637ea71401cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967924796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3967924796
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.694395294
Short name T279
Test name
Test status
Simulation time 6745485986 ps
CPU time 100.99 seconds
Started Apr 25 01:12:17 PM PDT 24
Finished Apr 25 01:13:59 PM PDT 24
Peak memory 240524 kb
Host smart-d9f63a1e-64cc-49dc-9011-44033e5fc18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694395294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.694395294
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2110204993
Short name T164
Test name
Test status
Simulation time 1437182253 ps
CPU time 9.06 seconds
Started Apr 25 01:12:37 PM PDT 24
Finished Apr 25 01:12:47 PM PDT 24
Peak memory 222696 kb
Host smart-af9cfb0b-8114-40b4-a1c3-8893694daaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110204993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2110204993
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.641749884
Short name T188
Test name
Test status
Simulation time 1290736196 ps
CPU time 8.23 seconds
Started Apr 25 01:10:37 PM PDT 24
Finished Apr 25 01:10:47 PM PDT 24
Peak memory 222872 kb
Host smart-8eae5d72-e2d3-49fc-a350-df3f63df3bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641749884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.641749884
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3811221471
Short name T340
Test name
Test status
Simulation time 4244845855 ps
CPU time 6.59 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:18 PM PDT 24
Peak memory 234800 kb
Host smart-799b6efa-f32f-4c18-9d16-d8d9458554ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811221471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3811221471
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3150219463
Short name T561
Test name
Test status
Simulation time 6223008305 ps
CPU time 45.13 seconds
Started Apr 25 01:11:00 PM PDT 24
Finished Apr 25 01:11:46 PM PDT 24
Peak memory 216380 kb
Host smart-8f7a2dcf-4ebf-4d63-91ec-bbf297028805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150219463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3150219463
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3972619830
Short name T66
Test name
Test status
Simulation time 229107742 ps
CPU time 3.46 seconds
Started Apr 25 01:11:41 PM PDT 24
Finished Apr 25 01:11:46 PM PDT 24
Peak memory 218644 kb
Host smart-66b2e9dd-f768-4ed6-b4f5-cba15771ee6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972619830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3972619830
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_upload.579244097
Short name T319
Test name
Test status
Simulation time 45182220202 ps
CPU time 23.77 seconds
Started Apr 25 01:12:02 PM PDT 24
Finished Apr 25 01:12:26 PM PDT 24
Peak memory 240692 kb
Host smart-0063a13b-8090-468d-b698-e803576b358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579244097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.579244097
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3869583539
Short name T357
Test name
Test status
Simulation time 123148965 ps
CPU time 3.95 seconds
Started Apr 25 12:39:33 PM PDT 24
Finished Apr 25 12:39:40 PM PDT 24
Peak memory 215184 kb
Host smart-b0466083-eea2-4e8f-824f-22e50d819107
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869583539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3869583539
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3869617673
Short name T788
Test name
Test status
Simulation time 548873866 ps
CPU time 18.02 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 215500 kb
Host smart-a4d4089a-9293-4e4b-a1d9-59ad72949cef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869617673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3869617673
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_upload.860918375
Short name T345
Test name
Test status
Simulation time 1469269709 ps
CPU time 5.92 seconds
Started Apr 25 01:10:11 PM PDT 24
Finished Apr 25 01:10:18 PM PDT 24
Peak memory 219260 kb
Host smart-9d54cab5-4cd8-4433-bcd2-590d3eb5aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860918375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.860918375
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3065297791
Short name T704
Test name
Test status
Simulation time 1700732302 ps
CPU time 18.95 seconds
Started Apr 25 01:10:51 PM PDT 24
Finished Apr 25 01:11:11 PM PDT 24
Peak memory 218868 kb
Host smart-b55628f9-fc9c-4e0e-9986-729e2f343cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065297791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3065297791
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.869860946
Short name T73
Test name
Test status
Simulation time 8543975479 ps
CPU time 15.85 seconds
Started Apr 25 01:10:55 PM PDT 24
Finished Apr 25 01:11:12 PM PDT 24
Peak memory 232208 kb
Host smart-7c826bab-c379-49fa-9f45-e560838cc0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869860946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.869860946
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2663153594
Short name T167
Test name
Test status
Simulation time 2349129981 ps
CPU time 8.47 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:20 PM PDT 24
Peak memory 223568 kb
Host smart-24768bff-8382-4cdb-8e72-d27bc40bbdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663153594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2663153594
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.139958357
Short name T383
Test name
Test status
Simulation time 16971165651 ps
CPU time 29.13 seconds
Started Apr 25 01:11:25 PM PDT 24
Finished Apr 25 01:11:56 PM PDT 24
Peak memory 216328 kb
Host smart-07ac7acc-e06b-4213-82b3-3fa4f5781cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139958357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.139958357
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2413984413
Short name T308
Test name
Test status
Simulation time 4268212594 ps
CPU time 21.68 seconds
Started Apr 25 01:12:02 PM PDT 24
Finished Apr 25 01:12:25 PM PDT 24
Peak memory 238952 kb
Host smart-a3b4d52f-3958-4287-8cd1-4afd966f7037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413984413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2413984413
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3411244834
Short name T76
Test name
Test status
Simulation time 7436314463 ps
CPU time 12.07 seconds
Started Apr 25 01:10:17 PM PDT 24
Finished Apr 25 01:10:31 PM PDT 24
Peak memory 238036 kb
Host smart-f9aee83e-99e3-4169-9304-eda72162750c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411244834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3411244834
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2824335817
Short name T270
Test name
Test status
Simulation time 2550633043 ps
CPU time 7.91 seconds
Started Apr 25 01:10:07 PM PDT 24
Finished Apr 25 01:10:16 PM PDT 24
Peak memory 218628 kb
Host smart-ff4d920d-1c19-4657-a719-18adce0fe16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824335817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2824335817
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2423624354
Short name T286
Test name
Test status
Simulation time 11851490345 ps
CPU time 41.71 seconds
Started Apr 25 01:10:17 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 240900 kb
Host smart-1e055395-87d9-47b9-83f0-a0847e9f9bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423624354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2423624354
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_upload.3810903490
Short name T31
Test name
Test status
Simulation time 109292369 ps
CPU time 2.98 seconds
Started Apr 25 01:10:39 PM PDT 24
Finished Apr 25 01:10:43 PM PDT 24
Peak memory 223036 kb
Host smart-21bd1395-0bed-4f10-9cae-ad656b869832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810903490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3810903490
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_upload.17211877
Short name T195
Test name
Test status
Simulation time 1156041451 ps
CPU time 9.03 seconds
Started Apr 25 01:09:38 PM PDT 24
Finished Apr 25 01:09:49 PM PDT 24
Peak memory 216272 kb
Host smart-73869db9-0e94-40be-8df0-5dae6478ebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17211877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.17211877
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1182006380
Short name T334
Test name
Test status
Simulation time 886912161 ps
CPU time 4.85 seconds
Started Apr 25 01:11:37 PM PDT 24
Finished Apr 25 01:11:43 PM PDT 24
Peak memory 223040 kb
Host smart-63053131-8a25-4f8f-b1b5-8f8d2fdc9409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182006380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1182006380
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3744952604
Short name T260
Test name
Test status
Simulation time 41429416668 ps
CPU time 12.67 seconds
Started Apr 25 01:11:42 PM PDT 24
Finished Apr 25 01:11:55 PM PDT 24
Peak memory 224480 kb
Host smart-67324d87-58cc-490d-99da-21c94172a0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744952604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3744952604
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3055165851
Short name T77
Test name
Test status
Simulation time 444160255 ps
CPU time 3.42 seconds
Started Apr 25 01:12:39 PM PDT 24
Finished Apr 25 01:12:43 PM PDT 24
Peak memory 223468 kb
Host smart-089ec63f-76d1-485f-815c-2857f79cfea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055165851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3055165851
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.803906648
Short name T136
Test name
Test status
Simulation time 91603867 ps
CPU time 1.94 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 215156 kb
Host smart-93575f03-30d6-4d4b-ac38-788101c26bed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803906648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.803906648
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1234673989
Short name T24
Test name
Test status
Simulation time 1622921671 ps
CPU time 5.63 seconds
Started Apr 25 01:10:49 PM PDT 24
Finished Apr 25 01:10:55 PM PDT 24
Peak memory 218616 kb
Host smart-002ac835-360f-4199-8e84-183d417113bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234673989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1234673989
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3586482122
Short name T92
Test name
Test status
Simulation time 99919968 ps
CPU time 2.92 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:10:12 PM PDT 24
Peak memory 223016 kb
Host smart-d3ecf3f8-c7e8-48ed-b0bc-b6896a212071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586482122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3586482122
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3572622807
Short name T269
Test name
Test status
Simulation time 5000370293 ps
CPU time 8.77 seconds
Started Apr 25 01:09:33 PM PDT 24
Finished Apr 25 01:09:45 PM PDT 24
Peak memory 235128 kb
Host smart-a8a6c7e9-2f89-43b2-9784-799d156f4da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572622807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3572622807
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_intercept.203464582
Short name T265
Test name
Test status
Simulation time 3051706719 ps
CPU time 30.68 seconds
Started Apr 25 01:10:18 PM PDT 24
Finished Apr 25 01:10:51 PM PDT 24
Peak memory 223632 kb
Host smart-6f37f134-8eba-4c70-848d-b86e5fc5097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203464582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.203464582
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3112090214
Short name T177
Test name
Test status
Simulation time 912635448 ps
CPU time 8.95 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 223384 kb
Host smart-60471a38-5656-47f4-8341-677e250b1da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112090214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3112090214
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2511042742
Short name T101
Test name
Test status
Simulation time 49537689174 ps
CPU time 56.94 seconds
Started Apr 25 01:10:23 PM PDT 24
Finished Apr 25 01:11:21 PM PDT 24
Peak memory 216292 kb
Host smart-55d92805-d4e6-4907-a887-faa6ca969a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511042742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2511042742
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3325716590
Short name T192
Test name
Test status
Simulation time 334057189 ps
CPU time 4.27 seconds
Started Apr 25 01:10:19 PM PDT 24
Finished Apr 25 01:10:24 PM PDT 24
Peak memory 218716 kb
Host smart-f78de251-c1ca-45c5-a9ab-fc4a8ab91d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325716590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3325716590
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1064281989
Short name T254
Test name
Test status
Simulation time 34022057670 ps
CPU time 10.01 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:10:26 PM PDT 24
Peak memory 222872 kb
Host smart-d9b8c0da-6121-4e11-a7fd-a7a277386900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064281989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1064281989
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2642257773
Short name T349
Test name
Test status
Simulation time 3690797728 ps
CPU time 70.82 seconds
Started Apr 25 01:10:24 PM PDT 24
Finished Apr 25 01:11:36 PM PDT 24
Peak memory 240692 kb
Host smart-794142de-f240-47f0-b6de-71020a141603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642257773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2642257773
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_upload.542613857
Short name T253
Test name
Test status
Simulation time 7180864012 ps
CPU time 6.01 seconds
Started Apr 25 01:10:39 PM PDT 24
Finished Apr 25 01:10:46 PM PDT 24
Peak memory 224596 kb
Host smart-261d3112-64e9-44f7-97dc-51e0ece9dc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542613857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.542613857
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1802094533
Short name T70
Test name
Test status
Simulation time 1866289395 ps
CPU time 6.4 seconds
Started Apr 25 01:10:47 PM PDT 24
Finished Apr 25 01:10:54 PM PDT 24
Peak memory 234448 kb
Host smart-3275dc68-0be7-4818-832a-cb22f596f6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802094533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1802094533
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4106212959
Short name T189
Test name
Test status
Simulation time 537933506 ps
CPU time 6.85 seconds
Started Apr 25 01:10:44 PM PDT 24
Finished Apr 25 01:10:52 PM PDT 24
Peak memory 232588 kb
Host smart-eb822e5b-b386-426e-aee0-e7f4926bacd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106212959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4106212959
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_upload.2972988257
Short name T329
Test name
Test status
Simulation time 24635997187 ps
CPU time 19.43 seconds
Started Apr 25 01:10:45 PM PDT 24
Finished Apr 25 01:11:06 PM PDT 24
Peak memory 219096 kb
Host smart-b1dfd051-9980-4019-a2cc-1053c2f579d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972988257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2972988257
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.310994515
Short name T79
Test name
Test status
Simulation time 1128001623 ps
CPU time 6.03 seconds
Started Apr 25 01:10:49 PM PDT 24
Finished Apr 25 01:10:56 PM PDT 24
Peak memory 222144 kb
Host smart-f7ee9c37-8663-4984-9737-696db8b6bb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310994515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.310994515
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_upload.3871636117
Short name T326
Test name
Test status
Simulation time 4407315620 ps
CPU time 6.9 seconds
Started Apr 25 01:10:55 PM PDT 24
Finished Apr 25 01:11:03 PM PDT 24
Peak memory 233340 kb
Host smart-2bf0305b-194e-4d4c-a69a-8b4fbe7a4354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871636117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3871636117
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.278856766
Short name T267
Test name
Test status
Simulation time 2640768669 ps
CPU time 6.54 seconds
Started Apr 25 01:11:00 PM PDT 24
Finished Apr 25 01:11:08 PM PDT 24
Peak memory 222140 kb
Host smart-312bb880-64f5-4b9b-b161-d371274fb4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278856766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.278856766
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3855246411
Short name T247
Test name
Test status
Simulation time 9679413857 ps
CPU time 47.17 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:53 PM PDT 24
Peak memory 232816 kb
Host smart-3ace067e-4b3c-4e84-8f4f-ddd5f0d172ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855246411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3855246411
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1702732735
Short name T352
Test name
Test status
Simulation time 10313378624 ps
CPU time 49.92 seconds
Started Apr 25 01:11:02 PM PDT 24
Finished Apr 25 01:11:53 PM PDT 24
Peak memory 233096 kb
Host smart-15bbf1a1-f1bd-4438-beb2-4e6ea7df316c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702732735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1702732735
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3178715651
Short name T283
Test name
Test status
Simulation time 597616691 ps
CPU time 14.05 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:11:59 PM PDT 24
Peak memory 232808 kb
Host smart-37649157-2f46-4d21-acb9-481b4abc7d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178715651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3178715651
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.190372338
Short name T384
Test name
Test status
Simulation time 7869317756 ps
CPU time 12.68 seconds
Started Apr 25 01:11:35 PM PDT 24
Finished Apr 25 01:11:48 PM PDT 24
Peak memory 216396 kb
Host smart-e6ce1dab-3942-4852-877d-8fcd3bf4221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190372338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.190372338
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.52044428
Short name T317
Test name
Test status
Simulation time 651572425 ps
CPU time 4.06 seconds
Started Apr 25 01:11:33 PM PDT 24
Finished Apr 25 01:11:38 PM PDT 24
Peak memory 223180 kb
Host smart-c8b87e3b-424e-45f3-b4d4-3d8217b3f40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52044428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.52044428
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3457298823
Short name T311
Test name
Test status
Simulation time 16083505302 ps
CPU time 24.91 seconds
Started Apr 25 01:11:42 PM PDT 24
Finished Apr 25 01:12:07 PM PDT 24
Peak memory 224732 kb
Host smart-b7cba679-001f-406e-819f-a9c11ed469b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457298823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3457298823
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2025238880
Short name T228
Test name
Test status
Simulation time 1047697145 ps
CPU time 5.77 seconds
Started Apr 25 01:11:49 PM PDT 24
Finished Apr 25 01:11:56 PM PDT 24
Peak memory 220444 kb
Host smart-ab3d3432-4fec-42e5-b0fb-4f9fb04aeff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025238880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2025238880
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4259280259
Short name T50
Test name
Test status
Simulation time 113389430 ps
CPU time 3.75 seconds
Started Apr 25 01:09:46 PM PDT 24
Finished Apr 25 01:09:51 PM PDT 24
Peak memory 218424 kb
Host smart-db28ccbf-f929-491c-b072-ee4cce277a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259280259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4259280259
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3987791070
Short name T128
Test name
Test status
Simulation time 2155050382 ps
CPU time 21.79 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:39 PM PDT 24
Peak memory 215124 kb
Host smart-360104cb-a43c-4820-9ad4-0ac2347de443
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987791070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3987791070
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2394739000
Short name T813
Test name
Test status
Simulation time 8237123764 ps
CPU time 15.7 seconds
Started Apr 25 12:39:15 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 215128 kb
Host smart-99bd08dd-c7da-4fa8-8ed4-38b93dd24156
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394739000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2394739000
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1613062734
Short name T363
Test name
Test status
Simulation time 1126507121 ps
CPU time 14.36 seconds
Started Apr 25 12:39:18 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 215052 kb
Host smart-49764c98-5e3e-455a-9ca4-38613fe78ef6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613062734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1613062734
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3547599415
Short name T209
Test name
Test status
Simulation time 780213576 ps
CPU time 4.89 seconds
Started Apr 25 01:09:35 PM PDT 24
Finished Apr 25 01:09:42 PM PDT 24
Peak memory 218412 kb
Host smart-4ad21844-b357-4261-b513-f4117c2f1d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547599415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3547599415
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3514451845
Short name T327
Test name
Test status
Simulation time 16482523316 ps
CPU time 16.83 seconds
Started Apr 25 01:09:32 PM PDT 24
Finished Apr 25 01:09:51 PM PDT 24
Peak memory 218664 kb
Host smart-8195c5b6-7ddd-4086-9c17-c33239880cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514451845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3514451845
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3230317014
Short name T295
Test name
Test status
Simulation time 994294949 ps
CPU time 22.25 seconds
Started Apr 25 01:10:05 PM PDT 24
Finished Apr 25 01:10:28 PM PDT 24
Peak memory 240656 kb
Host smart-f3fe0503-4763-43fb-acca-87aabf7af5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230317014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3230317014
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.210236051
Short name T226
Test name
Test status
Simulation time 615805967 ps
CPU time 8.66 seconds
Started Apr 25 01:10:09 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 224084 kb
Host smart-a306975e-0700-4c0e-af4d-1133c9fafc94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210236051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.210236051
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3400386620
Short name T273
Test name
Test status
Simulation time 1548442960 ps
CPU time 6.58 seconds
Started Apr 25 01:10:40 PM PDT 24
Finished Apr 25 01:10:48 PM PDT 24
Peak memory 223180 kb
Host smart-69cdc1d5-613c-4fda-b863-642a1563c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400386620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3400386620
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2349238371
Short name T249
Test name
Test status
Simulation time 70758289508 ps
CPU time 110.85 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:12:00 PM PDT 24
Peak memory 231396 kb
Host smart-688a565b-659b-4030-92f3-ced06706ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349238371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2349238371
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2110457517
Short name T339
Test name
Test status
Simulation time 950677434 ps
CPU time 7.23 seconds
Started Apr 25 01:10:06 PM PDT 24
Finished Apr 25 01:10:14 PM PDT 24
Peak memory 225876 kb
Host smart-4ee81907-0cd9-4e63-9dd1-638ba97bd930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110457517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2110457517
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1266958707
Short name T256
Test name
Test status
Simulation time 28901955772 ps
CPU time 25.61 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:10:35 PM PDT 24
Peak memory 232752 kb
Host smart-e275ced1-490f-4281-90ef-92114372dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266958707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1266958707
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4010093686
Short name T332
Test name
Test status
Simulation time 16690150613 ps
CPU time 50.92 seconds
Started Apr 25 01:10:09 PM PDT 24
Finished Apr 25 01:11:02 PM PDT 24
Peak memory 218896 kb
Host smart-b7e22ada-b9f9-4c58-93ae-f851f2dac06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010093686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4010093686
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.170992440
Short name T110
Test name
Test status
Simulation time 13926005261 ps
CPU time 38.55 seconds
Started Apr 25 01:10:18 PM PDT 24
Finished Apr 25 01:10:58 PM PDT 24
Peak memory 223452 kb
Host smart-a2a6f03d-3ba0-424c-a3c4-538dcd4dcfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170992440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.170992440
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2184642829
Short name T335
Test name
Test status
Simulation time 2323331579 ps
CPU time 10.56 seconds
Started Apr 25 01:10:07 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 232688 kb
Host smart-6f2caffc-633f-4036-9685-9ef53d2b16dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184642829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2184642829
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2813892640
Short name T294
Test name
Test status
Simulation time 262429954 ps
CPU time 8.83 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:23 PM PDT 24
Peak memory 232632 kb
Host smart-2817d85d-47a9-47b1-adf9-ff80c9b271d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813892640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2813892640
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2710337391
Short name T342
Test name
Test status
Simulation time 6539204968 ps
CPU time 13.83 seconds
Started Apr 25 01:10:24 PM PDT 24
Finished Apr 25 01:10:39 PM PDT 24
Peak memory 234432 kb
Host smart-1b942939-9d27-4c71-80e3-f017f1d37d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710337391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2710337391
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3929104442
Short name T186
Test name
Test status
Simulation time 12177261986 ps
CPU time 42.59 seconds
Started Apr 25 01:10:17 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 236344 kb
Host smart-c76c7e52-5f64-4aab-943a-1a0cfbc33b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929104442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3929104442
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4215102994
Short name T78
Test name
Test status
Simulation time 6041341282 ps
CPU time 18.42 seconds
Started Apr 25 01:10:24 PM PDT 24
Finished Apr 25 01:10:43 PM PDT 24
Peak memory 232368 kb
Host smart-7cb9dfe4-1581-49c9-9742-c8d70829e2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215102994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4215102994
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.666864188
Short name T211
Test name
Test status
Simulation time 45554850465 ps
CPU time 140.49 seconds
Started Apr 25 01:10:31 PM PDT 24
Finished Apr 25 01:12:53 PM PDT 24
Peak memory 231100 kb
Host smart-e64cbad9-b9b8-4947-bed3-60c48f8e4681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666864188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.666864188
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3694248253
Short name T336
Test name
Test status
Simulation time 195400563 ps
CPU time 2.68 seconds
Started Apr 25 01:10:28 PM PDT 24
Finished Apr 25 01:10:32 PM PDT 24
Peak memory 222712 kb
Host smart-62d4117e-f2e4-49cd-ba07-c0713728833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694248253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3694248253
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.838855059
Short name T75
Test name
Test status
Simulation time 7322574973 ps
CPU time 18.51 seconds
Started Apr 25 01:09:38 PM PDT 24
Finished Apr 25 01:09:59 PM PDT 24
Peak memory 224372 kb
Host smart-06b935b7-21d2-4ab7-9194-803899c2f887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838855059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
838855059
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2246205682
Short name T1
Test name
Test status
Simulation time 1360682977 ps
CPU time 6.55 seconds
Started Apr 25 01:09:42 PM PDT 24
Finished Apr 25 01:09:51 PM PDT 24
Peak memory 222244 kb
Host smart-78c4aa21-5a67-46b0-b14c-dbbaf4750f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246205682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2246205682
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1465846905
Short name T323
Test name
Test status
Simulation time 1239879181 ps
CPU time 8.94 seconds
Started Apr 25 01:10:43 PM PDT 24
Finished Apr 25 01:10:53 PM PDT 24
Peak memory 221620 kb
Host smart-7032f053-4222-4f9e-acd5-6e48f113bf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465846905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1465846905
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1033040320
Short name T333
Test name
Test status
Simulation time 29747596167 ps
CPU time 14.99 seconds
Started Apr 25 01:10:37 PM PDT 24
Finished Apr 25 01:10:53 PM PDT 24
Peak memory 224312 kb
Host smart-93700e5b-03ef-47ab-a3d7-281150af65f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033040320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1033040320
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2078411764
Short name T377
Test name
Test status
Simulation time 2329945947 ps
CPU time 41.82 seconds
Started Apr 25 01:10:37 PM PDT 24
Finished Apr 25 01:11:20 PM PDT 24
Peak memory 216344 kb
Host smart-8769ba25-05ed-48b0-b47e-8f5a8522ad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078411764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2078411764
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3898784768
Short name T303
Test name
Test status
Simulation time 4766412161 ps
CPU time 64.78 seconds
Started Apr 25 01:10:59 PM PDT 24
Finished Apr 25 01:12:05 PM PDT 24
Peak memory 219084 kb
Host smart-77f6ff92-c530-4195-bbe3-910746e3993e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898784768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3898784768
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2768213978
Short name T107
Test name
Test status
Simulation time 1748917169 ps
CPU time 13.23 seconds
Started Apr 25 01:10:49 PM PDT 24
Finished Apr 25 01:11:03 PM PDT 24
Peak memory 239152 kb
Host smart-7695d036-be85-4247-aa1c-f86723d3faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768213978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2768213978
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1282975113
Short name T261
Test name
Test status
Simulation time 10660488308 ps
CPU time 10.75 seconds
Started Apr 25 01:10:59 PM PDT 24
Finished Apr 25 01:11:11 PM PDT 24
Peak memory 224044 kb
Host smart-adbea72c-c0a1-4940-8d5f-5306ca80ae13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282975113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1282975113
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2161857658
Short name T321
Test name
Test status
Simulation time 5689752099 ps
CPU time 11.69 seconds
Started Apr 25 01:10:56 PM PDT 24
Finished Apr 25 01:11:09 PM PDT 24
Peak memory 232692 kb
Host smart-387d9999-e0d6-4e46-a60d-e60d28afe0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161857658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2161857658
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.326609888
Short name T316
Test name
Test status
Simulation time 4062684501 ps
CPU time 6.76 seconds
Started Apr 25 01:10:56 PM PDT 24
Finished Apr 25 01:11:04 PM PDT 24
Peak memory 221068 kb
Host smart-c0139507-7e16-4a43-bbef-16a4e1de5e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326609888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.326609888
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2130721111
Short name T52
Test name
Test status
Simulation time 1831232779 ps
CPU time 8.81 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:15 PM PDT 24
Peak memory 218732 kb
Host smart-62c1950a-90c7-457b-be47-c57b8803f631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130721111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2130721111
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.745797275
Short name T191
Test name
Test status
Simulation time 304252566 ps
CPU time 3.38 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:15 PM PDT 24
Peak memory 222476 kb
Host smart-97592fd4-8f67-41fd-bcab-64760f93ebeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745797275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.745797275
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.819412439
Short name T325
Test name
Test status
Simulation time 4114358494 ps
CPU time 8.89 seconds
Started Apr 25 01:11:08 PM PDT 24
Finished Apr 25 01:11:17 PM PDT 24
Peak memory 222916 kb
Host smart-04605517-550f-498a-8f77-3582a8824b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819412439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.819412439
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.413303654
Short name T341
Test name
Test status
Simulation time 181042528 ps
CPU time 2.65 seconds
Started Apr 25 01:11:31 PM PDT 24
Finished Apr 25 01:11:34 PM PDT 24
Peak memory 222728 kb
Host smart-cf1c29be-4254-41d0-9bf1-7a3fc83402b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413303654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.413303654
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.967884204
Short name T235
Test name
Test status
Simulation time 1078830973 ps
CPU time 10.61 seconds
Started Apr 25 01:11:30 PM PDT 24
Finished Apr 25 01:11:42 PM PDT 24
Peak memory 216728 kb
Host smart-a5c76330-6e5d-47b7-bf06-de83aa59e1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967884204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.967884204
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.611699225
Short name T93
Test name
Test status
Simulation time 3654574546 ps
CPU time 37.4 seconds
Started Apr 25 01:11:31 PM PDT 24
Finished Apr 25 01:12:09 PM PDT 24
Peak memory 240404 kb
Host smart-6001ea79-e6f4-436e-a85d-29f5e891e8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611699225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.611699225
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_upload.3919433012
Short name T231
Test name
Test status
Simulation time 209103656 ps
CPU time 3.53 seconds
Started Apr 25 01:11:35 PM PDT 24
Finished Apr 25 01:11:39 PM PDT 24
Peak memory 216208 kb
Host smart-633354da-45ac-4271-8199-f7baefe1cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919433012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3919433012
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1003687267
Short name T210
Test name
Test status
Simulation time 310030261 ps
CPU time 7.25 seconds
Started Apr 25 01:11:34 PM PDT 24
Finished Apr 25 01:11:42 PM PDT 24
Peak memory 237436 kb
Host smart-ed53c5c6-5b29-443b-b59b-adccadfb774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003687267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1003687267
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1234189066
Short name T173
Test name
Test status
Simulation time 5480680025 ps
CPU time 19.56 seconds
Started Apr 25 01:11:49 PM PDT 24
Finished Apr 25 01:12:10 PM PDT 24
Peak memory 224412 kb
Host smart-50de019e-ea06-44e2-821e-f0b36c8fed04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234189066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1234189066
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1402298045
Short name T251
Test name
Test status
Simulation time 579364587 ps
CPU time 5.26 seconds
Started Apr 25 01:11:54 PM PDT 24
Finished Apr 25 01:12:00 PM PDT 24
Peak memory 221776 kb
Host smart-007de501-112c-470e-8049-7c743987f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402298045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1402298045
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_upload.3220512609
Short name T206
Test name
Test status
Simulation time 412478233 ps
CPU time 3.52 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:10:01 PM PDT 24
Peak memory 218940 kb
Host smart-11e380bb-cd8d-4fd5-b716-5c842576e31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220512609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3220512609
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1103046515
Short name T266
Test name
Test status
Simulation time 374567226 ps
CPU time 3.19 seconds
Started Apr 25 01:12:03 PM PDT 24
Finished Apr 25 01:12:07 PM PDT 24
Peak memory 218756 kb
Host smart-2549b9da-9799-40ad-9f7b-2b8ac5d07b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103046515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1103046515
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_upload.198236839
Short name T218
Test name
Test status
Simulation time 12453591523 ps
CPU time 13.64 seconds
Started Apr 25 01:12:03 PM PDT 24
Finished Apr 25 01:12:18 PM PDT 24
Peak memory 216352 kb
Host smart-3d3c65d5-987b-467a-95ff-1f957f1b6053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198236839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.198236839
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_upload.465322238
Short name T171
Test name
Test status
Simulation time 3209813903 ps
CPU time 8.58 seconds
Started Apr 25 01:12:06 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 236228 kb
Host smart-4f093c42-b9ce-4963-904e-b9349ff2a855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465322238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.465322238
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1545652825
Short name T250
Test name
Test status
Simulation time 1747586969 ps
CPU time 8.84 seconds
Started Apr 25 01:12:19 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 218636 kb
Host smart-4b2b2de0-e151-47f4-af7b-ff61dad5d09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545652825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1545652825
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4262274253
Short name T6
Test name
Test status
Simulation time 23227729116 ps
CPU time 18.43 seconds
Started Apr 25 01:12:26 PM PDT 24
Finished Apr 25 01:12:45 PM PDT 24
Peak memory 223080 kb
Host smart-b4b303a0-1bae-4a06-99d2-2a3f1af50b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262274253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4262274253
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2735028305
Short name T217
Test name
Test status
Simulation time 81396089 ps
CPU time 2.66 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:12:31 PM PDT 24
Peak memory 223004 kb
Host smart-47870ad5-ceab-4ef0-be31-cc49fe6f0e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735028305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2735028305
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3165789711
Short name T74
Test name
Test status
Simulation time 659067012 ps
CPU time 2.46 seconds
Started Apr 25 01:12:34 PM PDT 24
Finished Apr 25 01:12:37 PM PDT 24
Peak memory 218836 kb
Host smart-acb52fa1-de4a-4905-bf36-c2715c423de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165789711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3165789711
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.677080648
Short name T243
Test name
Test status
Simulation time 4064660506 ps
CPU time 10.27 seconds
Started Apr 25 01:09:53 PM PDT 24
Finished Apr 25 01:10:05 PM PDT 24
Peak memory 232388 kb
Host smart-f980f3b8-2c7a-409d-bfe6-0c9082f6c783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677080648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
677080648
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2913835364
Short name T86
Test name
Test status
Simulation time 3453395480 ps
CPU time 13.28 seconds
Started Apr 25 01:09:58 PM PDT 24
Finished Apr 25 01:10:13 PM PDT 24
Peak memory 224456 kb
Host smart-bfcaddd1-a551-4dc2-8ab0-4d08a607cd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913835364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2913835364
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2979723856
Short name T99
Test name
Test status
Simulation time 25428181 ps
CPU time 1.32 seconds
Started Apr 25 12:39:15 PM PDT 24
Finished Apr 25 12:39:22 PM PDT 24
Peak memory 215984 kb
Host smart-cbc9e6cf-8fb5-420c-be4f-e0aee3f13a58
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979723856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2979723856
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1235887421
Short name T27
Test name
Test status
Simulation time 149687220 ps
CPU time 2.4 seconds
Started Apr 25 01:09:34 PM PDT 24
Finished Apr 25 01:09:39 PM PDT 24
Peak memory 218508 kb
Host smart-7ffb8419-16bb-412f-ac44-aa557fdc8791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235887421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1235887421
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1963624819
Short name T152
Test name
Test status
Simulation time 1161947511 ps
CPU time 6.08 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:10 PM PDT 24
Peak memory 222480 kb
Host smart-a987ed12-8c94-4ca3-8a94-82a04781bf47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1963624819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1963624819
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2659491372
Short name T155
Test name
Test status
Simulation time 3950151992 ps
CPU time 16.86 seconds
Started Apr 25 12:39:11 PM PDT 24
Finished Apr 25 12:39:33 PM PDT 24
Peak memory 215092 kb
Host smart-decb35d4-f07f-4900-aaef-1617803c2575
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659491372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2659491372
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2536478706
Short name T812
Test name
Test status
Simulation time 2821201957 ps
CPU time 39.28 seconds
Started Apr 25 12:39:07 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 206808 kb
Host smart-1fbb0175-ba95-4758-925c-d25e17273646
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536478706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2536478706
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4152946262
Short name T98
Test name
Test status
Simulation time 43528049 ps
CPU time 1.34 seconds
Started Apr 25 12:39:15 PM PDT 24
Finished Apr 25 12:39:22 PM PDT 24
Peak memory 206868 kb
Host smart-9b28c362-1587-47c8-aba2-c8d7b119299b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152946262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4152946262
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2003689645
Short name T124
Test name
Test status
Simulation time 125374074 ps
CPU time 3.57 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 216664 kb
Host smart-638ae32a-b94f-4e2d-aef5-f69b214d40db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003689645 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2003689645
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1694390880
Short name T766
Test name
Test status
Simulation time 392611854 ps
CPU time 1.35 seconds
Started Apr 25 12:39:05 PM PDT 24
Finished Apr 25 12:39:09 PM PDT 24
Peak memory 206928 kb
Host smart-18e857b4-e123-4e2a-bd53-d2f8df53ee94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694390880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
694390880
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.580818217
Short name T786
Test name
Test status
Simulation time 54849303 ps
CPU time 0.75 seconds
Started Apr 25 12:39:10 PM PDT 24
Finished Apr 25 12:39:14 PM PDT 24
Peak memory 203724 kb
Host smart-68ce15bb-7d31-4ed4-a10c-78bdae893f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580818217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.580818217
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3504618186
Short name T816
Test name
Test status
Simulation time 11602149 ps
CPU time 0.65 seconds
Started Apr 25 12:39:07 PM PDT 24
Finished Apr 25 12:39:10 PM PDT 24
Peak memory 203304 kb
Host smart-ddde6f78-c089-4c9e-94b7-64c6e7bc81ed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504618186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3504618186
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1476589292
Short name T146
Test name
Test status
Simulation time 186002292 ps
CPU time 3.82 seconds
Started Apr 25 12:39:14 PM PDT 24
Finished Apr 25 12:39:24 PM PDT 24
Peak memory 215028 kb
Host smart-e29ce309-ba54-4362-b52a-9635c18c4500
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476589292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1476589292
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3191687438
Short name T119
Test name
Test status
Simulation time 663608436 ps
CPU time 3.16 seconds
Started Apr 25 12:39:06 PM PDT 24
Finished Apr 25 12:39:12 PM PDT 24
Peak memory 215340 kb
Host smart-2eb58bfe-0d8f-492c-97f8-cdd52908d80d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191687438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
191687438
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1625960380
Short name T125
Test name
Test status
Simulation time 1599009751 ps
CPU time 24.19 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 215012 kb
Host smart-1fa806f5-68a9-493d-abd6-8fae2bb6ef50
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625960380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1625960380
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2451334887
Short name T752
Test name
Test status
Simulation time 46415508 ps
CPU time 1.63 seconds
Started Apr 25 12:39:10 PM PDT 24
Finished Apr 25 12:39:14 PM PDT 24
Peak memory 215108 kb
Host smart-717f689d-7f75-4480-810d-2d613dfc65a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451334887 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2451334887
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3005760109
Short name T737
Test name
Test status
Simulation time 54267895 ps
CPU time 1.83 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 215024 kb
Host smart-2a715986-5db4-4e4b-a55a-a07bce9af0dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005760109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
005760109
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3830686013
Short name T719
Test name
Test status
Simulation time 36051879 ps
CPU time 0.69 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 203816 kb
Host smart-e3e57037-442a-4522-92b6-b94d7b847cbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830686013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
830686013
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1230114668
Short name T793
Test name
Test status
Simulation time 135809323 ps
CPU time 1.32 seconds
Started Apr 25 12:39:10 PM PDT 24
Finished Apr 25 12:39:14 PM PDT 24
Peak memory 215136 kb
Host smart-be2747a1-9974-4997-9d3c-49a5590cb1b9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230114668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1230114668
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1075906052
Short name T762
Test name
Test status
Simulation time 23446164 ps
CPU time 0.64 seconds
Started Apr 25 12:39:35 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 203328 kb
Host smart-c956a7cb-455b-456c-9938-3bf44aa05863
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075906052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1075906052
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1619351537
Short name T746
Test name
Test status
Simulation time 158504698 ps
CPU time 3.74 seconds
Started Apr 25 12:39:10 PM PDT 24
Finished Apr 25 12:39:16 PM PDT 24
Peak memory 215048 kb
Host smart-224b1b8d-476b-4478-9407-12f3c66831d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619351537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1619351537
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1436111146
Short name T735
Test name
Test status
Simulation time 23976980 ps
CPU time 1.51 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 216216 kb
Host smart-87129451-5049-479c-8801-8cba9436e8b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436111146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
436111146
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3389603290
Short name T156
Test name
Test status
Simulation time 2250521481 ps
CPU time 24.23 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:43 PM PDT 24
Peak memory 223364 kb
Host smart-caad9582-76b4-405a-a5d1-8e37c454da07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389603290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3389603290
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.252449234
Short name T726
Test name
Test status
Simulation time 56592274 ps
CPU time 3.86 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 218240 kb
Host smart-1f464e08-90ae-4f29-a894-c8d5cca11b0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252449234 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.252449234
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3107495721
Short name T139
Test name
Test status
Simulation time 44559273 ps
CPU time 1.44 seconds
Started Apr 25 12:39:31 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 206956 kb
Host smart-ca7a80b0-232c-402e-966c-6e910eb2a8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107495721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3107495721
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2555879625
Short name T814
Test name
Test status
Simulation time 15911324 ps
CPU time 0.71 seconds
Started Apr 25 12:39:22 PM PDT 24
Finished Apr 25 12:39:27 PM PDT 24
Peak memory 203504 kb
Host smart-87037097-859e-44e6-b7ce-b1e49c89362f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555879625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2555879625
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3308766905
Short name T157
Test name
Test status
Simulation time 138095777 ps
CPU time 3.03 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 215064 kb
Host smart-a42540de-e1e2-4121-8d2c-b97c642b3bbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308766905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3308766905
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3054435575
Short name T122
Test name
Test status
Simulation time 47222733 ps
CPU time 2.99 seconds
Started Apr 25 12:39:25 PM PDT 24
Finished Apr 25 12:39:31 PM PDT 24
Peak memory 215296 kb
Host smart-91be1558-c047-4e94-8111-a7641bfeec00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054435575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3054435575
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2347395352
Short name T765
Test name
Test status
Simulation time 1901801936 ps
CPU time 8.04 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:42 PM PDT 24
Peak memory 215060 kb
Host smart-45e08a96-ea05-4cb2-ae37-43acab046e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347395352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2347395352
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2249341479
Short name T745
Test name
Test status
Simulation time 28624040 ps
CPU time 1.94 seconds
Started Apr 25 12:39:20 PM PDT 24
Finished Apr 25 12:39:27 PM PDT 24
Peak memory 215128 kb
Host smart-80ee8979-656b-4e59-adf9-9bb1e3a1ab68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249341479 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2249341479
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3735603700
Short name T763
Test name
Test status
Simulation time 51515794 ps
CPU time 1.44 seconds
Started Apr 25 12:39:35 PM PDT 24
Finished Apr 25 12:39:39 PM PDT 24
Peak memory 206916 kb
Host smart-3ed319e1-11b3-4b40-b949-2455eadc2c89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735603700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3735603700
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1622909401
Short name T777
Test name
Test status
Simulation time 55905414 ps
CPU time 0.76 seconds
Started Apr 25 12:39:31 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 203808 kb
Host smart-d2089042-5e27-498c-9967-3125ebc51843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622909401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1622909401
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3425146400
Short name T740
Test name
Test status
Simulation time 211108391 ps
CPU time 4.26 seconds
Started Apr 25 12:39:25 PM PDT 24
Finished Apr 25 12:39:32 PM PDT 24
Peak memory 215060 kb
Host smart-9ca25619-6217-4a86-97c2-f3e1ea112bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425146400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3425146400
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3363853133
Short name T108
Test name
Test status
Simulation time 569137796 ps
CPU time 3.18 seconds
Started Apr 25 12:39:23 PM PDT 24
Finished Apr 25 12:39:30 PM PDT 24
Peak memory 215208 kb
Host smart-b4d14b9a-5597-45a3-963c-a2382ab3cbc2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363853133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3363853133
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1394189757
Short name T109
Test name
Test status
Simulation time 321335152 ps
CPU time 1.79 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:31 PM PDT 24
Peak memory 215092 kb
Host smart-c8713156-0172-4a55-a1ee-8247990261d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394189757 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1394189757
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2629381735
Short name T831
Test name
Test status
Simulation time 117694795 ps
CPU time 1.88 seconds
Started Apr 25 12:39:39 PM PDT 24
Finished Apr 25 12:39:42 PM PDT 24
Peak memory 215048 kb
Host smart-dd69ed94-97f9-42f2-9423-a86d84b24105
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629381735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2629381735
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.698732648
Short name T729
Test name
Test status
Simulation time 18469916 ps
CPU time 0.68 seconds
Started Apr 25 12:39:31 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 203712 kb
Host smart-2547256d-7d17-49a3-99ec-4e271ac3c22b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698732648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.698732648
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.559639211
Short name T147
Test name
Test status
Simulation time 331875878 ps
CPU time 4.14 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 215044 kb
Host smart-630bf6e0-0e31-4f4c-8255-927e631680fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559639211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.559639211
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3724646000
Short name T823
Test name
Test status
Simulation time 129581209 ps
CPU time 3.4 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:34 PM PDT 24
Peak memory 215316 kb
Host smart-69a054b0-e7f1-42c8-9bef-56a7ed4e2253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724646000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3724646000
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.988909717
Short name T129
Test name
Test status
Simulation time 86344035 ps
CPU time 2.71 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 216732 kb
Host smart-e27303f9-2acd-4394-afe7-708e8b974b6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988909717 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.988909717
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2458739373
Short name T829
Test name
Test status
Simulation time 127072673 ps
CPU time 2.09 seconds
Started Apr 25 12:39:25 PM PDT 24
Finished Apr 25 12:39:30 PM PDT 24
Peak memory 215000 kb
Host smart-4b4d6b22-2086-4d7a-b1e0-bc3eedab50f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458739373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2458739373
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2376442579
Short name T736
Test name
Test status
Simulation time 14097032 ps
CPU time 0.7 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:33 PM PDT 24
Peak memory 203520 kb
Host smart-372dd36d-91d1-4763-918b-9d40375a2ea6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376442579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2376442579
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2715426588
Short name T144
Test name
Test status
Simulation time 511877711 ps
CPU time 2.9 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 214956 kb
Host smart-20678000-5373-4a61-9ffb-1b145ceb3224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715426588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2715426588
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3637326390
Short name T722
Test name
Test status
Simulation time 1215054742 ps
CPU time 7.6 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 214980 kb
Host smart-a2e2cde6-36ae-4e92-8f69-6f43dd2cbe4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637326390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3637326390
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3383753596
Short name T725
Test name
Test status
Simulation time 83483246 ps
CPU time 1.58 seconds
Started Apr 25 12:39:22 PM PDT 24
Finished Apr 25 12:39:27 PM PDT 24
Peak memory 215056 kb
Host smart-489b4874-b015-4082-bf82-a99e5c267db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383753596 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3383753596
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4120658896
Short name T784
Test name
Test status
Simulation time 75153192 ps
CPU time 2.44 seconds
Started Apr 25 12:39:26 PM PDT 24
Finished Apr 25 12:39:31 PM PDT 24
Peak memory 206864 kb
Host smart-4dec7b52-22df-44a7-9766-b7a7cd780f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120658896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4120658896
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3256650239
Short name T754
Test name
Test status
Simulation time 13446003 ps
CPU time 0.69 seconds
Started Apr 25 12:39:20 PM PDT 24
Finished Apr 25 12:39:26 PM PDT 24
Peak memory 203808 kb
Host smart-68768983-a53f-481b-bf72-8dfe29e6417a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256650239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3256650239
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3397751775
Short name T796
Test name
Test status
Simulation time 1894005459 ps
CPU time 4.32 seconds
Started Apr 25 12:39:33 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 215020 kb
Host smart-22642b16-ccab-4245-9f48-c48c64f64d6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397751775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3397751775
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.332559615
Short name T117
Test name
Test status
Simulation time 35684246 ps
CPU time 2.15 seconds
Started Apr 25 12:39:44 PM PDT 24
Finished Apr 25 12:39:46 PM PDT 24
Peak memory 215176 kb
Host smart-072c2fcc-69a4-4d73-bc6f-889ae8b4e5ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332559615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.332559615
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3154893443
Short name T360
Test name
Test status
Simulation time 925939603 ps
CPU time 20.78 seconds
Started Apr 25 12:39:26 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 215092 kb
Host smart-aae7f1f0-bf4b-487a-84f8-7782c9c716fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154893443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3154893443
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2491806983
Short name T744
Test name
Test status
Simulation time 113242392 ps
CPU time 3.33 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 216124 kb
Host smart-7d31c62a-60cd-45ce-b37d-233d9bca8823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491806983 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2491806983
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.627180361
Short name T787
Test name
Test status
Simulation time 146809348 ps
CPU time 1.36 seconds
Started Apr 25 12:39:26 PM PDT 24
Finished Apr 25 12:39:30 PM PDT 24
Peak memory 214952 kb
Host smart-7f48f54b-c291-4a63-a263-e13cbf58c4aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627180361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.627180361
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1654247949
Short name T738
Test name
Test status
Simulation time 10733731 ps
CPU time 0.73 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:34 PM PDT 24
Peak memory 203440 kb
Host smart-52bc2f92-da46-4fcb-84fb-225791254abe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654247949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1654247949
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2469957357
Short name T782
Test name
Test status
Simulation time 131013686 ps
CPU time 2.95 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 215096 kb
Host smart-7e262d51-8992-468f-aef7-c3014f2040d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469957357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2469957357
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3105965300
Short name T362
Test name
Test status
Simulation time 110967461 ps
CPU time 6.2 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:40 PM PDT 24
Peak memory 215092 kb
Host smart-2c5e6b36-d04d-4e0d-9c09-610af1bf59f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105965300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3105965300
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1324870311
Short name T126
Test name
Test status
Simulation time 141647172 ps
CPU time 2.68 seconds
Started Apr 25 12:39:25 PM PDT 24
Finished Apr 25 12:39:30 PM PDT 24
Peak memory 216216 kb
Host smart-6042094f-f6c4-4256-a77f-8b8ce1acca77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324870311 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1324870311
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1874254736
Short name T142
Test name
Test status
Simulation time 74151855 ps
CPU time 1.29 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:52 PM PDT 24
Peak memory 206892 kb
Host smart-833f857a-7dcd-4553-a29b-3875b7408d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874254736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1874254736
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.108679760
Short name T792
Test name
Test status
Simulation time 43196579 ps
CPU time 0.75 seconds
Started Apr 25 12:39:46 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 203448 kb
Host smart-86733fca-27ee-4c73-b852-09aca6ecd36d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108679760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.108679760
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3769029069
Short name T38
Test name
Test status
Simulation time 50650229 ps
CPU time 1.74 seconds
Started Apr 25 12:39:35 PM PDT 24
Finished Apr 25 12:39:39 PM PDT 24
Peak memory 215008 kb
Host smart-e83131c5-aa8e-47cc-b9f9-116d31f85c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769029069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3769029069
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2128719876
Short name T775
Test name
Test status
Simulation time 48476174 ps
CPU time 1.55 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:31 PM PDT 24
Peak memory 215188 kb
Host smart-e6d102e2-edcc-4380-8738-6fffd0af03d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128719876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2128719876
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1197414842
Short name T819
Test name
Test status
Simulation time 47912135 ps
CPU time 1.64 seconds
Started Apr 25 12:39:22 PM PDT 24
Finished Apr 25 12:39:28 PM PDT 24
Peak memory 216088 kb
Host smart-479c1985-4a0d-4add-8bc7-e0c13b2ba6d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197414842 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1197414842
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3484130579
Short name T149
Test name
Test status
Simulation time 168270151 ps
CPU time 2.57 seconds
Started Apr 25 12:39:20 PM PDT 24
Finished Apr 25 12:39:27 PM PDT 24
Peak memory 215012 kb
Host smart-0334c0d0-e99a-455f-84bb-91d3fc20b9e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484130579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3484130579
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1004047723
Short name T781
Test name
Test status
Simulation time 15932396 ps
CPU time 0.75 seconds
Started Apr 25 12:39:35 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 203484 kb
Host smart-45217666-70c0-43fb-92a2-d0b4eea3ddae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004047723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1004047723
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2759530931
Short name T148
Test name
Test status
Simulation time 81457746 ps
CPU time 2.64 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:32 PM PDT 24
Peak memory 215052 kb
Host smart-db1eed11-defb-4f7d-b1a8-e14872ca85bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759530931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2759530931
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.220525594
Short name T827
Test name
Test status
Simulation time 30371310 ps
CPU time 1.86 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 215340 kb
Host smart-1b252e4a-9998-4c65-bb85-1eb1b27e8c38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220525594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.220525594
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3640996910
Short name T358
Test name
Test status
Simulation time 818814514 ps
CPU time 21.34 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:55 PM PDT 24
Peak memory 215204 kb
Host smart-7fc0eedb-f9c1-4c2c-af88-2cea504d5d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640996910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3640996910
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2311687998
Short name T799
Test name
Test status
Simulation time 111587269 ps
CPU time 2.76 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 217260 kb
Host smart-cc50fd81-7e9c-4e5a-a5dd-bfd49b21a63d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311687998 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2311687998
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.715065081
Short name T741
Test name
Test status
Simulation time 85724246 ps
CPU time 2.65 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 214976 kb
Host smart-40aa1048-d57e-4b31-bd4e-1b1208e837c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715065081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.715065081
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.691150410
Short name T756
Test name
Test status
Simulation time 18139776 ps
CPU time 0.71 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:34 PM PDT 24
Peak memory 203416 kb
Host smart-fe218a2a-3eac-4cd5-806d-9d71fde512de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691150410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.691150410
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.860537190
Short name T747
Test name
Test status
Simulation time 170951304 ps
CPU time 2.88 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:33 PM PDT 24
Peak memory 215040 kb
Host smart-581f8511-ab42-46c9-be60-665da253d9b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860537190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.860537190
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3557467912
Short name T121
Test name
Test status
Simulation time 700409483 ps
CPU time 4.65 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 215144 kb
Host smart-fb50c90d-122e-4ea9-8f8c-74c834381a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557467912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3557467912
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3641108118
Short name T364
Test name
Test status
Simulation time 15752376770 ps
CPU time 21.17 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:52 PM PDT 24
Peak memory 215456 kb
Host smart-a9467588-3e0b-4ba7-9be5-e5d86e2c0734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641108118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3641108118
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2169134618
Short name T794
Test name
Test status
Simulation time 178961109 ps
CPU time 2.86 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 216736 kb
Host smart-86c6b785-a54f-46f7-86af-71be65620f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169134618 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2169134618
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.711239315
Short name T141
Test name
Test status
Simulation time 386032260 ps
CPU time 2.58 seconds
Started Apr 25 12:39:37 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 215064 kb
Host smart-dc06e6a5-c5a8-49eb-9d36-fd3fe0f42e4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711239315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.711239315
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.877830436
Short name T790
Test name
Test status
Simulation time 67586705 ps
CPU time 0.76 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:34 PM PDT 24
Peak memory 203352 kb
Host smart-ebcd031c-eebd-42a2-9812-dbba5e1437d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877830436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.877830436
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.708239496
Short name T150
Test name
Test status
Simulation time 27501998 ps
CPU time 1.74 seconds
Started Apr 25 12:39:35 PM PDT 24
Finished Apr 25 12:39:39 PM PDT 24
Peak memory 206896 kb
Host smart-a97d410d-f1fa-4457-98cb-02aec85102b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708239496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.708239496
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4191111444
Short name T37
Test name
Test status
Simulation time 653164801 ps
CPU time 3.44 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 215108 kb
Host smart-f54d3c2a-7906-4c35-b6e7-c1fb7aae4dbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191111444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4191111444
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3371482601
Short name T359
Test name
Test status
Simulation time 408527165 ps
CPU time 13.1 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:47 PM PDT 24
Peak memory 215080 kb
Host smart-edaa8f64-71a2-4430-8a62-5f8eaed9f3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371482601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3371482601
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3608025525
Short name T132
Test name
Test status
Simulation time 1224988972 ps
CPU time 24.77 seconds
Started Apr 25 12:39:25 PM PDT 24
Finished Apr 25 12:39:53 PM PDT 24
Peak memory 215096 kb
Host smart-077435e7-224b-46ee-8c41-4ea47a8ece39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608025525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3608025525
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.681309990
Short name T137
Test name
Test status
Simulation time 1935659466 ps
CPU time 34.68 seconds
Started Apr 25 12:39:15 PM PDT 24
Finished Apr 25 12:39:56 PM PDT 24
Peak memory 206884 kb
Host smart-05dd9cd5-19f1-4d42-8601-89063731cefa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681309990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.681309990
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.271952865
Short name T97
Test name
Test status
Simulation time 31327030 ps
CPU time 1.17 seconds
Started Apr 25 12:39:11 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 206604 kb
Host smart-3aab1e2d-2b4a-4e74-842a-19037c178c20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271952865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.271952865
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.488034949
Short name T769
Test name
Test status
Simulation time 28275438 ps
CPU time 1.62 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 215064 kb
Host smart-0b3a063f-3807-4388-844f-0fbc0a214d30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488034949 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.488034949
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1274551741
Short name T801
Test name
Test status
Simulation time 199315691 ps
CPU time 2.59 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 215044 kb
Host smart-329eb52a-bfb2-40d3-8f46-8c7ae9ede404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274551741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
274551741
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1994713959
Short name T714
Test name
Test status
Simulation time 45414449 ps
CPU time 0.66 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 203744 kb
Host smart-7e8abc2b-cc49-4f47-ae65-751bb97ce1cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994713959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
994713959
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.268421052
Short name T797
Test name
Test status
Simulation time 41154992 ps
CPU time 1.59 seconds
Started Apr 25 12:39:14 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 215132 kb
Host smart-42fc2eae-040c-46a9-905c-bc3f670ca087
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268421052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.268421052
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4249090970
Short name T789
Test name
Test status
Simulation time 10749114 ps
CPU time 0.66 seconds
Started Apr 25 12:39:17 PM PDT 24
Finished Apr 25 12:39:23 PM PDT 24
Peak memory 203624 kb
Host smart-0abd5c3a-6f30-4e1f-aceb-6ff2f2fe20e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249090970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4249090970
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1909023947
Short name T805
Test name
Test status
Simulation time 1504799098 ps
CPU time 4.1 seconds
Started Apr 25 12:39:37 PM PDT 24
Finished Apr 25 12:39:42 PM PDT 24
Peak memory 215140 kb
Host smart-241d424c-a30c-4896-b1b2-6444b5febff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909023947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1909023947
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.753757560
Short name T783
Test name
Test status
Simulation time 92900727 ps
CPU time 1.64 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:20 PM PDT 24
Peak memory 215156 kb
Host smart-4bb01fca-97b1-4aa5-b40d-95d9b8a22df6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753757560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.753757560
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1149226403
Short name T767
Test name
Test status
Simulation time 1348206673 ps
CPU time 18.83 seconds
Started Apr 25 12:39:11 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 215336 kb
Host smart-573856c5-bee4-4d29-8ea2-0e90f81873ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149226403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1149226403
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.518206263
Short name T749
Test name
Test status
Simulation time 111302715 ps
CPU time 0.75 seconds
Started Apr 25 12:39:33 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 203516 kb
Host smart-84f5007a-2cab-4d8f-90b8-1b45fb8dab58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518206263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.518206263
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4008107109
Short name T720
Test name
Test status
Simulation time 45139519 ps
CPU time 0.68 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:32 PM PDT 24
Peak memory 203744 kb
Host smart-b5626637-e5d8-419d-a43d-39bff365c9bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008107109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4008107109
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4214224012
Short name T768
Test name
Test status
Simulation time 51774445 ps
CPU time 0.75 seconds
Started Apr 25 12:39:26 PM PDT 24
Finished Apr 25 12:39:29 PM PDT 24
Peak memory 203740 kb
Host smart-e9e92852-f945-406a-994d-5c650b47ddfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214224012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4214224012
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2412650396
Short name T791
Test name
Test status
Simulation time 34873915 ps
CPU time 0.79 seconds
Started Apr 25 12:39:36 PM PDT 24
Finished Apr 25 12:39:39 PM PDT 24
Peak memory 203500 kb
Host smart-7e2c574f-05f3-48d0-8541-0ab9720f74fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412650396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2412650396
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.49629538
Short name T727
Test name
Test status
Simulation time 69435881 ps
CPU time 0.78 seconds
Started Apr 25 12:39:33 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 203392 kb
Host smart-da7878e1-4ffe-4cb8-a64d-916ac4350b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49629538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.49629538
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2856459323
Short name T733
Test name
Test status
Simulation time 31199742 ps
CPU time 0.79 seconds
Started Apr 25 12:39:37 PM PDT 24
Finished Apr 25 12:39:39 PM PDT 24
Peak memory 203800 kb
Host smart-e588f32d-7d49-4e23-b80f-e5389181607c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856459323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2856459323
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1467549550
Short name T743
Test name
Test status
Simulation time 20175966 ps
CPU time 0.8 seconds
Started Apr 25 12:39:35 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 203440 kb
Host smart-b75d70a5-2e19-45fa-8423-7c02bc88acd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467549550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1467549550
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3570016733
Short name T758
Test name
Test status
Simulation time 16611383 ps
CPU time 0.73 seconds
Started Apr 25 12:39:51 PM PDT 24
Finished Apr 25 12:39:54 PM PDT 24
Peak memory 203468 kb
Host smart-d2b3dd79-b040-4c9a-9f84-2bc2e6d10dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570016733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3570016733
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.211477514
Short name T772
Test name
Test status
Simulation time 34170345 ps
CPU time 0.78 seconds
Started Apr 25 12:39:26 PM PDT 24
Finished Apr 25 12:39:29 PM PDT 24
Peak memory 203820 kb
Host smart-a702bf1e-04af-4075-8da1-77145b476176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211477514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.211477514
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.737980049
Short name T748
Test name
Test status
Simulation time 52091615 ps
CPU time 0.75 seconds
Started Apr 25 12:39:31 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 203440 kb
Host smart-9b4fd98b-90f4-4cd3-a715-fae69a0e621d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737980049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.737980049
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1592379714
Short name T143
Test name
Test status
Simulation time 1501591157 ps
CPU time 21.37 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:50 PM PDT 24
Peak memory 215132 kb
Host smart-d0f79acc-cddf-4981-9ca7-26872b50e3b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592379714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1592379714
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1558850196
Short name T806
Test name
Test status
Simulation time 912602861 ps
CPU time 14.17 seconds
Started Apr 25 12:39:17 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 206800 kb
Host smart-f860ace8-7fd5-451f-84b7-b04a435653b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558850196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1558850196
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1880972863
Short name T828
Test name
Test status
Simulation time 71569751 ps
CPU time 1.01 seconds
Started Apr 25 12:39:08 PM PDT 24
Finished Apr 25 12:39:12 PM PDT 24
Peak memory 206688 kb
Host smart-4a2b8d90-2ed9-414f-a052-f3836ea540e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880972863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1880972863
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1966092777
Short name T826
Test name
Test status
Simulation time 153577158 ps
CPU time 3.56 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:22 PM PDT 24
Peak memory 216508 kb
Host smart-053c290d-e718-440d-aee9-61e25bd81c6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966092777 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1966092777
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2227021983
Short name T761
Test name
Test status
Simulation time 40076062 ps
CPU time 1.28 seconds
Started Apr 25 12:39:08 PM PDT 24
Finished Apr 25 12:39:11 PM PDT 24
Peak memory 215076 kb
Host smart-bbe63707-15fc-476c-8e7d-9df6ac991372
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227021983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
227021983
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3009780019
Short name T724
Test name
Test status
Simulation time 29420933 ps
CPU time 0.69 seconds
Started Apr 25 12:39:17 PM PDT 24
Finished Apr 25 12:39:24 PM PDT 24
Peak memory 203764 kb
Host smart-a8ed95c2-e78e-41e7-a92f-43e44ce30287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009780019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
009780019
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.664807205
Short name T802
Test name
Test status
Simulation time 22957186 ps
CPU time 1.59 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:32 PM PDT 24
Peak memory 215184 kb
Host smart-b2ba5d91-4cd2-4d81-b7df-778c294327e9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664807205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.664807205
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1313211120
Short name T742
Test name
Test status
Simulation time 16947575 ps
CPU time 0.67 seconds
Started Apr 25 12:39:45 PM PDT 24
Finished Apr 25 12:39:47 PM PDT 24
Peak memory 203720 kb
Host smart-5f76c3f0-019f-4d5d-afb5-6571c25a2da1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313211120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1313211120
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4024845977
Short name T760
Test name
Test status
Simulation time 516478648 ps
CPU time 3.85 seconds
Started Apr 25 12:39:09 PM PDT 24
Finished Apr 25 12:39:15 PM PDT 24
Peak memory 215112 kb
Host smart-d8e547b2-a0fa-45dc-93c1-80e72e24f720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024845977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4024845977
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.986797909
Short name T773
Test name
Test status
Simulation time 103473055 ps
CPU time 1.85 seconds
Started Apr 25 12:39:10 PM PDT 24
Finished Apr 25 12:39:15 PM PDT 24
Peak memory 215240 kb
Host smart-78920f9c-3781-44cf-a687-1f43a8d9c85a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986797909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.986797909
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.334932860
Short name T127
Test name
Test status
Simulation time 312907258 ps
CPU time 19.29 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 215080 kb
Host smart-554ae454-35d7-4426-9ef3-fe54adedf255
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334932860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.334932860
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2306061789
Short name T815
Test name
Test status
Simulation time 19387581 ps
CPU time 0.76 seconds
Started Apr 25 12:39:42 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 203424 kb
Host smart-dd663257-d400-4328-8403-228a0509b043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306061789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2306061789
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3556796965
Short name T718
Test name
Test status
Simulation time 20768108 ps
CPU time 0.68 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 203420 kb
Host smart-1b716ff2-d3f4-4fa6-b908-9526b7cba6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556796965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3556796965
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2265508522
Short name T717
Test name
Test status
Simulation time 39328774 ps
CPU time 0.69 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 203740 kb
Host smart-03f21d94-f9b8-4753-83ce-96cbc052b22e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265508522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2265508522
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2074850012
Short name T778
Test name
Test status
Simulation time 63156752 ps
CPU time 0.73 seconds
Started Apr 25 12:39:35 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 203504 kb
Host smart-a2f84219-e446-4787-9299-2ac62a48d346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074850012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2074850012
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3738309786
Short name T715
Test name
Test status
Simulation time 12636005 ps
CPU time 0.71 seconds
Started Apr 25 12:39:44 PM PDT 24
Finished Apr 25 12:39:45 PM PDT 24
Peak memory 203436 kb
Host smart-a071455f-479c-471c-9808-626446a16abd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738309786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3738309786
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2884043705
Short name T807
Test name
Test status
Simulation time 14103669 ps
CPU time 0.68 seconds
Started Apr 25 12:39:42 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 203828 kb
Host smart-3a3c3686-ee61-4e38-bb34-5d797ea50688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884043705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2884043705
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1183626493
Short name T723
Test name
Test status
Simulation time 25925105 ps
CPU time 0.72 seconds
Started Apr 25 12:39:40 PM PDT 24
Finished Apr 25 12:39:43 PM PDT 24
Peak memory 203428 kb
Host smart-feb3eb32-f4a0-4761-ba35-ef018dc1c8b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183626493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1183626493
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.404822092
Short name T750
Test name
Test status
Simulation time 100226768 ps
CPU time 0.72 seconds
Started Apr 25 12:39:38 PM PDT 24
Finished Apr 25 12:39:40 PM PDT 24
Peak memory 203800 kb
Host smart-177fcaf1-4a16-439b-8d04-51b09208d617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404822092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.404822092
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3737516614
Short name T811
Test name
Test status
Simulation time 37073109 ps
CPU time 0.67 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 203720 kb
Host smart-c7ddd0db-f327-4e73-8919-a2d0d8ed5ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737516614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3737516614
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3789679107
Short name T820
Test name
Test status
Simulation time 11564867 ps
CPU time 0.7 seconds
Started Apr 25 12:39:48 PM PDT 24
Finished Apr 25 12:39:51 PM PDT 24
Peak memory 203440 kb
Host smart-12032944-94ee-4caa-97c3-bd9f5e7ed178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789679107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3789679107
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.221687063
Short name T134
Test name
Test status
Simulation time 2444965027 ps
CPU time 14.43 seconds
Started Apr 25 12:39:18 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 215088 kb
Host smart-0955d32f-42fb-4e27-a517-6a2b875a3194
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221687063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.221687063
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2576487565
Short name T133
Test name
Test status
Simulation time 1866670249 ps
CPU time 27.21 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 206776 kb
Host smart-d941bc43-2cf5-4dd4-82d4-cf8f1d26c7f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576487565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2576487565
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2745528371
Short name T100
Test name
Test status
Simulation time 23658522 ps
CPU time 0.98 seconds
Started Apr 25 12:39:11 PM PDT 24
Finished Apr 25 12:39:16 PM PDT 24
Peak memory 206688 kb
Host smart-29fe607f-e878-4e81-8336-a9fe98c427bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745528371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2745528371
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2637923639
Short name T776
Test name
Test status
Simulation time 45028630 ps
CPU time 1.5 seconds
Started Apr 25 12:39:26 PM PDT 24
Finished Apr 25 12:39:30 PM PDT 24
Peak memory 215120 kb
Host smart-2f0d7a66-8443-4465-b5a4-7bba0ce75b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637923639 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2637923639
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.539262073
Short name T825
Test name
Test status
Simulation time 376416137 ps
CPU time 2.58 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 206836 kb
Host smart-3ae75dd6-ea4b-42bb-b795-8254d0202aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539262073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.539262073
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.950920238
Short name T771
Test name
Test status
Simulation time 16391606 ps
CPU time 0.71 seconds
Started Apr 25 12:39:20 PM PDT 24
Finished Apr 25 12:39:25 PM PDT 24
Peak memory 203504 kb
Host smart-2ff53ea6-9fa9-4697-bb51-e3cf84c73abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950920238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.950920238
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.648569325
Short name T810
Test name
Test status
Simulation time 30516700 ps
CPU time 2.08 seconds
Started Apr 25 12:39:22 PM PDT 24
Finished Apr 25 12:39:28 PM PDT 24
Peak memory 215160 kb
Host smart-0203f06d-4837-4303-8a47-d62bd1798c81
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648569325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.648569325
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2990078352
Short name T821
Test name
Test status
Simulation time 17214212 ps
CPU time 0.65 seconds
Started Apr 25 12:39:22 PM PDT 24
Finished Apr 25 12:39:26 PM PDT 24
Peak memory 203644 kb
Host smart-b794e642-6e6c-41c3-a019-745c9d6e25cb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990078352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2990078352
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1585500153
Short name T757
Test name
Test status
Simulation time 334302444 ps
CPU time 1.84 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 215104 kb
Host smart-bf26a32e-f138-4855-8c2a-7ed5703264db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585500153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1585500153
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2347551805
Short name T822
Test name
Test status
Simulation time 1330223967 ps
CPU time 6.23 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:23 PM PDT 24
Peak memory 215172 kb
Host smart-c88c692e-648b-4144-bec7-c7299575e5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347551805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
347551805
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2117710748
Short name T751
Test name
Test status
Simulation time 46548498 ps
CPU time 0.72 seconds
Started Apr 25 12:39:38 PM PDT 24
Finished Apr 25 12:39:40 PM PDT 24
Peak memory 203516 kb
Host smart-6dc98993-ada2-428f-b50c-49e9ed5f809f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117710748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2117710748
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1251698945
Short name T817
Test name
Test status
Simulation time 13188414 ps
CPU time 0.71 seconds
Started Apr 25 12:39:43 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 203416 kb
Host smart-27f94f1e-1a72-422e-91b0-8b20c0ef17a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251698945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1251698945
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3971206279
Short name T808
Test name
Test status
Simulation time 13368739 ps
CPU time 0.68 seconds
Started Apr 25 12:39:41 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 203756 kb
Host smart-70eb978a-ad3d-430c-82ef-723f8b99db49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971206279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3971206279
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1852193886
Short name T759
Test name
Test status
Simulation time 25072248 ps
CPU time 0.68 seconds
Started Apr 25 12:39:36 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 203656 kb
Host smart-e05a2905-98e4-4784-a05b-f1f6246aaf88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852193886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1852193886
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1968202899
Short name T800
Test name
Test status
Simulation time 16198768 ps
CPU time 0.76 seconds
Started Apr 25 12:39:39 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 203472 kb
Host smart-4f4d6da9-9c55-4910-a990-dec95953236e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968202899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1968202899
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.547132222
Short name T716
Test name
Test status
Simulation time 12144633 ps
CPU time 0.71 seconds
Started Apr 25 12:39:33 PM PDT 24
Finished Apr 25 12:39:37 PM PDT 24
Peak memory 203812 kb
Host smart-a07d89c6-af55-4569-9320-6c26969ec1c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547132222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.547132222
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1762417049
Short name T785
Test name
Test status
Simulation time 39915878 ps
CPU time 0.73 seconds
Started Apr 25 12:39:40 PM PDT 24
Finished Apr 25 12:39:42 PM PDT 24
Peak memory 203756 kb
Host smart-9116d6aa-2a75-42b7-ace8-c68b3985b650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762417049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1762417049
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1346277331
Short name T809
Test name
Test status
Simulation time 27913200 ps
CPU time 0.75 seconds
Started Apr 25 12:39:40 PM PDT 24
Finished Apr 25 12:39:42 PM PDT 24
Peak memory 203836 kb
Host smart-d2bfd9a1-db51-4aa9-80ee-209d02fdf52d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346277331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1346277331
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.332022260
Short name T770
Test name
Test status
Simulation time 49449720 ps
CPU time 0.73 seconds
Started Apr 25 12:39:50 PM PDT 24
Finished Apr 25 12:39:52 PM PDT 24
Peak memory 203432 kb
Host smart-b0694f8b-57db-4428-890c-8adee177c452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332022260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.332022260
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1986788477
Short name T732
Test name
Test status
Simulation time 11260136 ps
CPU time 0.83 seconds
Started Apr 25 12:39:42 PM PDT 24
Finished Apr 25 12:39:44 PM PDT 24
Peak memory 203516 kb
Host smart-3dc1769a-5524-471d-9030-d26e3f702af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986788477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1986788477
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4118745902
Short name T739
Test name
Test status
Simulation time 209318311 ps
CPU time 3.54 seconds
Started Apr 25 12:39:11 PM PDT 24
Finished Apr 25 12:39:20 PM PDT 24
Peak memory 218272 kb
Host smart-3752d3ca-b4e2-4222-8fc7-aea23f1047a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118745902 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4118745902
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1506903171
Short name T795
Test name
Test status
Simulation time 154422214 ps
CPU time 1.38 seconds
Started Apr 25 12:39:06 PM PDT 24
Finished Apr 25 12:39:10 PM PDT 24
Peak memory 206908 kb
Host smart-95149e29-b00e-468f-b2cb-cdf33f319a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506903171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
506903171
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2587891501
Short name T721
Test name
Test status
Simulation time 52204169 ps
CPU time 0.76 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 203428 kb
Host smart-9df3e25a-3652-4f9d-b872-377003a25c20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587891501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
587891501
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1537706828
Short name T780
Test name
Test status
Simulation time 63633387 ps
CPU time 4.06 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:23 PM PDT 24
Peak memory 215032 kb
Host smart-c5dbcb3a-2745-4fb8-8033-534ccbb72cf8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537706828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1537706828
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1373171512
Short name T118
Test name
Test status
Simulation time 77144541 ps
CPU time 2.34 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 215224 kb
Host smart-3143b8e9-4d50-4f8d-bba3-37d8ce3eeac2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373171512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
373171512
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1394381953
Short name T114
Test name
Test status
Simulation time 3668075859 ps
CPU time 11.82 seconds
Started Apr 25 12:39:15 PM PDT 24
Finished Apr 25 12:39:33 PM PDT 24
Peak memory 216252 kb
Host smart-6f50c1dd-ee55-451f-a3bc-ca3457ee0d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394381953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1394381953
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3805591268
Short name T803
Test name
Test status
Simulation time 964065265 ps
CPU time 3.63 seconds
Started Apr 25 12:39:19 PM PDT 24
Finished Apr 25 12:39:28 PM PDT 24
Peak memory 217664 kb
Host smart-e8ad7c9c-a191-43cd-b13a-1749c9cc88c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805591268 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3805591268
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3536764948
Short name T138
Test name
Test status
Simulation time 145588157 ps
CPU time 2.49 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:20 PM PDT 24
Peak memory 214996 kb
Host smart-3c966a12-14c5-4fa9-a25d-f2ee6ec6bd90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536764948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
536764948
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.582110379
Short name T798
Test name
Test status
Simulation time 16595996 ps
CPU time 0.79 seconds
Started Apr 25 12:39:09 PM PDT 24
Finished Apr 25 12:39:12 PM PDT 24
Peak memory 203500 kb
Host smart-f3af5088-3683-4193-8c1d-5b723ae84373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582110379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.582110379
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3630509321
Short name T824
Test name
Test status
Simulation time 119848364 ps
CPU time 3.6 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:33 PM PDT 24
Peak memory 215052 kb
Host smart-da39b033-5489-4a0b-b205-c6948680ae27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630509321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3630509321
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2110992364
Short name T120
Test name
Test status
Simulation time 118215990 ps
CPU time 3.32 seconds
Started Apr 25 12:39:11 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 215360 kb
Host smart-8d9b5e07-b7f7-4093-81c5-099fd62dce23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110992364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
110992364
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.933193770
Short name T36
Test name
Test status
Simulation time 2203326179 ps
CPU time 13.83 seconds
Started Apr 25 12:39:16 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 215564 kb
Host smart-efd52724-978c-47ae-aac0-5540a05fda9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933193770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.933193770
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3100356112
Short name T731
Test name
Test status
Simulation time 40243096 ps
CPU time 2.41 seconds
Started Apr 25 12:39:17 PM PDT 24
Finished Apr 25 12:39:26 PM PDT 24
Peak memory 216080 kb
Host smart-33892f0b-45b0-42aa-b316-46e15166d0fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100356112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3100356112
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.599433616
Short name T140
Test name
Test status
Simulation time 451268985 ps
CPU time 2.7 seconds
Started Apr 25 12:39:22 PM PDT 24
Finished Apr 25 12:39:29 PM PDT 24
Peak memory 215036 kb
Host smart-1dbdaa9e-e91b-4570-80b4-f87031a9bf7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599433616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.599433616
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.149299843
Short name T728
Test name
Test status
Simulation time 80425382 ps
CPU time 0.73 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 203532 kb
Host smart-479b163b-92b3-400c-ab90-969b05bf7bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149299843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.149299843
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1969671835
Short name T774
Test name
Test status
Simulation time 157186291 ps
CPU time 2.62 seconds
Started Apr 25 12:39:13 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 215088 kb
Host smart-389709e1-063d-4620-8763-9203be5e6f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969671835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1969671835
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3285255207
Short name T755
Test name
Test status
Simulation time 55178916 ps
CPU time 1.73 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:19 PM PDT 24
Peak memory 215124 kb
Host smart-6eb6eee9-b64a-4fc4-b6cd-733fe5545410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285255207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
285255207
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3977099438
Short name T361
Test name
Test status
Simulation time 217885199 ps
CPU time 6.86 seconds
Started Apr 25 12:39:11 PM PDT 24
Finished Apr 25 12:39:21 PM PDT 24
Peak memory 214980 kb
Host smart-d1749a17-a085-489e-8f83-bce781f01eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977099438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3977099438
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1937649211
Short name T779
Test name
Test status
Simulation time 87464932 ps
CPU time 2.45 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:36 PM PDT 24
Peak memory 217164 kb
Host smart-c3578350-5c82-47ab-ab60-87a6f5c0af09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937649211 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1937649211
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1006810833
Short name T753
Test name
Test status
Simulation time 382906131 ps
CPU time 2.77 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:20 PM PDT 24
Peak memory 215056 kb
Host smart-55de27e6-de9e-4e35-bca3-09b2a052a43f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006810833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
006810833
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2994607717
Short name T161
Test name
Test status
Simulation time 15151098 ps
CPU time 0.71 seconds
Started Apr 25 12:39:12 PM PDT 24
Finished Apr 25 12:39:18 PM PDT 24
Peak memory 203464 kb
Host smart-b6b3ccd5-168c-4876-9e01-0dd86b8a559e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994607717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
994607717
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3920525955
Short name T734
Test name
Test status
Simulation time 393170306 ps
CPU time 3.71 seconds
Started Apr 25 12:39:10 PM PDT 24
Finished Apr 25 12:39:16 PM PDT 24
Peak memory 215136 kb
Host smart-cd3e65c2-db98-4833-9b71-9f865fc59af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920525955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3920525955
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.224597162
Short name T764
Test name
Test status
Simulation time 469092453 ps
CPU time 3.28 seconds
Started Apr 25 12:39:27 PM PDT 24
Finished Apr 25 12:39:33 PM PDT 24
Peak memory 215240 kb
Host smart-2dc3005e-a320-41f9-90c5-bdd957d3441d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224597162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.224597162
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.463992718
Short name T365
Test name
Test status
Simulation time 287772765 ps
CPU time 18.11 seconds
Started Apr 25 12:39:17 PM PDT 24
Finished Apr 25 12:39:41 PM PDT 24
Peak memory 215040 kb
Host smart-a4ea7c9d-cb65-477f-bc26-e8369661ae01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463992718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.463992718
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2883768043
Short name T730
Test name
Test status
Simulation time 137509308 ps
CPU time 3.91 seconds
Started Apr 25 12:39:24 PM PDT 24
Finished Apr 25 12:39:31 PM PDT 24
Peak memory 217624 kb
Host smart-4189f92c-c399-47ed-9749-d6aebc25dd3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883768043 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2883768043
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.953183128
Short name T818
Test name
Test status
Simulation time 65690766 ps
CPU time 1.76 seconds
Started Apr 25 12:39:28 PM PDT 24
Finished Apr 25 12:39:34 PM PDT 24
Peak memory 206780 kb
Host smart-ff0def10-3ebc-4893-82fe-a197121068ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953183128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.953183128
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2516930677
Short name T830
Test name
Test status
Simulation time 14842978 ps
CPU time 0.76 seconds
Started Apr 25 12:39:39 PM PDT 24
Finished Apr 25 12:39:40 PM PDT 24
Peak memory 203480 kb
Host smart-d5f2b6a1-b8c6-4fb0-ae19-2d436340e3be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516930677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
516930677
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2609697254
Short name T145
Test name
Test status
Simulation time 398672599 ps
CPU time 3.88 seconds
Started Apr 25 12:39:30 PM PDT 24
Finished Apr 25 12:39:38 PM PDT 24
Peak memory 215004 kb
Host smart-3a7c00c6-b336-42e8-bbbe-9a6c1c388d76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609697254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2609697254
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1890811746
Short name T123
Test name
Test status
Simulation time 86208837 ps
CPU time 1.73 seconds
Started Apr 25 12:39:29 PM PDT 24
Finished Apr 25 12:39:35 PM PDT 24
Peak memory 215228 kb
Host smart-ee42059a-9753-43b6-bf73-be88e7b3a09e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890811746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
890811746
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3665514665
Short name T804
Test name
Test status
Simulation time 269406910 ps
CPU time 7.27 seconds
Started Apr 25 12:39:41 PM PDT 24
Finished Apr 25 12:39:49 PM PDT 24
Peak memory 215168 kb
Host smart-9d16698e-a534-452a-9801-75e11f06f0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665514665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3665514665
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2991646247
Short name T468
Test name
Test status
Simulation time 13196753 ps
CPU time 0.72 seconds
Started Apr 25 01:09:32 PM PDT 24
Finished Apr 25 01:09:35 PM PDT 24
Peak memory 205436 kb
Host smart-8b9f5277-c54e-4a63-b306-700a0d4bf230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991646247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
991646247
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1685443278
Short name T687
Test name
Test status
Simulation time 238582731 ps
CPU time 0.8 seconds
Started Apr 25 01:09:36 PM PDT 24
Finished Apr 25 01:09:39 PM PDT 24
Peak memory 206652 kb
Host smart-e10044f7-b995-4834-b46f-602c31437ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685443278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1685443278
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.655659780
Short name T284
Test name
Test status
Simulation time 3915087769 ps
CPU time 20.23 seconds
Started Apr 25 01:09:37 PM PDT 24
Finished Apr 25 01:09:59 PM PDT 24
Peak memory 232828 kb
Host smart-7549bdc1-8130-4b7b-8d27-dd3630e7f95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655659780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.655659780
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1319193097
Short name T8
Test name
Test status
Simulation time 1022164271 ps
CPU time 16.68 seconds
Started Apr 25 01:09:32 PM PDT 24
Finished Apr 25 01:09:50 PM PDT 24
Peak memory 233088 kb
Host smart-92423017-4e81-471e-9917-0ffd70e7c0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319193097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1319193097
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2176931330
Short name T425
Test name
Test status
Simulation time 563870435 ps
CPU time 4.93 seconds
Started Apr 25 01:09:33 PM PDT 24
Finished Apr 25 01:09:41 PM PDT 24
Peak memory 222388 kb
Host smart-44c5e217-090e-4bf6-9283-17a93b0ce286
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2176931330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2176931330
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1407626376
Short name T556
Test name
Test status
Simulation time 84065683 ps
CPU time 0.91 seconds
Started Apr 25 01:09:30 PM PDT 24
Finished Apr 25 01:09:32 PM PDT 24
Peak memory 206904 kb
Host smart-661744a2-ab2c-4ef2-998a-eb7f47b9e8ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407626376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1407626376
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.130045251
Short name T369
Test name
Test status
Simulation time 5273571367 ps
CPU time 27.29 seconds
Started Apr 25 01:09:42 PM PDT 24
Finished Apr 25 01:10:11 PM PDT 24
Peak memory 216480 kb
Host smart-6d5d27c5-74ab-476a-8dd6-e81c96f72b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130045251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.130045251
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1736320067
Short name T589
Test name
Test status
Simulation time 10121404643 ps
CPU time 11.01 seconds
Started Apr 25 01:09:34 PM PDT 24
Finished Apr 25 01:09:48 PM PDT 24
Peak memory 216352 kb
Host smart-29282780-24a8-4c8f-97d5-876657134e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736320067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1736320067
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1459731634
Short name T641
Test name
Test status
Simulation time 512408387 ps
CPU time 2.44 seconds
Started Apr 25 01:09:33 PM PDT 24
Finished Apr 25 01:09:38 PM PDT 24
Peak memory 216160 kb
Host smart-51bdfc90-2f54-4a1c-a42c-c5af9d64e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459731634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1459731634
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1623760139
Short name T674
Test name
Test status
Simulation time 103945952 ps
CPU time 0.92 seconds
Started Apr 25 01:09:31 PM PDT 24
Finished Apr 25 01:09:34 PM PDT 24
Peak memory 206908 kb
Host smart-bfea4bec-ef98-45b5-a9b3-a51fc1e3a122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623760139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1623760139
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.82576625
Short name T174
Test name
Test status
Simulation time 9551398389 ps
CPU time 4.48 seconds
Started Apr 25 01:09:31 PM PDT 24
Finished Apr 25 01:09:38 PM PDT 24
Peak memory 216368 kb
Host smart-c2969520-8640-4f88-bec2-5e4965ddd7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82576625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.82576625
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.659226145
Short name T482
Test name
Test status
Simulation time 27188554 ps
CPU time 0.78 seconds
Started Apr 25 01:09:43 PM PDT 24
Finished Apr 25 01:09:46 PM PDT 24
Peak memory 205716 kb
Host smart-9596f3ef-7349-49fa-9758-68b2a47d8522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659226145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.659226145
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2133923443
Short name T51
Test name
Test status
Simulation time 75214783 ps
CPU time 0.82 seconds
Started Apr 25 01:09:31 PM PDT 24
Finished Apr 25 01:09:34 PM PDT 24
Peak memory 206672 kb
Host smart-5659eec3-2be3-45b8-b5bf-02ce93e9d42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133923443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2133923443
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3546447601
Short name T193
Test name
Test status
Simulation time 344565221 ps
CPU time 5.87 seconds
Started Apr 25 01:09:35 PM PDT 24
Finished Apr 25 01:09:43 PM PDT 24
Peak memory 221880 kb
Host smart-d5a982e8-fe88-43d5-8c6c-2f0e04a09163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546447601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3546447601
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3567714968
Short name T545
Test name
Test status
Simulation time 740017719 ps
CPU time 12.6 seconds
Started Apr 25 01:09:33 PM PDT 24
Finished Apr 25 01:09:48 PM PDT 24
Peak memory 219236 kb
Host smart-12cf4748-537b-4ccf-9eba-6b35a5d17403
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3567714968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3567714968
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3149271233
Short name T45
Test name
Test status
Simulation time 253190322 ps
CPU time 0.97 seconds
Started Apr 25 01:09:42 PM PDT 24
Finished Apr 25 01:09:45 PM PDT 24
Peak memory 234996 kb
Host smart-ce91c7c7-33fa-4b83-aa8d-73c528c9461c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149271233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3149271233
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1921050595
Short name T668
Test name
Test status
Simulation time 587128471 ps
CPU time 3.76 seconds
Started Apr 25 01:09:30 PM PDT 24
Finished Apr 25 01:09:35 PM PDT 24
Peak memory 215780 kb
Host smart-8c9ba9e7-bcfb-4b33-9bf5-1e1514bf0643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921050595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1921050595
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1755164377
Short name T541
Test name
Test status
Simulation time 11835168898 ps
CPU time 29.74 seconds
Started Apr 25 01:09:32 PM PDT 24
Finished Apr 25 01:10:04 PM PDT 24
Peak memory 216340 kb
Host smart-4efd6a27-2169-409d-b674-aae8f29a55d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755164377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1755164377
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3214286459
Short name T650
Test name
Test status
Simulation time 321522504 ps
CPU time 1.9 seconds
Started Apr 25 01:09:35 PM PDT 24
Finished Apr 25 01:09:39 PM PDT 24
Peak memory 216136 kb
Host smart-c3058032-4dd1-454f-9685-0edb55e8bf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214286459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3214286459
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3063560051
Short name T428
Test name
Test status
Simulation time 62660497 ps
CPU time 0.9 seconds
Started Apr 25 01:09:32 PM PDT 24
Finished Apr 25 01:09:36 PM PDT 24
Peak memory 205748 kb
Host smart-a8ee9c0a-4525-4855-9ad1-597d39329ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063560051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3063560051
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2825742460
Short name T585
Test name
Test status
Simulation time 38584907 ps
CPU time 0.71 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:06 PM PDT 24
Peak memory 205732 kb
Host smart-c8e58748-e56c-4af4-9b91-ad3bb816e039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825742460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2825742460
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.289990420
Short name T25
Test name
Test status
Simulation time 242954821 ps
CPU time 2.78 seconds
Started Apr 25 01:10:06 PM PDT 24
Finished Apr 25 01:10:10 PM PDT 24
Peak memory 222560 kb
Host smart-0bdf9bf8-9144-4aba-aa58-4b5f81fdbe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289990420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.289990420
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2678638235
Short name T441
Test name
Test status
Simulation time 68000498 ps
CPU time 0.83 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:05 PM PDT 24
Peak memory 206664 kb
Host smart-68837633-bbc6-4b1c-a125-f40e6227421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678638235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2678638235
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.283528017
Short name T322
Test name
Test status
Simulation time 1109253279 ps
CPU time 8.68 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:15 PM PDT 24
Peak memory 218984 kb
Host smart-8ad47e08-168d-4091-89ef-368148663d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283528017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.283528017
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3579586305
Short name T10
Test name
Test status
Simulation time 6737608141 ps
CPU time 6.83 seconds
Started Apr 25 01:10:03 PM PDT 24
Finished Apr 25 01:10:10 PM PDT 24
Peak memory 216936 kb
Host smart-aa6070e2-87da-4517-baee-d90923814e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579586305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3579586305
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1924745624
Short name T464
Test name
Test status
Simulation time 435283223 ps
CPU time 7.32 seconds
Started Apr 25 01:10:05 PM PDT 24
Finished Apr 25 01:10:13 PM PDT 24
Peak memory 220464 kb
Host smart-949b603d-6065-43e5-bae9-3b19044bc8c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1924745624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1924745624
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.534177962
Short name T395
Test name
Test status
Simulation time 823673425 ps
CPU time 5.97 seconds
Started Apr 25 01:10:05 PM PDT 24
Finished Apr 25 01:10:13 PM PDT 24
Peak memory 216304 kb
Host smart-4cc8b582-d5a8-43c9-a47c-1fdceff22a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534177962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.534177962
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4256772991
Short name T388
Test name
Test status
Simulation time 93381572 ps
CPU time 1.94 seconds
Started Apr 25 01:10:06 PM PDT 24
Finished Apr 25 01:10:10 PM PDT 24
Peak memory 216208 kb
Host smart-55221a60-a807-43ac-8ef2-af5a79727653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256772991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4256772991
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1226512296
Short name T403
Test name
Test status
Simulation time 67656856 ps
CPU time 0.9 seconds
Started Apr 25 01:10:03 PM PDT 24
Finished Apr 25 01:10:05 PM PDT 24
Peak memory 205736 kb
Host smart-4a78ff25-682e-4ad9-a0c9-2e9c808f3c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226512296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1226512296
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1704750910
Short name T402
Test name
Test status
Simulation time 11583225 ps
CPU time 0.71 seconds
Started Apr 25 01:10:05 PM PDT 24
Finished Apr 25 01:10:07 PM PDT 24
Peak memory 205348 kb
Host smart-ffb4ca2e-edb0-4684-a0f7-dbacd79f59a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704750910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1704750910
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1286010443
Short name T430
Test name
Test status
Simulation time 23423318 ps
CPU time 0.78 seconds
Started Apr 25 01:10:03 PM PDT 24
Finished Apr 25 01:10:04 PM PDT 24
Peak memory 206620 kb
Host smart-56b256e4-95e5-4250-b09a-f87a2be871d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286010443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1286010443
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.831611704
Short name T617
Test name
Test status
Simulation time 10516555054 ps
CPU time 157.72 seconds
Started Apr 25 01:10:06 PM PDT 24
Finished Apr 25 01:12:45 PM PDT 24
Peak memory 251312 kb
Host smart-a448becf-825d-4e88-a238-d6bfbe775012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831611704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.831611704
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.581620495
Short name T299
Test name
Test status
Simulation time 61360527 ps
CPU time 2.56 seconds
Started Apr 25 01:10:07 PM PDT 24
Finished Apr 25 01:10:11 PM PDT 24
Peak memory 218668 kb
Host smart-8e055256-3c26-4db1-ae31-641175165a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581620495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.581620495
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.692396188
Short name T407
Test name
Test status
Simulation time 8555967346 ps
CPU time 24.73 seconds
Started Apr 25 01:10:10 PM PDT 24
Finished Apr 25 01:10:36 PM PDT 24
Peak memory 216304 kb
Host smart-5f407a31-3713-48fb-8dd0-d42a06ce2ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692396188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.692396188
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2728335697
Short name T448
Test name
Test status
Simulation time 43063804 ps
CPU time 0.98 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:10:10 PM PDT 24
Peak memory 207224 kb
Host smart-67b1a92a-9aa6-4896-8ae4-d99530d62011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728335697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2728335697
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1177403019
Short name T665
Test name
Test status
Simulation time 31746231 ps
CPU time 0.78 seconds
Started Apr 25 01:10:05 PM PDT 24
Finished Apr 25 01:10:08 PM PDT 24
Peak memory 205656 kb
Host smart-67d0e445-389c-4fa6-bf7b-5442546ee8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177403019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1177403019
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2218340973
Short name T240
Test name
Test status
Simulation time 607671194 ps
CPU time 3.54 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:10:13 PM PDT 24
Peak memory 218644 kb
Host smart-dae22578-6147-4920-95ff-179d1b6da0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218340973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2218340973
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2049369690
Short name T438
Test name
Test status
Simulation time 14239895 ps
CPU time 0.73 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:10:17 PM PDT 24
Peak memory 205340 kb
Host smart-1c96962d-21f6-4d4f-a912-5b0a3d68eabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049369690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2049369690
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1400856798
Short name T568
Test name
Test status
Simulation time 18822370 ps
CPU time 0.76 seconds
Started Apr 25 01:10:06 PM PDT 24
Finished Apr 25 01:10:08 PM PDT 24
Peak memory 206748 kb
Host smart-f61c941d-eeec-444c-a56a-4271579a9565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400856798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1400856798
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3915184460
Short name T103
Test name
Test status
Simulation time 2549242375 ps
CPU time 36.11 seconds
Started Apr 25 01:10:23 PM PDT 24
Finished Apr 25 01:11:00 PM PDT 24
Peak memory 232676 kb
Host smart-6c272b56-69df-4ae7-a98d-5e0dcaa2e9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915184460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3915184460
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.388988678
Short name T355
Test name
Test status
Simulation time 2642205586 ps
CPU time 14.75 seconds
Started Apr 25 01:10:11 PM PDT 24
Finished Apr 25 01:10:28 PM PDT 24
Peak memory 236812 kb
Host smart-161e3a72-cbf6-4698-bf88-06b323ded53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388988678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.388988678
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1966350556
Short name T711
Test name
Test status
Simulation time 5637723963 ps
CPU time 9.2 seconds
Started Apr 25 01:10:09 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 219032 kb
Host smart-88b7d2e3-7484-41dd-9210-6c63d9a89eee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1966350556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1966350556
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4045522562
Short name T542
Test name
Test status
Simulation time 572567991 ps
CPU time 8.14 seconds
Started Apr 25 01:10:07 PM PDT 24
Finished Apr 25 01:10:17 PM PDT 24
Peak memory 216344 kb
Host smart-6cba3bba-4ef4-4a69-b49b-618d6c40ae48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045522562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4045522562
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.683288525
Short name T627
Test name
Test status
Simulation time 551842555 ps
CPU time 4.18 seconds
Started Apr 25 01:10:07 PM PDT 24
Finished Apr 25 01:10:12 PM PDT 24
Peak memory 216280 kb
Host smart-f82cc395-c111-4dee-a15e-c493fef5e320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683288525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.683288525
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3662436111
Short name T653
Test name
Test status
Simulation time 116385921 ps
CPU time 1.26 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:07 PM PDT 24
Peak memory 207732 kb
Host smart-a347f765-9dba-4ad8-93b6-682e52863c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662436111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3662436111
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.208269481
Short name T13
Test name
Test status
Simulation time 352296070 ps
CPU time 1.07 seconds
Started Apr 25 01:10:11 PM PDT 24
Finished Apr 25 01:10:15 PM PDT 24
Peak memory 206824 kb
Host smart-f2690ba9-4040-41f7-a919-3cf439fe034f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208269481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.208269481
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3692216723
Short name T565
Test name
Test status
Simulation time 15789823 ps
CPU time 0.75 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:15 PM PDT 24
Peak memory 204832 kb
Host smart-c74f5df6-b234-4cd1-a2f5-d98dcece6b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692216723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3692216723
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.526556070
Short name T516
Test name
Test status
Simulation time 108746526 ps
CPU time 0.77 seconds
Started Apr 25 01:10:10 PM PDT 24
Finished Apr 25 01:10:12 PM PDT 24
Peak memory 206688 kb
Host smart-73994c2b-393e-42e0-9de9-ebc6051c27a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526556070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.526556070
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4198183971
Short name T638
Test name
Test status
Simulation time 103684359 ps
CPU time 2.46 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:16 PM PDT 24
Peak memory 221936 kb
Host smart-e0656050-ca7e-4942-9341-d552ff1ff80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198183971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4198183971
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1074162470
Short name T615
Test name
Test status
Simulation time 2344438677 ps
CPU time 4.81 seconds
Started Apr 25 01:10:24 PM PDT 24
Finished Apr 25 01:10:30 PM PDT 24
Peak memory 220460 kb
Host smart-64943586-b65d-49b5-87fc-abca9946b084
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074162470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1074162470
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2043236812
Short name T385
Test name
Test status
Simulation time 11695486723 ps
CPU time 54.72 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:11:11 PM PDT 24
Peak memory 216392 kb
Host smart-6f037abe-c983-46b5-8e8a-e4e71007d316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043236812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2043236812
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1163339666
Short name T703
Test name
Test status
Simulation time 19374119435 ps
CPU time 14.02 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:28 PM PDT 24
Peak memory 216336 kb
Host smart-7a5532d0-effc-483f-be39-bd7f64915da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163339666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1163339666
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1187354623
Short name T477
Test name
Test status
Simulation time 161705210 ps
CPU time 2.16 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:16 PM PDT 24
Peak memory 216236 kb
Host smart-730f8258-2c1d-44cf-811a-5daea993c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187354623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1187354623
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.93585479
Short name T698
Test name
Test status
Simulation time 101604653 ps
CPU time 0.84 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:10:17 PM PDT 24
Peak memory 205736 kb
Host smart-8cb2463a-848b-46f2-9a58-cdcf0b9d7a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93585479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.93585479
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2145848602
Short name T452
Test name
Test status
Simulation time 24870657 ps
CPU time 0.69 seconds
Started Apr 25 01:10:17 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 204860 kb
Host smart-efeb7cb8-5005-4813-980a-4b49471e09de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145848602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2145848602
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1074934970
Short name T607
Test name
Test status
Simulation time 22188926 ps
CPU time 0.77 seconds
Started Apr 25 01:10:11 PM PDT 24
Finished Apr 25 01:10:14 PM PDT 24
Peak memory 206728 kb
Host smart-ae699a6b-62fb-4feb-a37a-bce88d86beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074934970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1074934970
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.133019666
Short name T353
Test name
Test status
Simulation time 28439284575 ps
CPU time 33.56 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:48 PM PDT 24
Peak memory 240760 kb
Host smart-da16dcde-1d02-4c1d-a78c-7d5a65e0ea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133019666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.133019666
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2375150646
Short name T227
Test name
Test status
Simulation time 251778999 ps
CPU time 5.14 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 234380 kb
Host smart-921c13ac-ac43-4e1a-a919-a5cda2450d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375150646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2375150646
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2288030336
Short name T636
Test name
Test status
Simulation time 82923522 ps
CPU time 4.1 seconds
Started Apr 25 01:10:13 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 222856 kb
Host smart-6ed8b331-892c-4f60-9d19-9d9802b03c21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2288030336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2288030336
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.232063804
Short name T640
Test name
Test status
Simulation time 92641025 ps
CPU time 1.16 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:15 PM PDT 24
Peak memory 207148 kb
Host smart-e465d490-1fe5-4fd5-ab52-2fa2fdea19c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232063804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.232063804
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.262551663
Short name T495
Test name
Test status
Simulation time 26749924770 ps
CPU time 17.54 seconds
Started Apr 25 01:10:10 PM PDT 24
Finished Apr 25 01:10:29 PM PDT 24
Peak memory 216264 kb
Host smart-9f75505e-f892-41cd-b982-af366a464294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262551663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.262551663
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.336177020
Short name T670
Test name
Test status
Simulation time 130312193 ps
CPU time 1.62 seconds
Started Apr 25 01:10:10 PM PDT 24
Finished Apr 25 01:10:12 PM PDT 24
Peak memory 216232 kb
Host smart-9f258b8c-ea3e-4c6c-b1ec-77e51d811a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336177020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.336177020
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1869584164
Short name T537
Test name
Test status
Simulation time 2659703146 ps
CPU time 1.13 seconds
Started Apr 25 01:10:11 PM PDT 24
Finished Apr 25 01:10:13 PM PDT 24
Peak memory 206928 kb
Host smart-f9997abd-acbb-4ed1-b8f2-3f833a2f8a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869584164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1869584164
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3763514126
Short name T264
Test name
Test status
Simulation time 17853022971 ps
CPU time 26.96 seconds
Started Apr 25 01:10:22 PM PDT 24
Finished Apr 25 01:10:50 PM PDT 24
Peak memory 223296 kb
Host smart-3dcee2a5-01d9-4d74-953f-78f9b443e213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763514126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3763514126
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.804611389
Short name T527
Test name
Test status
Simulation time 41848302 ps
CPU time 0.71 seconds
Started Apr 25 01:10:16 PM PDT 24
Finished Apr 25 01:10:18 PM PDT 24
Peak memory 205704 kb
Host smart-57b376de-ea9a-4f51-92fd-603b629459d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804611389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.804611389
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2609146950
Short name T667
Test name
Test status
Simulation time 321569949 ps
CPU time 0.81 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:15 PM PDT 24
Peak memory 206884 kb
Host smart-f6bdf891-ba2b-4d4c-b20d-d4efe6c2df39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609146950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2609146950
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3851613634
Short name T57
Test name
Test status
Simulation time 7276581991 ps
CPU time 41.78 seconds
Started Apr 25 01:10:14 PM PDT 24
Finished Apr 25 01:10:57 PM PDT 24
Peak memory 233088 kb
Host smart-a54d1ca4-0a6d-477f-a5a2-1b332df59c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851613634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3851613634
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1655403935
Short name T315
Test name
Test status
Simulation time 81233837 ps
CPU time 3.45 seconds
Started Apr 25 01:10:17 PM PDT 24
Finished Apr 25 01:10:22 PM PDT 24
Peak memory 232164 kb
Host smart-83d39376-fdd0-4c71-99e7-f97acfa29232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655403935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1655403935
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1838850165
Short name T234
Test name
Test status
Simulation time 633796009 ps
CPU time 9.98 seconds
Started Apr 25 01:10:17 PM PDT 24
Finished Apr 25 01:10:29 PM PDT 24
Peak memory 236000 kb
Host smart-4ee1b782-9f9c-4ba7-b853-b3fcc63d1ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838850165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1838850165
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1722132976
Short name T447
Test name
Test status
Simulation time 931554937 ps
CPU time 8.33 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:10:25 PM PDT 24
Peak memory 222012 kb
Host smart-fe496146-f1ea-4031-badf-cbecdb47d0ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1722132976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1722132976
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3476885952
Short name T367
Test name
Test status
Simulation time 11876478128 ps
CPU time 31.99 seconds
Started Apr 25 01:10:16 PM PDT 24
Finished Apr 25 01:10:50 PM PDT 24
Peak memory 216332 kb
Host smart-8abe1236-30de-4b43-b383-daf654c151ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476885952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3476885952
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3696780069
Short name T597
Test name
Test status
Simulation time 1131268231 ps
CPU time 3.86 seconds
Started Apr 25 01:10:17 PM PDT 24
Finished Apr 25 01:10:23 PM PDT 24
Peak memory 216236 kb
Host smart-f6c9af34-5e69-4ee1-805d-f86392ae421f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696780069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3696780069
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2946480569
Short name T648
Test name
Test status
Simulation time 143082192 ps
CPU time 1.62 seconds
Started Apr 25 01:10:22 PM PDT 24
Finished Apr 25 01:10:24 PM PDT 24
Peak memory 216316 kb
Host smart-12ffaf9b-6e1d-4708-bb61-62113432a3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946480569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2946480569
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3610446643
Short name T470
Test name
Test status
Simulation time 20800679 ps
CPU time 0.75 seconds
Started Apr 25 01:10:16 PM PDT 24
Finished Apr 25 01:10:18 PM PDT 24
Peak memory 205760 kb
Host smart-03825455-6fcd-4924-a590-01c9c10b309a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610446643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3610446643
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3617637334
Short name T304
Test name
Test status
Simulation time 473782434 ps
CPU time 7.33 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:10:24 PM PDT 24
Peak memory 218796 kb
Host smart-bd096b35-8e63-400f-9328-62caf8c58129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617637334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3617637334
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3925179468
Short name T663
Test name
Test status
Simulation time 29944188 ps
CPU time 0.71 seconds
Started Apr 25 01:10:23 PM PDT 24
Finished Apr 25 01:10:24 PM PDT 24
Peak memory 204792 kb
Host smart-c66796b8-438a-44a8-a940-29fa3d2f0ec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925179468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3925179468
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.50762348
Short name T681
Test name
Test status
Simulation time 61716266 ps
CPU time 0.81 seconds
Started Apr 25 01:10:18 PM PDT 24
Finished Apr 25 01:10:21 PM PDT 24
Peak memory 206684 kb
Host smart-2a223198-d9d1-4cb7-83c8-141f4f5f4be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50762348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.50762348
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2520473728
Short name T165
Test name
Test status
Simulation time 5469475697 ps
CPU time 14.39 seconds
Started Apr 25 01:10:18 PM PDT 24
Finished Apr 25 01:10:34 PM PDT 24
Peak memory 218572 kb
Host smart-2f7f95c2-4be0-446b-9f0a-448d34040f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520473728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2520473728
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1001223864
Short name T241
Test name
Test status
Simulation time 611167938 ps
CPU time 5.52 seconds
Started Apr 25 01:10:32 PM PDT 24
Finished Apr 25 01:10:38 PM PDT 24
Peak memory 218736 kb
Host smart-383c960e-0e50-48d3-bb8a-b860e02cc85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001223864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1001223864
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2854396638
Short name T202
Test name
Test status
Simulation time 26192386053 ps
CPU time 8.77 seconds
Started Apr 25 01:10:22 PM PDT 24
Finished Apr 25 01:10:31 PM PDT 24
Peak memory 218564 kb
Host smart-784bfc00-f9ba-43cc-a9ab-d6a46147c48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854396638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2854396638
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2329248971
Short name T461
Test name
Test status
Simulation time 4547496948 ps
CPU time 12.96 seconds
Started Apr 25 01:10:22 PM PDT 24
Finished Apr 25 01:10:36 PM PDT 24
Peak memory 222472 kb
Host smart-2967bdcd-db50-4f90-945c-0934f584adff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2329248971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2329248971
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.756228759
Short name T366
Test name
Test status
Simulation time 3668150222 ps
CPU time 34.94 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:10:51 PM PDT 24
Peak memory 217784 kb
Host smart-d24dd8ab-caee-41b2-af75-416cdd0f6217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756228759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.756228759
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1457276472
Short name T511
Test name
Test status
Simulation time 9226735345 ps
CPU time 9.74 seconds
Started Apr 25 01:10:16 PM PDT 24
Finished Apr 25 01:10:28 PM PDT 24
Peak memory 216336 kb
Host smart-7e1654c4-17b8-49cc-b3ca-f1e1da7520d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457276472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1457276472
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2795718257
Short name T449
Test name
Test status
Simulation time 72023443 ps
CPU time 0.84 seconds
Started Apr 25 01:10:16 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 206936 kb
Host smart-cd81132f-c8a1-43ba-a1df-954ccd70c4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795718257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2795718257
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1462818790
Short name T476
Test name
Test status
Simulation time 52813312 ps
CPU time 0.77 seconds
Started Apr 25 01:10:15 PM PDT 24
Finished Apr 25 01:10:17 PM PDT 24
Peak memory 205700 kb
Host smart-3e8b4221-5052-49c8-92bf-579696a8678f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462818790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1462818790
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.238709396
Short name T205
Test name
Test status
Simulation time 428032678 ps
CPU time 4.5 seconds
Started Apr 25 01:10:18 PM PDT 24
Finished Apr 25 01:10:24 PM PDT 24
Peak memory 222224 kb
Host smart-6cb433f0-82ac-4721-810a-09880b2393c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238709396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.238709396
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1493480644
Short name T427
Test name
Test status
Simulation time 148233414 ps
CPU time 0.74 seconds
Started Apr 25 01:10:29 PM PDT 24
Finished Apr 25 01:10:30 PM PDT 24
Peak memory 204776 kb
Host smart-79197f33-0bc2-4450-b99d-1088ff8c9ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493480644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1493480644
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.673214894
Short name T580
Test name
Test status
Simulation time 2320555011 ps
CPU time 19.73 seconds
Started Apr 25 01:10:22 PM PDT 24
Finished Apr 25 01:10:42 PM PDT 24
Peak memory 218584 kb
Host smart-d1b5846f-94d6-4dec-804a-6a5b310406c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673214894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.673214894
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1292691507
Short name T601
Test name
Test status
Simulation time 75853794 ps
CPU time 0.78 seconds
Started Apr 25 01:10:21 PM PDT 24
Finished Apr 25 01:10:23 PM PDT 24
Peak memory 206632 kb
Host smart-bfd9f3f4-d494-4f54-b4e9-467d7106ed60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292691507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1292691507
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4192633027
Short name T172
Test name
Test status
Simulation time 97040749 ps
CPU time 3.77 seconds
Started Apr 25 01:10:26 PM PDT 24
Finished Apr 25 01:10:30 PM PDT 24
Peak memory 221324 kb
Host smart-11ae4f18-b4a0-4698-b541-f6af2d512c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192633027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4192633027
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3059462312
Short name T106
Test name
Test status
Simulation time 7229369503 ps
CPU time 61.43 seconds
Started Apr 25 01:10:26 PM PDT 24
Finished Apr 25 01:11:28 PM PDT 24
Peak memory 232628 kb
Host smart-280ca46a-697b-401b-9bcd-b1ea4ee6264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059462312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3059462312
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2531132845
Short name T178
Test name
Test status
Simulation time 805542236 ps
CPU time 6.19 seconds
Started Apr 25 01:10:23 PM PDT 24
Finished Apr 25 01:10:30 PM PDT 24
Peak memory 222728 kb
Host smart-af9159a6-99ca-42d8-bfb3-af798d87c07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531132845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2531132845
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1504931759
Short name T613
Test name
Test status
Simulation time 266614423 ps
CPU time 3.33 seconds
Started Apr 25 01:10:23 PM PDT 24
Finished Apr 25 01:10:28 PM PDT 24
Peak memory 218688 kb
Host smart-44ee947c-f8e1-4b37-9581-e0cde58c5057
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1504931759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1504931759
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1670697960
Short name T581
Test name
Test status
Simulation time 138742161601 ps
CPU time 68.73 seconds
Started Apr 25 01:10:24 PM PDT 24
Finished Apr 25 01:11:34 PM PDT 24
Peak memory 216388 kb
Host smart-571c630a-e054-4fb0-b261-7fd98b25556c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670697960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1670697960
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3780362350
Short name T692
Test name
Test status
Simulation time 3159646369 ps
CPU time 8.25 seconds
Started Apr 25 01:10:22 PM PDT 24
Finished Apr 25 01:10:31 PM PDT 24
Peak memory 216380 kb
Host smart-b4f8cb19-f6a0-41a6-8d83-d63eca39edba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780362350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3780362350
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2153891450
Short name T394
Test name
Test status
Simulation time 59559550 ps
CPU time 2.58 seconds
Started Apr 25 01:10:23 PM PDT 24
Finished Apr 25 01:10:27 PM PDT 24
Peak memory 216312 kb
Host smart-6059783a-0961-48c2-9e2f-fd2b947751ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153891450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2153891450
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1842621969
Short name T481
Test name
Test status
Simulation time 41061904 ps
CPU time 0.86 seconds
Started Apr 25 01:10:25 PM PDT 24
Finished Apr 25 01:10:27 PM PDT 24
Peak memory 206728 kb
Host smart-1eec0b44-5455-4f1e-839f-d18d60d78fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842621969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1842621969
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.778305963
Short name T654
Test name
Test status
Simulation time 45696640 ps
CPU time 0.73 seconds
Started Apr 25 01:10:37 PM PDT 24
Finished Apr 25 01:10:39 PM PDT 24
Peak memory 205760 kb
Host smart-0990ec6a-ccab-4f48-b79d-219b3aa0db08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778305963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.778305963
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3546280444
Short name T494
Test name
Test status
Simulation time 172498398 ps
CPU time 0.87 seconds
Started Apr 25 01:10:29 PM PDT 24
Finished Apr 25 01:10:31 PM PDT 24
Peak memory 206668 kb
Host smart-4439bf7e-4a9a-4e73-a956-e92877997a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546280444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3546280444
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2324546987
Short name T313
Test name
Test status
Simulation time 2235197326 ps
CPU time 11.76 seconds
Started Apr 25 01:10:30 PM PDT 24
Finished Apr 25 01:10:43 PM PDT 24
Peak memory 223092 kb
Host smart-f0d7dade-9d55-4814-b574-2fe582e02e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324546987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2324546987
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2558549189
Short name T701
Test name
Test status
Simulation time 6953184914 ps
CPU time 14.91 seconds
Started Apr 25 01:10:31 PM PDT 24
Finished Apr 25 01:10:46 PM PDT 24
Peak memory 223088 kb
Host smart-782130d7-2beb-4546-8a26-faa931baa02c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2558549189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2558549189
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2864018088
Short name T391
Test name
Test status
Simulation time 1320375888 ps
CPU time 4.45 seconds
Started Apr 25 01:10:31 PM PDT 24
Finished Apr 25 01:10:36 PM PDT 24
Peak memory 216368 kb
Host smart-fe755618-8a06-42b6-b340-0b73f4bb85fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864018088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2864018088
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1312149689
Short name T445
Test name
Test status
Simulation time 17145444031 ps
CPU time 23.21 seconds
Started Apr 25 01:10:31 PM PDT 24
Finished Apr 25 01:10:55 PM PDT 24
Peak memory 216356 kb
Host smart-9be33389-20a5-4427-a5aa-76cc18de559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312149689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1312149689
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2921629482
Short name T622
Test name
Test status
Simulation time 56114043 ps
CPU time 0.94 seconds
Started Apr 25 01:10:30 PM PDT 24
Finished Apr 25 01:10:32 PM PDT 24
Peak memory 206660 kb
Host smart-55227a18-2904-4327-8559-39195b52994b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921629482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2921629482
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1999661829
Short name T415
Test name
Test status
Simulation time 71862446 ps
CPU time 0.8 seconds
Started Apr 25 01:10:31 PM PDT 24
Finished Apr 25 01:10:33 PM PDT 24
Peak memory 205784 kb
Host smart-8dbbb4fa-8885-4235-b9b7-8c7c3106893f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999661829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1999661829
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1144072438
Short name T686
Test name
Test status
Simulation time 24187863 ps
CPU time 0.7 seconds
Started Apr 25 01:10:45 PM PDT 24
Finished Apr 25 01:10:47 PM PDT 24
Peak memory 205384 kb
Host smart-93586d61-2889-418d-be8d-44fcbf8586b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144072438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1144072438
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.704481139
Short name T484
Test name
Test status
Simulation time 13274154 ps
CPU time 0.77 seconds
Started Apr 25 01:10:38 PM PDT 24
Finished Apr 25 01:10:40 PM PDT 24
Peak memory 205596 kb
Host smart-dec3e463-1080-4648-91e4-1eaa9c204bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704481139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.704481139
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1634126637
Short name T611
Test name
Test status
Simulation time 14739959670 ps
CPU time 101.13 seconds
Started Apr 25 01:10:39 PM PDT 24
Finished Apr 25 01:12:21 PM PDT 24
Peak memory 249144 kb
Host smart-134b8421-f017-43ad-a1fa-88803866f96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634126637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1634126637
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1656333720
Short name T696
Test name
Test status
Simulation time 20682867927 ps
CPU time 153.09 seconds
Started Apr 25 01:10:38 PM PDT 24
Finished Apr 25 01:13:12 PM PDT 24
Peak memory 231988 kb
Host smart-270af110-7cdc-4994-8879-9725ad94f820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656333720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1656333720
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1760236238
Short name T214
Test name
Test status
Simulation time 6760257826 ps
CPU time 13.98 seconds
Started Apr 25 01:10:39 PM PDT 24
Finished Apr 25 01:10:54 PM PDT 24
Peak memory 222816 kb
Host smart-0ad10ce7-fb3f-4482-8399-0da539fed7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760236238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1760236238
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1660295846
Short name T424
Test name
Test status
Simulation time 1453492855 ps
CPU time 14.42 seconds
Started Apr 25 01:10:45 PM PDT 24
Finished Apr 25 01:11:00 PM PDT 24
Peak memory 222648 kb
Host smart-55ec991b-3752-4d45-b974-30897ac69e65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1660295846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1660295846
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.525330701
Short name T162
Test name
Test status
Simulation time 1706066887 ps
CPU time 11.41 seconds
Started Apr 25 01:10:44 PM PDT 24
Finished Apr 25 01:10:56 PM PDT 24
Peak memory 219356 kb
Host smart-7272dfc6-25b4-4881-b7fa-4f0eefd6662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525330701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.525330701
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2509763249
Short name T560
Test name
Test status
Simulation time 353765480 ps
CPU time 1.73 seconds
Started Apr 25 01:10:44 PM PDT 24
Finished Apr 25 01:10:47 PM PDT 24
Peak memory 207868 kb
Host smart-bc4803a2-d74b-4950-bea1-811eedd9aa81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509763249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2509763249
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3330738863
Short name T660
Test name
Test status
Simulation time 26913675 ps
CPU time 0.89 seconds
Started Apr 25 01:10:39 PM PDT 24
Finished Apr 25 01:10:41 PM PDT 24
Peak memory 206936 kb
Host smart-73c61977-9fce-4967-b82e-35f4bb77fc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330738863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3330738863
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3891407779
Short name T587
Test name
Test status
Simulation time 50791673 ps
CPU time 0.88 seconds
Started Apr 25 01:10:37 PM PDT 24
Finished Apr 25 01:10:39 PM PDT 24
Peak memory 205740 kb
Host smart-21f99af9-10ca-4877-8d8f-68bcb559b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891407779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3891407779
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2917297397
Short name T673
Test name
Test status
Simulation time 38423047 ps
CPU time 0.75 seconds
Started Apr 25 01:09:37 PM PDT 24
Finished Apr 25 01:09:39 PM PDT 24
Peak memory 205396 kb
Host smart-e01b2dac-f6be-45f8-912f-9a5cd949c81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917297397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
917297397
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.315536172
Short name T3
Test name
Test status
Simulation time 77585548 ps
CPU time 0.84 seconds
Started Apr 25 01:09:39 PM PDT 24
Finished Apr 25 01:09:41 PM PDT 24
Peak memory 206708 kb
Host smart-6ffc55bc-46d5-4ded-8973-9b2a481c3114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315536172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.315536172
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2562436516
Short name T90
Test name
Test status
Simulation time 6637113402 ps
CPU time 72.83 seconds
Started Apr 25 01:09:42 PM PDT 24
Finished Apr 25 01:10:57 PM PDT 24
Peak memory 249192 kb
Host smart-4a269f25-e25a-48f9-87cc-82d6b9fa0a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562436516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2562436516
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2183601140
Short name T182
Test name
Test status
Simulation time 1333378588 ps
CPU time 8.83 seconds
Started Apr 25 01:09:41 PM PDT 24
Finished Apr 25 01:09:52 PM PDT 24
Peak memory 234172 kb
Host smart-76b768fa-4775-4ced-a87e-24f10febda8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183601140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2183601140
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1512536673
Short name T555
Test name
Test status
Simulation time 980976932 ps
CPU time 6.02 seconds
Started Apr 25 01:09:43 PM PDT 24
Finished Apr 25 01:09:51 PM PDT 24
Peak memory 219276 kb
Host smart-aa83d779-2692-42a9-bc9a-a00ce5720a9e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1512536673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1512536673
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1664926604
Short name T46
Test name
Test status
Simulation time 37796385 ps
CPU time 0.99 seconds
Started Apr 25 01:09:40 PM PDT 24
Finished Apr 25 01:09:42 PM PDT 24
Peak memory 235024 kb
Host smart-bdbe7829-66ca-465a-a0c7-aad3ca229271
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664926604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1664926604
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1108126637
Short name T382
Test name
Test status
Simulation time 2282164236 ps
CPU time 20.04 seconds
Started Apr 25 01:09:39 PM PDT 24
Finished Apr 25 01:10:01 PM PDT 24
Peak memory 216244 kb
Host smart-bcc8629f-f754-48b0-8d2b-48368557bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108126637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1108126637
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.930210915
Short name T620
Test name
Test status
Simulation time 52082620171 ps
CPU time 33.7 seconds
Started Apr 25 01:09:38 PM PDT 24
Finished Apr 25 01:10:14 PM PDT 24
Peak memory 216332 kb
Host smart-61a790a4-21cd-4a3b-be92-249dbb028168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930210915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.930210915
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4175546390
Short name T514
Test name
Test status
Simulation time 17532139 ps
CPU time 0.77 seconds
Started Apr 25 01:09:39 PM PDT 24
Finished Apr 25 01:09:42 PM PDT 24
Peak memory 205772 kb
Host smart-e44e8552-d337-47a2-b4be-ce3ce7d98c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175546390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4175546390
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.904477342
Short name T609
Test name
Test status
Simulation time 28209073 ps
CPU time 0.88 seconds
Started Apr 25 01:09:38 PM PDT 24
Finished Apr 25 01:09:41 PM PDT 24
Peak memory 205728 kb
Host smart-13e07754-a181-4565-a7ac-d3c4180475b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904477342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.904477342
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.828828108
Short name T437
Test name
Test status
Simulation time 13277964 ps
CPU time 0.7 seconds
Started Apr 25 01:10:45 PM PDT 24
Finished Apr 25 01:10:46 PM PDT 24
Peak memory 205388 kb
Host smart-886cf1f3-c567-4fce-b788-c6478b8735ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828828108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.828828108
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.13310442
Short name T406
Test name
Test status
Simulation time 56160257 ps
CPU time 0.88 seconds
Started Apr 25 01:10:42 PM PDT 24
Finished Apr 25 01:10:43 PM PDT 24
Peak memory 205696 kb
Host smart-80d8ecec-b381-4b39-9a72-e1638edb441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13310442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.13310442
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1952760524
Short name T281
Test name
Test status
Simulation time 14715448136 ps
CPU time 55.57 seconds
Started Apr 25 01:10:42 PM PDT 24
Finished Apr 25 01:11:38 PM PDT 24
Peak memory 249160 kb
Host smart-392c7aa8-1433-4f83-80c9-0d24be27e5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952760524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1952760524
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1492437281
Short name T417
Test name
Test status
Simulation time 2640665958 ps
CPU time 8.12 seconds
Started Apr 25 01:10:40 PM PDT 24
Finished Apr 25 01:10:49 PM PDT 24
Peak memory 219188 kb
Host smart-1e3aaf47-cafa-48ab-97e1-9bbf342fffb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1492437281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1492437281
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1693118679
Short name T446
Test name
Test status
Simulation time 1359856078 ps
CPU time 7.99 seconds
Started Apr 25 01:10:50 PM PDT 24
Finished Apr 25 01:10:59 PM PDT 24
Peak memory 216204 kb
Host smart-f88002c6-ab75-425f-8f5f-c957674046a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693118679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1693118679
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3389651875
Short name T473
Test name
Test status
Simulation time 144475193 ps
CPU time 1.41 seconds
Started Apr 25 01:10:40 PM PDT 24
Finished Apr 25 01:10:42 PM PDT 24
Peak memory 216100 kb
Host smart-9c11fe7b-dc3f-430d-8e8f-d52643a52b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389651875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3389651875
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2508947223
Short name T431
Test name
Test status
Simulation time 46620968 ps
CPU time 0.85 seconds
Started Apr 25 01:10:44 PM PDT 24
Finished Apr 25 01:10:46 PM PDT 24
Peak memory 205760 kb
Host smart-22a28f40-fbad-4a93-b91f-009c9a2cfb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508947223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2508947223
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1014413906
Short name T510
Test name
Test status
Simulation time 34855646 ps
CPU time 0.7 seconds
Started Apr 25 01:10:45 PM PDT 24
Finished Apr 25 01:10:47 PM PDT 24
Peak memory 204840 kb
Host smart-565a572b-f27f-401e-9b0c-eb7e3106f35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014413906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1014413906
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.939416710
Short name T456
Test name
Test status
Simulation time 59052357 ps
CPU time 0.79 seconds
Started Apr 25 01:10:43 PM PDT 24
Finished Apr 25 01:10:45 PM PDT 24
Peak memory 206684 kb
Host smart-13284f28-4a8e-4b2e-beb4-f0cff1400af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939416710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.939416710
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_intercept.226892495
Short name T305
Test name
Test status
Simulation time 1311292608 ps
CPU time 9.3 seconds
Started Apr 25 01:10:44 PM PDT 24
Finished Apr 25 01:10:54 PM PDT 24
Peak memory 222964 kb
Host smart-0a8209c3-1e70-4ec7-bc41-4cba5229f24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226892495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.226892495
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.235933106
Short name T215
Test name
Test status
Simulation time 1825836050 ps
CPU time 3.26 seconds
Started Apr 25 01:10:47 PM PDT 24
Finished Apr 25 01:10:51 PM PDT 24
Peak memory 218596 kb
Host smart-a82aca6b-0ce3-4bd7-95ec-cd21630018cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235933106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.235933106
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1765548146
Short name T669
Test name
Test status
Simulation time 1478494448 ps
CPU time 7.08 seconds
Started Apr 25 01:10:43 PM PDT 24
Finished Apr 25 01:10:51 PM PDT 24
Peak memory 219448 kb
Host smart-47f8cea4-52ef-424e-a04d-f6b19c480c90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765548146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1765548146
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3722528398
Short name T18
Test name
Test status
Simulation time 2044084265 ps
CPU time 32.81 seconds
Started Apr 25 01:10:44 PM PDT 24
Finished Apr 25 01:11:18 PM PDT 24
Peak memory 216460 kb
Host smart-f2325dc6-0640-45b4-ad94-4a90e5e712d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722528398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3722528398
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.493680700
Short name T423
Test name
Test status
Simulation time 1670394096 ps
CPU time 10.87 seconds
Started Apr 25 01:10:47 PM PDT 24
Finished Apr 25 01:10:59 PM PDT 24
Peak memory 216308 kb
Host smart-34c3802e-5f00-4df5-9762-d1e3cd65787a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493680700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.493680700
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1974803101
Short name T390
Test name
Test status
Simulation time 405189089 ps
CPU time 1.41 seconds
Started Apr 25 01:10:44 PM PDT 24
Finished Apr 25 01:10:47 PM PDT 24
Peak memory 208044 kb
Host smart-fda8bd98-6c6c-4d65-9b55-83ff66ec2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974803101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1974803101
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.370101103
Short name T662
Test name
Test status
Simulation time 104150720 ps
CPU time 1.01 seconds
Started Apr 25 01:10:47 PM PDT 24
Finished Apr 25 01:10:49 PM PDT 24
Peak memory 206776 kb
Host smart-690983c4-7c2c-424c-8d1f-782821c3f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370101103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.370101103
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.815089253
Short name T498
Test name
Test status
Simulation time 22343157 ps
CPU time 0.7 seconds
Started Apr 25 01:10:52 PM PDT 24
Finished Apr 25 01:10:54 PM PDT 24
Peak memory 205476 kb
Host smart-e09e53c6-7c74-4e47-b0fc-736a38d96a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815089253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.815089253
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1550692107
Short name T614
Test name
Test status
Simulation time 17968778 ps
CPU time 0.75 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:10:48 PM PDT 24
Peak memory 205880 kb
Host smart-6c65bd60-b4ec-483d-a3d3-3d19e33a92ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550692107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1550692107
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1312387751
Short name T296
Test name
Test status
Simulation time 2041843388 ps
CPU time 19.98 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:11:08 PM PDT 24
Peak memory 248988 kb
Host smart-5ad10fa5-ba99-432b-a9bb-fec6f301027c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312387751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1312387751
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1513728035
Short name T237
Test name
Test status
Simulation time 1788667791 ps
CPU time 17.85 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:11:05 PM PDT 24
Peak memory 223444 kb
Host smart-1f0613e2-4335-48fc-b177-bbb1093e7a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513728035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1513728035
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.419297921
Short name T713
Test name
Test status
Simulation time 13078540848 ps
CPU time 24.47 seconds
Started Apr 25 01:10:43 PM PDT 24
Finished Apr 25 01:11:08 PM PDT 24
Peak memory 222412 kb
Host smart-1ea91547-7cbb-4d62-97c3-859bfef0082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419297921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.419297921
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3312064548
Short name T130
Test name
Test status
Simulation time 948474397 ps
CPU time 9.17 seconds
Started Apr 25 01:10:43 PM PDT 24
Finished Apr 25 01:10:53 PM PDT 24
Peak memory 222760 kb
Host smart-ae396a2e-8f02-4296-86fd-ac7e683a6b92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3312064548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3312064548
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3663385799
Short name T375
Test name
Test status
Simulation time 7615247032 ps
CPU time 39.2 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:11:26 PM PDT 24
Peak memory 216636 kb
Host smart-5138ce5d-4d7b-48d0-971a-c0248cf8a6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663385799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3663385799
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4119456729
Short name T488
Test name
Test status
Simulation time 2893712307 ps
CPU time 8.79 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:10:56 PM PDT 24
Peak memory 215584 kb
Host smart-434a94bf-c782-40e1-9d9c-ae6b1de8a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119456729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4119456729
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1850496502
Short name T618
Test name
Test status
Simulation time 1276846734 ps
CPU time 10.63 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:10:58 PM PDT 24
Peak memory 216316 kb
Host smart-a328beab-dcd6-49e1-a59e-12c365526772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850496502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1850496502
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4212097027
Short name T434
Test name
Test status
Simulation time 24519547 ps
CPU time 0.78 seconds
Started Apr 25 01:10:46 PM PDT 24
Finished Apr 25 01:10:48 PM PDT 24
Peak memory 205656 kb
Host smart-57023b2b-7b3f-4042-80ad-c15554d11088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212097027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4212097027
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2630706061
Short name T559
Test name
Test status
Simulation time 25776029 ps
CPU time 0.74 seconds
Started Apr 25 01:10:53 PM PDT 24
Finished Apr 25 01:10:55 PM PDT 24
Peak memory 205320 kb
Host smart-afae9f13-c1d9-414a-a04b-dc717de77877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630706061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2630706061
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3953904171
Short name T454
Test name
Test status
Simulation time 199144434 ps
CPU time 0.81 seconds
Started Apr 25 01:10:51 PM PDT 24
Finished Apr 25 01:10:53 PM PDT 24
Peak memory 206972 kb
Host smart-04542dc4-2611-47a6-9b66-4970639e41a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953904171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3953904171
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.155244989
Short name T566
Test name
Test status
Simulation time 363417056 ps
CPU time 12.54 seconds
Started Apr 25 01:10:59 PM PDT 24
Finished Apr 25 01:11:13 PM PDT 24
Peak memory 239536 kb
Host smart-a1a24457-c7dc-4606-a658-9cc8c9047314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155244989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.155244989
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3660681043
Short name T232
Test name
Test status
Simulation time 9797481216 ps
CPU time 14.11 seconds
Started Apr 25 01:10:54 PM PDT 24
Finished Apr 25 01:11:09 PM PDT 24
Peak memory 231944 kb
Host smart-3cab29d2-5663-4c91-b049-069fb4707ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660681043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3660681043
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3681983280
Short name T621
Test name
Test status
Simulation time 1034301241 ps
CPU time 5.08 seconds
Started Apr 25 01:10:53 PM PDT 24
Finished Apr 25 01:10:59 PM PDT 24
Peak memory 222852 kb
Host smart-384d879b-3420-4769-a5a8-c31d69dc7bca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3681983280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3681983280
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2289249091
Short name T682
Test name
Test status
Simulation time 11790168145 ps
CPU time 28.31 seconds
Started Apr 25 01:10:52 PM PDT 24
Finished Apr 25 01:11:21 PM PDT 24
Peak memory 216372 kb
Host smart-249ee008-0474-4f1b-97de-ed12a8dd3bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289249091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2289249091
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4108203208
Short name T664
Test name
Test status
Simulation time 8624143924 ps
CPU time 7.16 seconds
Started Apr 25 01:10:53 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 217284 kb
Host smart-f5478902-a8d8-4666-9557-effbeb9e8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108203208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4108203208
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2214106396
Short name T578
Test name
Test status
Simulation time 277523412 ps
CPU time 1.56 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 215580 kb
Host smart-7d8d671e-c17b-4539-9fdd-bb6b8de3c47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214106396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2214106396
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3512840106
Short name T582
Test name
Test status
Simulation time 128833701 ps
CPU time 0.98 seconds
Started Apr 25 01:10:52 PM PDT 24
Finished Apr 25 01:10:54 PM PDT 24
Peak memory 206776 kb
Host smart-7e8ee0ac-a9bc-4dba-a136-43c0d30a7b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512840106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3512840106
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.380226019
Short name T675
Test name
Test status
Simulation time 12249639 ps
CPU time 0.75 seconds
Started Apr 25 01:10:53 PM PDT 24
Finished Apr 25 01:10:55 PM PDT 24
Peak memory 204780 kb
Host smart-b512f105-586e-466d-a16a-1c20efd86bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380226019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.380226019
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1240451906
Short name T547
Test name
Test status
Simulation time 1521645167 ps
CPU time 12.74 seconds
Started Apr 25 01:10:53 PM PDT 24
Finished Apr 25 01:11:07 PM PDT 24
Peak memory 218584 kb
Host smart-158d9c8d-653d-456a-a922-1aedd17b2ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240451906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1240451906
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1134250454
Short name T400
Test name
Test status
Simulation time 41720814 ps
CPU time 0.76 seconds
Started Apr 25 01:10:50 PM PDT 24
Finished Apr 25 01:10:51 PM PDT 24
Peak memory 206576 kb
Host smart-3ab7581f-a556-4a2a-a6ca-defa42ce3a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134250454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1134250454
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3720574594
Short name T710
Test name
Test status
Simulation time 3073288363 ps
CPU time 45.32 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:45 PM PDT 24
Peak memory 250192 kb
Host smart-eb19d938-7b0b-48d5-8bd6-4c10f54f0e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720574594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3720574594
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2841977064
Short name T212
Test name
Test status
Simulation time 4238456836 ps
CPU time 10.97 seconds
Started Apr 25 01:10:50 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 223856 kb
Host smart-2dec83fb-b476-4517-9d1d-04d19e5b1061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841977064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2841977064
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1632702503
Short name T331
Test name
Test status
Simulation time 5236381534 ps
CPU time 23.75 seconds
Started Apr 25 01:10:50 PM PDT 24
Finished Apr 25 01:11:15 PM PDT 24
Peak memory 223216 kb
Host smart-e9d9acb9-2c3e-43c2-b5eb-f379304a91e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632702503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1632702503
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.664326392
Short name T11
Test name
Test status
Simulation time 123217514 ps
CPU time 4.57 seconds
Started Apr 25 01:10:51 PM PDT 24
Finished Apr 25 01:10:56 PM PDT 24
Peak memory 222880 kb
Host smart-ba321ee0-d2d3-47ba-91cc-7d80472063d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=664326392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.664326392
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3806912762
Short name T635
Test name
Test status
Simulation time 63910084 ps
CPU time 0.98 seconds
Started Apr 25 01:10:51 PM PDT 24
Finished Apr 25 01:10:52 PM PDT 24
Peak memory 206952 kb
Host smart-b8bfaaa5-501f-4637-8341-b3258654389c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806912762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3806912762
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2843725617
Short name T624
Test name
Test status
Simulation time 6688960206 ps
CPU time 35.13 seconds
Started Apr 25 01:10:51 PM PDT 24
Finished Apr 25 01:11:28 PM PDT 24
Peak memory 216316 kb
Host smart-72ab24d2-8dad-4a55-94ff-23666d88f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843725617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2843725617
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2212935550
Short name T562
Test name
Test status
Simulation time 19021838306 ps
CPU time 5.62 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:16 PM PDT 24
Peak memory 216360 kb
Host smart-f3245709-7cc6-4d6b-9a41-69b9df1cf0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212935550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2212935550
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3181883117
Short name T389
Test name
Test status
Simulation time 43866415 ps
CPU time 1.43 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 215520 kb
Host smart-0dc87007-bf6f-4290-b1e7-b93bfaaed771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181883117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3181883117
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1482135710
Short name T656
Test name
Test status
Simulation time 117634017 ps
CPU time 0.83 seconds
Started Apr 25 01:10:50 PM PDT 24
Finished Apr 25 01:10:52 PM PDT 24
Peak memory 205828 kb
Host smart-0ea41afd-3610-4494-ad3d-7ec33a95862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482135710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1482135710
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.858759130
Short name T564
Test name
Test status
Simulation time 10736206 ps
CPU time 0.69 seconds
Started Apr 25 01:10:56 PM PDT 24
Finished Apr 25 01:10:58 PM PDT 24
Peak memory 205332 kb
Host smart-e3ca70e9-def9-4cd5-85e7-de9e5be6503c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858759130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.858759130
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3798725963
Short name T29
Test name
Test status
Simulation time 703707704 ps
CPU time 6.39 seconds
Started Apr 25 01:11:00 PM PDT 24
Finished Apr 25 01:11:07 PM PDT 24
Peak memory 218788 kb
Host smart-684b2cab-f5f5-4218-a69d-543e2c80130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798725963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3798725963
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.176784435
Short name T705
Test name
Test status
Simulation time 26909690 ps
CPU time 0.78 seconds
Started Apr 25 01:10:59 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 206728 kb
Host smart-58ce789e-05b5-419c-b015-abe83a45dfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176784435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.176784435
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.523481997
Short name T563
Test name
Test status
Simulation time 2572503973 ps
CPU time 23.23 seconds
Started Apr 25 01:11:00 PM PDT 24
Finished Apr 25 01:11:24 PM PDT 24
Peak memory 239432 kb
Host smart-426bc819-cd25-48e3-9141-65619ac1cca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523481997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.523481997
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4238206238
Short name T185
Test name
Test status
Simulation time 816118506 ps
CPU time 5.8 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:05 PM PDT 24
Peak memory 218880 kb
Host smart-e2b658e8-5cc4-4fb1-8038-b99df3427004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238206238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4238206238
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1462727407
Short name T348
Test name
Test status
Simulation time 1147959127 ps
CPU time 13.66 seconds
Started Apr 25 01:10:59 PM PDT 24
Finished Apr 25 01:11:14 PM PDT 24
Peak memory 221944 kb
Host smart-80028062-a290-4a75-8277-8af3dafa586d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462727407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1462727407
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3087453046
Short name T268
Test name
Test status
Simulation time 2169192441 ps
CPU time 5.65 seconds
Started Apr 25 01:10:55 PM PDT 24
Finished Apr 25 01:11:02 PM PDT 24
Peak memory 219064 kb
Host smart-038c6c69-4dc8-4db3-ab7d-cf8bda4c9e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087453046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3087453046
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.720708400
Short name T588
Test name
Test status
Simulation time 232668674 ps
CPU time 4.4 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:03 PM PDT 24
Peak memory 222352 kb
Host smart-c688e700-4db8-4217-922c-22dc9aa5b692
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=720708400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.720708400
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4002426583
Short name T12
Test name
Test status
Simulation time 3168925368 ps
CPU time 12.17 seconds
Started Apr 25 01:10:59 PM PDT 24
Finished Apr 25 01:11:12 PM PDT 24
Peak memory 216376 kb
Host smart-d85a05b4-c7f0-426d-b0f3-78a7c4426d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002426583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4002426583
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3151407289
Short name T598
Test name
Test status
Simulation time 3062795171 ps
CPU time 12.15 seconds
Started Apr 25 01:10:52 PM PDT 24
Finished Apr 25 01:11:05 PM PDT 24
Peak memory 216304 kb
Host smart-25712006-7c36-4100-a269-9c84f254d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151407289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3151407289
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1297974927
Short name T576
Test name
Test status
Simulation time 372419514 ps
CPU time 13.24 seconds
Started Apr 25 01:10:53 PM PDT 24
Finished Apr 25 01:11:08 PM PDT 24
Peak memory 216256 kb
Host smart-50fd53b4-8f06-41c9-b26b-9e5669d402f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297974927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1297974927
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2792746633
Short name T549
Test name
Test status
Simulation time 199101000 ps
CPU time 1.32 seconds
Started Apr 25 01:10:53 PM PDT 24
Finished Apr 25 01:10:56 PM PDT 24
Peak memory 206732 kb
Host smart-db27aabe-ef35-4588-b446-12e06262e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792746633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2792746633
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2403017668
Short name T487
Test name
Test status
Simulation time 84869131 ps
CPU time 0.72 seconds
Started Apr 25 01:10:56 PM PDT 24
Finished Apr 25 01:10:58 PM PDT 24
Peak memory 205436 kb
Host smart-3a3bb9c0-e614-49bd-8d4f-41781e491c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403017668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2403017668
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2056178135
Short name T569
Test name
Test status
Simulation time 21588099 ps
CPU time 0.77 seconds
Started Apr 25 01:11:01 PM PDT 24
Finished Apr 25 01:11:02 PM PDT 24
Peak memory 206684 kb
Host smart-417b9e0b-961a-42e0-91fa-81744e5e561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056178135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2056178135
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1243432507
Short name T583
Test name
Test status
Simulation time 8526881762 ps
CPU time 87.3 seconds
Started Apr 25 01:10:57 PM PDT 24
Finished Apr 25 01:12:26 PM PDT 24
Peak memory 249068 kb
Host smart-2ac2d6e5-2330-45f6-945a-89f37cfe0d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243432507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1243432507
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.517696877
Short name T42
Test name
Test status
Simulation time 936747731 ps
CPU time 6.51 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:06 PM PDT 24
Peak memory 218800 kb
Host smart-35e4b412-1816-42e7-8eb3-c9e887829337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517696877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.517696877
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2111713310
Short name T72
Test name
Test status
Simulation time 2884138674 ps
CPU time 8 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:07 PM PDT 24
Peak memory 218748 kb
Host smart-5e967d64-51cd-442f-abd8-e6a5baa395f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111713310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2111713310
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2898839149
Short name T154
Test name
Test status
Simulation time 493402699 ps
CPU time 6.52 seconds
Started Apr 25 01:10:57 PM PDT 24
Finished Apr 25 01:11:04 PM PDT 24
Peak memory 222964 kb
Host smart-81f80c14-bd29-4b04-871a-235e320bf724
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2898839149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2898839149
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.12289036
Short name T574
Test name
Test status
Simulation time 458156415 ps
CPU time 1.12 seconds
Started Apr 25 01:10:59 PM PDT 24
Finished Apr 25 01:11:01 PM PDT 24
Peak memory 207364 kb
Host smart-f1e9ce8e-89f8-43bf-bece-3001293023cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12289036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress
_all.12289036
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.82614039
Short name T421
Test name
Test status
Simulation time 30131438438 ps
CPU time 23.97 seconds
Started Apr 25 01:11:01 PM PDT 24
Finished Apr 25 01:11:25 PM PDT 24
Peak memory 216320 kb
Host smart-e0ba9197-5ac6-43fe-9ed5-6f355ee9e7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82614039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.82614039
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2181786345
Short name T521
Test name
Test status
Simulation time 123726389 ps
CPU time 1.68 seconds
Started Apr 25 01:11:07 PM PDT 24
Finished Apr 25 01:11:09 PM PDT 24
Peak memory 216192 kb
Host smart-30bb9de7-6953-4dea-b574-af7519557a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181786345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2181786345
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3161983500
Short name T399
Test name
Test status
Simulation time 128742224 ps
CPU time 1 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:00 PM PDT 24
Peak memory 206248 kb
Host smart-d752b95c-b6ee-4f53-8ec7-841900437d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161983500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3161983500
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1789073065
Short name T258
Test name
Test status
Simulation time 627497846 ps
CPU time 7.78 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:07 PM PDT 24
Peak memory 217348 kb
Host smart-4b039948-8bd7-4208-829c-b9741adaf63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789073065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1789073065
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3264195312
Short name T661
Test name
Test status
Simulation time 15043776 ps
CPU time 0.69 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:07 PM PDT 24
Peak memory 204816 kb
Host smart-af3e3031-010f-4f38-8385-4c4eb162cb79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264195312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3264195312
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3879461740
Short name T548
Test name
Test status
Simulation time 163989094 ps
CPU time 3.49 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:09 PM PDT 24
Peak memory 222704 kb
Host smart-36dc5454-8fea-4e47-ae2c-cfdd1ec7c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879461740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3879461740
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3539143795
Short name T695
Test name
Test status
Simulation time 16597044 ps
CPU time 0.77 seconds
Started Apr 25 01:11:00 PM PDT 24
Finished Apr 25 01:11:02 PM PDT 24
Peak memory 206680 kb
Host smart-b6106c2e-9c30-4a82-9fa8-05a400629470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539143795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3539143795
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2129294194
Short name T291
Test name
Test status
Simulation time 3341744680 ps
CPU time 33.9 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:39 PM PDT 24
Peak memory 239508 kb
Host smart-e9d8f329-a42c-4004-b694-56d54b9f8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129294194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2129294194
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1319663060
Short name T684
Test name
Test status
Simulation time 564310157 ps
CPU time 3.85 seconds
Started Apr 25 01:11:04 PM PDT 24
Finished Apr 25 01:11:09 PM PDT 24
Peak memory 219340 kb
Host smart-9fbe1459-7ebe-49c0-80be-465080b50399
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1319663060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1319663060
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4229293559
Short name T401
Test name
Test status
Simulation time 5339839848 ps
CPU time 3.55 seconds
Started Apr 25 01:11:00 PM PDT 24
Finished Apr 25 01:11:05 PM PDT 24
Peak memory 216380 kb
Host smart-c5a79999-6233-407e-a249-da28eebd0a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229293559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4229293559
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2307022003
Short name T19
Test name
Test status
Simulation time 84662124 ps
CPU time 3.94 seconds
Started Apr 25 01:11:04 PM PDT 24
Finished Apr 25 01:11:08 PM PDT 24
Peak memory 216128 kb
Host smart-c6c7ad32-0bd8-485c-a1a2-7bf266a14a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307022003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2307022003
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.501966399
Short name T471
Test name
Test status
Simulation time 124798576 ps
CPU time 1.09 seconds
Started Apr 25 01:10:58 PM PDT 24
Finished Apr 25 01:11:00 PM PDT 24
Peak memory 206732 kb
Host smart-e03189ce-bb5a-40c0-8975-87492291025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501966399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.501966399
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3609656306
Short name T53
Test name
Test status
Simulation time 8224773241 ps
CPU time 31.4 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:37 PM PDT 24
Peak memory 240100 kb
Host smart-02ba0666-8dc5-4dd6-af07-a8876b5cffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609656306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3609656306
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4022431052
Short name T443
Test name
Test status
Simulation time 12154752 ps
CPU time 0.69 seconds
Started Apr 25 01:11:11 PM PDT 24
Finished Apr 25 01:11:14 PM PDT 24
Peak memory 205368 kb
Host smart-07aa7f01-ec02-4594-a5db-e7c022a6758c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022431052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4022431052
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1771425307
Short name T409
Test name
Test status
Simulation time 12749763 ps
CPU time 0.77 seconds
Started Apr 25 01:11:04 PM PDT 24
Finished Apr 25 01:11:05 PM PDT 24
Peak memory 206984 kb
Host smart-11bab018-5669-4461-8968-8cfcfe02a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771425307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1771425307
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_intercept.958893344
Short name T111
Test name
Test status
Simulation time 5014903536 ps
CPU time 14.51 seconds
Started Apr 25 01:11:06 PM PDT 24
Finished Apr 25 01:11:21 PM PDT 24
Peak memory 223800 kb
Host smart-be543cb5-8bf3-47e9-91c0-6f75e2ba180a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958893344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.958893344
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.58461103
Short name T413
Test name
Test status
Simulation time 1151843076 ps
CPU time 16.31 seconds
Started Apr 25 01:11:03 PM PDT 24
Finished Apr 25 01:11:20 PM PDT 24
Peak memory 220056 kb
Host smart-d6d78b7e-22f4-4707-ae6b-218d3728ba1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58461103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direc
t.58461103
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3850111635
Short name T158
Test name
Test status
Simulation time 54186995 ps
CPU time 0.99 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:12 PM PDT 24
Peak memory 207112 kb
Host smart-fad9b026-66f4-43a0-952d-7cc7f38c607d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850111635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3850111635
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1452886791
Short name T678
Test name
Test status
Simulation time 42016242 ps
CPU time 0.81 seconds
Started Apr 25 01:11:03 PM PDT 24
Finished Apr 25 01:11:05 PM PDT 24
Peak memory 205832 kb
Host smart-93dac4f4-37a3-4ee0-9fc6-fe07d26ad414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452886791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1452886791
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4134638623
Short name T520
Test name
Test status
Simulation time 1185896047 ps
CPU time 0.89 seconds
Started Apr 25 01:11:05 PM PDT 24
Finished Apr 25 01:11:07 PM PDT 24
Peak memory 205728 kb
Host smart-d9af2543-a8b2-49f9-b908-ad4370fae9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134638623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4134638623
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1516121211
Short name T459
Test name
Test status
Simulation time 15457673 ps
CPU time 0.69 seconds
Started Apr 25 01:11:16 PM PDT 24
Finished Apr 25 01:11:17 PM PDT 24
Peak memory 204736 kb
Host smart-6d7ecec8-bddf-4ea2-b12e-d7bfa3ccb182
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516121211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1516121211
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2014986796
Short name T91
Test name
Test status
Simulation time 294466664 ps
CPU time 3.36 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:15 PM PDT 24
Peak memory 218940 kb
Host smart-dd177872-fb62-4afa-a3ef-b089a237e365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014986796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2014986796
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3343121167
Short name T396
Test name
Test status
Simulation time 20860512 ps
CPU time 0.82 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:12 PM PDT 24
Peak memory 206984 kb
Host smart-fec5060c-62bd-4679-a015-b03ed65b10e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343121167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3343121167
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2808887240
Short name T356
Test name
Test status
Simulation time 4677905318 ps
CPU time 14.15 seconds
Started Apr 25 01:11:12 PM PDT 24
Finished Apr 25 01:11:28 PM PDT 24
Peak memory 240180 kb
Host smart-ab706042-77de-482e-8531-0296100a9b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808887240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2808887240
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.786226988
Short name T7
Test name
Test status
Simulation time 390891243 ps
CPU time 6.4 seconds
Started Apr 25 01:11:13 PM PDT 24
Finished Apr 25 01:11:20 PM PDT 24
Peak memory 221796 kb
Host smart-684f683b-18c4-444d-a73e-ffaac802617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786226988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.786226988
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3017392890
Short name T200
Test name
Test status
Simulation time 1677437345 ps
CPU time 7.3 seconds
Started Apr 25 01:11:19 PM PDT 24
Finished Apr 25 01:11:27 PM PDT 24
Peak memory 218828 kb
Host smart-36dc5f33-04ad-479a-9cec-51537bb6861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017392890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3017392890
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1535242392
Short name T96
Test name
Test status
Simulation time 304890447 ps
CPU time 6.39 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:18 PM PDT 24
Peak memory 223084 kb
Host smart-b7aa73f7-9906-4c54-bbd8-03afaf6722fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1535242392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1535242392
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4236493799
Short name T378
Test name
Test status
Simulation time 2068642259 ps
CPU time 11.53 seconds
Started Apr 25 01:11:12 PM PDT 24
Finished Apr 25 01:11:25 PM PDT 24
Peak memory 216236 kb
Host smart-c11f226d-ca8d-45df-a8e3-1e66cd9e8ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236493799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4236493799
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2755428173
Short name T533
Test name
Test status
Simulation time 34706247251 ps
CPU time 20.95 seconds
Started Apr 25 01:11:10 PM PDT 24
Finished Apr 25 01:11:33 PM PDT 24
Peak memory 216300 kb
Host smart-1f5bced3-7771-49a0-8ae2-74dc11a7c240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755428173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2755428173
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.217526611
Short name T497
Test name
Test status
Simulation time 232262351 ps
CPU time 1.67 seconds
Started Apr 25 01:11:12 PM PDT 24
Finished Apr 25 01:11:15 PM PDT 24
Peak memory 216372 kb
Host smart-c8dddefd-da2f-4232-b769-3980c9f4e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217526611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.217526611
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.616085374
Short name T512
Test name
Test status
Simulation time 70554477 ps
CPU time 0.82 seconds
Started Apr 25 01:11:09 PM PDT 24
Finished Apr 25 01:11:10 PM PDT 24
Peak memory 205744 kb
Host smart-797795e1-7bc0-46d4-9451-e49f87aa5c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616085374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.616085374
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2723956604
Short name T551
Test name
Test status
Simulation time 14658686 ps
CPU time 0.74 seconds
Started Apr 25 01:09:44 PM PDT 24
Finished Apr 25 01:09:47 PM PDT 24
Peak memory 205436 kb
Host smart-0077748e-92c7-4ace-9ae2-b1431035ebea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723956604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
723956604
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1453321058
Short name T685
Test name
Test status
Simulation time 34085641 ps
CPU time 0.81 seconds
Started Apr 25 01:09:40 PM PDT 24
Finished Apr 25 01:09:43 PM PDT 24
Peak memory 206984 kb
Host smart-50af0342-c311-42f2-9d94-f4276a4b82ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453321058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1453321058
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2445007151
Short name T85
Test name
Test status
Simulation time 129054778 ps
CPU time 3.88 seconds
Started Apr 25 01:10:16 PM PDT 24
Finished Apr 25 01:10:21 PM PDT 24
Peak memory 218924 kb
Host smart-010a8f1a-828c-446f-9d89-eb3058c0c966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445007151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2445007151
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2731131126
Short name T274
Test name
Test status
Simulation time 1160730629 ps
CPU time 6.54 seconds
Started Apr 25 01:09:43 PM PDT 24
Finished Apr 25 01:09:51 PM PDT 24
Peak memory 216896 kb
Host smart-7e0f0318-f7cb-403c-bb75-de161eae2725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731131126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2731131126
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.611077685
Short name T530
Test name
Test status
Simulation time 861951011 ps
CPU time 2.79 seconds
Started Apr 25 01:09:38 PM PDT 24
Finished Apr 25 01:09:43 PM PDT 24
Peak memory 218948 kb
Host smart-b138a032-5841-48cb-9679-b64f02fec66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611077685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.611077685
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1007297968
Short name T553
Test name
Test status
Simulation time 914537885 ps
CPU time 7.52 seconds
Started Apr 25 01:09:40 PM PDT 24
Finished Apr 25 01:09:49 PM PDT 24
Peak memory 219428 kb
Host smart-c1a73e64-bb86-45c2-b9bb-313063036baf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1007297968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1007297968
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1509025226
Short name T47
Test name
Test status
Simulation time 277948858 ps
CPU time 1.15 seconds
Started Apr 25 01:09:44 PM PDT 24
Finished Apr 25 01:09:47 PM PDT 24
Peak memory 235076 kb
Host smart-f189afd7-b976-4b4e-a16e-dd2aa5e9610b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509025226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1509025226
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.359543519
Short name T505
Test name
Test status
Simulation time 1297446525 ps
CPU time 22.03 seconds
Started Apr 25 01:09:41 PM PDT 24
Finished Apr 25 01:10:05 PM PDT 24
Peak memory 216244 kb
Host smart-eb5797f2-9376-4abb-b5bc-3bacf26d1b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359543519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.359543519
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2870013813
Short name T631
Test name
Test status
Simulation time 14027452682 ps
CPU time 13.18 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:10:00 PM PDT 24
Peak memory 216276 kb
Host smart-bf09f227-ceb4-478b-bff0-93c47690570f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870013813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2870013813
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3107852287
Short name T55
Test name
Test status
Simulation time 104299457 ps
CPU time 1.26 seconds
Started Apr 25 01:09:38 PM PDT 24
Finished Apr 25 01:09:41 PM PDT 24
Peak memory 207356 kb
Host smart-ac21543c-525e-40dd-a70f-5df6b308ce6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107852287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3107852287
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3170886864
Short name T693
Test name
Test status
Simulation time 541514719 ps
CPU time 1.09 seconds
Started Apr 25 01:09:39 PM PDT 24
Finished Apr 25 01:09:42 PM PDT 24
Peak memory 206828 kb
Host smart-38e55450-2d4b-46f7-a61f-bee5c32e55e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170886864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3170886864
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3755514586
Short name T610
Test name
Test status
Simulation time 42171560 ps
CPU time 0.76 seconds
Started Apr 25 01:11:21 PM PDT 24
Finished Apr 25 01:11:23 PM PDT 24
Peak memory 205364 kb
Host smart-a7a4e0a4-48cd-47c7-8e91-f10e5099055d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755514586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3755514586
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2557804037
Short name T706
Test name
Test status
Simulation time 31126203 ps
CPU time 0.76 seconds
Started Apr 25 01:11:16 PM PDT 24
Finished Apr 25 01:11:18 PM PDT 24
Peak memory 206620 kb
Host smart-9dc16931-719f-418a-88ff-67b6677ea3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557804037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2557804037
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1932695900
Short name T509
Test name
Test status
Simulation time 66613691964 ps
CPU time 92.33 seconds
Started Apr 25 01:11:22 PM PDT 24
Finished Apr 25 01:12:55 PM PDT 24
Peak memory 248464 kb
Host smart-f167b215-dcdc-41c8-89fc-f96bc2f6f299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932695900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1932695900
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3057083015
Short name T83
Test name
Test status
Simulation time 342368755 ps
CPU time 5.18 seconds
Started Apr 25 01:11:20 PM PDT 24
Finished Apr 25 01:11:26 PM PDT 24
Peak memory 216628 kb
Host smart-a54a080e-3cb3-473c-8a16-dc5830953f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057083015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3057083015
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.31884597
Short name T112
Test name
Test status
Simulation time 3795261386 ps
CPU time 11.65 seconds
Started Apr 25 01:11:17 PM PDT 24
Finished Apr 25 01:11:30 PM PDT 24
Peak memory 221400 kb
Host smart-f586adde-80c4-4f05-b23c-f630443a8252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31884597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.31884597
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2515933107
Short name T180
Test name
Test status
Simulation time 3224084881 ps
CPU time 9.21 seconds
Started Apr 25 01:11:18 PM PDT 24
Finished Apr 25 01:11:28 PM PDT 24
Peak memory 218924 kb
Host smart-d8cf3e2a-ef74-438f-a1e8-e83c6a9123f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515933107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2515933107
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.164411210
Short name T194
Test name
Test status
Simulation time 16640097846 ps
CPU time 15.37 seconds
Started Apr 25 01:11:20 PM PDT 24
Finished Apr 25 01:11:36 PM PDT 24
Peak memory 236244 kb
Host smart-ced84b9e-5268-4abf-adfd-8428fa05241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164411210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.164411210
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2185502531
Short name T416
Test name
Test status
Simulation time 374792256 ps
CPU time 3.93 seconds
Started Apr 25 01:11:17 PM PDT 24
Finished Apr 25 01:11:22 PM PDT 24
Peak memory 223020 kb
Host smart-3efb00d7-1ea9-4f06-a4ef-9545b4db5c38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2185502531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2185502531
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2684940576
Short name T546
Test name
Test status
Simulation time 170544077 ps
CPU time 0.97 seconds
Started Apr 25 01:11:24 PM PDT 24
Finished Apr 25 01:11:25 PM PDT 24
Peak memory 207100 kb
Host smart-b911d66d-59d3-4a3d-a0f8-088b9466cdd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684940576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2684940576
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1306770201
Short name T422
Test name
Test status
Simulation time 654315896 ps
CPU time 1.59 seconds
Started Apr 25 01:11:20 PM PDT 24
Finished Apr 25 01:11:22 PM PDT 24
Peak memory 207864 kb
Host smart-950e1483-d901-4bae-aac3-8cde24c20537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306770201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1306770201
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2507771319
Short name T392
Test name
Test status
Simulation time 115641401 ps
CPU time 1.58 seconds
Started Apr 25 01:11:15 PM PDT 24
Finished Apr 25 01:11:17 PM PDT 24
Peak memory 216368 kb
Host smart-14a43698-16b5-4df1-b26c-c947a8971cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507771319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2507771319
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2317487244
Short name T702
Test name
Test status
Simulation time 91051147 ps
CPU time 0.76 seconds
Started Apr 25 01:11:20 PM PDT 24
Finished Apr 25 01:11:21 PM PDT 24
Peak memory 205760 kb
Host smart-7dd4d436-4f5d-4560-81d9-2ddf113f3e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317487244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2317487244
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.4241431468
Short name T330
Test name
Test status
Simulation time 4485773982 ps
CPU time 16.61 seconds
Started Apr 25 01:11:21 PM PDT 24
Finished Apr 25 01:11:39 PM PDT 24
Peak memory 223624 kb
Host smart-8de17a07-1adb-4393-afba-2ba096c084c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241431468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4241431468
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2999936373
Short name T526
Test name
Test status
Simulation time 11031212 ps
CPU time 0.71 seconds
Started Apr 25 01:11:23 PM PDT 24
Finished Apr 25 01:11:24 PM PDT 24
Peak memory 205488 kb
Host smart-26dc2a37-84ec-4d42-a6ab-7743d0c3e622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999936373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2999936373
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1848584754
Short name T523
Test name
Test status
Simulation time 42018012 ps
CPU time 0.76 seconds
Started Apr 25 01:11:23 PM PDT 24
Finished Apr 25 01:11:25 PM PDT 24
Peak memory 205644 kb
Host smart-2bbc3e82-0e69-476f-ab36-c80520cc754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848584754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1848584754
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1847188327
Short name T288
Test name
Test status
Simulation time 4633484182 ps
CPU time 67.88 seconds
Started Apr 25 01:11:21 PM PDT 24
Finished Apr 25 01:12:29 PM PDT 24
Peak memory 254484 kb
Host smart-e70231d1-b986-4674-8b4f-8bd7b12a9e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847188327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1847188327
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3970009395
Short name T190
Test name
Test status
Simulation time 8047245911 ps
CPU time 15.32 seconds
Started Apr 25 01:11:22 PM PDT 24
Finished Apr 25 01:11:39 PM PDT 24
Peak memory 222940 kb
Host smart-bb557559-965d-4046-b642-7dfc57e47c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970009395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3970009395
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2832194678
Short name T639
Test name
Test status
Simulation time 2061468644 ps
CPU time 18.76 seconds
Started Apr 25 01:11:25 PM PDT 24
Finished Apr 25 01:11:45 PM PDT 24
Peak memory 224420 kb
Host smart-25a7e6c1-ab47-4998-a0ee-53c403a5ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832194678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2832194678
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1389703948
Short name T272
Test name
Test status
Simulation time 2787636088 ps
CPU time 6.4 seconds
Started Apr 25 01:11:24 PM PDT 24
Finished Apr 25 01:11:31 PM PDT 24
Peak memory 224324 kb
Host smart-fef13c22-ac25-4870-aee2-4ecb745c8144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389703948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1389703948
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2472762632
Short name T435
Test name
Test status
Simulation time 157792785 ps
CPU time 3.85 seconds
Started Apr 25 01:11:26 PM PDT 24
Finished Apr 25 01:11:31 PM PDT 24
Peak memory 222812 kb
Host smart-b42ca2cf-1aee-4efd-ba6d-9def60d16d1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2472762632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2472762632
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1043362969
Short name T633
Test name
Test status
Simulation time 193316526 ps
CPU time 4.51 seconds
Started Apr 25 01:11:22 PM PDT 24
Finished Apr 25 01:11:28 PM PDT 24
Peak memory 216376 kb
Host smart-009a8458-954a-448e-b7c4-50d3987e8ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043362969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1043362969
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3306847474
Short name T645
Test name
Test status
Simulation time 7457312266 ps
CPU time 24.98 seconds
Started Apr 25 01:11:24 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 216184 kb
Host smart-398a1198-fd0d-4186-a472-478fe7e6cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306847474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3306847474
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.113428469
Short name T475
Test name
Test status
Simulation time 108333247 ps
CPU time 1.18 seconds
Started Apr 25 01:11:22 PM PDT 24
Finished Apr 25 01:11:24 PM PDT 24
Peak memory 216244 kb
Host smart-981cf763-79de-4dc2-be4e-410156a7a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113428469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.113428469
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2731450096
Short name T557
Test name
Test status
Simulation time 118321786 ps
CPU time 1.02 seconds
Started Apr 25 01:11:23 PM PDT 24
Finished Apr 25 01:11:25 PM PDT 24
Peak memory 206736 kb
Host smart-dfc298f9-6231-41fd-9593-9c398f28c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731450096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2731450096
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1399334581
Short name T181
Test name
Test status
Simulation time 385393822 ps
CPU time 3.56 seconds
Started Apr 25 01:11:22 PM PDT 24
Finished Apr 25 01:11:26 PM PDT 24
Peak memory 221528 kb
Host smart-5cd1acff-106e-4426-943e-438ec1417713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399334581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1399334581
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4209223671
Short name T444
Test name
Test status
Simulation time 16432883 ps
CPU time 0.72 seconds
Started Apr 25 01:11:30 PM PDT 24
Finished Apr 25 01:11:32 PM PDT 24
Peak memory 205372 kb
Host smart-ca02d84b-e101-42eb-a33c-0ff500be4fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209223671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4209223671
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4239776689
Short name T458
Test name
Test status
Simulation time 18374262 ps
CPU time 0.82 seconds
Started Apr 25 01:11:22 PM PDT 24
Finished Apr 25 01:11:24 PM PDT 24
Peak memory 206620 kb
Host smart-3bf7dc50-2e5c-46ec-b192-66e2e010ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239776689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4239776689
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3026001621
Short name T302
Test name
Test status
Simulation time 12490233402 ps
CPU time 72.63 seconds
Started Apr 25 01:11:33 PM PDT 24
Finished Apr 25 01:12:46 PM PDT 24
Peak memory 224120 kb
Host smart-2063b627-bf96-4db2-93d4-be1b54d5dba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026001621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3026001621
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2344813420
Short name T310
Test name
Test status
Simulation time 10696144724 ps
CPU time 30.58 seconds
Started Apr 25 01:11:29 PM PDT 24
Finished Apr 25 01:12:01 PM PDT 24
Peak memory 221220 kb
Host smart-b2b7020c-c861-4afb-ac84-257fdfe86f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344813420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2344813420
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1675965930
Short name T412
Test name
Test status
Simulation time 660445534 ps
CPU time 6.67 seconds
Started Apr 25 01:11:32 PM PDT 24
Finished Apr 25 01:11:39 PM PDT 24
Peak memory 222004 kb
Host smart-a5221ffd-7a93-4a59-ae84-3cf93430c643
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1675965930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1675965930
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2944411344
Short name T455
Test name
Test status
Simulation time 1375914866 ps
CPU time 9.31 seconds
Started Apr 25 01:11:21 PM PDT 24
Finished Apr 25 01:11:31 PM PDT 24
Peak memory 216268 kb
Host smart-249980d1-4f6a-4ee3-91ef-e81c905871a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944411344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2944411344
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3699320909
Short name T472
Test name
Test status
Simulation time 127992036 ps
CPU time 2.7 seconds
Started Apr 25 01:11:29 PM PDT 24
Finished Apr 25 01:11:33 PM PDT 24
Peak memory 216320 kb
Host smart-c124a4e9-8cf2-4712-8644-b90c368e829d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699320909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3699320909
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.456946529
Short name T677
Test name
Test status
Simulation time 189128857 ps
CPU time 0.87 seconds
Started Apr 25 01:11:22 PM PDT 24
Finished Apr 25 01:11:23 PM PDT 24
Peak memory 205784 kb
Host smart-d0acdaed-592e-479e-bd69-38dc59b13566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456946529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.456946529
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3277986741
Short name T632
Test name
Test status
Simulation time 14215417 ps
CPU time 0.69 seconds
Started Apr 25 01:11:35 PM PDT 24
Finished Apr 25 01:11:36 PM PDT 24
Peak memory 204844 kb
Host smart-9574a096-015b-4955-a7b4-4114e1b3f0a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277986741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3277986741
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2528097307
Short name T605
Test name
Test status
Simulation time 913399957 ps
CPU time 11.14 seconds
Started Apr 25 01:11:31 PM PDT 24
Finished Apr 25 01:11:43 PM PDT 24
Peak memory 218880 kb
Host smart-07cfc816-7014-490b-997d-533e6f7a7a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528097307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2528097307
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1276224178
Short name T626
Test name
Test status
Simulation time 34308358 ps
CPU time 0.76 seconds
Started Apr 25 01:11:30 PM PDT 24
Finished Apr 25 01:11:31 PM PDT 24
Peak memory 206688 kb
Host smart-e7844870-4142-46f5-b51d-d6f66e281e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276224178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1276224178
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3477297580
Short name T679
Test name
Test status
Simulation time 11669642389 ps
CPU time 86.27 seconds
Started Apr 25 01:12:07 PM PDT 24
Finished Apr 25 01:13:34 PM PDT 24
Peak memory 240200 kb
Host smart-3ed97143-6ee9-43d1-88d7-dff48f636aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477297580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3477297580
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4008717454
Short name T351
Test name
Test status
Simulation time 2765836521 ps
CPU time 26.52 seconds
Started Apr 25 01:11:28 PM PDT 24
Finished Apr 25 01:11:55 PM PDT 24
Peak memory 232768 kb
Host smart-231ff72b-8d95-4654-865f-b7ccb36d126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008717454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4008717454
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3079620401
Short name T198
Test name
Test status
Simulation time 573420880 ps
CPU time 4.51 seconds
Started Apr 25 01:11:28 PM PDT 24
Finished Apr 25 01:11:34 PM PDT 24
Peak memory 222884 kb
Host smart-a230d27a-c6dd-4075-859c-7ca6039d57db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079620401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3079620401
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.102755731
Short name T169
Test name
Test status
Simulation time 159141192 ps
CPU time 2.73 seconds
Started Apr 25 01:11:29 PM PDT 24
Finished Apr 25 01:11:33 PM PDT 24
Peak memory 220248 kb
Host smart-02b04f58-17cf-4512-ac11-4a1b253c3210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102755731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.102755731
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4201041288
Short name T432
Test name
Test status
Simulation time 897888710 ps
CPU time 10.49 seconds
Started Apr 25 01:11:30 PM PDT 24
Finished Apr 25 01:11:42 PM PDT 24
Peak memory 222500 kb
Host smart-5ed89cf6-efe1-4ef4-b040-edc2422b8c7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4201041288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4201041288
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2448887286
Short name T60
Test name
Test status
Simulation time 4010467003 ps
CPU time 18.92 seconds
Started Apr 25 01:11:30 PM PDT 24
Finished Apr 25 01:11:50 PM PDT 24
Peak memory 216368 kb
Host smart-ea782999-da07-42c7-b693-ec4d8b5e27f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448887286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2448887286
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2905299855
Short name T491
Test name
Test status
Simulation time 6198382438 ps
CPU time 6.71 seconds
Started Apr 25 01:11:29 PM PDT 24
Finished Apr 25 01:11:37 PM PDT 24
Peak memory 216324 kb
Host smart-b010e9f9-9e81-4e5f-a542-f5c6a876eda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905299855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2905299855
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.801016063
Short name T643
Test name
Test status
Simulation time 151239597 ps
CPU time 5.65 seconds
Started Apr 25 01:11:28 PM PDT 24
Finished Apr 25 01:11:34 PM PDT 24
Peak memory 216252 kb
Host smart-b741becb-44fb-418a-930e-932172f66e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801016063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.801016063
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3078027633
Short name T102
Test name
Test status
Simulation time 64608325 ps
CPU time 0.83 seconds
Started Apr 25 01:11:28 PM PDT 24
Finished Apr 25 01:11:30 PM PDT 24
Peak memory 205644 kb
Host smart-244ab711-26d9-49b4-b378-9c4bef198644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078027633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3078027633
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2208522981
Short name T550
Test name
Test status
Simulation time 14652872 ps
CPU time 0.74 seconds
Started Apr 25 01:11:40 PM PDT 24
Finished Apr 25 01:11:42 PM PDT 24
Peak memory 204844 kb
Host smart-80b40de4-e327-40e0-ab08-5a7468061c0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208522981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2208522981
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2468949758
Short name T187
Test name
Test status
Simulation time 56695958 ps
CPU time 2.19 seconds
Started Apr 25 01:11:34 PM PDT 24
Finished Apr 25 01:11:37 PM PDT 24
Peak memory 223052 kb
Host smart-0c197030-3e6a-4a2f-bf06-5d5ab1b47909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468949758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2468949758
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2269878977
Short name T474
Test name
Test status
Simulation time 25924840 ps
CPU time 0.78 seconds
Started Apr 25 01:11:35 PM PDT 24
Finished Apr 25 01:11:37 PM PDT 24
Peak memory 206672 kb
Host smart-cf7babfe-f4fa-4f30-9e8c-eabbb3788bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269878977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2269878977
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3444976008
Short name T257
Test name
Test status
Simulation time 684058712 ps
CPU time 3.71 seconds
Started Apr 25 01:11:34 PM PDT 24
Finished Apr 25 01:11:38 PM PDT 24
Peak memory 221480 kb
Host smart-f7854855-56b7-4a6a-8df1-5532fe6889f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444976008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3444976008
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1334732792
Short name T255
Test name
Test status
Simulation time 269245822 ps
CPU time 2.45 seconds
Started Apr 25 01:11:46 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 222776 kb
Host smart-6f22f665-a47a-4a7d-b70a-d1a5c5cb569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334732792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1334732792
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3780578569
Short name T420
Test name
Test status
Simulation time 3174778671 ps
CPU time 11.18 seconds
Started Apr 25 01:11:36 PM PDT 24
Finished Apr 25 01:11:48 PM PDT 24
Peak memory 220032 kb
Host smart-9b5ac416-67c7-429f-9bee-2dcb2170aeb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3780578569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3780578569
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3780859817
Short name T608
Test name
Test status
Simulation time 4438389694 ps
CPU time 10.78 seconds
Started Apr 25 01:11:40 PM PDT 24
Finished Apr 25 01:11:52 PM PDT 24
Peak memory 216320 kb
Host smart-94352bf3-b000-4dc1-8760-ed3386564c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780859817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3780859817
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3321115276
Short name T65
Test name
Test status
Simulation time 50814875 ps
CPU time 1.14 seconds
Started Apr 25 01:11:40 PM PDT 24
Finished Apr 25 01:11:42 PM PDT 24
Peak memory 207120 kb
Host smart-a5e28e1b-7eff-4517-a8a1-f22467beb832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321115276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3321115276
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2830032390
Short name T513
Test name
Test status
Simulation time 109480136 ps
CPU time 0.75 seconds
Started Apr 25 01:11:40 PM PDT 24
Finished Apr 25 01:11:42 PM PDT 24
Peak memory 205768 kb
Host smart-59973507-216e-43e1-9f51-b7b13aa46c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830032390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2830032390
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2939734194
Short name T414
Test name
Test status
Simulation time 38810789 ps
CPU time 0.7 seconds
Started Apr 25 01:11:41 PM PDT 24
Finished Apr 25 01:11:43 PM PDT 24
Peak memory 204836 kb
Host smart-e7fed10e-4b1a-4591-a5ef-172304a5cd49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939734194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2939734194
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1061360720
Short name T508
Test name
Test status
Simulation time 21025574 ps
CPU time 0.81 seconds
Started Apr 25 01:11:46 PM PDT 24
Finished Apr 25 01:11:48 PM PDT 24
Peak memory 206812 kb
Host smart-aaaf9019-1fa1-4c5a-8177-4cd17a499471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061360720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1061360720
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3936302632
Short name T354
Test name
Test status
Simulation time 17042915965 ps
CPU time 45.1 seconds
Started Apr 25 01:11:46 PM PDT 24
Finished Apr 25 01:12:32 PM PDT 24
Peak memory 240044 kb
Host smart-bf960590-8139-44ce-9d49-cf07ef92b237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936302632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3936302632
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4042962909
Short name T318
Test name
Test status
Simulation time 1654481456 ps
CPU time 5.95 seconds
Started Apr 25 01:11:36 PM PDT 24
Finished Apr 25 01:11:43 PM PDT 24
Peak memory 218516 kb
Host smart-442ace8d-5e24-4e2b-96f7-9d32fd561da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042962909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4042962909
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.346452654
Short name T224
Test name
Test status
Simulation time 14147275530 ps
CPU time 120.17 seconds
Started Apr 25 01:11:35 PM PDT 24
Finished Apr 25 01:13:36 PM PDT 24
Peak memory 232812 kb
Host smart-cf4a957b-9b71-4dec-8746-912dd69366b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346452654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.346452654
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.486679353
Short name T176
Test name
Test status
Simulation time 13389972291 ps
CPU time 9.79 seconds
Started Apr 25 01:11:40 PM PDT 24
Finished Apr 25 01:11:50 PM PDT 24
Peak memory 223468 kb
Host smart-2fb2a223-49b4-4835-b85a-f9d3d600a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486679353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.486679353
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2513723930
Short name T538
Test name
Test status
Simulation time 890666316 ps
CPU time 5.07 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 222380 kb
Host smart-3e1a27a8-5700-4c86-b9fe-164bbe11ef12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2513723930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2513723930
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4286520427
Short name T381
Test name
Test status
Simulation time 9073068253 ps
CPU time 48.78 seconds
Started Apr 25 01:11:35 PM PDT 24
Finished Apr 25 01:12:25 PM PDT 24
Peak memory 216396 kb
Host smart-e052e005-9109-46e3-9818-bdbc1e5ec362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286520427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4286520427
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4056867711
Short name T671
Test name
Test status
Simulation time 50499730468 ps
CPU time 33.76 seconds
Started Apr 25 01:11:35 PM PDT 24
Finished Apr 25 01:12:10 PM PDT 24
Peak memory 217316 kb
Host smart-2bf7caee-3d2b-4dcc-b021-be357b008f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056867711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4056867711
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4180767900
Short name T591
Test name
Test status
Simulation time 62507464 ps
CPU time 1.84 seconds
Started Apr 25 01:11:46 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 216176 kb
Host smart-8fe3ef6f-c857-4a7b-a1a6-208874d69a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180767900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4180767900
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3193202378
Short name T525
Test name
Test status
Simulation time 210845364 ps
CPU time 0.85 seconds
Started Apr 25 01:11:39 PM PDT 24
Finished Apr 25 01:11:41 PM PDT 24
Peak memory 205760 kb
Host smart-3dc76a92-f202-4235-8229-a1af45b4054b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193202378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3193202378
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3460447782
Short name T201
Test name
Test status
Simulation time 583442804 ps
CPU time 3.43 seconds
Started Apr 25 01:11:33 PM PDT 24
Finished Apr 25 01:11:37 PM PDT 24
Peak memory 222588 kb
Host smart-ca174bee-4750-4148-8a14-13b8df4edbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460447782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3460447782
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1184291348
Short name T486
Test name
Test status
Simulation time 44876465 ps
CPU time 0.71 seconds
Started Apr 25 01:11:45 PM PDT 24
Finished Apr 25 01:11:46 PM PDT 24
Peak memory 204716 kb
Host smart-a9352fde-e447-402a-9330-68d9332d6a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184291348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1184291348
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.638539874
Short name T531
Test name
Test status
Simulation time 58160356 ps
CPU time 0.71 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:11:45 PM PDT 24
Peak memory 205888 kb
Host smart-3c328725-bb91-4bb7-b1a6-92a12fb5988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638539874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.638539874
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2332450814
Short name T280
Test name
Test status
Simulation time 4874449732 ps
CPU time 65.53 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:12:50 PM PDT 24
Peak memory 232772 kb
Host smart-2e7f268c-8a88-4897-834f-c334ce94b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332450814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2332450814
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3548512633
Short name T221
Test name
Test status
Simulation time 6734112298 ps
CPU time 16.24 seconds
Started Apr 25 01:11:42 PM PDT 24
Finished Apr 25 01:11:59 PM PDT 24
Peak memory 218544 kb
Host smart-93662070-8b4b-4499-a205-f9113781d2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548512633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3548512633
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2280857875
Short name T4
Test name
Test status
Simulation time 9433186908 ps
CPU time 25.06 seconds
Started Apr 25 01:11:39 PM PDT 24
Finished Apr 25 01:12:05 PM PDT 24
Peak memory 224544 kb
Host smart-51c349c7-b9ee-4be7-a29a-485c85799594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280857875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2280857875
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3329484462
Short name T599
Test name
Test status
Simulation time 1296067035 ps
CPU time 4.78 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 223036 kb
Host smart-e634e65c-11a7-4ad4-afb7-387fb7e8e684
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3329484462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3329484462
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1741127347
Short name T159
Test name
Test status
Simulation time 93287622 ps
CPU time 0.95 seconds
Started Apr 25 01:11:42 PM PDT 24
Finished Apr 25 01:11:45 PM PDT 24
Peak memory 207112 kb
Host smart-d0fdfd5b-dc6e-4a13-ab03-497fb898616b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741127347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1741127347
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1827121063
Short name T372
Test name
Test status
Simulation time 2225802954 ps
CPU time 33.68 seconds
Started Apr 25 01:11:43 PM PDT 24
Finished Apr 25 01:12:18 PM PDT 24
Peak memory 216312 kb
Host smart-9214002f-c732-492a-a43e-776a6d8fff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827121063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1827121063
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4256129354
Short name T524
Test name
Test status
Simulation time 6621395312 ps
CPU time 10.99 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:11:55 PM PDT 24
Peak memory 216300 kb
Host smart-b78f55d6-c944-4652-94d9-13be49c4e42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256129354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4256129354
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1715506778
Short name T644
Test name
Test status
Simulation time 39824116 ps
CPU time 1.09 seconds
Started Apr 25 01:11:41 PM PDT 24
Finished Apr 25 01:11:43 PM PDT 24
Peak memory 207872 kb
Host smart-f12aee88-32e5-4105-9986-7ffa006c2954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715506778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1715506778
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.158425272
Short name T442
Test name
Test status
Simulation time 243693155 ps
CPU time 0.95 seconds
Started Apr 25 01:11:43 PM PDT 24
Finished Apr 25 01:11:45 PM PDT 24
Peak memory 206816 kb
Host smart-c6ec384a-bd7c-4af4-a5bc-2fc9699cb103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158425272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.158425272
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1212396991
Short name T628
Test name
Test status
Simulation time 11024415 ps
CPU time 0.73 seconds
Started Apr 25 01:11:48 PM PDT 24
Finished Apr 25 01:11:50 PM PDT 24
Peak memory 205396 kb
Host smart-9fd8b00f-6bd8-43e0-bb98-282bbf8c705b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212396991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1212396991
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1966261750
Short name T397
Test name
Test status
Simulation time 42378987 ps
CPU time 0.73 seconds
Started Apr 25 01:11:44 PM PDT 24
Finished Apr 25 01:11:45 PM PDT 24
Peak memory 205972 kb
Host smart-5fcf2331-a619-4474-ac58-ce6c1f25631b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966261750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1966261750
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1545264298
Short name T289
Test name
Test status
Simulation time 10664029725 ps
CPU time 36.37 seconds
Started Apr 25 01:11:48 PM PDT 24
Finished Apr 25 01:12:26 PM PDT 24
Peak memory 240924 kb
Host smart-4eb26ef5-e07c-47f7-b5fc-291ff4f8366e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545264298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1545264298
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2222073561
Short name T504
Test name
Test status
Simulation time 5541784738 ps
CPU time 27.64 seconds
Started Apr 25 01:11:48 PM PDT 24
Finished Apr 25 01:12:17 PM PDT 24
Peak memory 218564 kb
Host smart-2c4cee89-abe3-42dd-aa6b-c2e8f17a1778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222073561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2222073561
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3326121864
Short name T460
Test name
Test status
Simulation time 1251493946 ps
CPU time 10.21 seconds
Started Apr 25 01:11:47 PM PDT 24
Finished Apr 25 01:11:59 PM PDT 24
Peak memory 219252 kb
Host smart-cf787ee2-90e1-4d98-9b96-a4fcee3d008f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3326121864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3326121864
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.36958596
Short name T343
Test name
Test status
Simulation time 243429929 ps
CPU time 1.14 seconds
Started Apr 25 01:11:47 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 207272 kb
Host smart-fe2149f1-6a21-4789-b05c-81fe83a0a7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36958596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress
_all.36958596
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2121909399
Short name T518
Test name
Test status
Simulation time 22274006527 ps
CPU time 31.84 seconds
Started Apr 25 01:11:42 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 216380 kb
Host smart-42353373-f92d-44e5-b336-e4684c5c0bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121909399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2121909399
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2993273000
Short name T463
Test name
Test status
Simulation time 6818034052 ps
CPU time 18.03 seconds
Started Apr 25 01:11:42 PM PDT 24
Finished Apr 25 01:12:01 PM PDT 24
Peak memory 216392 kb
Host smart-22c35918-711f-4f8d-9379-37da642374f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993273000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2993273000
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.361513355
Short name T410
Test name
Test status
Simulation time 26924216 ps
CPU time 1.02 seconds
Started Apr 25 01:11:41 PM PDT 24
Finished Apr 25 01:11:43 PM PDT 24
Peak memory 207408 kb
Host smart-1c80bd17-f670-4df2-a285-e2bf90efade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361513355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.361513355
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2917817230
Short name T619
Test name
Test status
Simulation time 35413007 ps
CPU time 0.79 seconds
Started Apr 25 01:11:43 PM PDT 24
Finished Apr 25 01:11:45 PM PDT 24
Peak memory 205768 kb
Host smart-e4d4779d-a343-4876-ac8e-5742f7932a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917817230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2917817230
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1724858018
Short name T590
Test name
Test status
Simulation time 69163377 ps
CPU time 0.75 seconds
Started Apr 25 01:11:48 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 205724 kb
Host smart-58ec0338-1310-49f0-9d0a-fa7dc2a1af9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724858018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1724858018
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2202194102
Short name T20
Test name
Test status
Simulation time 21181979 ps
CPU time 0.84 seconds
Started Apr 25 01:11:50 PM PDT 24
Finished Apr 25 01:11:52 PM PDT 24
Peak memory 206612 kb
Host smart-17ccbc0f-773a-43d6-bc34-42507e746a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202194102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2202194102
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2067818587
Short name T350
Test name
Test status
Simulation time 1661492410 ps
CPU time 16.36 seconds
Started Apr 25 01:11:46 PM PDT 24
Finished Apr 25 01:12:03 PM PDT 24
Peak memory 234024 kb
Host smart-9536f4c8-57ee-4d0f-abec-6221b819b9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067818587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2067818587
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2798812083
Short name T248
Test name
Test status
Simulation time 12914436931 ps
CPU time 19.66 seconds
Started Apr 25 01:11:49 PM PDT 24
Finished Apr 25 01:12:10 PM PDT 24
Peak memory 226752 kb
Host smart-7d576473-38b3-4193-ad7a-84da4e5acc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798812083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2798812083
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1085396591
Short name T651
Test name
Test status
Simulation time 136187411 ps
CPU time 3.66 seconds
Started Apr 25 01:11:49 PM PDT 24
Finished Apr 25 01:11:54 PM PDT 24
Peak memory 220452 kb
Host smart-ab7829cb-224c-4297-96d0-89c7349063bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1085396591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1085396591
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1187682474
Short name T40
Test name
Test status
Simulation time 88600457 ps
CPU time 0.93 seconds
Started Apr 25 01:11:50 PM PDT 24
Finished Apr 25 01:11:52 PM PDT 24
Peak memory 206080 kb
Host smart-66ae39bc-1b5b-4fe2-a894-3f06a77971d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187682474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1187682474
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1635554392
Short name T709
Test name
Test status
Simulation time 5204482311 ps
CPU time 15.92 seconds
Started Apr 25 01:11:48 PM PDT 24
Finished Apr 25 01:12:05 PM PDT 24
Peak memory 216380 kb
Host smart-d9a1f190-0c4f-46a5-9e20-4d79b5393604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635554392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1635554392
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4230997941
Short name T82
Test name
Test status
Simulation time 475885706 ps
CPU time 2.26 seconds
Started Apr 25 01:11:48 PM PDT 24
Finished Apr 25 01:11:51 PM PDT 24
Peak memory 216316 kb
Host smart-b30c3b13-b731-4ddc-81b9-be2e93767886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230997941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4230997941
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2775659355
Short name T647
Test name
Test status
Simulation time 17285420 ps
CPU time 1 seconds
Started Apr 25 01:11:47 PM PDT 24
Finished Apr 25 01:11:49 PM PDT 24
Peak memory 206864 kb
Host smart-070b0aa3-5ad2-4a3f-b1ab-2faa389476f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775659355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2775659355
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.927876495
Short name T489
Test name
Test status
Simulation time 77374835 ps
CPU time 0.85 seconds
Started Apr 25 01:11:48 PM PDT 24
Finished Apr 25 01:11:50 PM PDT 24
Peak memory 206748 kb
Host smart-0e4d6db1-5071-4c5e-a350-3254878cbfb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927876495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.927876495
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.5408306
Short name T32
Test name
Test status
Simulation time 47886112 ps
CPU time 0.79 seconds
Started Apr 25 01:11:53 PM PDT 24
Finished Apr 25 01:11:55 PM PDT 24
Peak memory 205344 kb
Host smart-a552b26c-660d-4ab1-8ab8-4e4f94993170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5408306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.5408306
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.806247545
Short name T480
Test name
Test status
Simulation time 38457399 ps
CPU time 0.76 seconds
Started Apr 25 01:11:47 PM PDT 24
Finished Apr 25 01:11:48 PM PDT 24
Peak memory 206604 kb
Host smart-834e4b8d-414b-457b-be6b-689cc276fe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806247545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.806247545
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.9065598
Short name T275
Test name
Test status
Simulation time 16879803204 ps
CPU time 58.83 seconds
Started Apr 25 01:11:53 PM PDT 24
Finished Apr 25 01:12:53 PM PDT 24
Peak memory 249188 kb
Host smart-fcbb3e7a-2e84-4bef-bbc9-8ceb4543c166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9065598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.9065598
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4180327192
Short name T320
Test name
Test status
Simulation time 36207544209 ps
CPU time 62.2 seconds
Started Apr 25 01:11:58 PM PDT 24
Finished Apr 25 01:13:01 PM PDT 24
Peak memory 240576 kb
Host smart-8d838294-201d-438b-9a13-c050a87534f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180327192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4180327192
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1274286694
Short name T220
Test name
Test status
Simulation time 113596369 ps
CPU time 2.3 seconds
Started Apr 25 01:11:52 PM PDT 24
Finished Apr 25 01:11:55 PM PDT 24
Peak memory 218792 kb
Host smart-f0b61ac1-f138-45fd-a788-9235c1b6d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274286694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1274286694
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.886114011
Short name T629
Test name
Test status
Simulation time 227834416 ps
CPU time 3.52 seconds
Started Apr 25 01:11:55 PM PDT 24
Finished Apr 25 01:11:59 PM PDT 24
Peak memory 220108 kb
Host smart-7d002c80-5b89-497d-9504-b4121bcf5404
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886114011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.886114011
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1133520547
Short name T373
Test name
Test status
Simulation time 6430919613 ps
CPU time 19.53 seconds
Started Apr 25 01:11:49 PM PDT 24
Finished Apr 25 01:12:10 PM PDT 24
Peak memory 216680 kb
Host smart-84d74330-f3c7-4b31-a564-681f06548116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133520547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1133520547
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3215290562
Short name T584
Test name
Test status
Simulation time 3951196632 ps
CPU time 6.04 seconds
Started Apr 25 01:11:51 PM PDT 24
Finished Apr 25 01:11:58 PM PDT 24
Peak memory 216156 kb
Host smart-3d8837a2-e435-44db-b46b-b661a4801cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215290562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3215290562
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3834788758
Short name T387
Test name
Test status
Simulation time 114012418 ps
CPU time 1.87 seconds
Started Apr 25 01:11:46 PM PDT 24
Finished Apr 25 01:11:48 PM PDT 24
Peak memory 216276 kb
Host smart-ef26f1d7-08e5-4eee-b81a-337e1de964da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834788758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3834788758
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3765681201
Short name T84
Test name
Test status
Simulation time 218533192 ps
CPU time 0.9 seconds
Started Apr 25 01:11:51 PM PDT 24
Finished Apr 25 01:11:53 PM PDT 24
Peak memory 206760 kb
Host smart-61c11a2f-d075-431a-8a0e-7298ea63b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765681201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3765681201
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.837931058
Short name T263
Test name
Test status
Simulation time 3879243580 ps
CPU time 5.17 seconds
Started Apr 25 01:11:53 PM PDT 24
Finished Apr 25 01:11:59 PM PDT 24
Peak memory 216432 kb
Host smart-21d490e6-2275-4463-8abd-1e4c3f27ece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837931058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.837931058
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4094500395
Short name T16
Test name
Test status
Simulation time 39801068 ps
CPU time 0.71 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:09:58 PM PDT 24
Peak memory 205712 kb
Host smart-ae485485-27a1-4af2-af93-084e7843b6d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094500395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
094500395
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3759275910
Short name T699
Test name
Test status
Simulation time 23497355 ps
CPU time 0.82 seconds
Started Apr 25 01:09:46 PM PDT 24
Finished Apr 25 01:09:49 PM PDT 24
Peak memory 206720 kb
Host smart-f42a775b-7d02-4b96-bb4e-9299cf0d2cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759275910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3759275910
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3452441750
Short name T278
Test name
Test status
Simulation time 1737115951 ps
CPU time 17.31 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:10:04 PM PDT 24
Peak memory 232644 kb
Host smart-08177c3f-3a83-48c2-b550-47b399dcc3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452441750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3452441750
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3828861767
Short name T166
Test name
Test status
Simulation time 307948463 ps
CPU time 5.24 seconds
Started Apr 25 01:10:12 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 222648 kb
Host smart-141c6735-82d3-45a6-a41b-613c245c5b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828861767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3828861767
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1074934144
Short name T540
Test name
Test status
Simulation time 810918980 ps
CPU time 9.77 seconds
Started Apr 25 01:09:42 PM PDT 24
Finished Apr 25 01:09:54 PM PDT 24
Peak memory 220248 kb
Host smart-18d27aa4-9889-444f-8781-b2c43968e0c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1074934144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1074934144
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.661422476
Short name T44
Test name
Test status
Simulation time 62196811 ps
CPU time 1.07 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:09:58 PM PDT 24
Peak memory 235040 kb
Host smart-73402dab-7a9e-4bb8-a9b4-a98ef4eb6794
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661422476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.661422476
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2933225129
Short name T368
Test name
Test status
Simulation time 1751447147 ps
CPU time 17.95 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:10:05 PM PDT 24
Peak memory 216532 kb
Host smart-b5b2cca1-dfa0-45e8-a92d-8f1990d55f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933225129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2933225129
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3206602685
Short name T586
Test name
Test status
Simulation time 22092933034 ps
CPU time 32.37 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 216372 kb
Host smart-f7acdc9b-ea82-4322-bdad-0f0bcc5ff10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206602685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3206602685
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1983552051
Short name T478
Test name
Test status
Simulation time 18912288 ps
CPU time 0.8 seconds
Started Apr 25 01:09:46 PM PDT 24
Finished Apr 25 01:09:48 PM PDT 24
Peak memory 206256 kb
Host smart-0667b93d-34cc-456f-bbb1-7bf459702e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983552051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1983552051
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1763523809
Short name T418
Test name
Test status
Simulation time 93959732 ps
CPU time 1.08 seconds
Started Apr 25 01:09:43 PM PDT 24
Finished Apr 25 01:09:47 PM PDT 24
Peak memory 206848 kb
Host smart-7b4e7a8d-cd95-401c-b8e4-73dc1581b5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763523809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1763523809
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2457526508
Short name T683
Test name
Test status
Simulation time 15083300 ps
CPU time 0.71 seconds
Started Apr 25 01:12:05 PM PDT 24
Finished Apr 25 01:12:07 PM PDT 24
Peak memory 205328 kb
Host smart-cc0462c8-3e69-4a9f-b58b-d025ca11f696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457526508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2457526508
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2978736940
Short name T604
Test name
Test status
Simulation time 69737457 ps
CPU time 0.77 seconds
Started Apr 25 01:11:53 PM PDT 24
Finished Apr 25 01:11:55 PM PDT 24
Peak memory 206700 kb
Host smart-69afd8ed-3ca1-4557-ab28-515d74e38df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978736940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2978736940
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1688995852
Short name T293
Test name
Test status
Simulation time 33069538297 ps
CPU time 101.88 seconds
Started Apr 25 01:12:03 PM PDT 24
Finished Apr 25 01:13:46 PM PDT 24
Peak memory 233632 kb
Host smart-5d08a1fd-1087-4b38-8849-06f0a0ec1e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688995852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1688995852
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2348240130
Short name T95
Test name
Test status
Simulation time 349648755 ps
CPU time 6.21 seconds
Started Apr 25 01:12:01 PM PDT 24
Finished Apr 25 01:12:08 PM PDT 24
Peak memory 218772 kb
Host smart-10c00a1e-6abf-4ee2-9344-111ebc271f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348240130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2348240130
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.981048481
Short name T690
Test name
Test status
Simulation time 18469264948 ps
CPU time 87.46 seconds
Started Apr 25 01:12:01 PM PDT 24
Finished Apr 25 01:13:29 PM PDT 24
Peak memory 230896 kb
Host smart-e6b259c8-dccb-4ed5-80f5-d128b45ece9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981048481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.981048481
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3106323565
Short name T203
Test name
Test status
Simulation time 9112032031 ps
CPU time 14.36 seconds
Started Apr 25 01:12:03 PM PDT 24
Finished Apr 25 01:12:18 PM PDT 24
Peak memory 222892 kb
Host smart-04f1d9b3-9e63-45ed-8f82-d015f232b02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106323565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3106323565
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2905628655
Short name T196
Test name
Test status
Simulation time 246197044818 ps
CPU time 34.85 seconds
Started Apr 25 01:11:54 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 237596 kb
Host smart-ce357bad-1d36-46bf-b0fd-95302f79d465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905628655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2905628655
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1017969674
Short name T592
Test name
Test status
Simulation time 371397269 ps
CPU time 3.88 seconds
Started Apr 25 01:12:01 PM PDT 24
Finished Apr 25 01:12:06 PM PDT 24
Peak memory 222576 kb
Host smart-0b5e0816-db83-4105-a65e-da861234de4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1017969674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1017969674
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1164387060
Short name T370
Test name
Test status
Simulation time 2569914735 ps
CPU time 35.25 seconds
Started Apr 25 01:11:54 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 216348 kb
Host smart-f8069cff-0a70-48b3-a6af-c548e007b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164387060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1164387060
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.299077780
Short name T572
Test name
Test status
Simulation time 696885918 ps
CPU time 4.88 seconds
Started Apr 25 01:11:54 PM PDT 24
Finished Apr 25 01:12:00 PM PDT 24
Peak memory 216252 kb
Host smart-1fad96d1-ff41-471b-bccf-7938c20afd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299077780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.299077780
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.623632383
Short name T571
Test name
Test status
Simulation time 56561187 ps
CPU time 1.62 seconds
Started Apr 25 01:11:54 PM PDT 24
Finished Apr 25 01:11:56 PM PDT 24
Peak memory 216284 kb
Host smart-c3835716-2521-4b9c-88a0-b000deb1cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623632383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.623632383
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.648689124
Short name T462
Test name
Test status
Simulation time 118388257 ps
CPU time 0.94 seconds
Started Apr 25 01:11:54 PM PDT 24
Finished Apr 25 01:11:55 PM PDT 24
Peak memory 205824 kb
Host smart-503328d2-3450-4d57-b3c1-612fbb96bf78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648689124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.648689124
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.255893628
Short name T708
Test name
Test status
Simulation time 14437300 ps
CPU time 0.82 seconds
Started Apr 25 01:12:15 PM PDT 24
Finished Apr 25 01:12:17 PM PDT 24
Peak memory 205392 kb
Host smart-3d103870-5c10-41ad-8c05-09100d89c550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255893628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.255893628
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.445351339
Short name T22
Test name
Test status
Simulation time 17083179 ps
CPU time 0.85 seconds
Started Apr 25 01:12:04 PM PDT 24
Finished Apr 25 01:12:05 PM PDT 24
Peak memory 206956 kb
Host smart-f929cdd3-f44e-4dc0-9bc0-9d9196f6e228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445351339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.445351339
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3593329933
Short name T89
Test name
Test status
Simulation time 348567927 ps
CPU time 10.07 seconds
Started Apr 25 01:12:03 PM PDT 24
Finished Apr 25 01:12:14 PM PDT 24
Peak memory 239840 kb
Host smart-da5417e7-0f79-4261-bc84-8e266a8460c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593329933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3593329933
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.649287316
Short name T259
Test name
Test status
Simulation time 4010730032 ps
CPU time 5.29 seconds
Started Apr 25 01:12:00 PM PDT 24
Finished Apr 25 01:12:06 PM PDT 24
Peak memory 223112 kb
Host smart-802ab8a2-0906-452f-8971-866e0501929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649287316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.649287316
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.738653269
Short name T71
Test name
Test status
Simulation time 3818872669 ps
CPU time 6.2 seconds
Started Apr 25 01:12:04 PM PDT 24
Finished Apr 25 01:12:11 PM PDT 24
Peak memory 239708 kb
Host smart-b295f676-b1c6-4dcf-891c-d3d06a62927b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738653269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.738653269
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1926714970
Short name T88
Test name
Test status
Simulation time 4031449583 ps
CPU time 9.46 seconds
Started Apr 25 01:12:04 PM PDT 24
Finished Apr 25 01:12:14 PM PDT 24
Peak memory 222964 kb
Host smart-5807dc2e-9a20-4276-864c-b5a1d350c4b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1926714970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1926714970
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3820353599
Short name T34
Test name
Test status
Simulation time 172071877 ps
CPU time 1.06 seconds
Started Apr 25 01:12:16 PM PDT 24
Finished Apr 25 01:12:19 PM PDT 24
Peak memory 206840 kb
Host smart-3dc7149d-e82c-4d1c-8427-56baa389b778
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820353599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3820353599
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1020530718
Short name T616
Test name
Test status
Simulation time 13459490953 ps
CPU time 66.74 seconds
Started Apr 25 01:12:01 PM PDT 24
Finished Apr 25 01:13:09 PM PDT 24
Peak memory 216412 kb
Host smart-00a9b48f-ba87-468b-b828-af1fcea9e03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020530718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1020530718
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2025063860
Short name T451
Test name
Test status
Simulation time 2225138018 ps
CPU time 8.39 seconds
Started Apr 25 01:12:02 PM PDT 24
Finished Apr 25 01:12:11 PM PDT 24
Peak memory 216364 kb
Host smart-d894564c-7d16-41d9-9f96-188315a8bd01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025063860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2025063860
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3291502245
Short name T649
Test name
Test status
Simulation time 100579566 ps
CPU time 4.25 seconds
Started Apr 25 01:12:03 PM PDT 24
Finished Apr 25 01:12:08 PM PDT 24
Peak memory 216384 kb
Host smart-efa48e82-e22f-4830-92ba-6f40be5b832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291502245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3291502245
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1764013202
Short name T625
Test name
Test status
Simulation time 47556374 ps
CPU time 0.79 seconds
Started Apr 25 01:12:03 PM PDT 24
Finished Apr 25 01:12:05 PM PDT 24
Peak memory 205760 kb
Host smart-da9a60b5-e04a-413a-a2ec-e6b4760e67e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764013202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1764013202
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4085788055
Short name T426
Test name
Test status
Simulation time 19761555 ps
CPU time 0.73 seconds
Started Apr 25 01:12:20 PM PDT 24
Finished Apr 25 01:12:22 PM PDT 24
Peak memory 205428 kb
Host smart-97e61ac7-29cd-45d4-bad8-25cfaa8fc103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085788055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4085788055
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2216547291
Short name T688
Test name
Test status
Simulation time 246011676 ps
CPU time 5.92 seconds
Started Apr 25 01:12:17 PM PDT 24
Finished Apr 25 01:12:25 PM PDT 24
Peak memory 232528 kb
Host smart-e0dea2ee-0f4f-467d-813b-fea8e1ce71d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216547291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2216547291
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4162060006
Short name T659
Test name
Test status
Simulation time 16126747 ps
CPU time 0.76 seconds
Started Apr 25 01:12:13 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 206628 kb
Host smart-166961b2-fbe9-4e91-8c47-65de9cf13835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162060006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4162060006
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_intercept.112748669
Short name T271
Test name
Test status
Simulation time 800018865 ps
CPU time 5.6 seconds
Started Apr 25 01:12:06 PM PDT 24
Finished Apr 25 01:12:12 PM PDT 24
Peak memory 232696 kb
Host smart-528031bb-8bde-4f4f-86c7-17bcc31dfb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112748669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.112748669
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.415997296
Short name T593
Test name
Test status
Simulation time 2344450544 ps
CPU time 8.14 seconds
Started Apr 25 01:12:06 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 224496 kb
Host smart-5201ca7c-4194-4501-842b-001940d2de00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415997296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.415997296
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3461978515
Short name T216
Test name
Test status
Simulation time 197198556 ps
CPU time 3.74 seconds
Started Apr 25 01:12:16 PM PDT 24
Finished Apr 25 01:12:22 PM PDT 24
Peak memory 222824 kb
Host smart-c3a01cad-6452-44d4-bdaf-0ac3f650f216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461978515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3461978515
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1374879792
Short name T179
Test name
Test status
Simulation time 1562786425 ps
CPU time 13.69 seconds
Started Apr 25 01:12:09 PM PDT 24
Finished Apr 25 01:12:24 PM PDT 24
Peak memory 239304 kb
Host smart-19fcc689-8ebc-48d4-bf07-2d5ab5e2051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374879792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1374879792
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2892191658
Short name T439
Test name
Test status
Simulation time 283863990 ps
CPU time 5 seconds
Started Apr 25 01:12:09 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 218892 kb
Host smart-52279a67-b76e-4b69-9d1f-110165764027
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2892191658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2892191658
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1440360718
Short name T502
Test name
Test status
Simulation time 16396419405 ps
CPU time 51.96 seconds
Started Apr 25 01:12:07 PM PDT 24
Finished Apr 25 01:12:59 PM PDT 24
Peak memory 216372 kb
Host smart-32a3d1b2-ae94-4244-ba6c-404f7e556692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440360718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1440360718
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1841258070
Short name T501
Test name
Test status
Simulation time 3081860265 ps
CPU time 8.12 seconds
Started Apr 25 01:12:06 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 216408 kb
Host smart-f81ccf47-ccb8-46dd-950c-b1d8550da4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841258070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1841258070
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2545128915
Short name T612
Test name
Test status
Simulation time 241121227 ps
CPU time 1.58 seconds
Started Apr 25 01:12:12 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 216216 kb
Host smart-3837d75c-ea26-4cc9-be10-5f50b9d276fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545128915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2545128915
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4152613297
Short name T23
Test name
Test status
Simulation time 135920917 ps
CPU time 0.81 seconds
Started Apr 25 01:12:13 PM PDT 24
Finished Apr 25 01:12:15 PM PDT 24
Peak memory 205752 kb
Host smart-694cd8e1-8bcf-4734-95f4-df25122a71ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152613297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4152613297
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.360687701
Short name T419
Test name
Test status
Simulation time 25085693 ps
CPU time 0.68 seconds
Started Apr 25 01:12:16 PM PDT 24
Finished Apr 25 01:12:18 PM PDT 24
Peak memory 205468 kb
Host smart-452c8a27-ae26-4746-83f2-c23f489f72bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360687701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.360687701
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3502206824
Short name T554
Test name
Test status
Simulation time 44532812 ps
CPU time 0.74 seconds
Started Apr 25 01:12:14 PM PDT 24
Finished Apr 25 01:12:16 PM PDT 24
Peak memory 206648 kb
Host smart-ff7c0780-b6be-4d78-b801-a621be7c5503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502206824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3502206824
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.282234181
Short name T298
Test name
Test status
Simulation time 8964748496 ps
CPU time 34.9 seconds
Started Apr 25 01:12:16 PM PDT 24
Finished Apr 25 01:12:52 PM PDT 24
Peak memory 236940 kb
Host smart-d94a09a5-0bd1-40e0-8da3-25ced90da2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282234181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.282234181
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1600020693
Short name T222
Test name
Test status
Simulation time 923318044 ps
CPU time 5.35 seconds
Started Apr 25 01:12:15 PM PDT 24
Finished Apr 25 01:12:22 PM PDT 24
Peak memory 222932 kb
Host smart-285bab9e-1da3-4fd1-93d4-a0755ffaed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600020693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1600020693
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3187228130
Short name T652
Test name
Test status
Simulation time 88622521 ps
CPU time 3.36 seconds
Started Apr 25 01:12:15 PM PDT 24
Finished Apr 25 01:12:20 PM PDT 24
Peak memory 222556 kb
Host smart-2b92ab36-5ef3-4d51-b805-4a9928f66f2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3187228130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3187228130
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1104258538
Short name T62
Test name
Test status
Simulation time 8408247631 ps
CPU time 44.28 seconds
Started Apr 25 01:12:18 PM PDT 24
Finished Apr 25 01:13:04 PM PDT 24
Peak memory 216216 kb
Host smart-8a93e467-d5b7-4366-a793-142fda91bc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104258538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1104258538
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2732520726
Short name T496
Test name
Test status
Simulation time 51031523275 ps
CPU time 34.44 seconds
Started Apr 25 01:12:15 PM PDT 24
Finished Apr 25 01:12:51 PM PDT 24
Peak memory 216324 kb
Host smart-ee877dea-8794-4e47-aac5-2d1173d90a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732520726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2732520726
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.211903864
Short name T595
Test name
Test status
Simulation time 50820933 ps
CPU time 1.31 seconds
Started Apr 25 01:12:17 PM PDT 24
Finished Apr 25 01:12:20 PM PDT 24
Peak memory 207980 kb
Host smart-1dd81fc3-f33c-4cc7-816b-387b930dd322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211903864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.211903864
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1282290538
Short name T517
Test name
Test status
Simulation time 38824836 ps
CPU time 0.77 seconds
Started Apr 25 01:12:14 PM PDT 24
Finished Apr 25 01:12:16 PM PDT 24
Peak memory 205816 kb
Host smart-060969c8-55a7-467a-a956-d91fad2eee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282290538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1282290538
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.601535404
Short name T697
Test name
Test status
Simulation time 21552334 ps
CPU time 0.7 seconds
Started Apr 25 01:12:21 PM PDT 24
Finished Apr 25 01:12:23 PM PDT 24
Peak memory 204864 kb
Host smart-76d60a32-cf0c-4a38-9fe2-10c4e709acae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601535404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.601535404
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3222524422
Short name T213
Test name
Test status
Simulation time 760552177 ps
CPU time 3.66 seconds
Started Apr 25 01:12:23 PM PDT 24
Finished Apr 25 01:12:27 PM PDT 24
Peak memory 218752 kb
Host smart-030224de-1ad4-4dc7-9a2e-cee34acb0125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222524422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3222524422
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.965876139
Short name T485
Test name
Test status
Simulation time 88860108 ps
CPU time 0.77 seconds
Started Apr 25 01:12:15 PM PDT 24
Finished Apr 25 01:12:17 PM PDT 24
Peak memory 206972 kb
Host smart-de9539a6-590c-4697-8ac3-378ebf4434b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965876139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.965876139
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.837544941
Short name T285
Test name
Test status
Simulation time 2190867203 ps
CPU time 18.67 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:12:47 PM PDT 24
Peak memory 232684 kb
Host smart-25917780-0ae5-4024-b972-54c0ea0b1df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837544941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.837544941
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4264681186
Short name T225
Test name
Test status
Simulation time 976900764 ps
CPU time 3.23 seconds
Started Apr 25 01:12:18 PM PDT 24
Finished Apr 25 01:12:24 PM PDT 24
Peak memory 222684 kb
Host smart-b7088fa7-e5d5-4b15-8dae-18d7dc693053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264681186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4264681186
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4056122408
Short name T522
Test name
Test status
Simulation time 1639306116 ps
CPU time 9.94 seconds
Started Apr 25 01:12:20 PM PDT 24
Finished Apr 25 01:12:31 PM PDT 24
Peak memory 220044 kb
Host smart-b5aa31ad-7984-4677-8379-499286884f26
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4056122408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4056122408
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2728647429
Short name T689
Test name
Test status
Simulation time 5044006173 ps
CPU time 29.14 seconds
Started Apr 25 01:12:21 PM PDT 24
Finished Apr 25 01:12:51 PM PDT 24
Peak memory 216312 kb
Host smart-1014014f-d177-4f81-92f8-153a39976901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728647429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2728647429
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1137025364
Short name T408
Test name
Test status
Simulation time 16594055297 ps
CPU time 14.77 seconds
Started Apr 25 01:12:14 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 216288 kb
Host smart-a2bb2e75-5f9c-4129-b4cc-68c6c7c19219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137025364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1137025364
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.513833992
Short name T380
Test name
Test status
Simulation time 513460129 ps
CPU time 7.76 seconds
Started Apr 25 01:12:25 PM PDT 24
Finished Apr 25 01:12:33 PM PDT 24
Peak memory 216272 kb
Host smart-5f7532d0-f36d-4640-96e6-a205aa13af57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513833992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.513833992
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3187278149
Short name T529
Test name
Test status
Simulation time 178316278 ps
CPU time 0.78 seconds
Started Apr 25 01:12:21 PM PDT 24
Finished Apr 25 01:12:23 PM PDT 24
Peak memory 205760 kb
Host smart-3770e4ca-4bcc-4d25-9e1d-1c369e179e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187278149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3187278149
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.368971359
Short name T506
Test name
Test status
Simulation time 29444085 ps
CPU time 0.7 seconds
Started Apr 25 01:12:27 PM PDT 24
Finished Apr 25 01:12:28 PM PDT 24
Peak memory 205708 kb
Host smart-28b85e91-befc-4fef-acb5-68a8c78f238b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368971359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.368971359
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.13846451
Short name T602
Test name
Test status
Simulation time 7229645017 ps
CPU time 13 seconds
Started Apr 25 01:12:25 PM PDT 24
Finished Apr 25 01:12:39 PM PDT 24
Peak memory 218864 kb
Host smart-afbba231-0ef8-40f6-a128-74e212e130ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13846451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.13846451
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1898473382
Short name T606
Test name
Test status
Simulation time 52158382 ps
CPU time 0.74 seconds
Started Apr 25 01:12:19 PM PDT 24
Finished Apr 25 01:12:22 PM PDT 24
Peak memory 205556 kb
Host smart-894395b4-15b9-45f0-bf6a-aa0815540b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898473382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1898473382
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3048699715
Short name T700
Test name
Test status
Simulation time 290345945 ps
CPU time 10.88 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:12:40 PM PDT 24
Peak memory 239788 kb
Host smart-52eff5f3-a503-4e3f-870b-ddeaeea3a854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048699715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3048699715
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2942507661
Short name T245
Test name
Test status
Simulation time 437280655 ps
CPU time 7.78 seconds
Started Apr 25 01:12:26 PM PDT 24
Finished Apr 25 01:12:34 PM PDT 24
Peak memory 232700 kb
Host smart-9f6a02a4-b0a3-4119-9908-4d5894733c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942507661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2942507661
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1427090320
Short name T204
Test name
Test status
Simulation time 3510447090 ps
CPU time 6.02 seconds
Started Apr 25 01:12:27 PM PDT 24
Finished Apr 25 01:12:34 PM PDT 24
Peak memory 223104 kb
Host smart-a6c7a2ba-8dfa-4fcd-b6c7-9ee6e17b450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427090320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1427090320
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1105683907
Short name T570
Test name
Test status
Simulation time 1932211023 ps
CPU time 10.31 seconds
Started Apr 25 01:12:27 PM PDT 24
Finished Apr 25 01:12:38 PM PDT 24
Peak memory 218980 kb
Host smart-8687d249-9f01-4b46-9686-6e25a4ed6bb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1105683907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1105683907
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1475062104
Short name T33
Test name
Test status
Simulation time 184852982 ps
CPU time 0.9 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 205672 kb
Host smart-870edc36-c0d0-4200-8edb-ae8fd6eadab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475062104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1475062104
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.993753869
Short name T371
Test name
Test status
Simulation time 44556568203 ps
CPU time 43.14 seconds
Started Apr 25 01:12:55 PM PDT 24
Finished Apr 25 01:13:39 PM PDT 24
Peak memory 216448 kb
Host smart-1a70444a-ab78-460b-8b2d-e4e9cac4b348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993753869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.993753869
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3383207313
Short name T433
Test name
Test status
Simulation time 5117040876 ps
CPU time 9.31 seconds
Started Apr 25 01:12:19 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 216408 kb
Host smart-f8decb78-a3fd-4ffc-b197-c03a2528acb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383207313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3383207313
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3193035845
Short name T567
Test name
Test status
Simulation time 2800800303 ps
CPU time 6.85 seconds
Started Apr 25 01:12:21 PM PDT 24
Finished Apr 25 01:12:29 PM PDT 24
Peak memory 216236 kb
Host smart-7a9424dd-cc59-404f-b836-681821a3e241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193035845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3193035845
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1433854228
Short name T519
Test name
Test status
Simulation time 207439544 ps
CPU time 0.83 seconds
Started Apr 25 01:12:17 PM PDT 24
Finished Apr 25 01:12:19 PM PDT 24
Peak memory 205816 kb
Host smart-3716d11e-794f-4841-a6ec-996fa3b9cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433854228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1433854228
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1912422368
Short name T694
Test name
Test status
Simulation time 23466617 ps
CPU time 0.7 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 205348 kb
Host smart-c0e40783-1d5f-4439-8e31-84aa6a59d747
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912422368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1912422368
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1501738524
Short name T532
Test name
Test status
Simulation time 42909999 ps
CPU time 0.83 seconds
Started Apr 25 01:12:29 PM PDT 24
Finished Apr 25 01:12:31 PM PDT 24
Peak memory 205672 kb
Host smart-90f6eedc-50c1-4282-b274-439999cb1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501738524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1501738524
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1385027897
Short name T292
Test name
Test status
Simulation time 1447276610 ps
CPU time 12.29 seconds
Started Apr 25 01:12:29 PM PDT 24
Finished Apr 25 01:12:42 PM PDT 24
Peak memory 249048 kb
Host smart-b5108e99-07e0-4d7f-a973-da1f2c9554ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385027897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1385027897
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3263241436
Short name T170
Test name
Test status
Simulation time 1026335449 ps
CPU time 13.84 seconds
Started Apr 25 01:12:27 PM PDT 24
Finished Apr 25 01:12:42 PM PDT 24
Peak memory 218612 kb
Host smart-43bd6b6c-428e-4849-9b58-79a38aa14a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263241436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3263241436
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2326674813
Short name T300
Test name
Test status
Simulation time 640564600 ps
CPU time 3.92 seconds
Started Apr 25 01:12:29 PM PDT 24
Finished Apr 25 01:12:34 PM PDT 24
Peak memory 219080 kb
Host smart-8cbdfdbc-0f21-4ea9-a761-615b7c9b5085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326674813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2326674813
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1700360510
Short name T469
Test name
Test status
Simulation time 83613200 ps
CPU time 3.56 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:12:32 PM PDT 24
Peak memory 222916 kb
Host smart-e92b3d43-3b9e-4293-919d-7806c3d94432
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1700360510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1700360510
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3856703460
Short name T672
Test name
Test status
Simulation time 21687301284 ps
CPU time 57.75 seconds
Started Apr 25 01:12:28 PM PDT 24
Finished Apr 25 01:13:26 PM PDT 24
Peak memory 216364 kb
Host smart-0fbceb34-8063-4adb-93cb-80f43e18f998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856703460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3856703460
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3317771204
Short name T450
Test name
Test status
Simulation time 194909382 ps
CPU time 1.44 seconds
Started Apr 25 01:13:32 PM PDT 24
Finished Apr 25 01:13:34 PM PDT 24
Peak memory 207688 kb
Host smart-18613f20-6ec1-41a4-a975-c1193e215d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317771204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3317771204
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1835331263
Short name T63
Test name
Test status
Simulation time 79161657 ps
CPU time 1.2 seconds
Started Apr 25 01:12:29 PM PDT 24
Finished Apr 25 01:12:31 PM PDT 24
Peak memory 216208 kb
Host smart-ca5ff9eb-de9e-4a9a-8f26-150aced03fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835331263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1835331263
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.548147469
Short name T411
Test name
Test status
Simulation time 78458400 ps
CPU time 0.82 seconds
Started Apr 25 01:12:29 PM PDT 24
Finished Apr 25 01:12:30 PM PDT 24
Peak memory 205880 kb
Host smart-cdd5b567-afdf-4798-ab9a-33edc4bb13aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548147469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.548147469
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3763224523
Short name T534
Test name
Test status
Simulation time 15417236 ps
CPU time 0.79 seconds
Started Apr 25 01:12:32 PM PDT 24
Finished Apr 25 01:12:34 PM PDT 24
Peak memory 205432 kb
Host smart-a4216a0e-58b3-475b-8a0b-21cbbcece52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763224523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3763224523
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3204674672
Short name T630
Test name
Test status
Simulation time 2134093389 ps
CPU time 10.52 seconds
Started Apr 25 01:12:37 PM PDT 24
Finished Apr 25 01:12:48 PM PDT 24
Peak memory 218736 kb
Host smart-3a0f3197-18d9-4b2b-bc15-95138b7e9277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204674672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3204674672
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3922124084
Short name T577
Test name
Test status
Simulation time 95524100 ps
CPU time 0.77 seconds
Started Apr 25 01:12:34 PM PDT 24
Finished Apr 25 01:12:35 PM PDT 24
Peak memory 206688 kb
Host smart-827d1a00-ec18-4a22-8f5d-ea7af286c4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922124084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3922124084
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3151670699
Short name T282
Test name
Test status
Simulation time 10658897936 ps
CPU time 64.63 seconds
Started Apr 25 01:12:30 PM PDT 24
Finished Apr 25 01:13:36 PM PDT 24
Peak memory 249140 kb
Host smart-36dcdd74-7c94-4512-a2c4-3c7da1843d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151670699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3151670699
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.391410039
Short name T457
Test name
Test status
Simulation time 923525788 ps
CPU time 3.59 seconds
Started Apr 25 01:12:34 PM PDT 24
Finished Apr 25 01:12:38 PM PDT 24
Peak memory 222392 kb
Host smart-4885dd5f-4193-412f-89d1-4e732b71ac47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391410039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.391410039
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.657053022
Short name T328
Test name
Test status
Simulation time 20273647622 ps
CPU time 38.79 seconds
Started Apr 25 01:12:33 PM PDT 24
Finished Apr 25 01:13:12 PM PDT 24
Peak memory 239692 kb
Host smart-f032d653-ee34-4412-b383-ce37c324198a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657053022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.657053022
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2246121804
Short name T81
Test name
Test status
Simulation time 974079776 ps
CPU time 5.01 seconds
Started Apr 25 01:12:30 PM PDT 24
Finished Apr 25 01:12:36 PM PDT 24
Peak memory 234004 kb
Host smart-4257e5fa-53c9-4826-936b-c8af97410624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246121804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2246121804
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.419711543
Short name T544
Test name
Test status
Simulation time 1119604284 ps
CPU time 9.05 seconds
Started Apr 25 01:12:33 PM PDT 24
Finished Apr 25 01:12:42 PM PDT 24
Peak memory 222264 kb
Host smart-7763f7d5-3e7e-4b43-8e31-bef69ddf7a1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=419711543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.419711543
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1698392204
Short name T386
Test name
Test status
Simulation time 7931628940 ps
CPU time 9.74 seconds
Started Apr 25 01:12:31 PM PDT 24
Finished Apr 25 01:12:41 PM PDT 24
Peak memory 216352 kb
Host smart-e190f2ff-14ba-47cb-88a7-5350c7b275b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698392204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1698392204
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.720644106
Short name T436
Test name
Test status
Simulation time 35479932326 ps
CPU time 27.6 seconds
Started Apr 25 01:12:32 PM PDT 24
Finished Apr 25 01:13:00 PM PDT 24
Peak memory 216388 kb
Host smart-a8349619-92a8-43d1-b713-56c0eeab55a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720644106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.720644106
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2077310231
Short name T657
Test name
Test status
Simulation time 203002606 ps
CPU time 6.72 seconds
Started Apr 25 01:12:33 PM PDT 24
Finished Apr 25 01:12:41 PM PDT 24
Peak memory 216288 kb
Host smart-13b1608c-616a-488f-833b-05d371a0d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077310231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2077310231
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1651829988
Short name T528
Test name
Test status
Simulation time 42512787 ps
CPU time 0.89 seconds
Started Apr 25 01:12:29 PM PDT 24
Finished Apr 25 01:12:31 PM PDT 24
Peak memory 205640 kb
Host smart-8d8745d3-cc21-4138-8666-8ab0b728653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651829988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1651829988
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.583944960
Short name T9
Test name
Test status
Simulation time 1563604973 ps
CPU time 11.08 seconds
Started Apr 25 01:12:37 PM PDT 24
Finished Apr 25 01:12:48 PM PDT 24
Peak memory 236436 kb
Host smart-85267272-11e4-4605-a298-62d396737f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583944960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.583944960
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.404724955
Short name T596
Test name
Test status
Simulation time 17267292 ps
CPU time 0.75 seconds
Started Apr 25 01:12:40 PM PDT 24
Finished Apr 25 01:12:42 PM PDT 24
Peak memory 205380 kb
Host smart-bf726991-4a48-4e57-8d9e-6590c661c757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404724955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.404724955
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2401343855
Short name T600
Test name
Test status
Simulation time 22642457 ps
CPU time 0.75 seconds
Started Apr 25 01:12:32 PM PDT 24
Finished Apr 25 01:12:33 PM PDT 24
Peak memory 207032 kb
Host smart-921376b6-c70e-4d59-bfe8-131526e7e2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401343855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2401343855
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_intercept.25424850
Short name T242
Test name
Test status
Simulation time 5441358600 ps
CPU time 9.33 seconds
Started Apr 25 01:12:37 PM PDT 24
Finished Apr 25 01:12:47 PM PDT 24
Peak memory 222936 kb
Host smart-935df5b3-2ab0-4cdc-8006-75a00fc5fad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25424850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.25424850
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1518186577
Short name T236
Test name
Test status
Simulation time 225150975 ps
CPU time 2.53 seconds
Started Apr 25 01:12:33 PM PDT 24
Finished Apr 25 01:12:36 PM PDT 24
Peak memory 222924 kb
Host smart-f165bc50-cb2d-494f-aff4-0af0cf39ca9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518186577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1518186577
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4256240729
Short name T153
Test name
Test status
Simulation time 90640074 ps
CPU time 3.68 seconds
Started Apr 25 01:12:38 PM PDT 24
Finished Apr 25 01:12:43 PM PDT 24
Peak memory 223004 kb
Host smart-c897c22d-9a79-443c-8af2-18860609f9d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256240729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4256240729
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1982159791
Short name T666
Test name
Test status
Simulation time 3440196813 ps
CPU time 29 seconds
Started Apr 25 01:12:37 PM PDT 24
Finished Apr 25 01:13:07 PM PDT 24
Peak memory 221000 kb
Host smart-f9141c4d-16a6-4167-abe9-a435aafbc6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982159791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1982159791
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.517545976
Short name T467
Test name
Test status
Simulation time 9264597557 ps
CPU time 28.32 seconds
Started Apr 25 01:12:31 PM PDT 24
Finished Apr 25 01:13:00 PM PDT 24
Peak memory 216324 kb
Host smart-3817ad26-36d8-49dd-a8ed-763425b9eb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517545976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.517545976
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3425208936
Short name T594
Test name
Test status
Simulation time 302686718 ps
CPU time 3.42 seconds
Started Apr 25 01:12:37 PM PDT 24
Finished Apr 25 01:12:42 PM PDT 24
Peak memory 216256 kb
Host smart-7796732b-47dd-4f43-b68f-72186bf94ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425208936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3425208936
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1438059954
Short name T440
Test name
Test status
Simulation time 222694351 ps
CPU time 0.96 seconds
Started Apr 25 01:12:35 PM PDT 24
Finished Apr 25 01:12:36 PM PDT 24
Peak memory 206284 kb
Host smart-00ec658d-c433-43a9-950b-7b76abae7999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438059954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1438059954
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2316454710
Short name T492
Test name
Test status
Simulation time 15756089 ps
CPU time 0.69 seconds
Started Apr 25 01:12:44 PM PDT 24
Finished Apr 25 01:12:45 PM PDT 24
Peak memory 205364 kb
Host smart-1cc811b4-8ee0-4946-afc0-e2b527e4548f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316454710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2316454710
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1262288863
Short name T30
Test name
Test status
Simulation time 1991304120 ps
CPU time 18.56 seconds
Started Apr 25 01:12:38 PM PDT 24
Finished Apr 25 01:12:57 PM PDT 24
Peak memory 224140 kb
Host smart-5700333c-1f66-484e-b6b2-60716a10be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262288863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1262288863
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3857804627
Short name T515
Test name
Test status
Simulation time 30738425 ps
CPU time 0.81 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:12:47 PM PDT 24
Peak memory 206112 kb
Host smart-d25fbf81-7cdb-4702-beae-2dc6f61c7743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857804627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3857804627
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2567213105
Short name T297
Test name
Test status
Simulation time 50294790782 ps
CPU time 50.29 seconds
Started Apr 25 01:12:45 PM PDT 24
Finished Apr 25 01:13:36 PM PDT 24
Peak memory 239700 kb
Host smart-f7a58a72-8d83-4de5-afec-90b0d8b3f893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567213105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2567213105
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2001221647
Short name T691
Test name
Test status
Simulation time 9579460917 ps
CPU time 23 seconds
Started Apr 25 01:12:39 PM PDT 24
Finished Apr 25 01:13:03 PM PDT 24
Peak memory 232504 kb
Host smart-62247932-4cad-4ec9-9023-b5681c047f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001221647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2001221647
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3537632419
Short name T163
Test name
Test status
Simulation time 860718548 ps
CPU time 11.86 seconds
Started Apr 25 01:12:37 PM PDT 24
Finished Apr 25 01:12:50 PM PDT 24
Peak memory 222844 kb
Host smart-8df2e036-fe61-421c-bb4c-9df61381d7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537632419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3537632419
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3246024514
Short name T244
Test name
Test status
Simulation time 693697001 ps
CPU time 5.21 seconds
Started Apr 25 01:12:38 PM PDT 24
Finished Apr 25 01:12:45 PM PDT 24
Peak memory 218528 kb
Host smart-cef19908-af98-44e9-8446-c0788d1e197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246024514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3246024514
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4176928499
Short name T579
Test name
Test status
Simulation time 1775217741 ps
CPU time 7.38 seconds
Started Apr 25 01:12:39 PM PDT 24
Finished Apr 25 01:12:47 PM PDT 24
Peak memory 219992 kb
Host smart-d632035c-81bb-4a89-b42f-4c791b06c4c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176928499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4176928499
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4160318655
Short name T374
Test name
Test status
Simulation time 1046541724 ps
CPU time 5.18 seconds
Started Apr 25 01:12:41 PM PDT 24
Finished Apr 25 01:12:47 PM PDT 24
Peak memory 216452 kb
Host smart-d64e32a9-bbd9-4302-b0b2-b5ec770a2199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160318655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4160318655
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1430495470
Short name T500
Test name
Test status
Simulation time 8147954976 ps
CPU time 12.11 seconds
Started Apr 25 01:12:41 PM PDT 24
Finished Apr 25 01:12:54 PM PDT 24
Peak memory 216336 kb
Host smart-ceb5f452-4785-4c7d-891c-b001efb05cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430495470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1430495470
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1477133820
Short name T56
Test name
Test status
Simulation time 83711730 ps
CPU time 1.67 seconds
Started Apr 25 01:12:39 PM PDT 24
Finished Apr 25 01:12:42 PM PDT 24
Peak memory 216256 kb
Host smart-f3f44b02-8427-4e02-80c3-17799e295c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477133820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1477133820
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1195552969
Short name T493
Test name
Test status
Simulation time 184825468 ps
CPU time 0.95 seconds
Started Apr 25 01:12:39 PM PDT 24
Finished Apr 25 01:12:41 PM PDT 24
Peak memory 206828 kb
Host smart-5e78e402-ffcb-41c8-96ee-2b6b99550478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195552969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1195552969
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.587711812
Short name T398
Test name
Test status
Simulation time 43610896 ps
CPU time 0.7 seconds
Started Apr 25 01:09:54 PM PDT 24
Finished Apr 25 01:09:56 PM PDT 24
Peak memory 205308 kb
Host smart-ddd4ce5e-cefb-4b9e-af56-2c02ec0c80e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587711812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.587711812
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1799202535
Short name T499
Test name
Test status
Simulation time 24847336 ps
CPU time 0.82 seconds
Started Apr 25 01:09:46 PM PDT 24
Finished Apr 25 01:09:49 PM PDT 24
Peak memory 206664 kb
Host smart-0651db17-b0f9-41e7-a4aa-8b74ed5ed171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799202535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1799202535
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1981009503
Short name T287
Test name
Test status
Simulation time 3046464868 ps
CPU time 43.64 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:10:41 PM PDT 24
Peak memory 249000 kb
Host smart-15aa162f-db61-4773-a3ec-f9013ba26307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981009503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1981009503
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1811949239
Short name T184
Test name
Test status
Simulation time 1672888282 ps
CPU time 15.49 seconds
Started Apr 25 01:09:46 PM PDT 24
Finished Apr 25 01:10:03 PM PDT 24
Peak memory 223648 kb
Host smart-ea13d4d9-5291-4478-be3f-608666a61968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811949239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1811949239
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3402227618
Short name T246
Test name
Test status
Simulation time 4858933791 ps
CPU time 13.84 seconds
Started Apr 25 01:09:47 PM PDT 24
Finished Apr 25 01:10:03 PM PDT 24
Peak memory 222468 kb
Host smart-a55165b1-85df-485f-9e1f-8f36900375cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402227618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3402227618
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3246373136
Short name T239
Test name
Test status
Simulation time 729261766 ps
CPU time 4.38 seconds
Started Apr 25 01:10:09 PM PDT 24
Finished Apr 25 01:10:15 PM PDT 24
Peak memory 222792 kb
Host smart-3dfb0307-e402-4c9b-b683-4ec61e2ea0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246373136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3246373136
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2363030701
Short name T104
Test name
Test status
Simulation time 99167743 ps
CPU time 3.25 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:10:02 PM PDT 24
Peak memory 222536 kb
Host smart-d1039292-ac74-49da-a494-d6c6e19fcb43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2363030701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2363030701
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4007867503
Short name T160
Test name
Test status
Simulation time 51529730 ps
CPU time 1.02 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:09:57 PM PDT 24
Peak memory 207072 kb
Host smart-203fad01-68b5-4ef4-bc36-c9501eb73f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007867503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4007867503
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3068085323
Short name T64
Test name
Test status
Simulation time 7397159212 ps
CPU time 15.94 seconds
Started Apr 25 01:09:49 PM PDT 24
Finished Apr 25 01:10:06 PM PDT 24
Peak memory 216516 kb
Host smart-d11ec659-1569-4663-8b63-4383418f4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068085323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3068085323
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.682357844
Short name T59
Test name
Test status
Simulation time 22254802176 ps
CPU time 17.9 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:10:04 PM PDT 24
Peak memory 216372 kb
Host smart-16a23ae0-a8bd-4473-97b2-c216e71adf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682357844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.682357844
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.222561602
Short name T507
Test name
Test status
Simulation time 215537465 ps
CPU time 0.82 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:09:48 PM PDT 24
Peak memory 206464 kb
Host smart-478210dd-d9e3-47a9-97c8-de7d1733c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222561602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.222561602
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1273070258
Short name T466
Test name
Test status
Simulation time 163467693 ps
CPU time 0.92 seconds
Started Apr 25 01:09:45 PM PDT 24
Finished Apr 25 01:09:47 PM PDT 24
Peak memory 205816 kb
Host smart-2686262e-5a8b-4609-b29e-56beac4c24d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273070258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1273070258
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.627169659
Short name T229
Test name
Test status
Simulation time 1192098542 ps
CPU time 5.54 seconds
Started Apr 25 01:09:48 PM PDT 24
Finished Apr 25 01:09:55 PM PDT 24
Peak memory 234372 kb
Host smart-a6fe3d45-bcb7-4af4-8c64-ce901f10aa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627169659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.627169659
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.597052471
Short name T404
Test name
Test status
Simulation time 38288931 ps
CPU time 0.74 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:09:57 PM PDT 24
Peak memory 204880 kb
Host smart-99290df4-941b-45c8-aa9e-cda14d0d1872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597052471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.597052471
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.725871771
Short name T543
Test name
Test status
Simulation time 60535019 ps
CPU time 0.8 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:09:57 PM PDT 24
Peak memory 206696 kb
Host smart-08035521-aae5-420b-93c2-e15a70612234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725871771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.725871771
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2855719376
Short name T642
Test name
Test status
Simulation time 828459663 ps
CPU time 17.65 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:17 PM PDT 24
Peak memory 242280 kb
Host smart-7a39df49-e4a6-451d-8130-e0ccc33f2899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855719376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2855719376
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.733177991
Short name T43
Test name
Test status
Simulation time 299358826 ps
CPU time 5.62 seconds
Started Apr 25 01:09:54 PM PDT 24
Finished Apr 25 01:10:01 PM PDT 24
Peak memory 218984 kb
Host smart-ae99c724-7c9c-4179-9bc8-6acbf8fd30ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733177991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.733177991
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.863486699
Short name T183
Test name
Test status
Simulation time 2611856678 ps
CPU time 15.47 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:10:14 PM PDT 24
Peak memory 219740 kb
Host smart-f18cb30c-0ad3-479a-8e1f-b6fc2c9eeb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863486699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.863486699
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1461474542
Short name T131
Test name
Test status
Simulation time 967402849 ps
CPU time 3.74 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:10:01 PM PDT 24
Peak memory 224068 kb
Host smart-0b8be7c5-5b61-4757-b777-2a6a6492c5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461474542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1461474542
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1994329602
Short name T277
Test name
Test status
Simulation time 721426202 ps
CPU time 3.9 seconds
Started Apr 25 01:10:00 PM PDT 24
Finished Apr 25 01:10:05 PM PDT 24
Peak memory 223044 kb
Host smart-854d0837-7fd5-43c2-990a-ad18f29e919a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994329602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1994329602
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2949655251
Short name T483
Test name
Test status
Simulation time 196381794 ps
CPU time 4.28 seconds
Started Apr 25 01:09:53 PM PDT 24
Finished Apr 25 01:09:58 PM PDT 24
Peak memory 222524 kb
Host smart-1fe8f83e-c162-4ecb-8fc0-a6d07ed8d55d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2949655251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2949655251
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2817411485
Short name T646
Test name
Test status
Simulation time 1391571757 ps
CPU time 20.54 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:10:17 PM PDT 24
Peak memory 216328 kb
Host smart-83bb66f1-c05b-42ac-b51d-4bcfd747cfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817411485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2817411485
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3679475085
Short name T552
Test name
Test status
Simulation time 8759123716 ps
CPU time 26.5 seconds
Started Apr 25 01:09:53 PM PDT 24
Finished Apr 25 01:10:21 PM PDT 24
Peak memory 216328 kb
Host smart-a9a804ef-b251-472b-adb6-440736eaffbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679475085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3679475085
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2413005122
Short name T637
Test name
Test status
Simulation time 532533350 ps
CPU time 2.38 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:02 PM PDT 24
Peak memory 216256 kb
Host smart-03cb5543-eb60-4965-84bd-d03842d200af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413005122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2413005122
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.618396014
Short name T15
Test name
Test status
Simulation time 61529039 ps
CPU time 0.96 seconds
Started Apr 25 01:09:53 PM PDT 24
Finished Apr 25 01:09:55 PM PDT 24
Peak memory 206780 kb
Host smart-28132a46-61bd-402f-90a3-90846c9d429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618396014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.618396014
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3289902068
Short name T276
Test name
Test status
Simulation time 11018592963 ps
CPU time 34.34 seconds
Started Apr 25 01:09:54 PM PDT 24
Finished Apr 25 01:10:29 PM PDT 24
Peak memory 232732 kb
Host smart-9d48c134-383c-4d4d-8b97-625517153553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289902068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3289902068
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2929002301
Short name T429
Test name
Test status
Simulation time 21769509 ps
CPU time 0.74 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:00 PM PDT 24
Peak memory 205424 kb
Host smart-a936a689-f5b7-431f-9ceb-aa9bb579b621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929002301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
929002301
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4153345245
Short name T453
Test name
Test status
Simulation time 30755059 ps
CPU time 0.76 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:09:58 PM PDT 24
Peak memory 206740 kb
Host smart-cd7d4cca-c69a-46fe-acbf-40ebc9495482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153345245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4153345245
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1625476604
Short name T207
Test name
Test status
Simulation time 2731099622 ps
CPU time 9.91 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:10:06 PM PDT 24
Peak memory 219040 kb
Host smart-de5750df-f7aa-443c-8d74-5de65180fcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625476604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1625476604
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4018134340
Short name T707
Test name
Test status
Simulation time 14673051775 ps
CPU time 13.66 seconds
Started Apr 25 01:09:55 PM PDT 24
Finished Apr 25 01:10:10 PM PDT 24
Peak memory 224512 kb
Host smart-d61de876-3b47-4387-a947-11369c4d0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018134340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4018134340
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2018804578
Short name T658
Test name
Test status
Simulation time 510223476 ps
CPU time 5.63 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:04 PM PDT 24
Peak memory 220408 kb
Host smart-47dee150-1211-4be6-a9a3-663728046d6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2018804578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2018804578
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3458457122
Short name T573
Test name
Test status
Simulation time 6558686932 ps
CPU time 45.69 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:10:43 PM PDT 24
Peak memory 216432 kb
Host smart-ea2ad2f5-0cdb-4bd7-b609-86a1ee486819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458457122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3458457122
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3749126026
Short name T465
Test name
Test status
Simulation time 14822067880 ps
CPU time 21.08 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:20 PM PDT 24
Peak memory 216264 kb
Host smart-8a63e48b-fc55-4650-90fe-b8478da85e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749126026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3749126026
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1801832375
Short name T680
Test name
Test status
Simulation time 32743751 ps
CPU time 0.87 seconds
Started Apr 25 01:09:56 PM PDT 24
Finished Apr 25 01:09:59 PM PDT 24
Peak memory 206768 kb
Host smart-e08a9155-e34a-4d78-88ca-96b7ac45ac20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801832375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1801832375
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3411482503
Short name T676
Test name
Test status
Simulation time 75450945 ps
CPU time 0.92 seconds
Started Apr 25 01:09:54 PM PDT 24
Finished Apr 25 01:09:56 PM PDT 24
Peak memory 205780 kb
Host smart-98999d0b-81ee-4808-849c-ad4bda5308ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411482503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3411482503
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3814961978
Short name T306
Test name
Test status
Simulation time 661435589 ps
CPU time 4.54 seconds
Started Apr 25 01:10:01 PM PDT 24
Finished Apr 25 01:10:07 PM PDT 24
Peak memory 216324 kb
Host smart-c6fbc099-9fd1-4deb-a38d-17872bab3347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814961978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3814961978
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.214751
Short name T539
Test name
Test status
Simulation time 14850094 ps
CPU time 0.73 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:06 PM PDT 24
Peak memory 204828 kb
Host smart-f7af9d6b-c661-46bf-842a-9588217a31a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.214751
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2307284100
Short name T309
Test name
Test status
Simulation time 55492969 ps
CPU time 2.65 seconds
Started Apr 25 01:10:00 PM PDT 24
Finished Apr 25 01:10:04 PM PDT 24
Peak memory 223108 kb
Host smart-e874f373-37da-40bb-92f7-82f237606e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307284100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2307284100
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2749690686
Short name T503
Test name
Test status
Simulation time 19867362 ps
CPU time 0.79 seconds
Started Apr 25 01:10:39 PM PDT 24
Finished Apr 25 01:10:41 PM PDT 24
Peak memory 206684 kb
Host smart-23e39ecb-80c2-407f-858c-700113294c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749690686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2749690686
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1506072417
Short name T655
Test name
Test status
Simulation time 1276590523 ps
CPU time 12.39 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:11 PM PDT 24
Peak memory 249052 kb
Host smart-987486c7-6bbb-4206-b553-5bd795a8c549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506072417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1506072417
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3853056453
Short name T347
Test name
Test status
Simulation time 5137846061 ps
CPU time 18.95 seconds
Started Apr 25 01:09:58 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 238312 kb
Host smart-1a96c498-23ec-4b43-9293-6f489b260e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853056453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3853056453
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.454184960
Short name T199
Test name
Test status
Simulation time 5795696352 ps
CPU time 17.42 seconds
Started Apr 25 01:09:59 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 218684 kb
Host smart-e9471511-3431-4073-b5b3-213435cea950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454184960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.454184960
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1710195884
Short name T151
Test name
Test status
Simulation time 1565447332 ps
CPU time 7.09 seconds
Started Apr 25 01:10:00 PM PDT 24
Finished Apr 25 01:10:09 PM PDT 24
Peak memory 220552 kb
Host smart-08303b73-8415-4901-afaf-024f9b067325
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1710195884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1710195884
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4094091657
Short name T39
Test name
Test status
Simulation time 100816749 ps
CPU time 1.12 seconds
Started Apr 25 01:09:58 PM PDT 24
Finished Apr 25 01:10:02 PM PDT 24
Peak memory 208020 kb
Host smart-5ae88400-7c44-4dc4-ad42-f90108e03de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094091657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4094091657
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4180374613
Short name T634
Test name
Test status
Simulation time 14691662592 ps
CPU time 44.58 seconds
Started Apr 25 01:09:58 PM PDT 24
Finished Apr 25 01:10:45 PM PDT 24
Peak memory 216212 kb
Host smart-e7862a4c-da26-4e59-8e96-e73036acc5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180374613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4180374613
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.711238088
Short name T575
Test name
Test status
Simulation time 2011395121 ps
CPU time 6 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:09 PM PDT 24
Peak memory 216188 kb
Host smart-317a9a7d-0f6b-4489-b07e-eb3b997f783f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711238088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.711238088
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.628871656
Short name T490
Test name
Test status
Simulation time 299764729 ps
CPU time 5.08 seconds
Started Apr 25 01:09:59 PM PDT 24
Finished Apr 25 01:10:06 PM PDT 24
Peak memory 216204 kb
Host smart-336f6464-cd72-4994-99ab-d58453478271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628871656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.628871656
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2419192172
Short name T558
Test name
Test status
Simulation time 182873720 ps
CPU time 0.97 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:00 PM PDT 24
Peak memory 206812 kb
Host smart-2a682ee4-7d6f-4de4-8ed1-c8c3c725ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419192172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2419192172
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3162508912
Short name T712
Test name
Test status
Simulation time 28254735 ps
CPU time 0.81 seconds
Started Apr 25 01:09:59 PM PDT 24
Finished Apr 25 01:10:02 PM PDT 24
Peak memory 206680 kb
Host smart-dbdcc35c-c589-42b2-a689-c91e6a7fcb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162508912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3162508912
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3034815581
Short name T603
Test name
Test status
Simulation time 2726495540 ps
CPU time 13.5 seconds
Started Apr 25 01:10:04 PM PDT 24
Finished Apr 25 01:10:19 PM PDT 24
Peak memory 232748 kb
Host smart-75812896-ac17-4a6c-b463-2a75eb45677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034815581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3034815581
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2993279367
Short name T2
Test name
Test status
Simulation time 7900357117 ps
CPU time 26 seconds
Started Apr 25 01:10:00 PM PDT 24
Finished Apr 25 01:10:28 PM PDT 24
Peak memory 230148 kb
Host smart-21ff5372-a8fd-45b6-b841-ddcf953c354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993279367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2993279367
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.948674955
Short name T219
Test name
Test status
Simulation time 9088612745 ps
CPU time 26.89 seconds
Started Apr 25 01:10:00 PM PDT 24
Finished Apr 25 01:10:29 PM PDT 24
Peak memory 232544 kb
Host smart-fe1386bc-a8a2-44a7-8797-72ae63f32231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948674955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.948674955
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3866906236
Short name T623
Test name
Test status
Simulation time 191396403 ps
CPU time 5.61 seconds
Started Apr 25 01:09:58 PM PDT 24
Finished Apr 25 01:10:06 PM PDT 24
Peak memory 222980 kb
Host smart-16d0e812-e107-4419-a3a9-7341ae978ec6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3866906236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3866906236
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1468847571
Short name T344
Test name
Test status
Simulation time 47368798 ps
CPU time 1.04 seconds
Started Apr 25 01:10:09 PM PDT 24
Finished Apr 25 01:10:11 PM PDT 24
Peak memory 207312 kb
Host smart-6cf8bea9-699b-40aa-8260-52a147fc3f4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468847571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1468847571
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4048535358
Short name T536
Test name
Test status
Simulation time 2577283199 ps
CPU time 13.1 seconds
Started Apr 25 01:10:08 PM PDT 24
Finished Apr 25 01:10:22 PM PDT 24
Peak memory 216376 kb
Host smart-df26ffb5-c487-47f4-b6ba-46c95c89e1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048535358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4048535358
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2767515415
Short name T405
Test name
Test status
Simulation time 9808008333 ps
CPU time 10.26 seconds
Started Apr 25 01:10:07 PM PDT 24
Finished Apr 25 01:10:18 PM PDT 24
Peak memory 216248 kb
Host smart-ab3bfe53-d45b-43dd-a82f-4802e7cfa9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767515415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2767515415
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.643689484
Short name T393
Test name
Test status
Simulation time 680149458 ps
CPU time 2.26 seconds
Started Apr 25 01:09:57 PM PDT 24
Finished Apr 25 01:10:02 PM PDT 24
Peak memory 216292 kb
Host smart-6deb091a-f999-40de-90cc-89fd108968c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643689484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.643689484
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2550531822
Short name T535
Test name
Test status
Simulation time 54568211 ps
CPU time 0.85 seconds
Started Apr 25 01:10:07 PM PDT 24
Finished Apr 25 01:10:09 PM PDT 24
Peak memory 205708 kb
Host smart-e8dbe707-aefa-409f-b052-0fb376ba0473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550531822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2550531822
Directory /workspace/9.spi_device_tpm_sts_read/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%