Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1236112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1402212

1

T1

956

T2

904

T3

2844

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1989636	1			T1	157		T2	9		T3	3847
values[0x0]	323690	1			T1	448		T2	454		T3	449
values[0x1]	324998	1			T1	445		T2	449		T3	442

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	932914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1705410

1

T1

979

T2

906

T3

3228

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12443	1			T3	12		T11	3		T5	33
valid_sources[0x01]	9853	1			T2	3		T3	20		T11	4
valid_sources[0x02]	9160	1			T1	23		T2	8		T3	15
valid_sources[0x03]	28574	1			T2	2		T3	12		T11	1
valid_sources[0x04]	8607	1			T1	6		T2	3		T3	14
valid_sources[0x05]	7889	1			T2	7		T3	23		T11	2
valid_sources[0x06]	8367	1			T1	2		T2	3		T3	20
valid_sources[0x07]	8402	1			T1	39		T2	3		T3	16
valid_sources[0x08]	30865	1			T2	3		T3	14		T11	5
valid_sources[0x09]	8311	1			T2	2		T3	26		T5	42
valid_sources[0x0a]	8694	1			T2	7		T3	22		T5	20
valid_sources[0x0b]	8085	1			T2	4		T3	16		T11	1
valid_sources[0x0c]	8432	1			T2	3		T3	14		T5	121
valid_sources[0x0d]	8138	1			T2	3		T3	9		T11	3
valid_sources[0x0e]	8124	1			T2	6		T3	12		T5	206
valid_sources[0x0f]	8303	1			T2	5		T3	16		T11	4
valid_sources[0x10]	8853	1			T1	2		T2	2		T3	13
valid_sources[0x11]	8587	1			T2	2		T3	17		T11	3
valid_sources[0x12]	8691	1			T2	2		T3	25		T5	194
valid_sources[0x13]	8265	1			T2	5		T3	14		T11	1
valid_sources[0x14]	10737	1			T2	5		T3	16		T14	2
valid_sources[0x15]	8875	1			T1	7		T2	4		T3	20
valid_sources[0x16]	9102	1			T3	18		T11	9		T5	95
valid_sources[0x17]	9755	1			T1	1		T2	1		T3	23
valid_sources[0x18]	9781	1			T2	5		T3	25		T11	7
valid_sources[0x19]	9416	1			T1	7		T2	4		T3	19
valid_sources[0x1a]	27756	1			T2	8		T3	15		T11	8
valid_sources[0x1b]	21476	1			T1	4		T2	12		T3	19
valid_sources[0x1c]	16370	1			T1	23		T2	6		T3	23
valid_sources[0x1d]	10544	1			T2	10		T3	14		T11	7
valid_sources[0x1e]	8696	1			T1	4		T2	2		T3	21
valid_sources[0x1f]	9399	1			T1	13		T3	11		T11	3
valid_sources[0x20]	8291	1			T1	3		T3	13		T11	4
valid_sources[0x21]	8344	1			T2	9		T3	19		T11	7
valid_sources[0x22]	14402	1			T1	1		T2	1		T3	22
valid_sources[0x23]	8655	1			T1	4		T2	10		T3	15
valid_sources[0x24]	8634	1			T2	1		T3	19		T11	3
valid_sources[0x25]	8494	1			T2	1		T3	23		T11	3
valid_sources[0x26]	8934	1			T2	6		T3	17		T11	4
valid_sources[0x27]	9813	1			T1	15		T2	4		T3	15
valid_sources[0x28]	10533	1			T2	7		T3	18		T11	9
valid_sources[0x29]	8326	1			T1	3		T2	2		T3	14
valid_sources[0x2a]	8582	1			T2	1		T3	25		T11	3
valid_sources[0x2b]	8539	1			T3	11		T11	6		T5	115
valid_sources[0x2c]	11093	1			T2	5		T3	25		T15	3
valid_sources[0x2d]	8513	1			T1	35		T2	1		T3	15
valid_sources[0x2e]	8118	1			T1	10		T2	2		T3	18
valid_sources[0x2f]	8543	1			T1	3		T3	25		T11	3
valid_sources[0x30]	7912	1			T2	4		T3	19		T11	4
valid_sources[0x31]	8619	1			T1	14		T2	2		T3	11
valid_sources[0x32]	9161	1			T1	5		T2	2		T3	25
valid_sources[0x33]	11291	1			T3	10		T11	9		T5	41
valid_sources[0x34]	7569	1			T1	1		T2	3		T3	23
valid_sources[0x35]	9843	1			T1	23		T2	10		T3	22
valid_sources[0x36]	7929	1			T2	7		T3	23		T14	2
valid_sources[0x37]	9601	1			T1	2		T2	3		T3	24
valid_sources[0x38]	8416	1			T1	15		T2	2		T3	24
valid_sources[0x39]	11197	1			T3	28		T11	3		T15	4
valid_sources[0x3a]	20665	1			T1	1		T2	1		T3	15
valid_sources[0x3b]	9474	1			T2	3		T3	20		T11	1
valid_sources[0x3c]	8708	1			T1	12		T3	16		T14	1
valid_sources[0x3d]	8257	1			T1	4		T2	2		T3	30
valid_sources[0x3e]	8177	1			T2	5		T3	17		T11	7
valid_sources[0x3f]	9507	1			T3	13		T11	13		T4	914
valid_sources[0x40]	12020	1			T3	17		T11	5		T5	115
valid_sources[0x41]	7771	1			T2	2		T3	16		T11	8
valid_sources[0x42]	10197	1			T1	6		T3	22		T11	5
valid_sources[0x43]	7360	1			T2	4		T3	20		T11	3
valid_sources[0x44]	21212	1			T2	6		T3	17		T11	3
valid_sources[0x45]	8067	1			T1	1		T2	1		T3	17
valid_sources[0x46]	8479	1			T1	8		T2	5		T3	19
valid_sources[0x47]	8625	1			T2	3		T3	12		T11	9
valid_sources[0x48]	8689	1			T3	21		T11	6		T5	189
valid_sources[0x49]	8708	1			T2	11		T3	14		T11	4
valid_sources[0x4a]	15195	1			T3	25		T5	51		T8	7
valid_sources[0x4b]	9350	1			T1	20		T2	1		T3	15
valid_sources[0x4c]	10161	1			T3	24		T5	141		T8	8
valid_sources[0x4d]	8482	1			T2	2		T3	22		T11	3
valid_sources[0x4e]	9619	1			T1	1		T2	4		T3	10
valid_sources[0x4f]	8994	1			T2	1		T3	21		T11	3
valid_sources[0x50]	8331	1			T1	4		T2	2		T3	16
valid_sources[0x51]	20136	1			T1	13		T2	7		T3	12
valid_sources[0x52]	9438	1			T2	2		T3	18		T11	5
valid_sources[0x53]	14775	1			T2	1		T3	18		T5	143
valid_sources[0x54]	7787	1			T2	3		T3	17		T11	6
valid_sources[0x55]	11194	1			T2	2		T3	14		T11	5
valid_sources[0x56]	7673	1			T1	11		T2	4		T3	18
valid_sources[0x57]	9067	1			T2	3		T3	10		T11	3
valid_sources[0x58]	21825	1			T1	1		T2	10		T3	19
valid_sources[0x59]	8612	1			T2	3		T3	16		T11	7
valid_sources[0x5a]	10046	1			T3	19		T11	5		T5	466
valid_sources[0x5b]	8416	1			T1	4		T2	4		T3	21
valid_sources[0x5c]	7622	1			T3	20		T5	27		T7	4
valid_sources[0x5d]	9584	1			T3	23		T11	1		T5	15
valid_sources[0x5e]	8657	1			T1	35		T3	20		T11	5
valid_sources[0x5f]	9455	1			T2	2		T3	17		T11	1
valid_sources[0x60]	10506	1			T2	4		T3	20		T14	2
valid_sources[0x61]	9817	1			T1	18		T2	3		T3	19
valid_sources[0x62]	8911	1			T2	7		T3	17		T11	4
valid_sources[0x63]	9289	1			T2	9		T3	18		T11	6
valid_sources[0x64]	9484	1			T1	19		T2	2		T3	21
valid_sources[0x65]	8077	1			T1	24		T2	3		T3	18
valid_sources[0x66]	8486	1			T2	7		T3	12		T11	3
valid_sources[0x67]	8048	1			T1	16		T2	4		T3	26
valid_sources[0x68]	13775	1			T2	3		T3	18		T5	193
valid_sources[0x69]	8396	1			T2	3		T3	16		T11	1
valid_sources[0x6a]	9362	1			T1	1		T2	2		T3	21
valid_sources[0x6b]	9612	1			T1	7		T2	6		T3	13
valid_sources[0x6c]	10760	1			T2	1		T3	24		T11	2
valid_sources[0x6d]	9519	1			T2	1		T3	25		T11	1
valid_sources[0x6e]	8518	1			T2	5		T3	15		T11	2
valid_sources[0x6f]	15614	1			T2	8		T3	18		T15	3
valid_sources[0x70]	10547	1			T2	2		T3	27		T11	12
valid_sources[0x71]	8009	1			T3	22		T14	4		T11	6
valid_sources[0x72]	8398	1			T1	2		T2	2		T3	29
valid_sources[0x73]	8545	1			T2	8		T3	31		T11	8
valid_sources[0x74]	9284	1			T1	23		T2	4		T3	12
valid_sources[0x75]	8621	1			T2	2		T3	14		T11	1
valid_sources[0x76]	8569	1			T3	24		T11	2		T5	134
valid_sources[0x77]	8067	1			T1	13		T2	7		T3	26
valid_sources[0x78]	8384	1			T1	23		T2	3		T3	14
valid_sources[0x79]	11358	1			T3	13		T11	4		T5	209
valid_sources[0x7a]	8252	1			T1	9		T2	2		T3	23
valid_sources[0x7b]	10772	1			T3	13		T11	1		T5	218
valid_sources[0x7c]	10788	1			T3	12		T11	4		T5	117
valid_sources[0x7d]	10026	1			T2	3		T3	20		T11	2
valid_sources[0x7e]	7937	1			T2	2		T3	21		T11	2
valid_sources[0x7f]	8394	1			T1	3		T2	5		T3	18
valid_sources[0x80]	11265	1			T2	4		T3	22		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

815436

1

T1

67

T2

3

T3

1965

values[0x0]

all_enables

biggest_size

296031

1

T1

446

T2

454

T3

446

values[0x1]

all_enables

biggest_size

290745

1

T1

443

T2

447

T3

433