Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1254928

1

T1

94

T2

8

T3

1894

full_word

1403288

1

T1

956

T2

904

T3

2844

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2657856	1			T1	1050		T2	912		T3	4738
auto[TlIntgErrCmd]	104	1			T34	2		T38	1		T118	4
auto[TlIntgErrData]	126	1			T34	2		T38	6		T118	4
auto[TlIntgErrBoth]	130	1			T34	6		T38	3		T118	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1992762

1

T1

157

T2

9

T3

3847

auto[1]

665454

1

T1

893

T2

903

T3

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1176951	1			T1	90		T2	6		T3	1882
auto[TlIntgErrNone]	partial	auto[1]	77646	1			T1	4		T2	2		T3	12
auto[TlIntgErrNone]	full_word	auto[0]	815658	1			T1	67		T2	3		T3	1965
auto[TlIntgErrNone]	full_word	auto[1]	587601	1			T1	889		T2	901		T3	879
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T34	1		T38	1		T118	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T34	1		T118	3		T134	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T134	1		T374	1		T375	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T376	1		T375	1		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1			T34	2		T118	2		T134	5
auto[TlIntgErrData]	partial	auto[1]	64	1			T38	4		T118	1		T134	6
auto[TlIntgErrData]	full_word	auto[0]	7	1			T38	2		T134	2		T376	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T118	1		T136	1		T377	2
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T34	1		T38	2		T134	2
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T34	4		T118	1		T134	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T34	1		T376	1		T378	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T38	1		T118	1		T379	2