Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
3510 |
0 |
0 |
T35 |
13981 |
228 |
0 |
0 |
T36 |
2801 |
2 |
0 |
0 |
T112 |
6735 |
101 |
0 |
0 |
T113 |
2550 |
88 |
0 |
0 |
T114 |
4716 |
71 |
0 |
0 |
T127 |
2988 |
83 |
0 |
0 |
T129 |
5127 |
27 |
0 |
0 |
T134 |
29551 |
7 |
0 |
0 |
T135 |
3779 |
20 |
0 |
0 |
T136 |
62152 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
1930 |
0 |
0 |
T34 |
33754 |
48 |
0 |
0 |
T95 |
3119 |
2 |
0 |
0 |
T96 |
2246 |
3 |
0 |
0 |
T136 |
62152 |
46 |
0 |
0 |
T143 |
7502 |
5 |
0 |
0 |
T147 |
11709 |
13 |
0 |
0 |
T155 |
6887 |
3 |
0 |
0 |
T162 |
12921 |
8 |
0 |
0 |
T163 |
15648 |
39 |
0 |
0 |
T164 |
13681 |
19 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
1915 |
0 |
0 |
T34 |
33754 |
46 |
0 |
0 |
T95 |
3119 |
5 |
0 |
0 |
T98 |
2239 |
3 |
0 |
0 |
T136 |
62152 |
45 |
0 |
0 |
T143 |
7502 |
5 |
0 |
0 |
T147 |
11709 |
13 |
0 |
0 |
T162 |
12921 |
8 |
0 |
0 |
T163 |
15648 |
37 |
0 |
0 |
T164 |
13681 |
41 |
0 |
0 |
T165 |
35862 |
42 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2621 |
0 |
0 |
T34 |
33754 |
107 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T136 |
62152 |
93 |
0 |
0 |
T139 |
11174 |
12 |
0 |
0 |
T143 |
7502 |
9 |
0 |
0 |
T147 |
11709 |
17 |
0 |
0 |
T155 |
6887 |
29 |
0 |
0 |
T162 |
12921 |
25 |
0 |
0 |
T163 |
15648 |
71 |
0 |
0 |
T164 |
13681 |
26 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
10174 |
0 |
0 |
T34 |
33754 |
590 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T96 |
2246 |
3 |
0 |
0 |
T136 |
62152 |
757 |
0 |
0 |
T139 |
11174 |
134 |
0 |
0 |
T143 |
7502 |
125 |
0 |
0 |
T147 |
11709 |
213 |
0 |
0 |
T155 |
6887 |
133 |
0 |
0 |
T162 |
12921 |
85 |
0 |
0 |
T163 |
15648 |
105 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
9640 |
0 |
0 |
T34 |
33754 |
435 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T96 |
2246 |
4 |
0 |
0 |
T136 |
62152 |
649 |
0 |
0 |
T139 |
11174 |
118 |
0 |
0 |
T147 |
11709 |
103 |
0 |
0 |
T155 |
6887 |
2 |
0 |
0 |
T162 |
12921 |
81 |
0 |
0 |
T163 |
15648 |
20 |
0 |
0 |
T164 |
13681 |
34 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
10079 |
0 |
0 |
T34 |
33754 |
590 |
0 |
0 |
T95 |
3119 |
9 |
0 |
0 |
T136 |
62152 |
724 |
0 |
0 |
T139 |
11174 |
223 |
0 |
0 |
T143 |
7502 |
91 |
0 |
0 |
T147 |
11709 |
96 |
0 |
0 |
T150 |
2875 |
45 |
0 |
0 |
T162 |
12921 |
120 |
0 |
0 |
T163 |
15648 |
47 |
0 |
0 |
T164 |
13681 |
19 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
11209 |
0 |
0 |
T34 |
33754 |
812 |
0 |
0 |
T95 |
3119 |
11 |
0 |
0 |
T96 |
2246 |
3 |
0 |
0 |
T136 |
62152 |
569 |
0 |
0 |
T139 |
11174 |
185 |
0 |
0 |
T143 |
7502 |
232 |
0 |
0 |
T147 |
11709 |
267 |
0 |
0 |
T155 |
6887 |
8 |
0 |
0 |
T162 |
12921 |
19 |
0 |
0 |
T163 |
15648 |
78 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
11254 |
0 |
0 |
T34 |
33754 |
543 |
0 |
0 |
T35 |
13981 |
5 |
0 |
0 |
T95 |
3119 |
4 |
0 |
0 |
T136 |
62152 |
671 |
0 |
0 |
T139 |
11174 |
109 |
0 |
0 |
T143 |
7502 |
4 |
0 |
0 |
T147 |
11709 |
252 |
0 |
0 |
T155 |
6887 |
155 |
0 |
0 |
T162 |
12921 |
12 |
0 |
0 |
T163 |
15648 |
31 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
10571 |
0 |
0 |
T34 |
33754 |
289 |
0 |
0 |
T95 |
3119 |
11 |
0 |
0 |
T96 |
2246 |
3 |
0 |
0 |
T136 |
62152 |
520 |
0 |
0 |
T139 |
11174 |
201 |
0 |
0 |
T143 |
7502 |
133 |
0 |
0 |
T147 |
11709 |
93 |
0 |
0 |
T155 |
6887 |
91 |
0 |
0 |
T162 |
12921 |
224 |
0 |
0 |
T163 |
15648 |
24 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
10913 |
0 |
0 |
T34 |
33754 |
910 |
0 |
0 |
T95 |
3119 |
9 |
0 |
0 |
T136 |
62152 |
471 |
0 |
0 |
T139 |
11174 |
115 |
0 |
0 |
T143 |
7502 |
10 |
0 |
0 |
T147 |
11709 |
121 |
0 |
0 |
T155 |
6887 |
95 |
0 |
0 |
T162 |
12921 |
122 |
0 |
0 |
T163 |
15648 |
26 |
0 |
0 |
T164 |
13681 |
32 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
10962 |
0 |
0 |
T34 |
33754 |
758 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T136 |
62152 |
557 |
0 |
0 |
T139 |
11174 |
64 |
0 |
0 |
T143 |
7502 |
118 |
0 |
0 |
T147 |
11709 |
242 |
0 |
0 |
T155 |
6887 |
157 |
0 |
0 |
T162 |
12921 |
82 |
0 |
0 |
T163 |
15648 |
38 |
0 |
0 |
T164 |
13681 |
75 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5400 |
0 |
0 |
T34 |
33754 |
314 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T136 |
62152 |
397 |
0 |
0 |
T139 |
11174 |
43 |
0 |
0 |
T143 |
7502 |
60 |
0 |
0 |
T147 |
11709 |
88 |
0 |
0 |
T155 |
6887 |
94 |
0 |
0 |
T162 |
12921 |
106 |
0 |
0 |
T163 |
15648 |
37 |
0 |
0 |
T164 |
13681 |
81 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5247 |
0 |
0 |
T34 |
33754 |
302 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T96 |
2246 |
3 |
0 |
0 |
T136 |
62152 |
202 |
0 |
0 |
T139 |
11174 |
47 |
0 |
0 |
T143 |
7502 |
48 |
0 |
0 |
T147 |
11709 |
49 |
0 |
0 |
T155 |
6887 |
23 |
0 |
0 |
T162 |
12921 |
49 |
0 |
0 |
T163 |
15648 |
27 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5120 |
0 |
0 |
T34 |
33754 |
126 |
0 |
0 |
T95 |
3119 |
5 |
0 |
0 |
T136 |
62152 |
280 |
0 |
0 |
T139 |
11174 |
81 |
0 |
0 |
T143 |
7502 |
89 |
0 |
0 |
T147 |
11709 |
107 |
0 |
0 |
T155 |
6887 |
51 |
0 |
0 |
T162 |
12921 |
38 |
0 |
0 |
T163 |
15648 |
75 |
0 |
0 |
T164 |
13681 |
70 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5806 |
0 |
0 |
T34 |
33754 |
299 |
0 |
0 |
T95 |
3119 |
8 |
0 |
0 |
T96 |
2246 |
4 |
0 |
0 |
T136 |
62152 |
174 |
0 |
0 |
T139 |
11174 |
61 |
0 |
0 |
T143 |
7502 |
98 |
0 |
0 |
T147 |
11709 |
59 |
0 |
0 |
T155 |
6887 |
21 |
0 |
0 |
T162 |
12921 |
77 |
0 |
0 |
T163 |
15648 |
49 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5268 |
0 |
0 |
T34 |
33754 |
229 |
0 |
0 |
T95 |
3119 |
8 |
0 |
0 |
T96 |
2246 |
5 |
0 |
0 |
T136 |
62152 |
261 |
0 |
0 |
T139 |
11174 |
62 |
0 |
0 |
T143 |
7502 |
29 |
0 |
0 |
T147 |
11709 |
118 |
0 |
0 |
T155 |
6887 |
22 |
0 |
0 |
T162 |
12921 |
24 |
0 |
0 |
T163 |
15648 |
83 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5284 |
0 |
0 |
T34 |
33754 |
367 |
0 |
0 |
T95 |
3119 |
8 |
0 |
0 |
T96 |
2246 |
2 |
0 |
0 |
T136 |
62152 |
340 |
0 |
0 |
T139 |
11174 |
30 |
0 |
0 |
T143 |
7502 |
5 |
0 |
0 |
T147 |
11709 |
88 |
0 |
0 |
T155 |
6887 |
7 |
0 |
0 |
T162 |
12921 |
50 |
0 |
0 |
T163 |
15648 |
24 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
4897 |
0 |
0 |
T34 |
33754 |
198 |
0 |
0 |
T95 |
3119 |
18 |
0 |
0 |
T96 |
2246 |
1 |
0 |
0 |
T136 |
62152 |
322 |
0 |
0 |
T139 |
11174 |
43 |
0 |
0 |
T143 |
7502 |
53 |
0 |
0 |
T147 |
11709 |
5 |
0 |
0 |
T155 |
6887 |
14 |
0 |
0 |
T162 |
12921 |
14 |
0 |
0 |
T163 |
15648 |
55 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5462 |
0 |
0 |
T34 |
33754 |
373 |
0 |
0 |
T95 |
3119 |
14 |
0 |
0 |
T136 |
62152 |
376 |
0 |
0 |
T139 |
11174 |
50 |
0 |
0 |
T143 |
7502 |
108 |
0 |
0 |
T147 |
11709 |
52 |
0 |
0 |
T155 |
6887 |
42 |
0 |
0 |
T162 |
12921 |
25 |
0 |
0 |
T163 |
15648 |
35 |
0 |
0 |
T164 |
13681 |
51 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5295 |
0 |
0 |
T34 |
33754 |
335 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T136 |
62152 |
407 |
0 |
0 |
T139 |
11174 |
31 |
0 |
0 |
T143 |
7502 |
68 |
0 |
0 |
T147 |
11709 |
11 |
0 |
0 |
T155 |
6887 |
35 |
0 |
0 |
T162 |
12921 |
12 |
0 |
0 |
T163 |
15648 |
51 |
0 |
0 |
T164 |
13681 |
19 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
4827 |
0 |
0 |
T34 |
33754 |
311 |
0 |
0 |
T95 |
3119 |
4 |
0 |
0 |
T98 |
2239 |
8 |
0 |
0 |
T136 |
62152 |
227 |
0 |
0 |
T139 |
11174 |
56 |
0 |
0 |
T143 |
7502 |
107 |
0 |
0 |
T147 |
11709 |
97 |
0 |
0 |
T155 |
6887 |
8 |
0 |
0 |
T162 |
12921 |
26 |
0 |
0 |
T164 |
13681 |
52 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5695 |
0 |
0 |
T34 |
33754 |
207 |
0 |
0 |
T95 |
3119 |
8 |
0 |
0 |
T96 |
2246 |
1 |
0 |
0 |
T136 |
62152 |
285 |
0 |
0 |
T139 |
11174 |
60 |
0 |
0 |
T143 |
7502 |
1 |
0 |
0 |
T147 |
11709 |
54 |
0 |
0 |
T155 |
6887 |
8 |
0 |
0 |
T162 |
12921 |
46 |
0 |
0 |
T163 |
15648 |
57 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5268 |
0 |
0 |
T34 |
33754 |
287 |
0 |
0 |
T95 |
3119 |
11 |
0 |
0 |
T136 |
62152 |
191 |
0 |
0 |
T139 |
11174 |
15 |
0 |
0 |
T143 |
7502 |
66 |
0 |
0 |
T147 |
11709 |
111 |
0 |
0 |
T155 |
6887 |
8 |
0 |
0 |
T162 |
12921 |
2 |
0 |
0 |
T163 |
15648 |
37 |
0 |
0 |
T164 |
13681 |
34 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5787 |
0 |
0 |
T34 |
33754 |
337 |
0 |
0 |
T95 |
3119 |
4 |
0 |
0 |
T136 |
62152 |
342 |
0 |
0 |
T139 |
11174 |
1 |
0 |
0 |
T143 |
7502 |
10 |
0 |
0 |
T147 |
11709 |
112 |
0 |
0 |
T155 |
6887 |
42 |
0 |
0 |
T162 |
12921 |
56 |
0 |
0 |
T163 |
15648 |
78 |
0 |
0 |
T164 |
13681 |
17 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5306 |
0 |
0 |
T34 |
33754 |
192 |
0 |
0 |
T95 |
3119 |
6 |
0 |
0 |
T136 |
62152 |
227 |
0 |
0 |
T139 |
11174 |
30 |
0 |
0 |
T143 |
7502 |
55 |
0 |
0 |
T147 |
11709 |
148 |
0 |
0 |
T155 |
6887 |
44 |
0 |
0 |
T162 |
12921 |
11 |
0 |
0 |
T163 |
15648 |
61 |
0 |
0 |
T164 |
13681 |
19 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5326 |
0 |
0 |
T34 |
33754 |
230 |
0 |
0 |
T95 |
3119 |
6 |
0 |
0 |
T136 |
62152 |
262 |
0 |
0 |
T139 |
11174 |
3 |
0 |
0 |
T143 |
7502 |
98 |
0 |
0 |
T147 |
11709 |
101 |
0 |
0 |
T155 |
6887 |
37 |
0 |
0 |
T162 |
12921 |
83 |
0 |
0 |
T163 |
15648 |
101 |
0 |
0 |
T164 |
13681 |
35 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5372 |
0 |
0 |
T34 |
33754 |
233 |
0 |
0 |
T95 |
3119 |
8 |
0 |
0 |
T136 |
62152 |
321 |
0 |
0 |
T139 |
11174 |
18 |
0 |
0 |
T143 |
7502 |
6 |
0 |
0 |
T147 |
11709 |
55 |
0 |
0 |
T155 |
6887 |
37 |
0 |
0 |
T162 |
12921 |
31 |
0 |
0 |
T163 |
15648 |
28 |
0 |
0 |
T164 |
13681 |
29 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5463 |
0 |
0 |
T34 |
33754 |
325 |
0 |
0 |
T95 |
3119 |
9 |
0 |
0 |
T96 |
2246 |
2 |
0 |
0 |
T136 |
62152 |
242 |
0 |
0 |
T139 |
11174 |
63 |
0 |
0 |
T143 |
7502 |
64 |
0 |
0 |
T147 |
11709 |
102 |
0 |
0 |
T155 |
6887 |
4 |
0 |
0 |
T162 |
12921 |
76 |
0 |
0 |
T163 |
15648 |
59 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
4967 |
0 |
0 |
T34 |
33754 |
241 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T136 |
62152 |
300 |
0 |
0 |
T139 |
11174 |
61 |
0 |
0 |
T143 |
7502 |
76 |
0 |
0 |
T147 |
11709 |
54 |
0 |
0 |
T155 |
6887 |
6 |
0 |
0 |
T162 |
12921 |
79 |
0 |
0 |
T163 |
15648 |
45 |
0 |
0 |
T164 |
13681 |
30 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
4980 |
0 |
0 |
T34 |
33754 |
217 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T96 |
2246 |
4 |
0 |
0 |
T136 |
62152 |
204 |
0 |
0 |
T139 |
11174 |
69 |
0 |
0 |
T143 |
7502 |
50 |
0 |
0 |
T147 |
11709 |
126 |
0 |
0 |
T155 |
6887 |
37 |
0 |
0 |
T162 |
12921 |
5 |
0 |
0 |
T163 |
15648 |
31 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5180 |
0 |
0 |
T34 |
33754 |
311 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T96 |
2246 |
3 |
0 |
0 |
T136 |
62152 |
214 |
0 |
0 |
T139 |
11174 |
61 |
0 |
0 |
T143 |
7502 |
76 |
0 |
0 |
T147 |
11709 |
103 |
0 |
0 |
T162 |
12921 |
41 |
0 |
0 |
T163 |
15648 |
36 |
0 |
0 |
T164 |
13681 |
20 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5079 |
0 |
0 |
T34 |
33754 |
253 |
0 |
0 |
T95 |
3119 |
6 |
0 |
0 |
T96 |
2246 |
9 |
0 |
0 |
T136 |
62152 |
235 |
0 |
0 |
T139 |
11174 |
55 |
0 |
0 |
T143 |
7502 |
1 |
0 |
0 |
T147 |
11709 |
39 |
0 |
0 |
T155 |
6887 |
40 |
0 |
0 |
T162 |
12921 |
30 |
0 |
0 |
T163 |
15648 |
9 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5460 |
0 |
0 |
T34 |
33754 |
203 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T136 |
62152 |
203 |
0 |
0 |
T139 |
11174 |
73 |
0 |
0 |
T143 |
7502 |
58 |
0 |
0 |
T147 |
11709 |
83 |
0 |
0 |
T155 |
6887 |
30 |
0 |
0 |
T162 |
12921 |
5 |
0 |
0 |
T163 |
15648 |
38 |
0 |
0 |
T164 |
13681 |
62 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5942 |
0 |
0 |
T34 |
33754 |
299 |
0 |
0 |
T95 |
3119 |
4 |
0 |
0 |
T96 |
2246 |
2 |
0 |
0 |
T136 |
62152 |
267 |
0 |
0 |
T139 |
11174 |
64 |
0 |
0 |
T143 |
7502 |
53 |
0 |
0 |
T147 |
11709 |
95 |
0 |
0 |
T155 |
6887 |
19 |
0 |
0 |
T162 |
12921 |
44 |
0 |
0 |
T163 |
15648 |
56 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
5395 |
0 |
0 |
T34 |
33754 |
276 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T96 |
2246 |
1 |
0 |
0 |
T136 |
62152 |
310 |
0 |
0 |
T139 |
11174 |
57 |
0 |
0 |
T143 |
7502 |
52 |
0 |
0 |
T147 |
11709 |
160 |
0 |
0 |
T155 |
6887 |
24 |
0 |
0 |
T162 |
12921 |
90 |
0 |
0 |
T163 |
15648 |
42 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2315 |
0 |
0 |
T34 |
33754 |
56 |
0 |
0 |
T95 |
3119 |
7 |
0 |
0 |
T96 |
2246 |
5 |
0 |
0 |
T136 |
62152 |
28 |
0 |
0 |
T139 |
11174 |
8 |
0 |
0 |
T143 |
7502 |
8 |
0 |
0 |
T147 |
11709 |
33 |
0 |
0 |
T162 |
12921 |
27 |
0 |
0 |
T163 |
15648 |
53 |
0 |
0 |
T164 |
13681 |
22 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2314 |
0 |
0 |
T34 |
33754 |
52 |
0 |
0 |
T95 |
3119 |
4 |
0 |
0 |
T136 |
62152 |
59 |
0 |
0 |
T139 |
11174 |
13 |
0 |
0 |
T143 |
7502 |
8 |
0 |
0 |
T147 |
11709 |
10 |
0 |
0 |
T150 |
2875 |
17 |
0 |
0 |
T162 |
12921 |
4 |
0 |
0 |
T163 |
15648 |
32 |
0 |
0 |
T164 |
13681 |
38 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2201 |
0 |
0 |
T34 |
33754 |
65 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T136 |
62152 |
57 |
0 |
0 |
T139 |
11174 |
9 |
0 |
0 |
T143 |
7502 |
3 |
0 |
0 |
T147 |
11709 |
13 |
0 |
0 |
T155 |
6887 |
20 |
0 |
0 |
T162 |
12921 |
9 |
0 |
0 |
T163 |
15648 |
34 |
0 |
0 |
T164 |
13681 |
55 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2202 |
0 |
0 |
T34 |
33754 |
53 |
0 |
0 |
T95 |
3119 |
7 |
0 |
0 |
T96 |
2246 |
6 |
0 |
0 |
T136 |
62152 |
48 |
0 |
0 |
T139 |
11174 |
7 |
0 |
0 |
T143 |
7502 |
19 |
0 |
0 |
T147 |
11709 |
12 |
0 |
0 |
T162 |
12921 |
19 |
0 |
0 |
T163 |
15648 |
38 |
0 |
0 |
T164 |
13681 |
60 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2747 |
0 |
0 |
T34 |
33754 |
68 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T136 |
62152 |
86 |
0 |
0 |
T139 |
11174 |
9 |
0 |
0 |
T143 |
7502 |
19 |
0 |
0 |
T147 |
11709 |
21 |
0 |
0 |
T150 |
2875 |
1 |
0 |
0 |
T162 |
12921 |
14 |
0 |
0 |
T163 |
15648 |
21 |
0 |
0 |
T164 |
13681 |
42 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
4607 |
0 |
0 |
T34 |
0 |
212 |
0 |
0 |
T39 |
7914 |
44 |
0 |
0 |
T90 |
75413 |
0 |
0 |
0 |
T91 |
160117 |
0 |
0 |
0 |
T95 |
0 |
3 |
0 |
0 |
T139 |
0 |
17 |
0 |
0 |
T155 |
0 |
19 |
0 |
0 |
T166 |
0 |
54 |
0 |
0 |
T167 |
0 |
19 |
0 |
0 |
T168 |
0 |
27 |
0 |
0 |
T169 |
0 |
5 |
0 |
0 |
T170 |
0 |
24 |
0 |
0 |
T171 |
828381 |
0 |
0 |
0 |
T172 |
1535 |
0 |
0 |
0 |
T173 |
6576 |
0 |
0 |
0 |
T174 |
43301 |
0 |
0 |
0 |
T175 |
1528 |
0 |
0 |
0 |
T176 |
11787 |
0 |
0 |
0 |
T177 |
32867 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2335 |
0 |
0 |
T34 |
33754 |
53 |
0 |
0 |
T95 |
3119 |
2 |
0 |
0 |
T96 |
2246 |
2 |
0 |
0 |
T136 |
62152 |
58 |
0 |
0 |
T139 |
11174 |
10 |
0 |
0 |
T143 |
7502 |
5 |
0 |
0 |
T147 |
11709 |
5 |
0 |
0 |
T155 |
6887 |
3 |
0 |
0 |
T162 |
12921 |
16 |
0 |
0 |
T163 |
15648 |
66 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2172 |
0 |
0 |
T34 |
33754 |
55 |
0 |
0 |
T95 |
3119 |
8 |
0 |
0 |
T136 |
62152 |
63 |
0 |
0 |
T139 |
11174 |
23 |
0 |
0 |
T143 |
7502 |
13 |
0 |
0 |
T147 |
11709 |
21 |
0 |
0 |
T155 |
6887 |
4 |
0 |
0 |
T162 |
12921 |
11 |
0 |
0 |
T163 |
15648 |
21 |
0 |
0 |
T164 |
13681 |
13 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2030 |
0 |
0 |
T34 |
33754 |
41 |
0 |
0 |
T95 |
3119 |
2 |
0 |
0 |
T96 |
2246 |
6 |
0 |
0 |
T136 |
62152 |
41 |
0 |
0 |
T139 |
11174 |
1 |
0 |
0 |
T143 |
7502 |
2 |
0 |
0 |
T147 |
11709 |
14 |
0 |
0 |
T155 |
6887 |
1 |
0 |
0 |
T163 |
15648 |
46 |
0 |
0 |
T164 |
13681 |
23 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2101 |
0 |
0 |
T34 |
33754 |
37 |
0 |
0 |
T95 |
3119 |
6 |
0 |
0 |
T96 |
2246 |
2 |
0 |
0 |
T136 |
62152 |
55 |
0 |
0 |
T139 |
11174 |
6 |
0 |
0 |
T143 |
7502 |
9 |
0 |
0 |
T147 |
11709 |
11 |
0 |
0 |
T155 |
6887 |
4 |
0 |
0 |
T162 |
12921 |
15 |
0 |
0 |
T163 |
15648 |
61 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
1797 |
0 |
0 |
T34 |
33754 |
28 |
0 |
0 |
T95 |
3119 |
10 |
0 |
0 |
T136 |
62152 |
44 |
0 |
0 |
T139 |
11174 |
2 |
0 |
0 |
T143 |
7502 |
2 |
0 |
0 |
T147 |
11709 |
12 |
0 |
0 |
T155 |
6887 |
8 |
0 |
0 |
T162 |
12921 |
2 |
0 |
0 |
T163 |
15648 |
52 |
0 |
0 |
T164 |
13681 |
30 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2116 |
0 |
0 |
T34 |
33754 |
44 |
0 |
0 |
T95 |
3119 |
9 |
0 |
0 |
T96 |
2246 |
4 |
0 |
0 |
T136 |
62152 |
30 |
0 |
0 |
T139 |
11174 |
1 |
0 |
0 |
T143 |
7502 |
5 |
0 |
0 |
T147 |
11709 |
11 |
0 |
0 |
T155 |
6887 |
10 |
0 |
0 |
T162 |
12921 |
6 |
0 |
0 |
T163 |
15648 |
62 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2628 |
0 |
0 |
T34 |
33754 |
34 |
0 |
0 |
T95 |
3119 |
2 |
0 |
0 |
T136 |
62152 |
71 |
0 |
0 |
T139 |
11174 |
15 |
0 |
0 |
T143 |
7502 |
13 |
0 |
0 |
T147 |
11709 |
34 |
0 |
0 |
T155 |
6887 |
1 |
0 |
0 |
T162 |
12921 |
18 |
0 |
0 |
T163 |
15648 |
21 |
0 |
0 |
T164 |
13681 |
8 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
1881 |
0 |
0 |
T34 |
33754 |
25 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T136 |
62152 |
32 |
0 |
0 |
T143 |
7502 |
9 |
0 |
0 |
T147 |
11709 |
7 |
0 |
0 |
T162 |
12921 |
10 |
0 |
0 |
T163 |
15648 |
19 |
0 |
0 |
T164 |
13681 |
56 |
0 |
0 |
T165 |
35862 |
31 |
0 |
0 |
T178 |
17888 |
11 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
3344 |
0 |
0 |
T34 |
33754 |
132 |
0 |
0 |
T95 |
3119 |
6 |
0 |
0 |
T96 |
2246 |
5 |
0 |
0 |
T136 |
62152 |
175 |
0 |
0 |
T139 |
11174 |
16 |
0 |
0 |
T143 |
7502 |
33 |
0 |
0 |
T147 |
11709 |
31 |
0 |
0 |
T155 |
6887 |
9 |
0 |
0 |
T162 |
12921 |
14 |
0 |
0 |
T163 |
15648 |
42 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2190 |
0 |
0 |
T34 |
33754 |
40 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T96 |
2246 |
7 |
0 |
0 |
T136 |
62152 |
63 |
0 |
0 |
T139 |
11174 |
10 |
0 |
0 |
T143 |
7502 |
8 |
0 |
0 |
T147 |
11709 |
3 |
0 |
0 |
T155 |
6887 |
1 |
0 |
0 |
T162 |
12921 |
24 |
0 |
0 |
T163 |
15648 |
35 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
1890 |
0 |
0 |
T34 |
33754 |
43 |
0 |
0 |
T95 |
3119 |
8 |
0 |
0 |
T136 |
62152 |
34 |
0 |
0 |
T139 |
11174 |
5 |
0 |
0 |
T143 |
7502 |
13 |
0 |
0 |
T147 |
11709 |
8 |
0 |
0 |
T155 |
6887 |
1 |
0 |
0 |
T162 |
12921 |
16 |
0 |
0 |
T163 |
15648 |
57 |
0 |
0 |
T164 |
13681 |
18 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
1890 |
0 |
0 |
T34 |
33754 |
27 |
0 |
0 |
T95 |
3119 |
9 |
0 |
0 |
T96 |
2246 |
3 |
0 |
0 |
T136 |
62152 |
40 |
0 |
0 |
T143 |
7502 |
6 |
0 |
0 |
T147 |
11709 |
9 |
0 |
0 |
T155 |
6887 |
3 |
0 |
0 |
T162 |
12921 |
16 |
0 |
0 |
T163 |
15648 |
34 |
0 |
0 |
T164 |
13681 |
56 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2078 |
0 |
0 |
T34 |
33754 |
53 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T96 |
2246 |
6 |
0 |
0 |
T136 |
62152 |
50 |
0 |
0 |
T139 |
11174 |
11 |
0 |
0 |
T143 |
7502 |
9 |
0 |
0 |
T147 |
11709 |
11 |
0 |
0 |
T155 |
6887 |
7 |
0 |
0 |
T162 |
12921 |
27 |
0 |
0 |
T163 |
15648 |
54 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2040 |
0 |
0 |
T34 |
33754 |
32 |
0 |
0 |
T95 |
3119 |
12 |
0 |
0 |
T96 |
2246 |
7 |
0 |
0 |
T136 |
62152 |
37 |
0 |
0 |
T139 |
11174 |
4 |
0 |
0 |
T143 |
7502 |
7 |
0 |
0 |
T147 |
11709 |
14 |
0 |
0 |
T162 |
12921 |
12 |
0 |
0 |
T163 |
15648 |
12 |
0 |
0 |
T164 |
13681 |
82 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2022 |
0 |
0 |
T34 |
33754 |
38 |
0 |
0 |
T35 |
13981 |
6 |
0 |
0 |
T95 |
3119 |
3 |
0 |
0 |
T96 |
2246 |
5 |
0 |
0 |
T136 |
62152 |
26 |
0 |
0 |
T139 |
11174 |
7 |
0 |
0 |
T143 |
7502 |
7 |
0 |
0 |
T155 |
6887 |
2 |
0 |
0 |
T162 |
12921 |
30 |
0 |
0 |
T163 |
15648 |
86 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
108070557 |
2071 |
0 |
0 |
T34 |
33754 |
51 |
0 |
0 |
T95 |
3119 |
11 |
0 |
0 |
T136 |
62152 |
46 |
0 |
0 |
T139 |
11174 |
5 |
0 |
0 |
T143 |
7502 |
5 |
0 |
0 |
T147 |
11709 |
16 |
0 |
0 |
T150 |
2875 |
9 |
0 |
0 |
T162 |
12921 |
16 |
0 |
0 |
T163 |
15648 |
95 |
0 |
0 |
T164 |
13681 |
82 |
0 |
0 |