Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.06 97.50 92.82 98.61 80.85 95.87 90.94 87.83


Total test records in report: 824
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T764 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.462218182 Apr 28 01:04:23 PM PDT 24 Apr 28 01:04:27 PM PDT 24 278054856 ps
T765 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3559814231 Apr 28 01:04:23 PM PDT 24 Apr 28 01:04:48 PM PDT 24 1060227684 ps
T151 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.174983237 Apr 28 01:04:15 PM PDT 24 Apr 28 01:04:19 PM PDT 24 104904611 ps
T374 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.222166609 Apr 28 01:04:14 PM PDT 24 Apr 28 01:04:37 PM PDT 24 1032102035 ps
T766 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1263389622 Apr 28 01:04:02 PM PDT 24 Apr 28 01:04:04 PM PDT 24 121093971 ps
T767 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3612893778 Apr 28 01:04:40 PM PDT 24 Apr 28 01:04:41 PM PDT 24 37780571 ps
T126 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3318949279 Apr 28 01:04:20 PM PDT 24 Apr 28 01:04:25 PM PDT 24 1029394313 ps
T130 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.830576744 Apr 28 01:04:24 PM PDT 24 Apr 28 01:04:28 PM PDT 24 189555052 ps
T378 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3252781418 Apr 28 01:04:07 PM PDT 24 Apr 28 01:04:16 PM PDT 24 555035463 ps
T768 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3575602581 Apr 28 01:04:34 PM PDT 24 Apr 28 01:04:36 PM PDT 24 27195705 ps
T769 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.664519382 Apr 28 01:04:07 PM PDT 24 Apr 28 01:04:10 PM PDT 24 40992043 ps
T770 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1766229829 Apr 28 01:04:13 PM PDT 24 Apr 28 01:04:16 PM PDT 24 61184113 ps
T771 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1942605435 Apr 28 01:03:58 PM PDT 24 Apr 28 01:04:00 PM PDT 24 22219621 ps
T375 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2165596319 Apr 28 01:04:19 PM PDT 24 Apr 28 01:04:26 PM PDT 24 107291083 ps
T772 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2268307315 Apr 28 01:04:37 PM PDT 24 Apr 28 01:04:38 PM PDT 24 46290697 ps
T773 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1796462751 Apr 28 01:04:13 PM PDT 24 Apr 28 01:04:16 PM PDT 24 211649354 ps
T774 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4198907990 Apr 28 01:04:38 PM PDT 24 Apr 28 01:04:39 PM PDT 24 12257543 ps
T775 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2245436149 Apr 28 01:04:08 PM PDT 24 Apr 28 01:04:10 PM PDT 24 95854197 ps
T371 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.314188168 Apr 28 01:04:03 PM PDT 24 Apr 28 01:04:18 PM PDT 24 2460758406 ps
T152 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3823340675 Apr 28 01:04:23 PM PDT 24 Apr 28 01:04:26 PM PDT 24 165260949 ps
T776 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1989284689 Apr 28 01:04:23 PM PDT 24 Apr 28 01:04:27 PM PDT 24 3025988826 ps
T372 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1879889156 Apr 28 01:04:17 PM PDT 24 Apr 28 01:04:24 PM PDT 24 106363305 ps
T777 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2540470280 Apr 28 01:04:27 PM PDT 24 Apr 28 01:04:30 PM PDT 24 41770690 ps
T373 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2337340296 Apr 28 01:04:27 PM PDT 24 Apr 28 01:04:42 PM PDT 24 666873761 ps
T778 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1851407688 Apr 28 01:04:32 PM PDT 24 Apr 28 01:04:33 PM PDT 24 89756359 ps
T779 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1152168126 Apr 28 01:04:35 PM PDT 24 Apr 28 01:04:37 PM PDT 24 47902457 ps
T780 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4166685414 Apr 28 01:04:18 PM PDT 24 Apr 28 01:04:21 PM PDT 24 124519487 ps
T781 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.478926082 Apr 28 01:04:34 PM PDT 24 Apr 28 01:04:36 PM PDT 24 16607620 ps
T782 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.324164316 Apr 28 01:04:23 PM PDT 24 Apr 28 01:04:28 PM PDT 24 129735420 ps
T783 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4141036870 Apr 28 01:04:32 PM PDT 24 Apr 28 01:04:33 PM PDT 24 159328944 ps
T784 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2514050326 Apr 28 01:04:10 PM PDT 24 Apr 28 01:04:11 PM PDT 24 20525457 ps
T785 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.469195885 Apr 28 01:04:23 PM PDT 24 Apr 28 01:04:28 PM PDT 24 682193253 ps
T786 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2105242818 Apr 28 01:04:41 PM PDT 24 Apr 28 01:04:43 PM PDT 24 17796917 ps
T787 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2485711996 Apr 28 01:04:04 PM PDT 24 Apr 28 01:04:31 PM PDT 24 1895793325 ps
T788 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4007308206 Apr 28 01:04:38 PM PDT 24 Apr 28 01:04:39 PM PDT 24 17565221 ps
T789 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.652016626 Apr 28 01:04:08 PM PDT 24 Apr 28 01:04:12 PM PDT 24 244931090 ps
T131 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3111122276 Apr 28 01:04:02 PM PDT 24 Apr 28 01:04:06 PM PDT 24 421282073 ps
T790 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1603012526 Apr 28 01:04:22 PM PDT 24 Apr 28 01:04:25 PM PDT 24 63423366 ps
T791 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.721506241 Apr 28 01:04:29 PM PDT 24 Apr 28 01:04:36 PM PDT 24 427599472 ps
T792 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.391791753 Apr 28 01:04:27 PM PDT 24 Apr 28 01:04:29 PM PDT 24 191434466 ps
T793 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1434644582 Apr 28 01:04:22 PM PDT 24 Apr 28 01:04:26 PM PDT 24 77974762 ps
T794 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2056021580 Apr 28 01:04:02 PM PDT 24 Apr 28 01:04:26 PM PDT 24 731578568 ps
T795 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.860314394 Apr 28 01:03:59 PM PDT 24 Apr 28 01:04:01 PM PDT 24 23002676 ps
T796 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3858086173 Apr 28 01:04:12 PM PDT 24 Apr 28 01:04:25 PM PDT 24 200132966 ps
T797 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4061937213 Apr 28 01:04:05 PM PDT 24 Apr 28 01:04:27 PM PDT 24 1064238593 ps
T798 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1296434035 Apr 28 01:04:13 PM PDT 24 Apr 28 01:04:18 PM PDT 24 261447602 ps
T799 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.907651118 Apr 28 01:04:02 PM PDT 24 Apr 28 01:04:05 PM PDT 24 62278582 ps
T800 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.812134769 Apr 28 01:04:19 PM PDT 24 Apr 28 01:04:23 PM PDT 24 1800751250 ps
T801 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4035942621 Apr 28 01:04:28 PM PDT 24 Apr 28 01:04:33 PM PDT 24 201721011 ps
T802 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1599708429 Apr 28 01:04:09 PM PDT 24 Apr 28 01:04:18 PM PDT 24 387007378 ps
T97 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1311002046 Apr 28 01:04:04 PM PDT 24 Apr 28 01:04:06 PM PDT 24 125762185 ps
T803 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3408631012 Apr 28 01:04:22 PM PDT 24 Apr 28 01:04:23 PM PDT 24 12150117 ps
T804 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2491508741 Apr 28 01:04:34 PM PDT 24 Apr 28 01:04:36 PM PDT 24 56497164 ps
T805 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3511803342 Apr 28 01:04:18 PM PDT 24 Apr 28 01:04:20 PM PDT 24 135627721 ps
T806 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3012653210 Apr 28 01:03:57 PM PDT 24 Apr 28 01:04:05 PM PDT 24 789874979 ps
T807 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1074386888 Apr 28 01:04:26 PM PDT 24 Apr 28 01:04:29 PM PDT 24 35673370 ps
T377 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.133209916 Apr 28 01:04:28 PM PDT 24 Apr 28 01:04:42 PM PDT 24 760144917 ps
T808 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2352454091 Apr 28 01:04:04 PM PDT 24 Apr 28 01:04:16 PM PDT 24 387034307 ps
T809 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2802391211 Apr 28 01:04:21 PM PDT 24 Apr 28 01:04:25 PM PDT 24 564540093 ps
T810 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1242267934 Apr 28 01:04:18 PM PDT 24 Apr 28 01:04:21 PM PDT 24 71392048 ps
T811 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1382888879 Apr 28 01:04:02 PM PDT 24 Apr 28 01:04:17 PM PDT 24 911266157 ps
T812 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3386843191 Apr 28 01:04:04 PM PDT 24 Apr 28 01:04:06 PM PDT 24 37967213 ps
T813 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2036231625 Apr 28 01:04:10 PM PDT 24 Apr 28 01:04:33 PM PDT 24 1396911145 ps
T814 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4129931771 Apr 28 01:04:28 PM PDT 24 Apr 28 01:04:32 PM PDT 24 390368495 ps
T815 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.492472362 Apr 28 01:04:01 PM PDT 24 Apr 28 01:04:03 PM PDT 24 69638588 ps
T816 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1532151848 Apr 28 01:04:10 PM PDT 24 Apr 28 01:04:11 PM PDT 24 46480624 ps
T817 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2966815018 Apr 28 01:04:05 PM PDT 24 Apr 28 01:04:07 PM PDT 24 102025296 ps
T818 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3638008499 Apr 28 01:04:17 PM PDT 24 Apr 28 01:04:19 PM PDT 24 26699112 ps
T819 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4002761215 Apr 28 01:04:23 PM PDT 24 Apr 28 01:04:25 PM PDT 24 26078841 ps
T820 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3872478280 Apr 28 01:04:27 PM PDT 24 Apr 28 01:04:29 PM PDT 24 28198120 ps
T821 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3669418889 Apr 28 01:04:07 PM PDT 24 Apr 28 01:04:08 PM PDT 24 269357444 ps
T822 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2922866845 Apr 28 01:04:37 PM PDT 24 Apr 28 01:04:39 PM PDT 24 22629221 ps
T823 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.400258216 Apr 28 01:04:02 PM PDT 24 Apr 28 01:04:05 PM PDT 24 44104607 ps
T824 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1961138947 Apr 28 01:04:09 PM PDT 24 Apr 28 01:04:13 PM PDT 24 97567777 ps

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.109415299
Short name T2
Test name
Test status
Simulation time 9141821650 ps
CPU time 13.51 seconds
Started Apr 28 01:12:49 PM PDT 24
Finished Apr 28 01:13:03 PM PDT 24
Peak memory 235112 kb
Host smart-17ecde9d-696c-4d12-8150-1bfd2bf8ec62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109415299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.109415299
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.747150615
Short name T61
Test name
Test status
Simulation time 472561688 ps
CPU time 3.88 seconds
Started Apr 28 01:17:03 PM PDT 24
Finished Apr 28 01:17:53 PM PDT 24
Peak memory 218844 kb
Host smart-1abc03d4-9733-4782-b6b6-a16949fd716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747150615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.747150615
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1840134673
Short name T17
Test name
Test status
Simulation time 156368527 ps
CPU time 2.78 seconds
Started Apr 28 01:16:47 PM PDT 24
Finished Apr 28 01:17:36 PM PDT 24
Peak memory 216204 kb
Host smart-68d85fb7-cedd-4a0e-83f4-a8be1117b148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840134673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1840134673
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_upload.4119180358
Short name T8
Test name
Test status
Simulation time 24609939718 ps
CPU time 29.58 seconds
Started Apr 28 01:12:39 PM PDT 24
Finished Apr 28 01:13:09 PM PDT 24
Peak memory 240956 kb
Host smart-1db8e2d2-92a9-45f1-a5bc-2bca2f3e0831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119180358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4119180358
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_intercept.882763043
Short name T43
Test name
Test status
Simulation time 1405591480 ps
CPU time 7.98 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:55 PM PDT 24
Peak memory 218484 kb
Host smart-29c2a9c8-12da-46dd-8b23-fcec213ae10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882763043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.882763043
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.100491200
Short name T34
Test name
Test status
Simulation time 347985522 ps
CPU time 8.13 seconds
Started Apr 28 01:04:09 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 215200 kb
Host smart-07613914-85da-4637-bae1-f6bd4791fbbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100491200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.100491200
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1441699556
Short name T33
Test name
Test status
Simulation time 198761677 ps
CPU time 1 seconds
Started Apr 28 01:13:31 PM PDT 24
Finished Apr 28 01:13:34 PM PDT 24
Peak memory 206880 kb
Host smart-058bb635-b716-4874-b5aa-da322c3a5c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441699556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1441699556
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.714774955
Short name T401
Test name
Test status
Simulation time 2678783769 ps
CPU time 31.22 seconds
Started Apr 28 01:15:15 PM PDT 24
Finished Apr 28 01:16:22 PM PDT 24
Peak memory 216312 kb
Host smart-54a02302-d95d-4ea1-ae25-471c1b698beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714774955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.714774955
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2363042826
Short name T88
Test name
Test status
Simulation time 473306902 ps
CPU time 8.35 seconds
Started Apr 28 01:16:52 PM PDT 24
Finished Apr 28 01:17:49 PM PDT 24
Peak memory 218752 kb
Host smart-c30512a4-2c3f-4965-a048-efb4cce4559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363042826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2363042826
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1804157833
Short name T100
Test name
Test status
Simulation time 40977454269 ps
CPU time 51.57 seconds
Started Apr 28 01:12:58 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 216284 kb
Host smart-9d8c6677-be6c-46db-bf96-758f4ab7679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804157833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1804157833
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1328679311
Short name T1
Test name
Test status
Simulation time 241741816 ps
CPU time 2.77 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:10 PM PDT 24
Peak memory 223168 kb
Host smart-ef559b53-8621-4eec-8948-bc385ee4e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328679311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1328679311
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1992687901
Short name T40
Test name
Test status
Simulation time 43988258 ps
CPU time 0.76 seconds
Started Apr 28 01:12:31 PM PDT 24
Finished Apr 28 01:12:33 PM PDT 24
Peak memory 216176 kb
Host smart-7ae474ae-749a-425e-8c28-c795fd343d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992687901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1992687901
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.570433275
Short name T44
Test name
Test status
Simulation time 2063726544 ps
CPU time 22.1 seconds
Started Apr 28 01:14:06 PM PDT 24
Finished Apr 28 01:14:36 PM PDT 24
Peak memory 224420 kb
Host smart-fe81a4a3-e1d7-451e-b3b5-83f909eac20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570433275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.570433275
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1077324659
Short name T412
Test name
Test status
Simulation time 7284220996 ps
CPU time 37.47 seconds
Started Apr 28 01:16:58 PM PDT 24
Finished Apr 28 01:18:22 PM PDT 24
Peak memory 218744 kb
Host smart-070e8b50-4a6a-4805-a1f5-5cff5a3fccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077324659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1077324659
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1173633046
Short name T83
Test name
Test status
Simulation time 520010408 ps
CPU time 15.7 seconds
Started Apr 28 01:13:52 PM PDT 24
Finished Apr 28 01:14:13 PM PDT 24
Peak memory 252692 kb
Host smart-64f26d2a-1fd3-4da2-a0fb-766e81f0bff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173633046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1173633046
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3217284488
Short name T35
Test name
Test status
Simulation time 141241094 ps
CPU time 3.38 seconds
Started Apr 28 01:04:19 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 215320 kb
Host smart-ea0cdd81-a218-4f83-8b36-ef4fb21c288c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217284488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
217284488
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.179986665
Short name T4
Test name
Test status
Simulation time 719727042 ps
CPU time 10.08 seconds
Started Apr 28 01:14:24 PM PDT 24
Finished Apr 28 01:15:00 PM PDT 24
Peak memory 224336 kb
Host smart-c3dd3e95-5a92-4416-b00c-d26240db48c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179986665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.179986665
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1394375407
Short name T385
Test name
Test status
Simulation time 12773033926 ps
CPU time 63.55 seconds
Started Apr 28 01:12:50 PM PDT 24
Finished Apr 28 01:13:55 PM PDT 24
Peak memory 216372 kb
Host smart-ac7a8146-346c-4a90-9996-5e9af73c4333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394375407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1394375407
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3484855416
Short name T350
Test name
Test status
Simulation time 533785043 ps
CPU time 12.04 seconds
Started Apr 28 01:12:21 PM PDT 24
Finished Apr 28 01:12:34 PM PDT 24
Peak memory 224064 kb
Host smart-d14e57fa-7c1c-4a1f-9c25-f944ef575023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484855416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3484855416
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4138908016
Short name T435
Test name
Test status
Simulation time 36715994 ps
CPU time 0.67 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:00 PM PDT 24
Peak memory 205412 kb
Host smart-df628dd1-9f44-4bfc-ad8c-e09f5b584160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138908016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
138908016
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3772927962
Short name T279
Test name
Test status
Simulation time 3932453157 ps
CPU time 9.52 seconds
Started Apr 28 01:15:09 PM PDT 24
Finished Apr 28 01:15:55 PM PDT 24
Peak memory 223060 kb
Host smart-bbc26c1d-ea2c-470f-922f-e9c5c1006eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772927962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3772927962
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_upload.108307758
Short name T290
Test name
Test status
Simulation time 595014151 ps
CPU time 4.66 seconds
Started Apr 28 01:12:58 PM PDT 24
Finished Apr 28 01:13:05 PM PDT 24
Peak memory 218528 kb
Host smart-5ec1a9d5-e4b2-48b5-95c5-99ec808adb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108307758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.108307758
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3360417406
Short name T140
Test name
Test status
Simulation time 79188142 ps
CPU time 2.35 seconds
Started Apr 28 01:04:31 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 215044 kb
Host smart-31f91988-2cb5-45fa-88cd-522fecbf951b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360417406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3360417406
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1324694246
Short name T347
Test name
Test status
Simulation time 493433364 ps
CPU time 12.14 seconds
Started Apr 28 01:16:59 PM PDT 24
Finished Apr 28 01:17:58 PM PDT 24
Peak memory 233744 kb
Host smart-254112f3-ad68-47c9-ab47-109872f19700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324694246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1324694246
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2178413282
Short name T406
Test name
Test status
Simulation time 14160022404 ps
CPU time 67.54 seconds
Started Apr 28 01:14:45 PM PDT 24
Finished Apr 28 01:16:29 PM PDT 24
Peak memory 216288 kb
Host smart-550a781a-b15a-4cb9-9408-7c082990e631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178413282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2178413282
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.926126992
Short name T73
Test name
Test status
Simulation time 13725324620 ps
CPU time 15.54 seconds
Started Apr 28 01:15:47 PM PDT 24
Finished Apr 28 01:16:37 PM PDT 24
Peak memory 234268 kb
Host smart-e272fdce-d73f-4c86-afec-7f0261c9aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926126992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.926126992
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2653129177
Short name T275
Test name
Test status
Simulation time 4319398912 ps
CPU time 11.12 seconds
Started Apr 28 01:13:17 PM PDT 24
Finished Apr 28 01:13:28 PM PDT 24
Peak memory 227144 kb
Host smart-3d49c105-7967-4c61-9294-27af64ee8253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653129177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2653129177
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2783219649
Short name T68
Test name
Test status
Simulation time 37591479945 ps
CPU time 17.78 seconds
Started Apr 28 01:14:07 PM PDT 24
Finished Apr 28 01:14:33 PM PDT 24
Peak memory 223232 kb
Host smart-5e5b4b0d-b3ad-4ae6-8c89-65ca109f2831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783219649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2783219649
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3611714435
Short name T243
Test name
Test status
Simulation time 3934201878 ps
CPU time 15.1 seconds
Started Apr 28 01:14:30 PM PDT 24
Finished Apr 28 01:15:16 PM PDT 24
Peak memory 224536 kb
Host smart-1320d1aa-74e7-4279-ac7b-2313f7c0c0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611714435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3611714435
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1271406429
Short name T396
Test name
Test status
Simulation time 13128974895 ps
CPU time 62.26 seconds
Started Apr 28 01:15:36 PM PDT 24
Finished Apr 28 01:17:13 PM PDT 24
Peak memory 216364 kb
Host smart-c236fcf1-04b5-4939-9080-8f191a3fbe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271406429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1271406429
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3300180563
Short name T225
Test name
Test status
Simulation time 10627879507 ps
CPU time 15.41 seconds
Started Apr 28 01:17:09 PM PDT 24
Finished Apr 28 01:18:09 PM PDT 24
Peak memory 238992 kb
Host smart-3e80f738-b89d-4293-b508-41b76f812716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300180563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3300180563
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4078401423
Short name T74
Test name
Test status
Simulation time 1561268291 ps
CPU time 8.54 seconds
Started Apr 28 01:17:26 PM PDT 24
Finished Apr 28 01:18:17 PM PDT 24
Peak memory 223036 kb
Host smart-36f1575e-dd84-44df-869e-dd34781fb2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078401423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4078401423
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2393285622
Short name T92
Test name
Test status
Simulation time 6408608441 ps
CPU time 15.73 seconds
Started Apr 28 01:13:25 PM PDT 24
Finished Apr 28 01:13:42 PM PDT 24
Peak memory 233628 kb
Host smart-db04adf7-9995-4bbf-95fd-d8c90530d6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393285622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2393285622
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3607647453
Short name T10
Test name
Test status
Simulation time 1545574122 ps
CPU time 9.37 seconds
Started Apr 28 01:14:40 PM PDT 24
Finished Apr 28 01:15:25 PM PDT 24
Peak memory 222800 kb
Host smart-6d80272d-1ba9-4d6c-915e-75c696bd051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607647453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3607647453
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1301382046
Short name T11
Test name
Test status
Simulation time 52498361073 ps
CPU time 22.58 seconds
Started Apr 28 01:14:55 PM PDT 24
Finished Apr 28 01:15:53 PM PDT 24
Peak memory 216388 kb
Host smart-01521e24-584e-4e2f-8cb2-0eb5d773cfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301382046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1301382046
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_upload.690036644
Short name T381
Test name
Test status
Simulation time 717555610 ps
CPU time 5.99 seconds
Started Apr 28 01:14:18 PM PDT 24
Finished Apr 28 01:14:45 PM PDT 24
Peak memory 224580 kb
Host smart-812993af-20f1-451c-a09d-006e375e6bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690036644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.690036644
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.26126209
Short name T200
Test name
Test status
Simulation time 6937486402 ps
CPU time 24.65 seconds
Started Apr 28 01:12:40 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 217720 kb
Host smart-8ed4bb9a-635d-4a2f-ba88-b65dfd3265e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26126209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.26126209
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1425976668
Short name T93
Test name
Test status
Simulation time 11726606139 ps
CPU time 67.69 seconds
Started Apr 28 01:17:48 PM PDT 24
Finished Apr 28 01:19:37 PM PDT 24
Peak memory 231500 kb
Host smart-b8cde19c-4a42-4f71-94f6-4a940b0edcc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425976668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1425976668
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1808063913
Short name T32
Test name
Test status
Simulation time 36607111 ps
CPU time 1.01 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:12:30 PM PDT 24
Peak memory 235004 kb
Host smart-62ff50b3-50ce-4d88-b1af-40d6586dfb81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808063913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1808063913
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3318949279
Short name T126
Test name
Test status
Simulation time 1029394313 ps
CPU time 4.66 seconds
Started Apr 28 01:04:20 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 215120 kb
Host smart-3d2f11ab-2978-4a04-a2e1-ade204b09d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318949279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3318949279
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.944636675
Short name T303
Test name
Test status
Simulation time 2423414661 ps
CPU time 23.82 seconds
Started Apr 28 01:13:59 PM PDT 24
Finished Apr 28 01:14:26 PM PDT 24
Peak memory 224492 kb
Host smart-79791c55-c617-4596-8ffa-03cdeae42d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944636675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.944636675
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3957955784
Short name T364
Test name
Test status
Simulation time 603117305 ps
CPU time 4.37 seconds
Started Apr 28 01:13:00 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 216736 kb
Host smart-14e5d473-9fd1-498c-b9fc-7f89e5d649c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957955784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3957955784
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1182028871
Short name T263
Test name
Test status
Simulation time 9469183841 ps
CPU time 75.66 seconds
Started Apr 28 01:17:10 PM PDT 24
Finished Apr 28 01:19:09 PM PDT 24
Peak memory 240396 kb
Host smart-fa1c5065-b380-43ea-a0b3-e8639522ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182028871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1182028871
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3608179874
Short name T91
Test name
Test status
Simulation time 6671654565 ps
CPU time 17.57 seconds
Started Apr 28 01:12:25 PM PDT 24
Finished Apr 28 01:12:43 PM PDT 24
Peak memory 224396 kb
Host smart-b9b3f3a9-e609-4423-8391-15a88578143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608179874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3608179874
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2678190798
Short name T415
Test name
Test status
Simulation time 15894203489 ps
CPU time 32.09 seconds
Started Apr 28 01:13:15 PM PDT 24
Finished Apr 28 01:13:47 PM PDT 24
Peak memory 216380 kb
Host smart-e72570dd-ece3-4848-b309-308ab684f36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678190798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2678190798
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1228833404
Short name T281
Test name
Test status
Simulation time 6888297027 ps
CPU time 11.48 seconds
Started Apr 28 01:14:43 PM PDT 24
Finished Apr 28 01:15:30 PM PDT 24
Peak memory 223160 kb
Host smart-1ae3b333-7940-4665-bde0-09955e730b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228833404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1228833404
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2104517866
Short name T118
Test name
Test status
Simulation time 395435489 ps
CPU time 6.68 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:35 PM PDT 24
Peak memory 215684 kb
Host smart-3f77b8c3-8ef7-4d63-a9b2-0af6667ebdea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104517866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2104517866
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1294536757
Short name T259
Test name
Test status
Simulation time 1011043579 ps
CPU time 9.89 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:17 PM PDT 24
Peak memory 223396 kb
Host smart-458737d2-7982-4ee5-ac7c-1779f38e14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294536757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1294536757
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2381725768
Short name T77
Test name
Test status
Simulation time 13563880332 ps
CPU time 14.86 seconds
Started Apr 28 01:13:09 PM PDT 24
Finished Apr 28 01:13:25 PM PDT 24
Peak memory 225148 kb
Host smart-8b0fb76b-e88c-4075-bf39-beb68e4f90da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381725768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2381725768
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_upload.777091572
Short name T25
Test name
Test status
Simulation time 8528900450 ps
CPU time 26.15 seconds
Started Apr 28 01:16:41 PM PDT 24
Finished Apr 28 01:17:54 PM PDT 24
Peak memory 235172 kb
Host smart-59ff4e3c-8431-4639-af99-3b119de1dcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777091572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.777091572
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.802274795
Short name T288
Test name
Test status
Simulation time 1606052582 ps
CPU time 3.76 seconds
Started Apr 28 01:14:11 PM PDT 24
Finished Apr 28 01:14:26 PM PDT 24
Peak memory 216748 kb
Host smart-6a868e1d-2545-42b3-ae2e-05e089cf0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802274795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.802274795
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_upload.2274058821
Short name T211
Test name
Test status
Simulation time 2317114436 ps
CPU time 8.91 seconds
Started Apr 28 01:14:32 PM PDT 24
Finished Apr 28 01:15:13 PM PDT 24
Peak memory 224560 kb
Host smart-f5bdd1e3-7e65-4980-8398-93dd44475e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274058821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2274058821
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1660252055
Short name T297
Test name
Test status
Simulation time 40537925400 ps
CPU time 34.43 seconds
Started Apr 28 01:16:57 PM PDT 24
Finished Apr 28 01:18:18 PM PDT 24
Peak memory 236920 kb
Host smart-e8582178-56bd-4cea-a56d-d84e6a898134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660252055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1660252055
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1581394764
Short name T361
Test name
Test status
Simulation time 2148855658 ps
CPU time 15.76 seconds
Started Apr 28 01:17:59 PM PDT 24
Finished Apr 28 01:18:52 PM PDT 24
Peak memory 218256 kb
Host smart-7a569d59-9d1f-4f4a-8245-50ef0fa27c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581394764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1581394764
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2298229017
Short name T339
Test name
Test status
Simulation time 919227423 ps
CPU time 6.59 seconds
Started Apr 28 01:12:25 PM PDT 24
Finished Apr 28 01:12:32 PM PDT 24
Peak memory 218420 kb
Host smart-dd9de056-71d9-4d3c-b689-137ab303d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298229017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2298229017
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1309213946
Short name T310
Test name
Test status
Simulation time 23693883799 ps
CPU time 71.08 seconds
Started Apr 28 01:13:07 PM PDT 24
Finished Apr 28 01:14:19 PM PDT 24
Peak memory 249092 kb
Host smart-8802d29b-b252-4cab-99bd-591592ff6e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309213946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1309213946
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3032883370
Short name T319
Test name
Test status
Simulation time 3100790842 ps
CPU time 53.66 seconds
Started Apr 28 01:13:43 PM PDT 24
Finished Apr 28 01:14:44 PM PDT 24
Peak memory 252772 kb
Host smart-a38ebb4f-570f-440a-85b9-44fea666eef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032883370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3032883370
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1425436206
Short name T362
Test name
Test status
Simulation time 1970813160 ps
CPU time 8.49 seconds
Started Apr 28 01:12:30 PM PDT 24
Finished Apr 28 01:12:40 PM PDT 24
Peak memory 232316 kb
Host smart-c4b1cd69-dceb-414b-9cf1-257a606d071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425436206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1425436206
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1608253904
Short name T325
Test name
Test status
Simulation time 1083738132 ps
CPU time 6.17 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:16 PM PDT 24
Peak memory 224480 kb
Host smart-4b126223-55c8-44d6-959e-b039dcdaee3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608253904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1608253904
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.462709112
Short name T314
Test name
Test status
Simulation time 1285298076 ps
CPU time 19.49 seconds
Started Apr 28 01:12:46 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 249788 kb
Host smart-a2cafedc-fd6c-46be-80bf-484fc6c38c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462709112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.462709112
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4150119371
Short name T218
Test name
Test status
Simulation time 89436428230 ps
CPU time 200.64 seconds
Started Apr 28 01:16:00 PM PDT 24
Finished Apr 28 01:20:02 PM PDT 24
Peak memory 249432 kb
Host smart-a7299eeb-f7d4-4f06-8baa-0061d8e4847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150119371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4150119371
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2146468446
Short name T195
Test name
Test status
Simulation time 1204926961 ps
CPU time 16.88 seconds
Started Apr 28 01:12:46 PM PDT 24
Finished Apr 28 01:13:04 PM PDT 24
Peak memory 222672 kb
Host smart-ccffaf4c-63db-4205-9e3e-98c036bbebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146468446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2146468446
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.458129070
Short name T28
Test name
Test status
Simulation time 12979310213 ps
CPU time 27.41 seconds
Started Apr 28 01:15:00 PM PDT 24
Finished Apr 28 01:16:02 PM PDT 24
Peak memory 224392 kb
Host smart-443dd933-14dc-4856-9999-bc9e47362f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458129070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.458129070
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1671073610
Short name T338
Test name
Test status
Simulation time 163877957 ps
CPU time 3.08 seconds
Started Apr 28 01:13:10 PM PDT 24
Finished Apr 28 01:13:14 PM PDT 24
Peak memory 222460 kb
Host smart-f2b0d8c5-3bb4-470d-a178-fac7514b769b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671073610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1671073610
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.524882544
Short name T299
Test name
Test status
Simulation time 6465839373 ps
CPU time 15.62 seconds
Started Apr 28 01:13:34 PM PDT 24
Finished Apr 28 01:13:52 PM PDT 24
Peak memory 232572 kb
Host smart-3432f497-e7e9-429a-8812-d11b4bc65fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524882544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.524882544
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2082894097
Short name T102
Test name
Test status
Simulation time 12498263728 ps
CPU time 39.51 seconds
Started Apr 28 01:13:56 PM PDT 24
Finished Apr 28 01:14:39 PM PDT 24
Peak memory 216408 kb
Host smart-de52ff46-26ae-4e7a-85bb-8f3e48a4ce56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082894097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2082894097
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3510792807
Short name T75
Test name
Test status
Simulation time 221216358 ps
CPU time 3.16 seconds
Started Apr 28 01:14:18 PM PDT 24
Finished Apr 28 01:14:42 PM PDT 24
Peak memory 222740 kb
Host smart-0a81269b-f68c-4937-9d88-213556383137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510792807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3510792807
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1685274738
Short name T210
Test name
Test status
Simulation time 25617789813 ps
CPU time 54.26 seconds
Started Apr 28 01:15:11 PM PDT 24
Finished Apr 28 01:16:40 PM PDT 24
Peak memory 218780 kb
Host smart-725b42aa-4605-4f2e-a5cf-488bdc4d5f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685274738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1685274738
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1030648004
Short name T179
Test name
Test status
Simulation time 994945925 ps
CPU time 7.06 seconds
Started Apr 28 01:16:22 PM PDT 24
Finished Apr 28 01:17:14 PM PDT 24
Peak memory 218468 kb
Host smart-ccabc0c9-5249-42b6-bf3b-4b69bf5e498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030648004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1030648004
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3558832907
Short name T216
Test name
Test status
Simulation time 4592601886 ps
CPU time 39.34 seconds
Started Apr 28 01:17:21 PM PDT 24
Finished Apr 28 01:18:43 PM PDT 24
Peak memory 219416 kb
Host smart-63e0881d-d429-4022-974f-f021d632e50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558832907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3558832907
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_intercept.269838118
Short name T251
Test name
Test status
Simulation time 252376646 ps
CPU time 6.61 seconds
Started Apr 28 01:12:59 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 232644 kb
Host smart-f4e92df8-9c9a-4677-9248-6e7145bdc1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269838118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.269838118
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3104329376
Short name T388
Test name
Test status
Simulation time 2370275563 ps
CPU time 21.09 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:21 PM PDT 24
Peak memory 216320 kb
Host smart-462f9b3e-f278-4678-b7fb-dd4f3dcc8787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104329376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3104329376
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.4159743076
Short name T19
Test name
Test status
Simulation time 6584737492 ps
CPU time 5.86 seconds
Started Apr 28 01:13:01 PM PDT 24
Finished Apr 28 01:13:09 PM PDT 24
Peak memory 218836 kb
Host smart-234f78b1-d86b-4188-bbf6-72f9282ee94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159743076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.4159743076
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1086249977
Short name T80
Test name
Test status
Simulation time 4205593797 ps
CPU time 11.98 seconds
Started Apr 28 01:13:33 PM PDT 24
Finished Apr 28 01:13:47 PM PDT 24
Peak memory 240880 kb
Host smart-9e90e3af-97f5-4c8e-b074-5a9d07d387a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086249977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1086249977
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1325815554
Short name T86
Test name
Test status
Simulation time 631565154 ps
CPU time 3.71 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:12 PM PDT 24
Peak memory 218932 kb
Host smart-7876dea3-828f-49a7-85db-c9b64eabf50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325815554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1325815554
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2165596319
Short name T375
Test name
Test status
Simulation time 107291083 ps
CPU time 6.23 seconds
Started Apr 28 01:04:19 PM PDT 24
Finished Apr 28 01:04:26 PM PDT 24
Peak memory 215004 kb
Host smart-f0af6105-3455-4678-8298-20ad7d05dd4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165596319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2165596319
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2750294763
Short name T359
Test name
Test status
Simulation time 2486122060 ps
CPU time 13.37 seconds
Started Apr 28 01:12:21 PM PDT 24
Finished Apr 28 01:12:35 PM PDT 24
Peak memory 232440 kb
Host smart-81211117-84c7-4adb-b354-4d58234ba101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750294763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2750294763
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.4242173276
Short name T184
Test name
Test status
Simulation time 3566113771 ps
CPU time 32.23 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:39 PM PDT 24
Peak memory 218948 kb
Host smart-c7268915-267f-4774-bd21-9515abbe4378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242173276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.4242173276
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_upload.576752472
Short name T207
Test name
Test status
Simulation time 359218206 ps
CPU time 5.92 seconds
Started Apr 28 01:13:05 PM PDT 24
Finished Apr 28 01:13:13 PM PDT 24
Peak memory 233048 kb
Host smart-326d55d4-1d19-4db3-9972-ab276e78ce67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576752472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.576752472
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2903760175
Short name T283
Test name
Test status
Simulation time 5380143657 ps
CPU time 27.15 seconds
Started Apr 28 01:13:07 PM PDT 24
Finished Apr 28 01:13:36 PM PDT 24
Peak memory 222104 kb
Host smart-1044f4f6-7def-4520-a0a3-8179fede783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903760175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2903760175
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2979823279
Short name T188
Test name
Test status
Simulation time 6741750459 ps
CPU time 11.08 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:19 PM PDT 24
Peak memory 218408 kb
Host smart-b71a08a0-cfa4-4cb8-8976-960c575c8a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979823279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2979823279
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2738208312
Short name T23
Test name
Test status
Simulation time 97408797 ps
CPU time 2.75 seconds
Started Apr 28 01:13:36 PM PDT 24
Finished Apr 28 01:13:43 PM PDT 24
Peak memory 222980 kb
Host smart-e2b26ea6-88c4-4783-826d-52f31e0bbe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738208312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2738208312
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.223984325
Short name T245
Test name
Test status
Simulation time 2528165183 ps
CPU time 11.63 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:59 PM PDT 24
Peak memory 218856 kb
Host smart-d8636cfc-e6e2-4df6-81ea-4b5537d3fc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223984325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.223984325
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_upload.1311103145
Short name T55
Test name
Test status
Simulation time 289612351 ps
CPU time 3.44 seconds
Started Apr 28 01:13:41 PM PDT 24
Finished Apr 28 01:13:53 PM PDT 24
Peak memory 222044 kb
Host smart-0ac649ec-755c-42ee-b15f-47c251b6c803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311103145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1311103145
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2379668224
Short name T277
Test name
Test status
Simulation time 262932118 ps
CPU time 3.24 seconds
Started Apr 28 01:13:45 PM PDT 24
Finished Apr 28 01:13:56 PM PDT 24
Peak memory 216808 kb
Host smart-33d2be80-b7e3-4375-8148-a91394a760ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379668224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2379668224
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1061978773
Short name T356
Test name
Test status
Simulation time 48444356 ps
CPU time 2.56 seconds
Started Apr 28 01:12:30 PM PDT 24
Finished Apr 28 01:12:34 PM PDT 24
Peak memory 222264 kb
Host smart-344a7ec1-22e7-495a-a759-b3e7b96b86d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061978773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1061978773
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2155822748
Short name T250
Test name
Test status
Simulation time 18353266813 ps
CPU time 6.87 seconds
Started Apr 28 01:13:51 PM PDT 24
Finished Apr 28 01:14:03 PM PDT 24
Peak memory 224964 kb
Host smart-a4126a03-9de0-40ce-9b0d-1800fe173055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155822748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2155822748
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3390074350
Short name T228
Test name
Test status
Simulation time 185187343 ps
CPU time 3.58 seconds
Started Apr 28 01:14:14 PM PDT 24
Finished Apr 28 01:14:34 PM PDT 24
Peak memory 235596 kb
Host smart-e99b40a0-95d0-4cb9-950e-73d7c3faac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390074350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3390074350
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3451916208
Short name T247
Test name
Test status
Simulation time 1273097387 ps
CPU time 2.92 seconds
Started Apr 28 01:14:23 PM PDT 24
Finished Apr 28 01:14:52 PM PDT 24
Peak memory 218672 kb
Host smart-de8480a7-9d7c-40c7-8f1d-ed3758adaaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451916208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3451916208
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2938630542
Short name T24
Test name
Test status
Simulation time 221746810 ps
CPU time 5.37 seconds
Started Apr 28 01:12:41 PM PDT 24
Finished Apr 28 01:12:47 PM PDT 24
Peak memory 232632 kb
Host smart-1e66d70f-6447-4b61-90eb-59bd4d4c2b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938630542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2938630542
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3526806605
Short name T268
Test name
Test status
Simulation time 461236947 ps
CPU time 5.82 seconds
Started Apr 28 01:12:37 PM PDT 24
Finished Apr 28 01:12:44 PM PDT 24
Peak memory 222504 kb
Host smart-5d3cd85b-ef1e-41fd-8a6b-bd76ee8cb1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526806605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3526806605
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2288392408
Short name T270
Test name
Test status
Simulation time 117595448 ps
CPU time 4.01 seconds
Started Apr 28 01:12:39 PM PDT 24
Finished Apr 28 01:12:44 PM PDT 24
Peak memory 232208 kb
Host smart-9efc9264-72f8-4ca8-af2d-b1b1103eaf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288392408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2288392408
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1433481251
Short name T366
Test name
Test status
Simulation time 3333692558 ps
CPU time 18.77 seconds
Started Apr 28 01:14:48 PM PDT 24
Finished Apr 28 01:15:43 PM PDT 24
Peak memory 239756 kb
Host smart-5c35623c-33f6-4bf4-aa30-f17097209bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433481251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1433481251
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_upload.4284460449
Short name T254
Test name
Test status
Simulation time 157037033 ps
CPU time 2.65 seconds
Started Apr 28 01:15:02 PM PDT 24
Finished Apr 28 01:15:40 PM PDT 24
Peak memory 222460 kb
Host smart-39c1c94e-d137-4106-9e6c-317cc21339ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284460449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4284460449
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.664847390
Short name T212
Test name
Test status
Simulation time 26307848173 ps
CPU time 18.29 seconds
Started Apr 28 01:16:36 PM PDT 24
Finished Apr 28 01:17:40 PM PDT 24
Peak memory 224312 kb
Host smart-f2362584-ba93-4692-918f-ad8fba2acebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664847390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.664847390
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3619566790
Short name T81
Test name
Test status
Simulation time 1631601775 ps
CPU time 17.01 seconds
Started Apr 28 01:16:51 PM PDT 24
Finished Apr 28 01:17:56 PM PDT 24
Peak memory 233544 kb
Host smart-bbe84049-fa40-4296-a0fc-99a6edbcb5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619566790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3619566790
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1706620794
Short name T203
Test name
Test status
Simulation time 11352038266 ps
CPU time 9.23 seconds
Started Apr 28 01:16:51 PM PDT 24
Finished Apr 28 01:17:48 PM PDT 24
Peak memory 222232 kb
Host smart-9bd2664f-b913-45d0-a43c-902c9f27f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706620794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1706620794
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2529540439
Short name T293
Test name
Test status
Simulation time 4795129738 ps
CPU time 5.87 seconds
Started Apr 28 01:17:16 PM PDT 24
Finished Apr 28 01:18:04 PM PDT 24
Peak memory 222956 kb
Host smart-eefc78f4-f7d7-41d2-9a01-402c9081d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529540439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2529540439
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1122618845
Short name T76
Test name
Test status
Simulation time 31561521750 ps
CPU time 18.16 seconds
Started Apr 28 01:12:45 PM PDT 24
Finished Apr 28 01:13:05 PM PDT 24
Peak memory 216976 kb
Host smart-3cc6d7f2-32ff-46d6-98a6-2458dafad1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122618845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1122618845
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1350773716
Short name T79
Test name
Test status
Simulation time 3238988260 ps
CPU time 12.77 seconds
Started Apr 28 01:12:50 PM PDT 24
Finished Apr 28 01:13:04 PM PDT 24
Peak memory 239168 kb
Host smart-306ff896-ca3a-43b7-b6b0-73abb508a716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350773716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1350773716
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1729371264
Short name T221
Test name
Test status
Simulation time 2127337576 ps
CPU time 7.98 seconds
Started Apr 28 01:12:52 PM PDT 24
Finished Apr 28 01:13:01 PM PDT 24
Peak memory 223024 kb
Host smart-da8d92ca-c8c6-4912-b162-061f84045f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729371264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1729371264
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3383064549
Short name T122
Test name
Test status
Simulation time 139406735 ps
CPU time 3.43 seconds
Started Apr 28 01:04:01 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 215320 kb
Host smart-ced1794c-9494-4b44-a33d-7756c5aeb4f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383064549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
383064549
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.574329792
Short name T38
Test name
Test status
Simulation time 499589432 ps
CPU time 7.18 seconds
Started Apr 28 01:04:01 PM PDT 24
Finished Apr 28 01:04:09 PM PDT 24
Peak memory 215100 kb
Host smart-85b52d3e-72a6-4c97-b164-8c4f5e91cbe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574329792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.574329792
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.579027586
Short name T78
Test name
Test status
Simulation time 14414317079 ps
CPU time 38.95 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 224540 kb
Host smart-a02ffbeb-16ec-46b0-b4d5-8689be47ec5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579027586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
579027586
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_upload.1575722091
Short name T348
Test name
Test status
Simulation time 3892112359 ps
CPU time 13.58 seconds
Started Apr 28 01:12:27 PM PDT 24
Finished Apr 28 01:12:41 PM PDT 24
Peak memory 223664 kb
Host smart-98d44b50-7128-4405-83c2-8cc3b0402239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575722091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1575722091
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1087415544
Short name T357
Test name
Test status
Simulation time 3908915421 ps
CPU time 6.43 seconds
Started Apr 28 01:13:08 PM PDT 24
Finished Apr 28 01:13:16 PM PDT 24
Peak memory 222804 kb
Host smart-c83453d4-8932-42f9-963a-4a0c236f4deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087415544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1087415544
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.670740984
Short name T344
Test name
Test status
Simulation time 46435655074 ps
CPU time 30.04 seconds
Started Apr 28 01:13:02 PM PDT 24
Finished Apr 28 01:13:34 PM PDT 24
Peak memory 224500 kb
Host smart-679397f0-00e3-4166-8600-ce99fc31031d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670740984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.670740984
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3353010120
Short name T355
Test name
Test status
Simulation time 419033429 ps
CPU time 5.8 seconds
Started Apr 28 01:13:09 PM PDT 24
Finished Apr 28 01:13:16 PM PDT 24
Peak memory 236040 kb
Host smart-200795b9-c694-48cc-8f40-c8de6b5e2743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353010120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3353010120
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4221656248
Short name T298
Test name
Test status
Simulation time 3845092607 ps
CPU time 10.66 seconds
Started Apr 28 01:13:10 PM PDT 24
Finished Apr 28 01:13:22 PM PDT 24
Peak memory 223564 kb
Host smart-f44f9b9e-8ec2-4d68-ab5b-3457af68f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221656248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4221656248
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1615765023
Short name T312
Test name
Test status
Simulation time 8194906128 ps
CPU time 108.53 seconds
Started Apr 28 01:13:15 PM PDT 24
Finished Apr 28 01:15:05 PM PDT 24
Peak memory 239208 kb
Host smart-42b826b6-b5f8-4124-9b4d-ef8b8561bad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615765023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1615765023
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1417205096
Short name T341
Test name
Test status
Simulation time 259336569 ps
CPU time 4.86 seconds
Started Apr 28 01:13:16 PM PDT 24
Finished Apr 28 01:13:22 PM PDT 24
Peak memory 222596 kb
Host smart-24fef649-8837-4207-925e-21bc9b6d5d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417205096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1417205096
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3824278885
Short name T189
Test name
Test status
Simulation time 26931670135 ps
CPU time 25.52 seconds
Started Apr 28 01:13:18 PM PDT 24
Finished Apr 28 01:13:44 PM PDT 24
Peak memory 232304 kb
Host smart-bc877dbf-2093-476c-b3af-4c2a1e356dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824278885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3824278885
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1336851136
Short name T240
Test name
Test status
Simulation time 1679146730 ps
CPU time 6.42 seconds
Started Apr 28 01:13:21 PM PDT 24
Finished Apr 28 01:13:28 PM PDT 24
Peak memory 223748 kb
Host smart-d96072c3-3b33-4b51-97e1-f99f7a3857bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336851136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1336851136
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1889443206
Short name T358
Test name
Test status
Simulation time 521603419 ps
CPU time 7.48 seconds
Started Apr 28 01:13:26 PM PDT 24
Finished Apr 28 01:13:35 PM PDT 24
Peak memory 223932 kb
Host smart-88776448-8393-4d68-9221-8f72e492f842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889443206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1889443206
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1079127623
Short name T223
Test name
Test status
Simulation time 19229232471 ps
CPU time 18.19 seconds
Started Apr 28 01:13:37 PM PDT 24
Finished Apr 28 01:14:00 PM PDT 24
Peak memory 234764 kb
Host smart-b774f851-08e4-42b1-bc04-77fa473ddcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079127623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1079127623
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2771200727
Short name T258
Test name
Test status
Simulation time 3364455779 ps
CPU time 10.71 seconds
Started Apr 28 01:13:37 PM PDT 24
Finished Apr 28 01:13:53 PM PDT 24
Peak memory 223336 kb
Host smart-ca5a756c-c53e-4fc1-b9e1-02d94c14a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771200727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2771200727
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3040993029
Short name T318
Test name
Test status
Simulation time 1000711608 ps
CPU time 9.96 seconds
Started Apr 28 01:13:43 PM PDT 24
Finished Apr 28 01:14:00 PM PDT 24
Peak memory 240920 kb
Host smart-85fe42c5-0550-4ece-9b9d-944f3142cddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040993029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3040993029
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.393079117
Short name T205
Test name
Test status
Simulation time 8187225789 ps
CPU time 12.34 seconds
Started Apr 28 01:13:42 PM PDT 24
Finished Apr 28 01:14:02 PM PDT 24
Peak memory 223128 kb
Host smart-908f4f19-19f8-499e-8c75-3e42673d1b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393079117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.393079117
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3356336733
Short name T316
Test name
Test status
Simulation time 2020702030 ps
CPU time 10.5 seconds
Started Apr 28 01:13:46 PM PDT 24
Finished Apr 28 01:14:04 PM PDT 24
Peak memory 238700 kb
Host smart-3f208093-6d97-4d19-8ac6-c4d61f9ca9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356336733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3356336733
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2363394570
Short name T244
Test name
Test status
Simulation time 905845287 ps
CPU time 2.39 seconds
Started Apr 28 01:13:39 PM PDT 24
Finished Apr 28 01:13:49 PM PDT 24
Peak memory 218692 kb
Host smart-1e990531-0ec2-4b18-91ed-2aa9f692359f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363394570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2363394570
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3766204623
Short name T121
Test name
Test status
Simulation time 406567822 ps
CPU time 3.69 seconds
Started Apr 28 01:13:47 PM PDT 24
Finished Apr 28 01:13:57 PM PDT 24
Peak memory 222812 kb
Host smart-76d4a513-e710-4523-bd3f-86dbabcde5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766204623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3766204623
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4282230670
Short name T71
Test name
Test status
Simulation time 68482902830 ps
CPU time 28.87 seconds
Started Apr 28 01:13:45 PM PDT 24
Finished Apr 28 01:14:21 PM PDT 24
Peak memory 236772 kb
Host smart-f6351a8a-db5a-4a77-a427-535beee2d656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282230670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4282230670
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.644691225
Short name T260
Test name
Test status
Simulation time 12392727224 ps
CPU time 14.28 seconds
Started Apr 28 01:13:53 PM PDT 24
Finished Apr 28 01:14:12 PM PDT 24
Peak memory 220900 kb
Host smart-0f815536-fd45-4da9-ad5d-c575727feb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644691225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.644691225
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_upload.1078143945
Short name T197
Test name
Test status
Simulation time 172439126 ps
CPU time 3.05 seconds
Started Apr 28 01:13:57 PM PDT 24
Finished Apr 28 01:14:03 PM PDT 24
Peak memory 222844 kb
Host smart-43092058-8e47-4790-842b-9037d644c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078143945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1078143945
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1162856830
Short name T230
Test name
Test status
Simulation time 1454148284 ps
CPU time 7.06 seconds
Started Apr 28 01:13:59 PM PDT 24
Finished Apr 28 01:14:10 PM PDT 24
Peak memory 219660 kb
Host smart-9a68d56a-6147-4a24-8708-239e0cae3a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162856830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1162856830
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3824241295
Short name T90
Test name
Test status
Simulation time 3428009789 ps
CPU time 8.51 seconds
Started Apr 28 01:14:13 PM PDT 24
Finished Apr 28 01:14:35 PM PDT 24
Peak memory 223396 kb
Host smart-4fe489df-6f70-4de4-9281-1461270ae65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824241295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3824241295
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4065914984
Short name T300
Test name
Test status
Simulation time 459787116 ps
CPU time 3.23 seconds
Started Apr 28 01:14:15 PM PDT 24
Finished Apr 28 01:14:35 PM PDT 24
Peak memory 221372 kb
Host smart-3ec5671f-9244-4ac7-8779-e64f84ec8a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065914984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4065914984
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4153558929
Short name T327
Test name
Test status
Simulation time 403155852 ps
CPU time 8.52 seconds
Started Apr 28 01:14:23 PM PDT 24
Finished Apr 28 01:14:58 PM PDT 24
Peak memory 234884 kb
Host smart-717c2632-54ac-40ff-b744-ae2c4fee33e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153558929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4153558929
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1644242213
Short name T271
Test name
Test status
Simulation time 2379430381 ps
CPU time 8.58 seconds
Started Apr 28 01:14:39 PM PDT 24
Finished Apr 28 01:15:22 PM PDT 24
Peak memory 218812 kb
Host smart-5cc9ffcd-6fa5-4555-963d-361dc386493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644242213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1644242213
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3815928028
Short name T337
Test name
Test status
Simulation time 1834144634 ps
CPU time 4.65 seconds
Started Apr 28 01:14:48 PM PDT 24
Finished Apr 28 01:15:28 PM PDT 24
Peak memory 216716 kb
Host smart-d20c9c23-17a5-4a0f-9f95-e73de0d613d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815928028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3815928028
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.449157327
Short name T192
Test name
Test status
Simulation time 3478615146 ps
CPU time 10.42 seconds
Started Apr 28 01:14:48 PM PDT 24
Finished Apr 28 01:15:35 PM PDT 24
Peak memory 231004 kb
Host smart-06264743-ebb2-46d4-a89c-66e8176079e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449157327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.449157327
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1083961608
Short name T232
Test name
Test status
Simulation time 102868496 ps
CPU time 2.45 seconds
Started Apr 28 01:14:58 PM PDT 24
Finished Apr 28 01:15:36 PM PDT 24
Peak memory 216908 kb
Host smart-04f92949-9fc4-4f79-989e-f1cf0289eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083961608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1083961608
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.846982545
Short name T287
Test name
Test status
Simulation time 26775089544 ps
CPU time 28.38 seconds
Started Apr 28 01:15:10 PM PDT 24
Finished Apr 28 01:16:14 PM PDT 24
Peak memory 232680 kb
Host smart-6a9b419b-0041-4992-82c3-65995263c40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846982545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.846982545
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_upload.763109394
Short name T72
Test name
Test status
Simulation time 8818890305 ps
CPU time 10.3 seconds
Started Apr 28 01:15:42 PM PDT 24
Finished Apr 28 01:16:27 PM PDT 24
Peak memory 222744 kb
Host smart-b1eb0022-8bf8-46a4-a7d3-de87955800f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763109394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.763109394
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1136876503
Short name T330
Test name
Test status
Simulation time 198188603 ps
CPU time 3.76 seconds
Started Apr 28 01:16:09 PM PDT 24
Finished Apr 28 01:16:55 PM PDT 24
Peak memory 224428 kb
Host smart-24f4e39a-586c-40ed-902b-425bf47808a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136876503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1136876503
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3229529417
Short name T252
Test name
Test status
Simulation time 3259779459 ps
CPU time 4.56 seconds
Started Apr 28 01:16:08 PM PDT 24
Finished Apr 28 01:16:55 PM PDT 24
Peak memory 222480 kb
Host smart-218953a4-5f09-4ce0-a170-db0660e701f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229529417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3229529417
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4189078550
Short name T9
Test name
Test status
Simulation time 5179110994 ps
CPU time 18.59 seconds
Started Apr 28 01:12:41 PM PDT 24
Finished Apr 28 01:13:00 PM PDT 24
Peak memory 235568 kb
Host smart-81c22263-0333-44ff-8b85-03aa5dd55ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189078550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4189078550
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1365022742
Short name T219
Test name
Test status
Simulation time 2322083549 ps
CPU time 10.24 seconds
Started Apr 28 01:16:20 PM PDT 24
Finished Apr 28 01:17:15 PM PDT 24
Peak memory 222724 kb
Host smart-103dbe0e-353d-48fd-ae1e-b4a14996052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365022742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1365022742
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3415651430
Short name T185
Test name
Test status
Simulation time 984916187 ps
CPU time 4.53 seconds
Started Apr 28 01:16:21 PM PDT 24
Finished Apr 28 01:17:10 PM PDT 24
Peak memory 217988 kb
Host smart-1676fc99-bd23-4ef7-b4f5-85edac2a437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415651430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3415651430
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3919093262
Short name T182
Test name
Test status
Simulation time 463188284 ps
CPU time 5.22 seconds
Started Apr 28 01:16:33 PM PDT 24
Finished Apr 28 01:17:24 PM PDT 24
Peak memory 225276 kb
Host smart-2dff2055-1b79-43a3-88e5-6c19081c394f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919093262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3919093262
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_upload.1083014400
Short name T186
Test name
Test status
Simulation time 2444840756 ps
CPU time 10.4 seconds
Started Apr 28 01:16:59 PM PDT 24
Finished Apr 28 01:17:56 PM PDT 24
Peak memory 226624 kb
Host smart-abced14f-147b-4606-a6e5-b8d2e8ced2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083014400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1083014400
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2428786916
Short name T266
Test name
Test status
Simulation time 191959569 ps
CPU time 3.22 seconds
Started Apr 28 01:17:10 PM PDT 24
Finished Apr 28 01:17:57 PM PDT 24
Peak memory 223012 kb
Host smart-e45378a1-b95b-426d-b6ce-3010d5fc6bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428786916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2428786916
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3224704708
Short name T239
Test name
Test status
Simulation time 139540225 ps
CPU time 2.71 seconds
Started Apr 28 01:17:21 PM PDT 24
Finished Apr 28 01:18:07 PM PDT 24
Peak memory 218592 kb
Host smart-c2e2e223-53fb-457b-9b00-acb6dbe8c61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224704708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3224704708
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.611973352
Short name T249
Test name
Test status
Simulation time 12258239564 ps
CPU time 29.1 seconds
Started Apr 28 01:17:48 PM PDT 24
Finished Apr 28 01:18:59 PM PDT 24
Peak memory 222280 kb
Host smart-44c2ae7e-57f6-4de6-ba64-5a1b054f1133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611973352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.611973352
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3885525113
Short name T187
Test name
Test status
Simulation time 2862564758 ps
CPU time 5.8 seconds
Started Apr 28 01:17:48 PM PDT 24
Finished Apr 28 01:18:35 PM PDT 24
Peak memory 223532 kb
Host smart-1750f2bf-c2ab-4aac-aa27-026e5c4cc20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885525113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3885525113
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3617001537
Short name T280
Test name
Test status
Simulation time 886926788 ps
CPU time 6.24 seconds
Started Apr 28 01:17:59 PM PDT 24
Finished Apr 28 01:18:42 PM PDT 24
Peak memory 223752 kb
Host smart-9ba24f48-fe89-4c78-87d4-cb6c9d088293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617001537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3617001537
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2809179173
Short name T305
Test name
Test status
Simulation time 2924732422 ps
CPU time 49.12 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:13:47 PM PDT 24
Peak memory 249148 kb
Host smart-4168ee7f-6d2a-45c2-a42a-bab99c67f2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809179173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2809179173
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3062440620
Short name T253
Test name
Test status
Simulation time 1402633706 ps
CPU time 7.54 seconds
Started Apr 28 01:12:58 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 222836 kb
Host smart-2e13b713-dd76-42d7-bb5e-9fbf05a9aec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062440620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3062440620
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1905801830
Short name T20
Test name
Test status
Simulation time 21399921 ps
CPU time 0.78 seconds
Started Apr 28 01:13:01 PM PDT 24
Finished Apr 28 01:13:04 PM PDT 24
Peak memory 206708 kb
Host smart-e15a5f6b-9d45-45fa-9d24-9b6b01f626e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905801830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1905801830
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2284915184
Short name T95
Test name
Test status
Simulation time 130002749 ps
CPU time 1.13 seconds
Started Apr 28 01:03:58 PM PDT 24
Finished Apr 28 01:04:00 PM PDT 24
Peak memory 206868 kb
Host smart-8fa95739-987d-46d9-b824-85c577662aec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284915184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2284915184
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2590810203
Short name T133
Test name
Test status
Simulation time 106181195 ps
CPU time 2.66 seconds
Started Apr 28 01:04:03 PM PDT 24
Finished Apr 28 01:04:06 PM PDT 24
Peak memory 216868 kb
Host smart-9b94f480-176b-438d-9081-75d7d372264a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590810203 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2590810203
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2302946454
Short name T742
Test name
Test status
Simulation time 9053588003 ps
CPU time 23.52 seconds
Started Apr 28 01:03:59 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 215132 kb
Host smart-d84d40a1-50be-449c-bdcd-c8b9758271fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302946454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2302946454
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2344005148
Short name T735
Test name
Test status
Simulation time 538097461 ps
CPU time 33.44 seconds
Started Apr 28 01:03:57 PM PDT 24
Finished Apr 28 01:04:31 PM PDT 24
Peak memory 206840 kb
Host smart-15bce631-7668-4fc9-8db9-d2effa66755a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344005148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2344005148
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1554868044
Short name T96
Test name
Test status
Simulation time 22493700 ps
CPU time 0.97 seconds
Started Apr 28 01:03:59 PM PDT 24
Finished Apr 28 01:04:01 PM PDT 24
Peak memory 206720 kb
Host smart-02af4667-4f7b-455e-bef1-3dded9a92be3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554868044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1554868044
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1288783153
Short name T145
Test name
Test status
Simulation time 32143496 ps
CPU time 1.31 seconds
Started Apr 28 01:03:58 PM PDT 24
Finished Apr 28 01:04:00 PM PDT 24
Peak memory 215132 kb
Host smart-80e696a0-e30b-4198-b4f7-d71c6d8b5e45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288783153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
288783153
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1342579012
Short name T731
Test name
Test status
Simulation time 12931444 ps
CPU time 0.75 seconds
Started Apr 28 01:03:59 PM PDT 24
Finished Apr 28 01:04:01 PM PDT 24
Peak memory 203668 kb
Host smart-eae7f339-8f18-4c54-b65a-c038dbbe3f6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342579012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
342579012
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.860314394
Short name T795
Test name
Test status
Simulation time 23002676 ps
CPU time 1.58 seconds
Started Apr 28 01:03:59 PM PDT 24
Finished Apr 28 01:04:01 PM PDT 24
Peak memory 215084 kb
Host smart-46d6f2f4-62d4-430b-8eb3-0f9a891d29f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860314394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.860314394
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.101780487
Short name T763
Test name
Test status
Simulation time 55202281 ps
CPU time 0.64 seconds
Started Apr 28 01:03:59 PM PDT 24
Finished Apr 28 01:04:00 PM PDT 24
Peak memory 203656 kb
Host smart-d9b789f8-a538-4354-8fc3-bfa93dbd8c47
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101780487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.101780487
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1208933158
Short name T153
Test name
Test status
Simulation time 1159571178 ps
CPU time 1.91 seconds
Started Apr 28 01:03:59 PM PDT 24
Finished Apr 28 01:04:02 PM PDT 24
Peak memory 215104 kb
Host smart-1462cfa4-8908-487c-ac20-6e7fd163b6d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208933158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1208933158
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3012653210
Short name T806
Test name
Test status
Simulation time 789874979 ps
CPU time 7.67 seconds
Started Apr 28 01:03:57 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 214988 kb
Host smart-3cd7dba3-3b2d-46d8-b463-adb54b7d12bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012653210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3012653210
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1419406854
Short name T144
Test name
Test status
Simulation time 2428076578 ps
CPU time 15.63 seconds
Started Apr 28 01:04:00 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 215108 kb
Host smart-a0766d80-4032-47ad-bd25-89c935c3736e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419406854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1419406854
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2056021580
Short name T794
Test name
Test status
Simulation time 731578568 ps
CPU time 22.88 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:26 PM PDT 24
Peak memory 215060 kb
Host smart-409b2060-b2eb-4fba-ae1f-ce4619c15cde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056021580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2056021580
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.438151135
Short name T132
Test name
Test status
Simulation time 413608266 ps
CPU time 1.8 seconds
Started Apr 28 01:04:07 PM PDT 24
Finished Apr 28 01:04:09 PM PDT 24
Peak memory 215104 kb
Host smart-53139418-ef48-4161-bad6-998f8de1752d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438151135 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.438151135
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2341099115
Short name T755
Test name
Test status
Simulation time 56360475 ps
CPU time 1.13 seconds
Started Apr 28 01:03:59 PM PDT 24
Finished Apr 28 01:04:01 PM PDT 24
Peak memory 206836 kb
Host smart-c1bdc008-e05d-4376-83e3-6accdf6b4b71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341099115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
341099115
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3023295294
Short name T757
Test name
Test status
Simulation time 17644965 ps
CPU time 0.71 seconds
Started Apr 28 01:03:57 PM PDT 24
Finished Apr 28 01:03:58 PM PDT 24
Peak memory 203732 kb
Host smart-027a8d0b-921b-40f5-bbb8-d8a894f13853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023295294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
023295294
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.400258216
Short name T823
Test name
Test status
Simulation time 44104607 ps
CPU time 1.76 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 215208 kb
Host smart-e41b5422-825d-4b60-aebf-9296d18732d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400258216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.400258216
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1942605435
Short name T771
Test name
Test status
Simulation time 22219621 ps
CPU time 0.64 seconds
Started Apr 28 01:03:58 PM PDT 24
Finished Apr 28 01:04:00 PM PDT 24
Peak memory 203712 kb
Host smart-3ee3efb8-7747-43ef-b3d8-3ccedcef918e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942605435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1942605435
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1666797539
Short name T154
Test name
Test status
Simulation time 105914451 ps
CPU time 2.97 seconds
Started Apr 28 01:04:00 PM PDT 24
Finished Apr 28 01:04:04 PM PDT 24
Peak memory 215068 kb
Host smart-792ac109-ee32-4538-9e1a-d20fb6bc2707
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666797539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1666797539
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.907651118
Short name T799
Test name
Test status
Simulation time 62278582 ps
CPU time 1.49 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 215192 kb
Host smart-2830ea96-834d-4c58-b31b-11c7c5f2d712
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907651118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.907651118
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.812134769
Short name T800
Test name
Test status
Simulation time 1800751250 ps
CPU time 3.6 seconds
Started Apr 28 01:04:19 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 217500 kb
Host smart-f69898eb-d767-4063-b56c-5a28bd4bea9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812134769 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.812134769
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.968110135
Short name T147
Test name
Test status
Simulation time 119501675 ps
CPU time 2.8 seconds
Started Apr 28 01:04:19 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 214992 kb
Host smart-5d3921d3-b2d2-4999-9d7a-88981f3a0bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968110135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.968110135
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.848071395
Short name T730
Test name
Test status
Simulation time 13300457 ps
CPU time 0.68 seconds
Started Apr 28 01:04:20 PM PDT 24
Finished Apr 28 01:04:21 PM PDT 24
Peak memory 203540 kb
Host smart-c2f583d4-ac85-4915-b7f8-5fed459c8208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848071395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.848071395
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4182603466
Short name T37
Test name
Test status
Simulation time 32170307 ps
CPU time 1.88 seconds
Started Apr 28 01:04:21 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 215128 kb
Host smart-863ba573-6ede-4c2e-bfd8-3d5e4b2f70f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182603466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4182603466
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3653895532
Short name T128
Test name
Test status
Simulation time 249253305 ps
CPU time 4.57 seconds
Started Apr 28 01:04:18 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 216300 kb
Host smart-e70ae46f-c796-495d-8381-37bcb1bee259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653895532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3653895532
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1879889156
Short name T372
Test name
Test status
Simulation time 106363305 ps
CPU time 6.21 seconds
Started Apr 28 01:04:17 PM PDT 24
Finished Apr 28 01:04:24 PM PDT 24
Peak memory 216440 kb
Host smart-6003678c-639f-4d55-8b69-eaad64c4afcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879889156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1879889156
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3511803342
Short name T805
Test name
Test status
Simulation time 135627721 ps
CPU time 1.82 seconds
Started Apr 28 01:04:18 PM PDT 24
Finished Apr 28 01:04:20 PM PDT 24
Peak memory 216208 kb
Host smart-92432ecd-cd9c-4abf-aecc-0e11be96296b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511803342 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3511803342
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.239704779
Short name T139
Test name
Test status
Simulation time 447015037 ps
CPU time 2.72 seconds
Started Apr 28 01:04:19 PM PDT 24
Finished Apr 28 01:04:22 PM PDT 24
Peak memory 215072 kb
Host smart-2257ff89-aa36-402b-a4f4-d4a639d54707
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239704779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.239704779
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3872478280
Short name T820
Test name
Test status
Simulation time 28198120 ps
CPU time 0.69 seconds
Started Apr 28 01:04:27 PM PDT 24
Finished Apr 28 01:04:29 PM PDT 24
Peak memory 203532 kb
Host smart-6a0933d1-ad60-44ce-9b4a-d75656bca8db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872478280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3872478280
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1242267934
Short name T810
Test name
Test status
Simulation time 71392048 ps
CPU time 2.65 seconds
Started Apr 28 01:04:18 PM PDT 24
Finished Apr 28 01:04:21 PM PDT 24
Peak memory 215012 kb
Host smart-da960763-5dea-497b-ba07-d3e756f93d5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242267934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1242267934
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.798559693
Short name T125
Test name
Test status
Simulation time 33858483 ps
CPU time 2.4 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 215236 kb
Host smart-a4c43883-9097-4429-94a9-907faf6b7d91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798559693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.798559693
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.489612727
Short name T165
Test name
Test status
Simulation time 373606613 ps
CPU time 7.4 seconds
Started Apr 28 01:04:17 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 215076 kb
Host smart-585ef033-2a63-4a15-8764-9c3c9c9359fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489612727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.489612727
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.559484790
Short name T743
Test name
Test status
Simulation time 56268970 ps
CPU time 1.65 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:24 PM PDT 24
Peak memory 216336 kb
Host smart-b6121d8d-693c-4d51-9a5d-d8fe64ed65ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559484790 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.559484790
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3823340675
Short name T152
Test name
Test status
Simulation time 165260949 ps
CPU time 2.07 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:26 PM PDT 24
Peak memory 206868 kb
Host smart-68bf5685-63d2-41bd-a5bc-dfb14da34cf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823340675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3823340675
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3885774541
Short name T751
Test name
Test status
Simulation time 13077917 ps
CPU time 0.72 seconds
Started Apr 28 01:04:17 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 203464 kb
Host smart-d987294b-9a14-4ab6-9bd6-317ffb90d84b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885774541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3885774541
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3023811680
Short name T737
Test name
Test status
Simulation time 216695287 ps
CPU time 2.89 seconds
Started Apr 28 01:04:19 PM PDT 24
Finished Apr 28 01:04:22 PM PDT 24
Peak memory 215100 kb
Host smart-a9f7b555-b1a1-46c7-b01d-1ad35abe559d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023811680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3023811680
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1756800037
Short name T739
Test name
Test status
Simulation time 130489786 ps
CPU time 3.47 seconds
Started Apr 28 01:04:33 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 217120 kb
Host smart-7aed4ddc-7af7-4fb2-b0b9-a3429c518a39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756800037 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1756800037
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1603012526
Short name T790
Test name
Test status
Simulation time 63423366 ps
CPU time 1.86 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 215028 kb
Host smart-7ccf04b8-abd2-4afe-b3d9-13790ec46445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603012526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1603012526
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2186568570
Short name T729
Test name
Test status
Simulation time 142583140 ps
CPU time 0.7 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 203768 kb
Host smart-92838269-669c-489f-bddf-f12b22ba64a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186568570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2186568570
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.586344501
Short name T157
Test name
Test status
Simulation time 156865299 ps
CPU time 2.81 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:32 PM PDT 24
Peak memory 215148 kb
Host smart-abc5241f-963f-47e7-afc1-74a5898bfe4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586344501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.586344501
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2802391211
Short name T809
Test name
Test status
Simulation time 564540093 ps
CPU time 3.41 seconds
Started Apr 28 01:04:21 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 215160 kb
Host smart-2dbd2531-e218-41d3-90c2-b15d8f3b37bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802391211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2802391211
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.35298313
Short name T376
Test name
Test status
Simulation time 1195315583 ps
CPU time 17.63 seconds
Started Apr 28 01:04:26 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 214916 kb
Host smart-871c6fda-03e4-4aa9-adf2-6a55fd6bebfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_
tl_intg_err.35298313
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4002761215
Short name T819
Test name
Test status
Simulation time 26078841 ps
CPU time 1.66 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 215196 kb
Host smart-06f1b51c-b357-4f3c-8701-2e8f85330bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002761215 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4002761215
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1074386888
Short name T807
Test name
Test status
Simulation time 35673370 ps
CPU time 2.23 seconds
Started Apr 28 01:04:26 PM PDT 24
Finished Apr 28 01:04:29 PM PDT 24
Peak memory 206688 kb
Host smart-f1182bf4-11bf-4bef-9f9f-e65fbc6b8394
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074386888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1074386888
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1156206467
Short name T749
Test name
Test status
Simulation time 42369875 ps
CPU time 0.74 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:24 PM PDT 24
Peak memory 203500 kb
Host smart-5e87e588-a83b-47c5-92b3-34de45cb952c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156206467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1156206467
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.444328903
Short name T733
Test name
Test status
Simulation time 118642710 ps
CPU time 3.83 seconds
Started Apr 28 01:04:33 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 215076 kb
Host smart-9d84c95e-7937-4602-a1ea-087a1a5d18d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444328903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.444328903
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.443815761
Short name T113
Test name
Test status
Simulation time 106295373 ps
CPU time 1.71 seconds
Started Apr 28 01:04:33 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 215292 kb
Host smart-4e6b6fa8-7738-4e65-9c3c-5318edfc9cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443815761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.443815761
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3559814231
Short name T765
Test name
Test status
Simulation time 1060227684 ps
CPU time 23.9 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:48 PM PDT 24
Peak memory 215416 kb
Host smart-637ed7a6-27dc-453d-a7db-371f49c23e7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559814231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3559814231
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.469195885
Short name T785
Test name
Test status
Simulation time 682193253 ps
CPU time 3.58 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:28 PM PDT 24
Peak memory 216612 kb
Host smart-38d99c29-3dc9-439e-b108-429976eeeb82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469195885 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.469195885
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1434644582
Short name T793
Test name
Test status
Simulation time 77974762 ps
CPU time 2.51 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:26 PM PDT 24
Peak memory 215072 kb
Host smart-82fcb192-6f78-4e1c-be41-ccea7a53b3ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434644582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1434644582
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3763328689
Short name T738
Test name
Test status
Simulation time 41454146 ps
CPU time 0.72 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 203464 kb
Host smart-fa78a926-57f5-46fd-8652-f640422c45ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763328689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3763328689
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1072585482
Short name T158
Test name
Test status
Simulation time 29063764 ps
CPU time 1.7 seconds
Started Apr 28 01:04:33 PM PDT 24
Finished Apr 28 01:04:35 PM PDT 24
Peak memory 206840 kb
Host smart-51a4da7c-81c9-4a82-aab9-1f99467716dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072585482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1072585482
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.830576744
Short name T130
Test name
Test status
Simulation time 189555052 ps
CPU time 3.09 seconds
Started Apr 28 01:04:24 PM PDT 24
Finished Apr 28 01:04:28 PM PDT 24
Peak memory 215240 kb
Host smart-3aa803ce-7519-4ae4-ad2c-a4b34526d346
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830576744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.830576744
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.644940986
Short name T379
Test name
Test status
Simulation time 827544366 ps
CPU time 21.93 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:44 PM PDT 24
Peak memory 215012 kb
Host smart-51e6175d-83ab-407b-9a8d-784715253857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644940986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.644940986
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.543830437
Short name T129
Test name
Test status
Simulation time 512897863 ps
CPU time 3.69 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 217952 kb
Host smart-83fafbf2-b41a-4550-beea-1a8da4814d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543830437 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.543830437
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2249241080
Short name T748
Test name
Test status
Simulation time 64195365 ps
CPU time 1.21 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:24 PM PDT 24
Peak memory 215148 kb
Host smart-a9c2507d-e767-4ceb-8a44-9d680e36e299
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249241080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2249241080
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3408631012
Short name T803
Test name
Test status
Simulation time 12150117 ps
CPU time 0.75 seconds
Started Apr 28 01:04:22 PM PDT 24
Finished Apr 28 01:04:23 PM PDT 24
Peak memory 203508 kb
Host smart-6f091642-9abb-42c7-9409-3ceaec70e177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408631012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3408631012
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.462218182
Short name T764
Test name
Test status
Simulation time 278054856 ps
CPU time 3.12 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 215096 kb
Host smart-39abb90e-368d-433e-87c5-61bcfefb3c3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462218182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.462218182
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1989284689
Short name T776
Test name
Test status
Simulation time 3025988826 ps
CPU time 3.56 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 215260 kb
Host smart-c8bbcb7b-4836-4f97-80b1-14bda697d1bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989284689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1989284689
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.138921061
Short name T136
Test name
Test status
Simulation time 3452987747 ps
CPU time 13.06 seconds
Started Apr 28 01:04:24 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 215220 kb
Host smart-3d9bf5db-b505-4b1f-869c-3a789243df55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138921061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.138921061
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.391791753
Short name T792
Test name
Test status
Simulation time 191434466 ps
CPU time 1.74 seconds
Started Apr 28 01:04:27 PM PDT 24
Finished Apr 28 01:04:29 PM PDT 24
Peak memory 215168 kb
Host smart-37cce7fc-b4c6-4c07-8021-6294126cecbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391791753 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.391791753
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4129931771
Short name T814
Test name
Test status
Simulation time 390368495 ps
CPU time 2.69 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:32 PM PDT 24
Peak memory 215132 kb
Host smart-684651a8-9b71-4095-b1e5-d5c413a8ce5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129931771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4129931771
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1847656895
Short name T720
Test name
Test status
Simulation time 11424339 ps
CPU time 0.69 seconds
Started Apr 28 01:04:29 PM PDT 24
Finished Apr 28 01:04:30 PM PDT 24
Peak memory 203816 kb
Host smart-021fcdde-7b2a-4ae5-9768-52129a8aa791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847656895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1847656895
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1968144669
Short name T156
Test name
Test status
Simulation time 86006971 ps
CPU time 2.75 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:32 PM PDT 24
Peak memory 215016 kb
Host smart-47b84257-c9b8-4cd8-971e-3805cb963d37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968144669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1968144669
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.14004178
Short name T123
Test name
Test status
Simulation time 624119243 ps
CPU time 3.95 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 215248 kb
Host smart-e795f070-92ce-447b-b948-fa331ba7a26c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14004178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.14004178
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2540470280
Short name T777
Test name
Test status
Simulation time 41770690 ps
CPU time 1.6 seconds
Started Apr 28 01:04:27 PM PDT 24
Finished Apr 28 01:04:30 PM PDT 24
Peak memory 214976 kb
Host smart-883c50f9-e5c3-413c-b89c-0b0826f63834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540470280 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2540470280
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3738911601
Short name T744
Test name
Test status
Simulation time 161928671 ps
CPU time 0.71 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:30 PM PDT 24
Peak memory 203748 kb
Host smart-6a300f3c-0d93-413e-b3de-c764cb37a7e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738911601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3738911601
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.4188711767
Short name T752
Test name
Test status
Simulation time 139508847 ps
CPU time 3.67 seconds
Started Apr 28 01:04:29 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 214964 kb
Host smart-059411ee-524c-42ff-90b5-9ddb2deea859
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188711767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.4188711767
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.12753776
Short name T762
Test name
Test status
Simulation time 54888783 ps
CPU time 1.64 seconds
Started Apr 28 01:04:29 PM PDT 24
Finished Apr 28 01:04:31 PM PDT 24
Peak memory 215160 kb
Host smart-61f775bf-14b2-413a-b4c6-014f5db417bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12753776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.12753776
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.133209916
Short name T377
Test name
Test status
Simulation time 760144917 ps
CPU time 12.38 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:42 PM PDT 24
Peak memory 215488 kb
Host smart-36525a54-bb75-4eba-a233-3b955b56111f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133209916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.133209916
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.585338932
Short name T135
Test name
Test status
Simulation time 151243189 ps
CPU time 2.77 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 217576 kb
Host smart-be448fd1-0f97-4950-a740-4595e6ba55aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585338932 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.585338932
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.570107418
Short name T142
Test name
Test status
Simulation time 128540276 ps
CPU time 2.61 seconds
Started Apr 28 01:04:32 PM PDT 24
Finished Apr 28 01:04:35 PM PDT 24
Peak memory 206956 kb
Host smart-54710ad0-42cc-476b-9103-f6c9439f3481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570107418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.570107418
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.755891580
Short name T167
Test name
Test status
Simulation time 15148106 ps
CPU time 0.72 seconds
Started Apr 28 01:04:29 PM PDT 24
Finished Apr 28 01:04:31 PM PDT 24
Peak memory 203424 kb
Host smart-26243e95-4cb5-4ef4-9878-a610ef1cad15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755891580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.755891580
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1111975185
Short name T164
Test name
Test status
Simulation time 1243866746 ps
CPU time 3.08 seconds
Started Apr 28 01:04:31 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 215056 kb
Host smart-8816d81a-38ab-44a1-abe2-dd71d70c75f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111975185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1111975185
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4035942621
Short name T801
Test name
Test status
Simulation time 201721011 ps
CPU time 3.79 seconds
Started Apr 28 01:04:28 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 215284 kb
Host smart-61b99514-9313-4e8f-8e86-1dd19db86582
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035942621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4035942621
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.721506241
Short name T791
Test name
Test status
Simulation time 427599472 ps
CPU time 6.51 seconds
Started Apr 28 01:04:29 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 215244 kb
Host smart-08108a5e-8291-462b-8dde-840f18da2ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721506241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.721506241
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4061937213
Short name T797
Test name
Test status
Simulation time 1064238593 ps
CPU time 21.8 seconds
Started Apr 28 01:04:05 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 206904 kb
Host smart-c98dd56a-055b-415f-b3cb-c82aa26cbdab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061937213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4061937213
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1382888879
Short name T811
Test name
Test status
Simulation time 911266157 ps
CPU time 13.3 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:17 PM PDT 24
Peak memory 206796 kb
Host smart-7c7b1f09-11a9-4a0e-b3e5-7a3116423b46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382888879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1382888879
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2116309502
Short name T94
Test name
Test status
Simulation time 31437805 ps
CPU time 1.14 seconds
Started Apr 28 01:04:01 PM PDT 24
Finished Apr 28 01:04:03 PM PDT 24
Peak memory 206716 kb
Host smart-2ab7e2cc-cd63-4fdb-9d96-482a10f414f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116309502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2116309502
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1390522070
Short name T741
Test name
Test status
Simulation time 121912913 ps
CPU time 1.93 seconds
Started Apr 28 01:04:03 PM PDT 24
Finished Apr 28 01:04:06 PM PDT 24
Peak memory 216268 kb
Host smart-2cb3b213-0dd6-47a2-a1c3-006e1eebee5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390522070 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1390522070
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1901088063
Short name T149
Test name
Test status
Simulation time 47725761 ps
CPU time 1.75 seconds
Started Apr 28 01:04:03 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 214948 kb
Host smart-b2aa0e81-a2ce-4507-af0f-86d5c676dda9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901088063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
901088063
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.492472362
Short name T815
Test name
Test status
Simulation time 69638588 ps
CPU time 0.72 seconds
Started Apr 28 01:04:01 PM PDT 24
Finished Apr 28 01:04:03 PM PDT 24
Peak memory 203452 kb
Host smart-b6b59c23-b13d-43ad-8296-5fbc65ae3fab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492472362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.492472362
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2324814835
Short name T141
Test name
Test status
Simulation time 187341155 ps
CPU time 1.97 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 215224 kb
Host smart-81e5a492-a0b9-4c94-85bc-b984353f2c6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324814835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2324814835
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3993548012
Short name T759
Test name
Test status
Simulation time 14503578 ps
CPU time 0.68 seconds
Started Apr 28 01:04:03 PM PDT 24
Finished Apr 28 01:04:05 PM PDT 24
Peak memory 203416 kb
Host smart-16b41018-2763-47c7-8367-e6998a3a1b2d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993548012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3993548012
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4204870474
Short name T740
Test name
Test status
Simulation time 61462550 ps
CPU time 1.82 seconds
Started Apr 28 01:04:06 PM PDT 24
Finished Apr 28 01:04:09 PM PDT 24
Peak memory 215048 kb
Host smart-bcd99405-e159-486f-9319-0e45be2cb2b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204870474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4204870474
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3111122276
Short name T131
Test name
Test status
Simulation time 421282073 ps
CPU time 3.24 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:06 PM PDT 24
Peak memory 215324 kb
Host smart-e7d50f5f-398a-4b96-bb4d-6232d4e5018a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111122276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
111122276
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2352454091
Short name T808
Test name
Test status
Simulation time 387034307 ps
CPU time 11.79 seconds
Started Apr 28 01:04:04 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 215120 kb
Host smart-22ae75e3-c329-4e00-915d-5fb1b16a7865
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352454091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2352454091
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2922866845
Short name T822
Test name
Test status
Simulation time 22629221 ps
CPU time 0.68 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:39 PM PDT 24
Peak memory 203432 kb
Host smart-3454f7ef-7db6-4fd4-ba30-4949e07bc96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922866845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2922866845
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1162846123
Short name T725
Test name
Test status
Simulation time 42760432 ps
CPU time 0.67 seconds
Started Apr 28 01:04:34 PM PDT 24
Finished Apr 28 01:04:35 PM PDT 24
Peak memory 203520 kb
Host smart-17699e3b-4d55-4efc-a38b-93090d8f26db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162846123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1162846123
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4261253463
Short name T753
Test name
Test status
Simulation time 13462586 ps
CPU time 0.72 seconds
Started Apr 28 01:04:34 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 203820 kb
Host smart-2bb9771f-d2c4-4261-8d9e-2923e33aaadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261253463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4261253463
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2268307315
Short name T772
Test name
Test status
Simulation time 46290697 ps
CPU time 0.71 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 203744 kb
Host smart-4312ed68-534b-4c4b-9d6a-2cdf06866171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268307315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2268307315
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2231134732
Short name T746
Test name
Test status
Simulation time 12422463 ps
CPU time 0.68 seconds
Started Apr 28 01:04:36 PM PDT 24
Finished Apr 28 01:04:37 PM PDT 24
Peak memory 203472 kb
Host smart-bb147088-7de1-4f19-b5b6-b891f01417a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231134732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2231134732
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1851407688
Short name T778
Test name
Test status
Simulation time 89756359 ps
CPU time 0.68 seconds
Started Apr 28 01:04:32 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 203460 kb
Host smart-f76bfb16-5142-4a65-9341-ba2ad959b1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851407688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1851407688
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3383853853
Short name T734
Test name
Test status
Simulation time 15363137 ps
CPU time 0.74 seconds
Started Apr 28 01:04:32 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 203760 kb
Host smart-0a3cceae-a3d0-4b18-94ee-882b00cddd91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383853853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3383853853
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.413597899
Short name T722
Test name
Test status
Simulation time 14922293 ps
CPU time 0.79 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:39 PM PDT 24
Peak memory 203416 kb
Host smart-11a98635-ae47-4b3f-9add-4865286fdc22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413597899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.413597899
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3129249460
Short name T728
Test name
Test status
Simulation time 38598802 ps
CPU time 0.75 seconds
Started Apr 28 01:04:34 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 203520 kb
Host smart-dca6e6a5-9cb6-47b3-b354-57e8e9b61ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129249460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3129249460
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3575602581
Short name T768
Test name
Test status
Simulation time 27195705 ps
CPU time 0.74 seconds
Started Apr 28 01:04:34 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 203504 kb
Host smart-fcafdd2f-58d2-4367-ad24-b70e9bea32ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575602581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3575602581
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1813535494
Short name T138
Test name
Test status
Simulation time 819628367 ps
CPU time 13.62 seconds
Started Apr 28 01:04:04 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 215072 kb
Host smart-7ad58ee6-0eb1-4206-8a7f-f74401a50a65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813535494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1813535494
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2485711996
Short name T787
Test name
Test status
Simulation time 1895793325 ps
CPU time 26.83 seconds
Started Apr 28 01:04:04 PM PDT 24
Finished Apr 28 01:04:31 PM PDT 24
Peak memory 206856 kb
Host smart-c8da4e0b-4485-4943-97b7-37e54c09ab41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485711996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2485711996
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1311002046
Short name T97
Test name
Test status
Simulation time 125762185 ps
CPU time 1.4 seconds
Started Apr 28 01:04:04 PM PDT 24
Finished Apr 28 01:04:06 PM PDT 24
Peak memory 216096 kb
Host smart-673fcd8a-ab0e-47a5-8232-efd51e4ffb9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311002046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1311002046
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1961138947
Short name T824
Test name
Test status
Simulation time 97567777 ps
CPU time 2.53 seconds
Started Apr 28 01:04:09 PM PDT 24
Finished Apr 28 01:04:13 PM PDT 24
Peak memory 216860 kb
Host smart-4666853d-ffa9-48d1-9b2b-cd0d97922ad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961138947 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1961138947
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1347877193
Short name T155
Test name
Test status
Simulation time 405233342 ps
CPU time 1.92 seconds
Started Apr 28 01:04:06 PM PDT 24
Finished Apr 28 01:04:09 PM PDT 24
Peak memory 215036 kb
Host smart-5924b5c3-eec7-48bd-8e18-fc21b713f6ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347877193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
347877193
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1263389622
Short name T766
Test name
Test status
Simulation time 121093971 ps
CPU time 0.7 seconds
Started Apr 28 01:04:02 PM PDT 24
Finished Apr 28 01:04:04 PM PDT 24
Peak memory 203480 kb
Host smart-9cbccbb0-8150-44c5-9b43-eb83d10b93bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263389622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
263389622
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3386843191
Short name T812
Test name
Test status
Simulation time 37967213 ps
CPU time 1.32 seconds
Started Apr 28 01:04:04 PM PDT 24
Finished Apr 28 01:04:06 PM PDT 24
Peak memory 215160 kb
Host smart-300e1745-bec9-4235-bfa8-ebee3141aee6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386843191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3386843191
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1248965029
Short name T732
Test name
Test status
Simulation time 10246027 ps
CPU time 0.65 seconds
Started Apr 28 01:04:06 PM PDT 24
Finished Apr 28 01:04:08 PM PDT 24
Peak memory 203312 kb
Host smart-74690f44-955e-407d-b146-3e7aa843d376
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248965029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1248965029
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.789830047
Short name T163
Test name
Test status
Simulation time 163031464 ps
CPU time 3.28 seconds
Started Apr 28 01:04:11 PM PDT 24
Finished Apr 28 01:04:15 PM PDT 24
Peak memory 215104 kb
Host smart-8014deda-8eea-4106-b3a2-d34e8675ae82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789830047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.789830047
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2966815018
Short name T817
Test name
Test status
Simulation time 102025296 ps
CPU time 1.25 seconds
Started Apr 28 01:04:05 PM PDT 24
Finished Apr 28 01:04:07 PM PDT 24
Peak memory 206824 kb
Host smart-b726be87-14c5-420c-a0f0-671ca28e47de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966815018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
966815018
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.314188168
Short name T371
Test name
Test status
Simulation time 2460758406 ps
CPU time 13.95 seconds
Started Apr 28 01:04:03 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 223308 kb
Host smart-ea4ad712-f147-4929-82d9-96d7d42550a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314188168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.314188168
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3484647061
Short name T169
Test name
Test status
Simulation time 21554037 ps
CPU time 0.77 seconds
Started Apr 28 01:04:35 PM PDT 24
Finished Apr 28 01:04:37 PM PDT 24
Peak memory 203796 kb
Host smart-7b00a8c3-9767-4dce-9ce9-82940abbf09e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484647061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3484647061
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2491951682
Short name T726
Test name
Test status
Simulation time 33092802 ps
CPU time 0.73 seconds
Started Apr 28 01:04:37 PM PDT 24
Finished Apr 28 01:04:39 PM PDT 24
Peak memory 203828 kb
Host smart-7b7c14ca-2e0f-449f-9c03-76419542a893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491951682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2491951682
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2991810458
Short name T727
Test name
Test status
Simulation time 23377145 ps
CPU time 0.7 seconds
Started Apr 28 01:04:33 PM PDT 24
Finished Apr 28 01:04:35 PM PDT 24
Peak memory 203468 kb
Host smart-bddf1dcc-ae35-4d8c-a9b6-e5ce161078ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991810458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2991810458
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.673764556
Short name T724
Test name
Test status
Simulation time 23595552 ps
CPU time 0.73 seconds
Started Apr 28 01:04:33 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 203828 kb
Host smart-39e2ec45-54a4-4995-a708-7edcdc72a178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673764556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.673764556
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.478926082
Short name T781
Test name
Test status
Simulation time 16607620 ps
CPU time 0.76 seconds
Started Apr 28 01:04:34 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 203800 kb
Host smart-f3f184f8-9662-4a4b-a34a-68fa6be2a5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478926082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.478926082
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3637109938
Short name T760
Test name
Test status
Simulation time 53373445 ps
CPU time 0.8 seconds
Started Apr 28 01:04:33 PM PDT 24
Finished Apr 28 01:04:35 PM PDT 24
Peak memory 203512 kb
Host smart-25cd971f-6e0f-4b5b-9c07-b79fd3f09de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637109938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3637109938
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3034788287
Short name T168
Test name
Test status
Simulation time 64991478 ps
CPU time 0.74 seconds
Started Apr 28 01:04:32 PM PDT 24
Finished Apr 28 01:04:34 PM PDT 24
Peak memory 203424 kb
Host smart-5301f121-7da7-4a8b-aa5b-45b4e640cd05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034788287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3034788287
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4141036870
Short name T783
Test name
Test status
Simulation time 159328944 ps
CPU time 0.69 seconds
Started Apr 28 01:04:32 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 203540 kb
Host smart-52d486e3-f4e6-4e81-bb53-d4d3dc188676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141036870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4141036870
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1152168126
Short name T779
Test name
Test status
Simulation time 47902457 ps
CPU time 0.74 seconds
Started Apr 28 01:04:35 PM PDT 24
Finished Apr 28 01:04:37 PM PDT 24
Peak memory 203824 kb
Host smart-ca07ba47-a0cc-4acd-838a-b4f5487a5908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152168126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1152168126
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1594245548
Short name T747
Test name
Test status
Simulation time 52170710 ps
CPU time 0.72 seconds
Started Apr 28 01:04:32 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 203532 kb
Host smart-24fb37bf-a389-4c60-adb0-def60e8e8c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594245548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1594245548
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1599708429
Short name T802
Test name
Test status
Simulation time 387007378 ps
CPU time 8.41 seconds
Started Apr 28 01:04:09 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 206960 kb
Host smart-ea6979f6-849a-4e6b-ba91-4b7ddd60a0f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599708429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1599708429
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2036231625
Short name T813
Test name
Test status
Simulation time 1396911145 ps
CPU time 22.88 seconds
Started Apr 28 01:04:10 PM PDT 24
Finished Apr 28 01:04:33 PM PDT 24
Peak memory 206736 kb
Host smart-b036dfee-a29f-4df0-a01a-4781c781d324
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036231625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2036231625
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3129039940
Short name T98
Test name
Test status
Simulation time 23102157 ps
CPU time 0.94 seconds
Started Apr 28 01:04:10 PM PDT 24
Finished Apr 28 01:04:12 PM PDT 24
Peak memory 206740 kb
Host smart-99039bce-795a-4d02-ad84-fa688ac9b790
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129039940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3129039940
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.664519382
Short name T769
Test name
Test status
Simulation time 40992043 ps
CPU time 2.54 seconds
Started Apr 28 01:04:07 PM PDT 24
Finished Apr 28 01:04:10 PM PDT 24
Peak memory 216176 kb
Host smart-96251159-bf6a-4693-9081-f085afd678e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664519382 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.664519382
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3669418889
Short name T821
Test name
Test status
Simulation time 269357444 ps
CPU time 1.29 seconds
Started Apr 28 01:04:07 PM PDT 24
Finished Apr 28 01:04:08 PM PDT 24
Peak memory 206780 kb
Host smart-f3de10ef-8624-455a-8a43-db52b8807de2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669418889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
669418889
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1532151848
Short name T816
Test name
Test status
Simulation time 46480624 ps
CPU time 0.71 seconds
Started Apr 28 01:04:10 PM PDT 24
Finished Apr 28 01:04:11 PM PDT 24
Peak memory 203360 kb
Host smart-6a660e03-d234-478e-bc20-f022b920dc1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532151848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
532151848
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.790321834
Short name T148
Test name
Test status
Simulation time 216575893 ps
CPU time 1.34 seconds
Started Apr 28 01:04:07 PM PDT 24
Finished Apr 28 01:04:09 PM PDT 24
Peak memory 215156 kb
Host smart-4f6d8b7a-6e6f-47ce-b710-305beb9ea48d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790321834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.790321834
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2418783979
Short name T745
Test name
Test status
Simulation time 11618023 ps
CPU time 0.65 seconds
Started Apr 28 01:04:09 PM PDT 24
Finished Apr 28 01:04:10 PM PDT 24
Peak memory 203332 kb
Host smart-30f126ba-95ed-43de-b4af-121073e773e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418783979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2418783979
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.652016626
Short name T789
Test name
Test status
Simulation time 244931090 ps
CPU time 3.9 seconds
Started Apr 28 01:04:08 PM PDT 24
Finished Apr 28 01:04:12 PM PDT 24
Peak memory 215044 kb
Host smart-dff49d3d-721e-4e14-928c-a3ade8c378c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652016626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.652016626
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.448916896
Short name T127
Test name
Test status
Simulation time 30818609 ps
CPU time 1.7 seconds
Started Apr 28 01:04:06 PM PDT 24
Finished Apr 28 01:04:09 PM PDT 24
Peak memory 216224 kb
Host smart-0ddf1939-8915-4e2d-abc4-94129f2d13be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448916896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.448916896
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2491508741
Short name T804
Test name
Test status
Simulation time 56497164 ps
CPU time 0.75 seconds
Started Apr 28 01:04:34 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 203516 kb
Host smart-139cae41-188c-4bb3-a6d8-2c44d3116c28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491508741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2491508741
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2969818348
Short name T758
Test name
Test status
Simulation time 37259071 ps
CPU time 0.7 seconds
Started Apr 28 01:04:35 PM PDT 24
Finished Apr 28 01:04:36 PM PDT 24
Peak memory 203796 kb
Host smart-825b4996-711a-4ebd-847c-cf16dc1ddaa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969818348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2969818348
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3956499135
Short name T736
Test name
Test status
Simulation time 20673085 ps
CPU time 0.77 seconds
Started Apr 28 01:04:38 PM PDT 24
Finished Apr 28 01:04:39 PM PDT 24
Peak memory 203472 kb
Host smart-75f7c86a-56b8-4295-895f-e5db00f68a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956499135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3956499135
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3612893778
Short name T767
Test name
Test status
Simulation time 37780571 ps
CPU time 0.74 seconds
Started Apr 28 01:04:40 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 203512 kb
Host smart-2286f3df-43b0-461b-9c80-9f741852ec3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612893778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3612893778
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2455942418
Short name T756
Test name
Test status
Simulation time 11882890 ps
CPU time 0.67 seconds
Started Apr 28 01:04:36 PM PDT 24
Finished Apr 28 01:04:38 PM PDT 24
Peak memory 203440 kb
Host smart-c3eb6c97-9339-4ddd-8db4-95b196b3adad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455942418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2455942418
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.325092973
Short name T170
Test name
Test status
Simulation time 65677748 ps
CPU time 0.77 seconds
Started Apr 28 01:04:39 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 203808 kb
Host smart-9f7c8707-2aa4-4b34-9634-2c2bf41b88ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325092973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.325092973
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2105242818
Short name T786
Test name
Test status
Simulation time 17796917 ps
CPU time 0.76 seconds
Started Apr 28 01:04:41 PM PDT 24
Finished Apr 28 01:04:43 PM PDT 24
Peak memory 203504 kb
Host smart-54841630-7c1a-4e2c-be1e-189a186df8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105242818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2105242818
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4198907990
Short name T774
Test name
Test status
Simulation time 12257543 ps
CPU time 0.67 seconds
Started Apr 28 01:04:38 PM PDT 24
Finished Apr 28 01:04:39 PM PDT 24
Peak memory 203460 kb
Host smart-a83b9781-5628-4398-a0b5-393068e16d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198907990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4198907990
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1101379075
Short name T718
Test name
Test status
Simulation time 22601867 ps
CPU time 0.68 seconds
Started Apr 28 01:04:39 PM PDT 24
Finished Apr 28 01:04:41 PM PDT 24
Peak memory 203444 kb
Host smart-1fe2c040-cf30-470b-928b-60dbacf00086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101379075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1101379075
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4007308206
Short name T788
Test name
Test status
Simulation time 17565221 ps
CPU time 0.68 seconds
Started Apr 28 01:04:38 PM PDT 24
Finished Apr 28 01:04:39 PM PDT 24
Peak memory 203492 kb
Host smart-b60a851c-ff3e-49df-9a30-232e906c15ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007308206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4007308206
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1143595458
Short name T761
Test name
Test status
Simulation time 54076524 ps
CPU time 1.8 seconds
Started Apr 28 01:04:08 PM PDT 24
Finished Apr 28 01:04:10 PM PDT 24
Peak memory 215292 kb
Host smart-3e49d8fe-31b4-4704-9a76-5c7dbaf035d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143595458 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1143595458
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2420706485
Short name T750
Test name
Test status
Simulation time 27480833 ps
CPU time 1.21 seconds
Started Apr 28 01:04:11 PM PDT 24
Finished Apr 28 01:04:13 PM PDT 24
Peak memory 215156 kb
Host smart-3d5c9dc1-311f-4a40-bb23-d18f3f0334bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420706485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
420706485
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2514050326
Short name T784
Test name
Test status
Simulation time 20525457 ps
CPU time 0.73 seconds
Started Apr 28 01:04:10 PM PDT 24
Finished Apr 28 01:04:11 PM PDT 24
Peak memory 203504 kb
Host smart-8d0aa9d9-8aa2-4b8d-8b4b-f2b58d5237d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514050326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
514050326
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2245436149
Short name T775
Test name
Test status
Simulation time 95854197 ps
CPU time 1.71 seconds
Started Apr 28 01:04:08 PM PDT 24
Finished Apr 28 01:04:10 PM PDT 24
Peak memory 215076 kb
Host smart-a2cfe8cd-4b03-4b23-b5bd-bc9fc755f91b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245436149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2245436149
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.713148024
Short name T112
Test name
Test status
Simulation time 962273877 ps
CPU time 2.21 seconds
Started Apr 28 01:04:07 PM PDT 24
Finished Apr 28 01:04:10 PM PDT 24
Peak memory 215160 kb
Host smart-7f1cfdf9-4864-4a2d-b8b9-217756439650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713148024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.713148024
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3252781418
Short name T378
Test name
Test status
Simulation time 555035463 ps
CPU time 7.86 seconds
Started Apr 28 01:04:07 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 215068 kb
Host smart-1c291a71-4e99-4164-ac8f-d24d52aa1c39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252781418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3252781418
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1796462751
Short name T773
Test name
Test status
Simulation time 211649354 ps
CPU time 1.84 seconds
Started Apr 28 01:04:13 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 215304 kb
Host smart-f51ef63a-0276-4e04-8359-026a78ebf954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796462751 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1796462751
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.174983237
Short name T151
Test name
Test status
Simulation time 104904611 ps
CPU time 2.46 seconds
Started Apr 28 01:04:15 PM PDT 24
Finished Apr 28 01:04:19 PM PDT 24
Peak memory 215096 kb
Host smart-e03a5624-3621-45b3-89ad-3515bbdb32d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174983237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.174983237
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3631054999
Short name T723
Test name
Test status
Simulation time 37343676 ps
CPU time 0.68 seconds
Started Apr 28 01:04:16 PM PDT 24
Finished Apr 28 01:04:17 PM PDT 24
Peak memory 203476 kb
Host smart-4823c8a6-09e4-45d2-8e46-04e39391c718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631054999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
631054999
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4162997803
Short name T754
Test name
Test status
Simulation time 28900403 ps
CPU time 1.99 seconds
Started Apr 28 01:04:14 PM PDT 24
Finished Apr 28 01:04:17 PM PDT 24
Peak memory 215024 kb
Host smart-4702cc49-9139-4409-8c20-59f6e66a625f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162997803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4162997803
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1549054219
Short name T124
Test name
Test status
Simulation time 42018187 ps
CPU time 2.51 seconds
Started Apr 28 01:04:15 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 218880 kb
Host smart-51b8f862-31aa-4e0d-8a26-10508ef99824
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549054219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
549054219
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3858086173
Short name T796
Test name
Test status
Simulation time 200132966 ps
CPU time 11.37 seconds
Started Apr 28 01:04:12 PM PDT 24
Finished Apr 28 01:04:25 PM PDT 24
Peak memory 215052 kb
Host smart-2f33780a-7a5b-483f-819f-c9bbab5858fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858086173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3858086173
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1016251341
Short name T162
Test name
Test status
Simulation time 538488491 ps
CPU time 3.21 seconds
Started Apr 28 01:04:14 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 217120 kb
Host smart-051546d2-9661-48b6-b2ef-b0eba91b3812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016251341 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1016251341
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1986640917
Short name T143
Test name
Test status
Simulation time 78181376 ps
CPU time 2 seconds
Started Apr 28 01:04:13 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 206896 kb
Host smart-8434d17f-ad40-4d43-9430-0bcdbd8d3bcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986640917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
986640917
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1411406830
Short name T721
Test name
Test status
Simulation time 11413410 ps
CPU time 0.75 seconds
Started Apr 28 01:04:13 PM PDT 24
Finished Apr 28 01:04:15 PM PDT 24
Peak memory 203504 kb
Host smart-fc137021-2d30-4390-8cc7-ad07d190e098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411406830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
411406830
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1766229829
Short name T770
Test name
Test status
Simulation time 61184113 ps
CPU time 1.76 seconds
Started Apr 28 01:04:13 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 215020 kb
Host smart-ab409073-05cd-422a-9ec8-da9b8325aee0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766229829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1766229829
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1912016724
Short name T114
Test name
Test status
Simulation time 96266133 ps
CPU time 1.5 seconds
Started Apr 28 01:04:13 PM PDT 24
Finished Apr 28 01:04:16 PM PDT 24
Peak memory 215252 kb
Host smart-1d360356-92af-4e1b-8ba6-1b555bd704cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912016724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
912016724
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.222166609
Short name T374
Test name
Test status
Simulation time 1032102035 ps
CPU time 22.21 seconds
Started Apr 28 01:04:14 PM PDT 24
Finished Apr 28 01:04:37 PM PDT 24
Peak memory 214984 kb
Host smart-52573953-f66c-4013-926e-8eef66f25294
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222166609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.222166609
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.324164316
Short name T782
Test name
Test status
Simulation time 129735420 ps
CPU time 3.68 seconds
Started Apr 28 01:04:23 PM PDT 24
Finished Apr 28 01:04:28 PM PDT 24
Peak memory 217228 kb
Host smart-df1a8cb4-5edf-4f27-87cf-09b0653f527f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324164316 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.324164316
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4169058845
Short name T150
Test name
Test status
Simulation time 115116509 ps
CPU time 1.13 seconds
Started Apr 28 01:04:19 PM PDT 24
Finished Apr 28 01:04:21 PM PDT 24
Peak memory 206800 kb
Host smart-48e0882c-e402-448a-930e-ef4a6232f90d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169058845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
169058845
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3638008499
Short name T818
Test name
Test status
Simulation time 26699112 ps
CPU time 0.8 seconds
Started Apr 28 01:04:17 PM PDT 24
Finished Apr 28 01:04:19 PM PDT 24
Peak memory 203524 kb
Host smart-f34dc567-8d6e-43e6-822f-7902b81ffd85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638008499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
638008499
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1511743438
Short name T178
Test name
Test status
Simulation time 186367746 ps
CPU time 3.92 seconds
Started Apr 28 01:04:17 PM PDT 24
Finished Apr 28 01:04:21 PM PDT 24
Peak memory 215084 kb
Host smart-f3f2b0ce-a200-45c8-aa9d-780078b46b00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511743438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1511743438
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1296434035
Short name T798
Test name
Test status
Simulation time 261447602 ps
CPU time 3.97 seconds
Started Apr 28 01:04:13 PM PDT 24
Finished Apr 28 01:04:18 PM PDT 24
Peak memory 216256 kb
Host smart-7ff0051a-3767-454a-aa9b-28b8fe0fdd19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296434035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
296434035
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3910267011
Short name T134
Test name
Test status
Simulation time 307863256 ps
CPU time 17.62 seconds
Started Apr 28 01:04:18 PM PDT 24
Finished Apr 28 01:04:37 PM PDT 24
Peak memory 215092 kb
Host smart-07f4575e-c86d-4274-9ea7-eb86d517fa00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910267011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3910267011
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2200562757
Short name T36
Test name
Test status
Simulation time 28317247 ps
CPU time 1.68 seconds
Started Apr 28 01:04:25 PM PDT 24
Finished Apr 28 01:04:27 PM PDT 24
Peak memory 216180 kb
Host smart-64b493fd-ae9b-4135-8f67-ed94b22951bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200562757 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2200562757
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4006531743
Short name T146
Test name
Test status
Simulation time 76304142 ps
CPU time 2.22 seconds
Started Apr 28 01:04:18 PM PDT 24
Finished Apr 28 01:04:21 PM PDT 24
Peak memory 215080 kb
Host smart-a24479e2-47f1-4e91-a8a5-4c8bddd3a95b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006531743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
006531743
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3361199701
Short name T719
Test name
Test status
Simulation time 191246950 ps
CPU time 0.77 seconds
Started Apr 28 01:04:20 PM PDT 24
Finished Apr 28 01:04:22 PM PDT 24
Peak memory 203460 kb
Host smart-df532030-407d-47a9-9eef-66a94054fac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361199701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
361199701
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4166685414
Short name T780
Test name
Test status
Simulation time 124519487 ps
CPU time 1.89 seconds
Started Apr 28 01:04:18 PM PDT 24
Finished Apr 28 01:04:21 PM PDT 24
Peak memory 214948 kb
Host smart-e5a817f8-fb0a-4844-9be6-3f37469eaab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166685414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4166685414
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2337340296
Short name T373
Test name
Test status
Simulation time 666873761 ps
CPU time 13.95 seconds
Started Apr 28 01:04:27 PM PDT 24
Finished Apr 28 01:04:42 PM PDT 24
Peak memory 215144 kb
Host smart-9d991bb1-644a-4395-bfe7-383569d2733b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337340296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2337340296
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.868463070
Short name T495
Test name
Test status
Simulation time 19388445 ps
CPU time 0.69 seconds
Started Apr 28 01:12:27 PM PDT 24
Finished Apr 28 01:12:29 PM PDT 24
Peak memory 205312 kb
Host smart-89faa6ce-4005-4dff-af10-d186bfe30627
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868463070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.868463070
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1104617939
Short name T710
Test name
Test status
Simulation time 28116688 ps
CPU time 0.75 seconds
Started Apr 28 01:12:22 PM PDT 24
Finished Apr 28 01:12:24 PM PDT 24
Peak memory 205696 kb
Host smart-e99d3883-1313-4759-8e0b-e033f891663c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104617939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1104617939
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1475025695
Short name T67
Test name
Test status
Simulation time 11842682336 ps
CPU time 48.88 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:13:18 PM PDT 24
Peak memory 252452 kb
Host smart-cbc26601-d440-43a0-9151-34732fa1db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475025695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1475025695
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2638089773
Short name T658
Test name
Test status
Simulation time 417899851 ps
CPU time 4.08 seconds
Started Apr 28 01:12:29 PM PDT 24
Finished Apr 28 01:12:34 PM PDT 24
Peak memory 222808 kb
Host smart-780f6bd7-a290-446f-bee3-4b73f3450a20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2638089773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2638089773
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1339181854
Short name T387
Test name
Test status
Simulation time 1907894242 ps
CPU time 27.29 seconds
Started Apr 28 01:12:25 PM PDT 24
Finished Apr 28 01:12:53 PM PDT 24
Peak memory 216248 kb
Host smart-b23ff496-4826-45d3-9fcd-3e86a0bb30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339181854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1339181854
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2316963632
Short name T701
Test name
Test status
Simulation time 2135262892 ps
CPU time 10.76 seconds
Started Apr 28 01:12:22 PM PDT 24
Finished Apr 28 01:12:34 PM PDT 24
Peak memory 216264 kb
Host smart-0ec73b17-a8de-4bd1-8ab7-f0abdf702853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316963632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2316963632
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.529048139
Short name T565
Test name
Test status
Simulation time 869544838 ps
CPU time 1.35 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:12:31 PM PDT 24
Peak memory 208120 kb
Host smart-8543e408-a3c5-4140-bad0-f68ca67efda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529048139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.529048139
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.427525265
Short name T447
Test name
Test status
Simulation time 114941521 ps
CPU time 0.82 seconds
Started Apr 28 01:12:22 PM PDT 24
Finished Apr 28 01:12:24 PM PDT 24
Peak memory 205784 kb
Host smart-9da1887c-9456-48cb-b09e-39e320b3c81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427525265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.427525265
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3338324957
Short name T336
Test name
Test status
Simulation time 846112443 ps
CPU time 2.41 seconds
Started Apr 28 01:12:21 PM PDT 24
Finished Apr 28 01:12:24 PM PDT 24
Peak memory 216396 kb
Host smart-18712767-0b40-4dae-bad6-a5238e841e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338324957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3338324957
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4113613234
Short name T472
Test name
Test status
Simulation time 71333635 ps
CPU time 0.76 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:12:30 PM PDT 24
Peak memory 206944 kb
Host smart-a21d889e-1465-4f14-86f9-5b6e93c90c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113613234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4113613234
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3686951904
Short name T306
Test name
Test status
Simulation time 2955673875 ps
CPU time 33.61 seconds
Started Apr 28 01:12:26 PM PDT 24
Finished Apr 28 01:13:00 PM PDT 24
Peak memory 240928 kb
Host smart-a5bf82a2-72c8-4de7-969e-df1b7435058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686951904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3686951904
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4148638342
Short name T335
Test name
Test status
Simulation time 87091792 ps
CPU time 3.27 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:12:32 PM PDT 24
Peak memory 222420 kb
Host smart-41535d6a-5667-4872-ac82-960f7b66b11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148638342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4148638342
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2051247749
Short name T256
Test name
Test status
Simulation time 3878554037 ps
CPU time 4.64 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:12:33 PM PDT 24
Peak memory 216896 kb
Host smart-5f91ccc2-2c4e-4e39-ab54-921857035d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051247749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2051247749
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3204127041
Short name T452
Test name
Test status
Simulation time 215057554 ps
CPU time 4.34 seconds
Started Apr 28 01:12:26 PM PDT 24
Finished Apr 28 01:12:31 PM PDT 24
Peak memory 219040 kb
Host smart-0a8bd031-a4d7-4c10-b4a7-f4f697955324
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3204127041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3204127041
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.660506346
Short name T48
Test name
Test status
Simulation time 183068755 ps
CPU time 1.11 seconds
Started Apr 28 01:12:31 PM PDT 24
Finished Apr 28 01:12:33 PM PDT 24
Peak memory 235024 kb
Host smart-6bc2ac12-940e-4b28-9668-a8767eadc9fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660506346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.660506346
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2264206876
Short name T714
Test name
Test status
Simulation time 154557247 ps
CPU time 0.96 seconds
Started Apr 28 01:12:37 PM PDT 24
Finished Apr 28 01:12:39 PM PDT 24
Peak memory 206692 kb
Host smart-dc34f384-1a59-41ba-b5d9-9413866fb108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264206876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2264206876
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.653509330
Short name T393
Test name
Test status
Simulation time 1558390347 ps
CPU time 10.49 seconds
Started Apr 28 01:12:27 PM PDT 24
Finished Apr 28 01:12:38 PM PDT 24
Peak memory 216244 kb
Host smart-fa69364b-cc00-400a-9dd3-b0ab5568b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653509330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.653509330
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2471498113
Short name T425
Test name
Test status
Simulation time 23164506321 ps
CPU time 11.32 seconds
Started Apr 28 01:12:30 PM PDT 24
Finished Apr 28 01:12:42 PM PDT 24
Peak memory 216308 kb
Host smart-6c8f3601-a00d-4f58-8126-0c7ea7bc1432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471498113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2471498113
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2772976694
Short name T646
Test name
Test status
Simulation time 56425667 ps
CPU time 1.58 seconds
Started Apr 28 01:12:27 PM PDT 24
Finished Apr 28 01:12:30 PM PDT 24
Peak memory 216400 kb
Host smart-d2fe0fd4-cf03-433d-8eaf-d14f2490adb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772976694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2772976694
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1963282889
Short name T690
Test name
Test status
Simulation time 46789663 ps
CPU time 0.74 seconds
Started Apr 28 01:12:28 PM PDT 24
Finished Apr 28 01:12:30 PM PDT 24
Peak memory 205816 kb
Host smart-e5428cce-b4a4-480f-9fb4-b42f0c0f0744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963282889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1963282889
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4181814180
Short name T613
Test name
Test status
Simulation time 19671183 ps
CPU time 0.68 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 205416 kb
Host smart-71d5afca-0a16-4b94-88f8-e2f69d8020b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181814180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4181814180
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3746771570
Short name T116
Test name
Test status
Simulation time 457331675 ps
CPU time 4 seconds
Started Apr 28 01:13:07 PM PDT 24
Finished Apr 28 01:13:12 PM PDT 24
Peak memory 232404 kb
Host smart-b8d54e95-5e51-45e2-b256-b2c7362029f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746771570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3746771570
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2278909172
Short name T590
Test name
Test status
Simulation time 3928106956 ps
CPU time 11.87 seconds
Started Apr 28 01:13:07 PM PDT 24
Finished Apr 28 01:13:21 PM PDT 24
Peak memory 221532 kb
Host smart-a0363985-c0f4-4e42-b238-aabc037edde7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2278909172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2278909172
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1038881376
Short name T671
Test name
Test status
Simulation time 108563970 ps
CPU time 0.92 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 206740 kb
Host smart-073217c1-1dfa-479b-8de6-91f74cd1b309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038881376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1038881376
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1553665634
Short name T400
Test name
Test status
Simulation time 4404585272 ps
CPU time 34.87 seconds
Started Apr 28 01:13:02 PM PDT 24
Finished Apr 28 01:13:39 PM PDT 24
Peak memory 216324 kb
Host smart-29132ba3-8f27-48ff-ba30-a3e878b7ba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553665634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1553665634
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1894417333
Short name T550
Test name
Test status
Simulation time 1100160827 ps
CPU time 3.6 seconds
Started Apr 28 01:13:00 PM PDT 24
Finished Apr 28 01:13:05 PM PDT 24
Peak memory 216300 kb
Host smart-d8d7cb51-9bb2-4c2e-99d3-e7cb1e260a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894417333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1894417333
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.607288749
Short name T560
Test name
Test status
Simulation time 17419193 ps
CPU time 0.84 seconds
Started Apr 28 01:13:02 PM PDT 24
Finished Apr 28 01:13:05 PM PDT 24
Peak memory 206540 kb
Host smart-b2160b01-8c88-436c-ba83-7661d9497f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607288749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.607288749
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3688662347
Short name T106
Test name
Test status
Simulation time 39016729 ps
CPU time 0.74 seconds
Started Apr 28 01:13:01 PM PDT 24
Finished Apr 28 01:13:04 PM PDT 24
Peak memory 205816 kb
Host smart-1c5fc086-644b-4aa3-bbb2-54babd6a57c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688662347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3688662347
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.137756582
Short name T456
Test name
Test status
Simulation time 11086059 ps
CPU time 0.67 seconds
Started Apr 28 01:13:10 PM PDT 24
Finished Apr 28 01:13:11 PM PDT 24
Peak memory 205652 kb
Host smart-c6f6211d-87c9-4da3-995a-04c4b84eccd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137756582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.137756582
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2245016017
Short name T644
Test name
Test status
Simulation time 27806884 ps
CPU time 0.77 seconds
Started Apr 28 01:13:05 PM PDT 24
Finished Apr 28 01:13:07 PM PDT 24
Peak memory 206656 kb
Host smart-c99d8dc2-b2b4-413e-9851-9070764be762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245016017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2245016017
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.67126270
Short name T365
Test name
Test status
Simulation time 20913678720 ps
CPU time 38.37 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:46 PM PDT 24
Peak memory 240288 kb
Host smart-38c65a1e-bf94-4220-99b6-0ff46550c89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67126270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.67126270
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3761853684
Short name T500
Test name
Test status
Simulation time 1510213204 ps
CPU time 5.75 seconds
Started Apr 28 01:13:09 PM PDT 24
Finished Apr 28 01:13:16 PM PDT 24
Peak memory 220020 kb
Host smart-000518b0-e711-4a40-b79f-98dfdd94e570
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3761853684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3761853684
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.381999137
Short name T390
Test name
Test status
Simulation time 48595239359 ps
CPU time 36.28 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:44 PM PDT 24
Peak memory 216328 kb
Host smart-7a1e078a-96f6-42b2-aee9-5df99ba7cad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381999137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.381999137
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4171538844
Short name T554
Test name
Test status
Simulation time 482881236 ps
CPU time 3.02 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:11 PM PDT 24
Peak memory 216272 kb
Host smart-8f63ddbd-3301-42f0-b31e-89aea2217e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171538844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4171538844
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2949500634
Short name T502
Test name
Test status
Simulation time 1262849640 ps
CPU time 12.1 seconds
Started Apr 28 01:13:06 PM PDT 24
Finished Apr 28 01:13:20 PM PDT 24
Peak memory 216388 kb
Host smart-8ea1c835-83ec-4c49-b12e-75fc2a25d40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949500634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2949500634
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3559260207
Short name T506
Test name
Test status
Simulation time 45457137 ps
CPU time 0.76 seconds
Started Apr 28 01:13:05 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 205764 kb
Host smart-442c6a3e-99ac-4673-83d7-c722abd70e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559260207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3559260207
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2644441846
Short name T481
Test name
Test status
Simulation time 39658300 ps
CPU time 0.68 seconds
Started Apr 28 01:13:15 PM PDT 24
Finished Apr 28 01:13:16 PM PDT 24
Peak memory 205664 kb
Host smart-6ea34764-b577-4018-9040-62666300120a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644441846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2644441846
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3552160582
Short name T226
Test name
Test status
Simulation time 239034078 ps
CPU time 4.1 seconds
Started Apr 28 01:13:11 PM PDT 24
Finished Apr 28 01:13:16 PM PDT 24
Peak memory 219028 kb
Host smart-399a46f2-78bc-4846-ac6a-d2df3bd2a866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552160582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3552160582
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4066870818
Short name T484
Test name
Test status
Simulation time 32426887 ps
CPU time 0.77 seconds
Started Apr 28 01:13:11 PM PDT 24
Finished Apr 28 01:13:13 PM PDT 24
Peak memory 206576 kb
Host smart-03edf031-6ef6-4721-a518-a90ebd3cbaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066870818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4066870818
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2703865225
Short name T496
Test name
Test status
Simulation time 1089952931 ps
CPU time 8.21 seconds
Started Apr 28 01:13:11 PM PDT 24
Finished Apr 28 01:13:20 PM PDT 24
Peak memory 220040 kb
Host smart-4cc02d28-94bb-4d80-8e43-990808ad4c01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703865225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2703865225
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2971732866
Short name T397
Test name
Test status
Simulation time 6622243192 ps
CPU time 34.98 seconds
Started Apr 28 01:13:10 PM PDT 24
Finished Apr 28 01:13:46 PM PDT 24
Peak memory 216432 kb
Host smart-f68c7508-3cde-440f-bbb8-ddc6c8273cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971732866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2971732866
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3973416816
Short name T428
Test name
Test status
Simulation time 11209917670 ps
CPU time 21.65 seconds
Started Apr 28 01:13:13 PM PDT 24
Finished Apr 28 01:13:35 PM PDT 24
Peak memory 216288 kb
Host smart-177e12d4-c92a-4b75-886d-8a5367fe325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973416816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3973416816
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1464838912
Short name T535
Test name
Test status
Simulation time 35711148 ps
CPU time 0.86 seconds
Started Apr 28 01:13:11 PM PDT 24
Finished Apr 28 01:13:12 PM PDT 24
Peak memory 205832 kb
Host smart-b606445c-1db6-4568-aeb1-a5495de62c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464838912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1464838912
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1718413131
Short name T588
Test name
Test status
Simulation time 207047835 ps
CPU time 0.99 seconds
Started Apr 28 01:13:12 PM PDT 24
Finished Apr 28 01:13:14 PM PDT 24
Peak memory 206704 kb
Host smart-10c5c0d3-27bd-457b-964a-f215ee7b0ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718413131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1718413131
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2073701321
Short name T273
Test name
Test status
Simulation time 1214460871 ps
CPU time 7.25 seconds
Started Apr 28 01:13:11 PM PDT 24
Finished Apr 28 01:13:19 PM PDT 24
Peak memory 219272 kb
Host smart-059762a2-0f67-4132-9d10-145e2870479b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073701321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2073701321
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3164160791
Short name T417
Test name
Test status
Simulation time 18933525 ps
CPU time 0.71 seconds
Started Apr 28 01:13:22 PM PDT 24
Finished Apr 28 01:13:23 PM PDT 24
Peak memory 205400 kb
Host smart-f834bd1d-230e-4d4d-8839-2c19231c0d3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164160791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3164160791
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2668075904
Short name T543
Test name
Test status
Simulation time 16558504 ps
CPU time 0.75 seconds
Started Apr 28 01:13:15 PM PDT 24
Finished Apr 28 01:13:17 PM PDT 24
Peak memory 205560 kb
Host smart-fd510a50-48a3-48fd-a890-23c0f7ca988d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668075904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2668075904
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2315843131
Short name T54
Test name
Test status
Simulation time 2871905762 ps
CPU time 24.69 seconds
Started Apr 28 01:13:14 PM PDT 24
Finished Apr 28 01:13:39 PM PDT 24
Peak memory 222180 kb
Host smart-3379ffcf-bd1c-400f-869c-bf092c52ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315843131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2315843131
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1961415952
Short name T111
Test name
Test status
Simulation time 1447678247 ps
CPU time 5.03 seconds
Started Apr 28 01:13:18 PM PDT 24
Finished Apr 28 01:13:23 PM PDT 24
Peak memory 219860 kb
Host smart-9fd31f7b-78d9-4e17-971e-a18e34be1c97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961415952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1961415952
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1434012922
Short name T577
Test name
Test status
Simulation time 50528413457 ps
CPU time 36.36 seconds
Started Apr 28 01:13:16 PM PDT 24
Finished Apr 28 01:13:53 PM PDT 24
Peak memory 216352 kb
Host smart-c32ab816-9808-4cbb-88dd-1b7789a4bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434012922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1434012922
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2958485547
Short name T499
Test name
Test status
Simulation time 25300415 ps
CPU time 1.45 seconds
Started Apr 28 01:13:15 PM PDT 24
Finished Apr 28 01:13:18 PM PDT 24
Peak memory 216180 kb
Host smart-083c3b54-e1da-4a36-b5f0-e0611fee120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958485547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2958485547
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3537550849
Short name T438
Test name
Test status
Simulation time 160810947 ps
CPU time 0.78 seconds
Started Apr 28 01:13:15 PM PDT 24
Finished Apr 28 01:13:17 PM PDT 24
Peak memory 206796 kb
Host smart-bf2b03df-a364-4965-a312-21de591d000f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537550849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3537550849
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1288750492
Short name T594
Test name
Test status
Simulation time 22903747 ps
CPU time 0.73 seconds
Started Apr 28 01:13:28 PM PDT 24
Finished Apr 28 01:13:30 PM PDT 24
Peak memory 204868 kb
Host smart-d7c7536b-63cd-4ed7-9e00-46677a74b3be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288750492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1288750492
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1713874736
Short name T602
Test name
Test status
Simulation time 28637230 ps
CPU time 0.77 seconds
Started Apr 28 01:13:20 PM PDT 24
Finished Apr 28 01:13:21 PM PDT 24
Peak memory 206688 kb
Host smart-9eba9385-e664-46de-b789-8bd729ebb0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713874736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1713874736
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2330493724
Short name T650
Test name
Test status
Simulation time 1073988483 ps
CPU time 16.55 seconds
Started Apr 28 01:13:29 PM PDT 24
Finished Apr 28 01:13:48 PM PDT 24
Peak memory 249848 kb
Host smart-1b9e3c7b-e55e-42ce-94c5-132a9e8dc702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330493724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2330493724
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.556700728
Short name T234
Test name
Test status
Simulation time 2784889788 ps
CPU time 16.8 seconds
Started Apr 28 01:13:20 PM PDT 24
Finished Apr 28 01:13:38 PM PDT 24
Peak memory 232056 kb
Host smart-f0cf77c1-ff44-4016-ba16-997d21bd7557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556700728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.556700728
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.642205817
Short name T433
Test name
Test status
Simulation time 310334947 ps
CPU time 3.56 seconds
Started Apr 28 01:13:26 PM PDT 24
Finished Apr 28 01:13:31 PM PDT 24
Peak memory 218836 kb
Host smart-cbebaf55-5ce6-4e9a-b0ff-83c7d1d9d9c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=642205817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.642205817
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3137337014
Short name T99
Test name
Test status
Simulation time 1868337923 ps
CPU time 3.21 seconds
Started Apr 28 01:13:22 PM PDT 24
Finished Apr 28 01:13:25 PM PDT 24
Peak memory 216332 kb
Host smart-cb27b6c5-b928-4ae1-8c95-225d993f28bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137337014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3137337014
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.268241479
Short name T446
Test name
Test status
Simulation time 1632990612 ps
CPU time 9.78 seconds
Started Apr 28 01:13:22 PM PDT 24
Finished Apr 28 01:13:33 PM PDT 24
Peak memory 216260 kb
Host smart-d55b679f-bf9a-4c10-ae2f-ab91438e75e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268241479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.268241479
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3902284648
Short name T534
Test name
Test status
Simulation time 173954676 ps
CPU time 2.44 seconds
Started Apr 28 01:13:19 PM PDT 24
Finished Apr 28 01:13:22 PM PDT 24
Peak memory 216296 kb
Host smart-54af6022-45da-4767-ae44-377a9f059151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902284648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3902284648
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.435409443
Short name T107
Test name
Test status
Simulation time 291163063 ps
CPU time 0.9 seconds
Started Apr 28 01:13:19 PM PDT 24
Finished Apr 28 01:13:21 PM PDT 24
Peak memory 206740 kb
Host smart-ecf80462-a975-4696-8c60-7730b13aa404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435409443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.435409443
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2234046511
Short name T233
Test name
Test status
Simulation time 7247158656 ps
CPU time 14.37 seconds
Started Apr 28 01:13:25 PM PDT 24
Finished Apr 28 01:13:41 PM PDT 24
Peak memory 235692 kb
Host smart-e169f184-d546-4d60-bc56-8d2c7cd26da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234046511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2234046511
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2254848098
Short name T621
Test name
Test status
Simulation time 21853278 ps
CPU time 0.68 seconds
Started Apr 28 01:13:30 PM PDT 24
Finished Apr 28 01:13:33 PM PDT 24
Peak memory 204816 kb
Host smart-bdcc0d21-9ce4-413c-af78-a1fa0dc4b139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254848098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2254848098
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2047616684
Short name T575
Test name
Test status
Simulation time 21609105 ps
CPU time 0.78 seconds
Started Apr 28 01:13:26 PM PDT 24
Finished Apr 28 01:13:28 PM PDT 24
Peak memory 206636 kb
Host smart-ebfea1c5-f16f-4f90-a9cc-fdd8c414ea98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047616684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2047616684
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_intercept.994792971
Short name T235
Test name
Test status
Simulation time 21290284546 ps
CPU time 10.36 seconds
Started Apr 28 01:13:29 PM PDT 24
Finished Apr 28 01:13:42 PM PDT 24
Peak memory 218892 kb
Host smart-72c28697-a961-4fa4-9a53-cfd44168e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994792971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.994792971
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2699004136
Short name T384
Test name
Test status
Simulation time 477778777 ps
CPU time 7.74 seconds
Started Apr 28 01:13:31 PM PDT 24
Finished Apr 28 01:13:41 PM PDT 24
Peak memory 222992 kb
Host smart-04a80e0d-76ab-46e8-8203-6f7c8f40edb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699004136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2699004136
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1339378829
Short name T51
Test name
Test status
Simulation time 148262405209 ps
CPU time 28.95 seconds
Started Apr 28 01:13:25 PM PDT 24
Finished Apr 28 01:13:55 PM PDT 24
Peak memory 236292 kb
Host smart-df567a11-527f-4e05-b070-d91b6cce3689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339378829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1339378829
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2879463352
Short name T559
Test name
Test status
Simulation time 5607820006 ps
CPU time 13.04 seconds
Started Apr 28 01:13:31 PM PDT 24
Finished Apr 28 01:13:46 PM PDT 24
Peak memory 219188 kb
Host smart-b1ed4ae0-ced7-4b16-889c-9980313a2125
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2879463352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2879463352
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1124503862
Short name T657
Test name
Test status
Simulation time 25869233992 ps
CPU time 63.32 seconds
Started Apr 28 01:13:25 PM PDT 24
Finished Apr 28 01:14:30 PM PDT 24
Peak memory 221864 kb
Host smart-fc3d28b9-86ce-4467-b546-2a706b35a0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124503862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1124503862
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.66291217
Short name T492
Test name
Test status
Simulation time 16874161010 ps
CPU time 42.55 seconds
Started Apr 28 01:13:31 PM PDT 24
Finished Apr 28 01:14:15 PM PDT 24
Peak memory 216388 kb
Host smart-7db6f752-9575-4c26-b9c5-536a90b8a3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66291217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.66291217
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.530931392
Short name T177
Test name
Test status
Simulation time 342405642 ps
CPU time 12.1 seconds
Started Apr 28 01:13:25 PM PDT 24
Finished Apr 28 01:13:39 PM PDT 24
Peak memory 216420 kb
Host smart-5a3e2cbc-89fa-42fe-ab08-a9e0ae6aa3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530931392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.530931392
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.204501395
Short name T423
Test name
Test status
Simulation time 66330126 ps
CPU time 0.92 seconds
Started Apr 28 01:13:26 PM PDT 24
Finished Apr 28 01:13:28 PM PDT 24
Peak memory 206804 kb
Host smart-48245c55-4934-4790-aaa4-78846bdf7aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204501395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.204501395
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1536536038
Short name T215
Test name
Test status
Simulation time 14140928174 ps
CPU time 20.34 seconds
Started Apr 28 01:13:30 PM PDT 24
Finished Apr 28 01:13:52 PM PDT 24
Peak memory 220940 kb
Host smart-69150999-3a57-4c28-b7b5-530fb45259fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536536038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1536536038
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1962389436
Short name T666
Test name
Test status
Simulation time 106053329 ps
CPU time 0.7 seconds
Started Apr 28 01:13:36 PM PDT 24
Finished Apr 28 01:13:40 PM PDT 24
Peak memory 205352 kb
Host smart-5cab3be3-f76d-41dc-bd56-13c29c50143b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962389436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1962389436
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1050426319
Short name T563
Test name
Test status
Simulation time 63938756 ps
CPU time 0.76 seconds
Started Apr 28 01:13:30 PM PDT 24
Finished Apr 28 01:13:33 PM PDT 24
Peak memory 206684 kb
Host smart-e9f8aa2a-3803-4659-9afa-a88e2d91143e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050426319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1050426319
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2777074077
Short name T593
Test name
Test status
Simulation time 1087289048 ps
CPU time 5.27 seconds
Started Apr 28 01:13:39 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 232472 kb
Host smart-4bb731dc-5d33-45d3-b720-24ffd9602a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777074077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2777074077
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1689318382
Short name T345
Test name
Test status
Simulation time 92729561471 ps
CPU time 56.68 seconds
Started Apr 28 01:13:38 PM PDT 24
Finished Apr 28 01:14:41 PM PDT 24
Peak memory 218988 kb
Host smart-c56e6c4e-2a5e-4534-8e88-8844bc7eede9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689318382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1689318382
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3986315170
Short name T696
Test name
Test status
Simulation time 4179794465 ps
CPU time 12.62 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:59 PM PDT 24
Peak memory 221944 kb
Host smart-bd2bc07e-bc70-49a2-a009-ca351d5cf58f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3986315170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3986315170
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4163847973
Short name T620
Test name
Test status
Simulation time 39274887 ps
CPU time 0.97 seconds
Started Apr 28 01:13:35 PM PDT 24
Finished Apr 28 01:13:39 PM PDT 24
Peak memory 207016 kb
Host smart-56e8a65a-c978-46c0-bc78-1c398df39ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163847973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4163847973
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4283661370
Short name T395
Test name
Test status
Simulation time 24416970009 ps
CPU time 32.6 seconds
Started Apr 28 01:13:30 PM PDT 24
Finished Apr 28 01:14:05 PM PDT 24
Peak memory 216392 kb
Host smart-29ac68f3-2664-42d6-9273-58f1b6400352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283661370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4283661370
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1456310394
Short name T687
Test name
Test status
Simulation time 2060357736 ps
CPU time 5.97 seconds
Started Apr 28 01:13:31 PM PDT 24
Finished Apr 28 01:13:39 PM PDT 24
Peak memory 216204 kb
Host smart-8022e671-15dc-478d-97fe-03896d3c0d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456310394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1456310394
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1363483021
Short name T539
Test name
Test status
Simulation time 300892788 ps
CPU time 1.18 seconds
Started Apr 28 01:13:32 PM PDT 24
Finished Apr 28 01:13:35 PM PDT 24
Peak memory 207760 kb
Host smart-bbfdeef3-0564-4fbf-b03b-144ff97e4c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363483021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1363483021
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4079717813
Short name T521
Test name
Test status
Simulation time 182951680 ps
CPU time 0.92 seconds
Started Apr 28 01:13:31 PM PDT 24
Finished Apr 28 01:13:34 PM PDT 24
Peak memory 206832 kb
Host smart-0dd065a6-6cbd-481f-a37f-b24c5d810147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079717813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4079717813
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4108724997
Short name T625
Test name
Test status
Simulation time 11379459 ps
CPU time 0.7 seconds
Started Apr 28 01:13:41 PM PDT 24
Finished Apr 28 01:13:50 PM PDT 24
Peak memory 205300 kb
Host smart-08061cf7-23e1-4773-af40-2df5fc6dda17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108724997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4108724997
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3802211178
Short name T599
Test name
Test status
Simulation time 28414662 ps
CPU time 0.75 seconds
Started Apr 28 01:13:43 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 205632 kb
Host smart-f381794d-9fb4-491f-bea1-dba4e360f1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802211178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3802211178
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1194895339
Short name T308
Test name
Test status
Simulation time 459613805 ps
CPU time 14.81 seconds
Started Apr 28 01:13:38 PM PDT 24
Finished Apr 28 01:13:59 PM PDT 24
Peak memory 252796 kb
Host smart-8f4b0525-25b0-423a-b511-486be85abaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194895339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1194895339
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.988949398
Short name T419
Test name
Test status
Simulation time 705008016 ps
CPU time 3.82 seconds
Started Apr 28 01:13:37 PM PDT 24
Finished Apr 28 01:13:47 PM PDT 24
Peak memory 220956 kb
Host smart-8dba75fc-d613-42eb-99ef-3e608f83b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988949398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.988949398
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1143105913
Short name T206
Test name
Test status
Simulation time 7411627322 ps
CPU time 47.85 seconds
Started Apr 28 01:13:38 PM PDT 24
Finished Apr 28 01:14:31 PM PDT 24
Peak memory 232784 kb
Host smart-f670f860-4abe-4b49-b318-c0497f6654ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143105913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1143105913
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.78691925
Short name T440
Test name
Test status
Simulation time 2121104759 ps
CPU time 12.87 seconds
Started Apr 28 01:13:38 PM PDT 24
Finished Apr 28 01:13:56 PM PDT 24
Peak memory 223040 kb
Host smart-29107daa-3e5a-4e0a-a802-c7b0876d864d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78691925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direc
t.78691925
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.687016768
Short name T368
Test name
Test status
Simulation time 69408311 ps
CPU time 0.96 seconds
Started Apr 28 01:13:43 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 206584 kb
Host smart-f158506d-0dd4-4715-ad82-6a2107984188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687016768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.687016768
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2459424794
Short name T708
Test name
Test status
Simulation time 6152204139 ps
CPU time 41.01 seconds
Started Apr 28 01:13:43 PM PDT 24
Finished Apr 28 01:14:31 PM PDT 24
Peak memory 216044 kb
Host smart-f71fab70-c9a5-49ef-90c9-a5c4d1af6d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459424794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2459424794
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.28826830
Short name T580
Test name
Test status
Simulation time 2312672784 ps
CPU time 8.24 seconds
Started Apr 28 01:13:37 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 216272 kb
Host smart-2294af1f-35ca-4835-99c0-f93951e21597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28826830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.28826830
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3040710
Short name T65
Test name
Test status
Simulation time 330801874 ps
CPU time 1.59 seconds
Started Apr 28 01:13:37 PM PDT 24
Finished Apr 28 01:13:43 PM PDT 24
Peak memory 216256 kb
Host smart-107a96ad-1b18-4bac-9a89-cf870137ff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3040710
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4026910545
Short name T461
Test name
Test status
Simulation time 188190165 ps
CPU time 0.84 seconds
Started Apr 28 01:13:37 PM PDT 24
Finished Apr 28 01:13:42 PM PDT 24
Peak memory 205760 kb
Host smart-dd0ee488-d7a0-4318-bda1-4125a81fa9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026910545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4026910545
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2992081836
Short name T624
Test name
Test status
Simulation time 1248045819 ps
CPU time 4.84 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 232616 kb
Host smart-fa037aa8-ab6e-4809-9e09-efd30aeccbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992081836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2992081836
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4150048594
Short name T660
Test name
Test status
Simulation time 14617440 ps
CPU time 0.72 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:48 PM PDT 24
Peak memory 204828 kb
Host smart-495f06c2-a434-4174-915e-e596a9881be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150048594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4150048594
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1391138225
Short name T611
Test name
Test status
Simulation time 230052287 ps
CPU time 0.75 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:48 PM PDT 24
Peak memory 206624 kb
Host smart-14f2f27c-7494-4f64-b2d3-d4ff29831f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391138225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1391138225
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1958767393
Short name T236
Test name
Test status
Simulation time 38840674207 ps
CPU time 17.26 seconds
Started Apr 28 01:13:43 PM PDT 24
Finished Apr 28 01:14:08 PM PDT 24
Peak memory 232740 kb
Host smart-4408f4ee-b3b8-4439-b87a-ea06abdf4378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958767393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1958767393
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.479452955
Short name T689
Test name
Test status
Simulation time 507338781 ps
CPU time 4.19 seconds
Started Apr 28 01:13:41 PM PDT 24
Finished Apr 28 01:13:53 PM PDT 24
Peak memory 223084 kb
Host smart-f90658ef-d767-4303-947f-b2f3f268957d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=479452955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.479452955
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1782563398
Short name T634
Test name
Test status
Simulation time 9136612565 ps
CPU time 31.58 seconds
Started Apr 28 01:13:41 PM PDT 24
Finished Apr 28 01:14:21 PM PDT 24
Peak memory 216328 kb
Host smart-013550c4-bf43-4226-a349-552486e73923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782563398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1782563398
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3037451706
Short name T498
Test name
Test status
Simulation time 990563789 ps
CPU time 5.08 seconds
Started Apr 28 01:13:41 PM PDT 24
Finished Apr 28 01:13:54 PM PDT 24
Peak memory 216288 kb
Host smart-d156395e-8d65-4048-98b2-311eae33078f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037451706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3037451706
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2205576473
Short name T471
Test name
Test status
Simulation time 234447655 ps
CPU time 4.71 seconds
Started Apr 28 01:13:41 PM PDT 24
Finished Apr 28 01:13:53 PM PDT 24
Peak memory 216280 kb
Host smart-512e9298-89dd-4be7-a83b-a6c51b325e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205576473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2205576473
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.453518682
Short name T529
Test name
Test status
Simulation time 142235617 ps
CPU time 0.73 seconds
Started Apr 28 01:13:43 PM PDT 24
Finished Apr 28 01:13:51 PM PDT 24
Peak memory 205788 kb
Host smart-921e2df8-3415-4384-9a0f-5b931ded7b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453518682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.453518682
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3009096694
Short name T606
Test name
Test status
Simulation time 11915639 ps
CPU time 0.69 seconds
Started Apr 28 01:13:47 PM PDT 24
Finished Apr 28 01:13:54 PM PDT 24
Peak memory 205400 kb
Host smart-d2b3a07c-de36-42cf-8a78-fb87e879d07f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009096694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3009096694
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2591596661
Short name T444
Test name
Test status
Simulation time 12626839 ps
CPU time 0.75 seconds
Started Apr 28 01:13:41 PM PDT 24
Finished Apr 28 01:13:50 PM PDT 24
Peak memory 205556 kb
Host smart-d578aca5-96e0-4ab0-b156-03082a752bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591596661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2591596661
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3986434687
Short name T418
Test name
Test status
Simulation time 1487799916 ps
CPU time 5.92 seconds
Started Apr 28 01:13:46 PM PDT 24
Finished Apr 28 01:13:59 PM PDT 24
Peak memory 222096 kb
Host smart-ea889881-ed07-4c93-a0b6-0341c7a3deb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986434687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3986434687
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3343869214
Short name T536
Test name
Test status
Simulation time 1434511791 ps
CPU time 5.34 seconds
Started Apr 28 01:13:45 PM PDT 24
Finished Apr 28 01:13:58 PM PDT 24
Peak memory 219112 kb
Host smart-4475bbf6-2bfb-418d-895f-9dc7931bb58b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3343869214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3343869214
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.609630861
Short name T407
Test name
Test status
Simulation time 1677401752 ps
CPU time 21.63 seconds
Started Apr 28 01:13:42 PM PDT 24
Finished Apr 28 01:14:12 PM PDT 24
Peak memory 216308 kb
Host smart-a3aaf9fe-105e-439c-9a90-913d99766ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609630861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.609630861
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.645297791
Short name T605
Test name
Test status
Simulation time 4120136531 ps
CPU time 6.99 seconds
Started Apr 28 01:13:45 PM PDT 24
Finished Apr 28 01:13:59 PM PDT 24
Peak memory 216352 kb
Host smart-c717444b-c1c8-4848-8c28-f0daa16c132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645297791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.645297791
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.491728826
Short name T63
Test name
Test status
Simulation time 139830985 ps
CPU time 1.75 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:49 PM PDT 24
Peak memory 216344 kb
Host smart-3200ef46-c233-402e-ae5c-053ff1519c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491728826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.491728826
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3243561708
Short name T12
Test name
Test status
Simulation time 30847989 ps
CPU time 0.76 seconds
Started Apr 28 01:13:40 PM PDT 24
Finished Apr 28 01:13:48 PM PDT 24
Peak memory 205712 kb
Host smart-fa71084a-e3f4-43bd-81c2-fc7f8d4f5338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243561708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3243561708
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2092810307
Short name T587
Test name
Test status
Simulation time 41106484 ps
CPU time 0.66 seconds
Started Apr 28 01:12:35 PM PDT 24
Finished Apr 28 01:12:36 PM PDT 24
Peak memory 205688 kb
Host smart-fd143059-6442-45ca-bbdf-1e41a0f91ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092810307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
092810307
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.911694556
Short name T172
Test name
Test status
Simulation time 15840986 ps
CPU time 0.75 seconds
Started Apr 28 01:12:30 PM PDT 24
Finished Apr 28 01:12:32 PM PDT 24
Peak memory 205680 kb
Host smart-828e6028-8dbc-4216-919c-10d243304e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911694556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.911694556
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1804458025
Short name T304
Test name
Test status
Simulation time 7076581611 ps
CPU time 32.6 seconds
Started Apr 28 01:12:33 PM PDT 24
Finished Apr 28 01:13:07 PM PDT 24
Peak memory 234612 kb
Host smart-7901c511-8157-4264-a781-c87dc4e34efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804458025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1804458025
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4197082869
Short name T286
Test name
Test status
Simulation time 692925504 ps
CPU time 6.34 seconds
Started Apr 28 01:12:30 PM PDT 24
Finished Apr 28 01:12:38 PM PDT 24
Peak memory 224368 kb
Host smart-61981375-34ea-4815-8b9a-c84a68a7ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197082869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4197082869
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2525149019
Short name T679
Test name
Test status
Simulation time 3861130142 ps
CPU time 10.61 seconds
Started Apr 28 01:12:38 PM PDT 24
Finished Apr 28 01:12:49 PM PDT 24
Peak memory 220304 kb
Host smart-123b30fc-ee7d-4a41-9e84-9b7f69ba67fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525149019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2525149019
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3563600633
Short name T46
Test name
Test status
Simulation time 37703531 ps
CPU time 0.97 seconds
Started Apr 28 01:12:36 PM PDT 24
Finished Apr 28 01:12:38 PM PDT 24
Peak memory 235052 kb
Host smart-76ab6d7b-900e-4a8f-bc4f-26c6c4044cc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563600633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3563600633
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1390889104
Short name T166
Test name
Test status
Simulation time 72856586 ps
CPU time 1.13 seconds
Started Apr 28 01:12:36 PM PDT 24
Finished Apr 28 01:12:38 PM PDT 24
Peak memory 207388 kb
Host smart-748c361c-076a-4b33-8c2b-03c6769d589f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390889104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1390889104
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1565617553
Short name T675
Test name
Test status
Simulation time 40324414121 ps
CPU time 53.1 seconds
Started Apr 28 01:12:32 PM PDT 24
Finished Apr 28 01:13:26 PM PDT 24
Peak memory 216292 kb
Host smart-3f0e50c2-6cc5-4578-8986-28bfceb35d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565617553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1565617553
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3928378300
Short name T466
Test name
Test status
Simulation time 4435724896 ps
CPU time 4.68 seconds
Started Apr 28 01:12:31 PM PDT 24
Finished Apr 28 01:12:37 PM PDT 24
Peak memory 216260 kb
Host smart-0234346f-03c6-48d4-bc88-72279784e456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928378300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3928378300
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2618130477
Short name T656
Test name
Test status
Simulation time 941854765 ps
CPU time 3.41 seconds
Started Apr 28 01:12:32 PM PDT 24
Finished Apr 28 01:12:36 PM PDT 24
Peak memory 216176 kb
Host smart-bf8f3e33-6330-46f8-a2ec-e887d623b3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618130477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2618130477
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.22947648
Short name T693
Test name
Test status
Simulation time 566315033 ps
CPU time 1.04 seconds
Started Apr 28 01:12:32 PM PDT 24
Finished Apr 28 01:12:34 PM PDT 24
Peak memory 206772 kb
Host smart-8772fbc5-12d1-4970-89ff-daa52f3ca887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22947648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.22947648
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1655255239
Short name T326
Test name
Test status
Simulation time 103806814 ps
CPU time 2.84 seconds
Started Apr 28 01:12:31 PM PDT 24
Finished Apr 28 01:12:35 PM PDT 24
Peak memory 222516 kb
Host smart-87ef8a8c-17fd-4465-81dd-75c154dc232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655255239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1655255239
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.437649567
Short name T698
Test name
Test status
Simulation time 14520557 ps
CPU time 0.72 seconds
Started Apr 28 01:13:53 PM PDT 24
Finished Apr 28 01:13:58 PM PDT 24
Peak memory 205424 kb
Host smart-8ea9bf1d-2055-4cbf-a7de-c850a2253ef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437649567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.437649567
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.263207850
Short name T52
Test name
Test status
Simulation time 21334234 ps
CPU time 0.75 seconds
Started Apr 28 01:13:46 PM PDT 24
Finished Apr 28 01:13:54 PM PDT 24
Peak memory 206664 kb
Host smart-372ea8c7-7c86-4dba-a7d8-e518b993b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263207850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.263207850
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1628720010
Short name T66
Test name
Test status
Simulation time 140548661 ps
CPU time 2.35 seconds
Started Apr 28 01:13:53 PM PDT 24
Finished Apr 28 01:14:00 PM PDT 24
Peak memory 221820 kb
Host smart-185264b7-db2e-45e0-aeba-9c480f7c014b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628720010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1628720010
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.36246827
Short name T274
Test name
Test status
Simulation time 9540061683 ps
CPU time 47.3 seconds
Started Apr 28 01:13:52 PM PDT 24
Finished Apr 28 01:14:44 PM PDT 24
Peak memory 221088 kb
Host smart-3341f746-185d-4304-9cba-ea49f68437ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36246827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.36246827
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2836851670
Short name T508
Test name
Test status
Simulation time 241945707 ps
CPU time 4.61 seconds
Started Apr 28 01:13:54 PM PDT 24
Finished Apr 28 01:14:03 PM PDT 24
Peak memory 221412 kb
Host smart-5566cc90-cac0-4b9d-b1b8-8a1ea35478e5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2836851670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2836851670
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1638995038
Short name T391
Test name
Test status
Simulation time 1828876850 ps
CPU time 6.89 seconds
Started Apr 28 01:13:47 PM PDT 24
Finished Apr 28 01:14:00 PM PDT 24
Peak memory 216572 kb
Host smart-cd4906e9-9aeb-434b-8838-4ef14d4a52c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638995038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1638995038
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1413350209
Short name T469
Test name
Test status
Simulation time 9755502110 ps
CPU time 5.95 seconds
Started Apr 28 01:13:48 PM PDT 24
Finished Apr 28 01:14:00 PM PDT 24
Peak memory 216348 kb
Host smart-936a8dc3-1070-4567-a220-c29d60723437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413350209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1413350209
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2388385526
Short name T176
Test name
Test status
Simulation time 119075775 ps
CPU time 2.61 seconds
Started Apr 28 01:13:46 PM PDT 24
Finished Apr 28 01:13:55 PM PDT 24
Peak memory 216272 kb
Host smart-c2a589b6-85d5-46a5-a2ff-90057aad3cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388385526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2388385526
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.621608805
Short name T457
Test name
Test status
Simulation time 165978464 ps
CPU time 1.11 seconds
Started Apr 28 01:13:45 PM PDT 24
Finished Apr 28 01:13:53 PM PDT 24
Peak memory 206780 kb
Host smart-d64a0936-0cfb-41ed-a07e-0d81f1a79c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621608805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.621608805
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.36892516
Short name T631
Test name
Test status
Simulation time 12777634 ps
CPU time 0.7 seconds
Started Apr 28 01:13:59 PM PDT 24
Finished Apr 28 01:14:04 PM PDT 24
Peak memory 204748 kb
Host smart-d877bf03-d23f-4ddc-96c2-bc55b9b88f13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36892516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.36892516
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3457703640
Short name T15
Test name
Test status
Simulation time 49615075 ps
CPU time 0.78 seconds
Started Apr 28 01:13:54 PM PDT 24
Finished Apr 28 01:13:59 PM PDT 24
Peak memory 206700 kb
Host smart-3cc17f82-79d9-4033-a919-3ed3974b02e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457703640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3457703640
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4262701738
Short name T269
Test name
Test status
Simulation time 1727276870 ps
CPU time 6.36 seconds
Started Apr 28 01:13:52 PM PDT 24
Finished Apr 28 01:14:04 PM PDT 24
Peak memory 222948 kb
Host smart-53f0cbc5-c4f6-4508-91f0-4e67390df198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262701738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4262701738
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3990705758
Short name T284
Test name
Test status
Simulation time 67175314 ps
CPU time 2.24 seconds
Started Apr 28 01:13:55 PM PDT 24
Finished Apr 28 01:14:01 PM PDT 24
Peak memory 222224 kb
Host smart-2edbb2e1-9d56-4afd-bc55-738cfe7b9a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990705758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3990705758
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2217364759
Short name T561
Test name
Test status
Simulation time 3498886491 ps
CPU time 10.75 seconds
Started Apr 28 01:13:59 PM PDT 24
Finished Apr 28 01:14:14 PM PDT 24
Peak memory 219424 kb
Host smart-ef0392db-e537-4bd4-9286-62e27a3960c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2217364759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2217364759
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3612548432
Short name T645
Test name
Test status
Simulation time 3372369949 ps
CPU time 17.22 seconds
Started Apr 28 01:13:55 PM PDT 24
Finished Apr 28 01:14:16 PM PDT 24
Peak memory 216388 kb
Host smart-658dd3e8-c94a-4885-877e-ca48c52e652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612548432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3612548432
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3235254269
Short name T612
Test name
Test status
Simulation time 5286796835 ps
CPU time 7.44 seconds
Started Apr 28 01:13:51 PM PDT 24
Finished Apr 28 01:14:04 PM PDT 24
Peak memory 216308 kb
Host smart-4b8379c0-d285-4425-85a5-33c07af0842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235254269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3235254269
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1405359400
Short name T453
Test name
Test status
Simulation time 261341016 ps
CPU time 1 seconds
Started Apr 28 01:13:51 PM PDT 24
Finished Apr 28 01:13:58 PM PDT 24
Peak memory 207896 kb
Host smart-2b14fa25-325e-4cc0-a9f9-92947071b3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405359400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1405359400
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.477317225
Short name T669
Test name
Test status
Simulation time 182535341 ps
CPU time 0.92 seconds
Started Apr 28 01:13:52 PM PDT 24
Finished Apr 28 01:13:58 PM PDT 24
Peak memory 206828 kb
Host smart-5fdcce63-209e-4193-b053-07f9b12f6925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477317225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.477317225
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3519829655
Short name T552
Test name
Test status
Simulation time 34688118 ps
CPU time 0.67 seconds
Started Apr 28 01:14:04 PM PDT 24
Finished Apr 28 01:14:12 PM PDT 24
Peak memory 205400 kb
Host smart-bc664ee5-85ef-4cc7-83ad-3e465b1564b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519829655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3519829655
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.697944417
Short name T421
Test name
Test status
Simulation time 13827330 ps
CPU time 0.75 seconds
Started Apr 28 01:14:00 PM PDT 24
Finished Apr 28 01:14:06 PM PDT 24
Peak memory 205644 kb
Host smart-d631b918-1e10-4665-ae63-48a127402553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697944417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.697944417
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1560879486
Short name T695
Test name
Test status
Simulation time 5824675182 ps
CPU time 77.33 seconds
Started Apr 28 01:13:58 PM PDT 24
Finished Apr 28 01:15:19 PM PDT 24
Peak memory 257228 kb
Host smart-7f148e46-cf81-4dd4-8115-7bc964d2f687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560879486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1560879486
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1645267676
Short name T191
Test name
Test status
Simulation time 4670333410 ps
CPU time 10.77 seconds
Started Apr 28 01:14:02 PM PDT 24
Finished Apr 28 01:14:18 PM PDT 24
Peak memory 218736 kb
Host smart-55257edf-c69c-42ef-814f-55cccb820f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645267676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1645267676
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1413915763
Short name T354
Test name
Test status
Simulation time 25462872531 ps
CPU time 12.84 seconds
Started Apr 28 01:14:02 PM PDT 24
Finished Apr 28 01:14:20 PM PDT 24
Peak memory 222492 kb
Host smart-56915d20-0afe-443e-8615-75f012476412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413915763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1413915763
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2803323279
Short name T70
Test name
Test status
Simulation time 10874912975 ps
CPU time 12.12 seconds
Started Apr 28 01:14:00 PM PDT 24
Finished Apr 28 01:14:16 PM PDT 24
Peak memory 224380 kb
Host smart-92c05935-fab7-4992-98b6-03eaafad06a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803323279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2803323279
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.185262339
Short name T460
Test name
Test status
Simulation time 1331078652 ps
CPU time 18.56 seconds
Started Apr 28 01:14:00 PM PDT 24
Finished Apr 28 01:14:24 PM PDT 24
Peak memory 220064 kb
Host smart-08b8fc4d-97aa-4c7a-85cd-7b0170d03d61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=185262339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.185262339
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.236041613
Short name T488
Test name
Test status
Simulation time 304710320 ps
CPU time 2.4 seconds
Started Apr 28 01:13:57 PM PDT 24
Finished Apr 28 01:14:04 PM PDT 24
Peak memory 216352 kb
Host smart-ffbe21b5-d960-4d1b-b841-94556a6222a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236041613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.236041613
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1282524520
Short name T717
Test name
Test status
Simulation time 67646731 ps
CPU time 1.26 seconds
Started Apr 28 01:13:59 PM PDT 24
Finished Apr 28 01:14:04 PM PDT 24
Peak memory 216316 kb
Host smart-9e3b5d2d-246d-47db-a0ff-4df24697d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282524520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1282524520
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3639731810
Short name T614
Test name
Test status
Simulation time 19609981 ps
CPU time 0.76 seconds
Started Apr 28 01:13:59 PM PDT 24
Finished Apr 28 01:14:03 PM PDT 24
Peak memory 205792 kb
Host smart-88da7890-c590-4ae6-aa75-63344d2dbbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639731810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3639731810
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4195038999
Short name T707
Test name
Test status
Simulation time 3350352410 ps
CPU time 11.52 seconds
Started Apr 28 01:13:58 PM PDT 24
Finished Apr 28 01:14:13 PM PDT 24
Peak memory 222192 kb
Host smart-09a3e938-6a44-452a-b0ba-3f54f67188b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195038999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4195038999
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3403409135
Short name T29
Test name
Test status
Simulation time 33685945 ps
CPU time 0.7 seconds
Started Apr 28 01:14:13 PM PDT 24
Finished Apr 28 01:14:28 PM PDT 24
Peak memory 204820 kb
Host smart-da258777-4dd5-4be2-8969-c5b05f9e20b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403409135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3403409135
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1837942798
Short name T14
Test name
Test status
Simulation time 18852829 ps
CPU time 0.78 seconds
Started Apr 28 01:14:03 PM PDT 24
Finished Apr 28 01:14:09 PM PDT 24
Peak memory 205620 kb
Host smart-0e36f33a-7059-4796-8145-47d1d1aea956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837942798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1837942798
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.576032977
Short name T309
Test name
Test status
Simulation time 32107866863 ps
CPU time 176.94 seconds
Started Apr 28 01:14:11 PM PDT 24
Finished Apr 28 01:17:18 PM PDT 24
Peak memory 235312 kb
Host smart-18abca2c-12ae-4741-8436-f1d6c24842a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576032977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.576032977
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1840844090
Short name T532
Test name
Test status
Simulation time 924145865 ps
CPU time 6.97 seconds
Started Apr 28 01:14:09 PM PDT 24
Finished Apr 28 01:14:25 PM PDT 24
Peak memory 220652 kb
Host smart-4bcb150d-0132-4466-8c31-2c4f0404ec93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1840844090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1840844090
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1677223966
Short name T411
Test name
Test status
Simulation time 3141055551 ps
CPU time 11.99 seconds
Started Apr 28 01:14:03 PM PDT 24
Finished Apr 28 01:14:21 PM PDT 24
Peak memory 216236 kb
Host smart-e036e3ca-a00b-424a-bc9a-61c0dc056bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677223966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1677223966
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4199704885
Short name T434
Test name
Test status
Simulation time 11968745360 ps
CPU time 11.38 seconds
Started Apr 28 01:14:03 PM PDT 24
Finished Apr 28 01:14:20 PM PDT 24
Peak memory 216292 kb
Host smart-6c760234-76c2-4674-83e8-3023199094cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199704885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4199704885
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1393730011
Short name T64
Test name
Test status
Simulation time 60522360 ps
CPU time 1.41 seconds
Started Apr 28 01:14:05 PM PDT 24
Finished Apr 28 01:14:14 PM PDT 24
Peak memory 216300 kb
Host smart-4c8001b6-ee44-4dc3-95ca-297c748dbc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393730011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1393730011
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1915641985
Short name T547
Test name
Test status
Simulation time 40480651 ps
CPU time 0.79 seconds
Started Apr 28 01:14:02 PM PDT 24
Finished Apr 28 01:14:08 PM PDT 24
Peak memory 205712 kb
Host smart-618585c1-c2cf-459c-aa38-4eac6e8dabb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915641985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1915641985
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3423246985
Short name T637
Test name
Test status
Simulation time 17936250 ps
CPU time 0.7 seconds
Started Apr 28 01:14:17 PM PDT 24
Finished Apr 28 01:14:38 PM PDT 24
Peak memory 205652 kb
Host smart-383c2077-0cb4-4c7d-9f28-5ec09b70950c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423246985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3423246985
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2990731484
Short name T208
Test name
Test status
Simulation time 678130329 ps
CPU time 4.06 seconds
Started Apr 28 01:14:15 PM PDT 24
Finished Apr 28 01:14:36 PM PDT 24
Peak memory 218576 kb
Host smart-9f5cdf1c-6ec8-4858-8754-79594d82d3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990731484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2990731484
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1112662587
Short name T627
Test name
Test status
Simulation time 129226976 ps
CPU time 0.78 seconds
Started Apr 28 01:14:08 PM PDT 24
Finished Apr 28 01:14:17 PM PDT 24
Peak memory 206972 kb
Host smart-807e9eb6-f5b3-40b3-81b2-7128d9af4699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112662587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1112662587
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1277731702
Short name T328
Test name
Test status
Simulation time 1918335463 ps
CPU time 12.44 seconds
Started Apr 28 01:14:14 PM PDT 24
Finished Apr 28 01:14:43 PM PDT 24
Peak memory 222752 kb
Host smart-511e7d0f-8f09-430d-b942-6f90371e9339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277731702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1277731702
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.624213045
Short name T713
Test name
Test status
Simulation time 528873648 ps
CPU time 6.14 seconds
Started Apr 28 01:14:14 PM PDT 24
Finished Apr 28 01:14:34 PM PDT 24
Peak memory 223004 kb
Host smart-b522b07c-258f-430b-bcf8-94358ca1d367
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=624213045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.624213045
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1324305063
Short name T626
Test name
Test status
Simulation time 270282000 ps
CPU time 4.6 seconds
Started Apr 28 01:14:10 PM PDT 24
Finished Apr 28 01:14:25 PM PDT 24
Peak memory 216180 kb
Host smart-dc02c2a4-1d79-4f23-8f38-ac21d06d3f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324305063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1324305063
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3249506067
Short name T538
Test name
Test status
Simulation time 1224431902 ps
CPU time 3.73 seconds
Started Apr 28 01:14:09 PM PDT 24
Finished Apr 28 01:14:23 PM PDT 24
Peak memory 216316 kb
Host smart-1f02969d-69c5-42d7-a726-1c8039a92f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249506067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3249506067
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1211352366
Short name T548
Test name
Test status
Simulation time 82579127 ps
CPU time 1.13 seconds
Started Apr 28 01:14:15 PM PDT 24
Finished Apr 28 01:14:32 PM PDT 24
Peak memory 207808 kb
Host smart-06fd7559-bda9-4050-9e04-a2e90d0a9cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211352366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1211352366
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3621144427
Short name T480
Test name
Test status
Simulation time 156188466 ps
CPU time 1.09 seconds
Started Apr 28 01:14:17 PM PDT 24
Finished Apr 28 01:14:38 PM PDT 24
Peak memory 206792 kb
Host smart-415d24d0-cbb9-4ac1-9077-5a94d963bb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621144427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3621144427
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1086211161
Short name T26
Test name
Test status
Simulation time 2642921404 ps
CPU time 8.45 seconds
Started Apr 28 01:14:13 PM PDT 24
Finished Apr 28 01:14:35 PM PDT 24
Peak memory 221444 kb
Host smart-239d25ea-fde4-4f97-b7a5-46517eeeb204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086211161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1086211161
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.791276130
Short name T700
Test name
Test status
Simulation time 20716853 ps
CPU time 0.7 seconds
Started Apr 28 01:14:18 PM PDT 24
Finished Apr 28 01:14:40 PM PDT 24
Peak memory 204784 kb
Host smart-e82e1c06-8a93-4a08-bc33-b06b3dbedb10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791276130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.791276130
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3880582727
Short name T635
Test name
Test status
Simulation time 52253915 ps
CPU time 0.72 seconds
Started Apr 28 01:14:15 PM PDT 24
Finished Apr 28 01:14:31 PM PDT 24
Peak memory 205624 kb
Host smart-ea038f98-36be-4dcb-b021-ed9781c99655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880582727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3880582727
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2515601680
Short name T201
Test name
Test status
Simulation time 267871846 ps
CPU time 2.75 seconds
Started Apr 28 01:14:19 PM PDT 24
Finished Apr 28 01:14:43 PM PDT 24
Peak memory 218756 kb
Host smart-c95e17b1-e77b-4c21-a3cb-1577b9383379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515601680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2515601680
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2714734098
Short name T282
Test name
Test status
Simulation time 164389846 ps
CPU time 4.14 seconds
Started Apr 28 01:14:18 PM PDT 24
Finished Apr 28 01:14:44 PM PDT 24
Peak memory 222672 kb
Host smart-bef1bd43-e0d8-4588-aacf-9b4e34dbac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714734098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2714734098
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3858889761
Short name T479
Test name
Test status
Simulation time 3755062790 ps
CPU time 9.54 seconds
Started Apr 28 01:14:18 PM PDT 24
Finished Apr 28 01:14:48 PM PDT 24
Peak memory 219664 kb
Host smart-58ce2427-844a-4e98-a90c-3da7f84b100d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3858889761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3858889761
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1032159397
Short name T630
Test name
Test status
Simulation time 12259205214 ps
CPU time 14.06 seconds
Started Apr 28 01:14:20 PM PDT 24
Finished Apr 28 01:14:56 PM PDT 24
Peak memory 216420 kb
Host smart-18d4275c-8384-40fa-989b-582228900c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032159397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1032159397
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2072360718
Short name T443
Test name
Test status
Simulation time 1218386544 ps
CPU time 6.3 seconds
Started Apr 28 01:14:19 PM PDT 24
Finished Apr 28 01:14:48 PM PDT 24
Peak memory 216324 kb
Host smart-03ee3670-74c8-4598-8bfe-71428bb8a568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072360718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2072360718
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.761877507
Short name T609
Test name
Test status
Simulation time 1017112855 ps
CPU time 3.69 seconds
Started Apr 28 01:14:20 PM PDT 24
Finished Apr 28 01:14:47 PM PDT 24
Peak memory 216320 kb
Host smart-2b089c54-84d8-4486-8beb-6c0bf294c22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761877507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.761877507
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1625889411
Short name T485
Test name
Test status
Simulation time 30759650 ps
CPU time 0.79 seconds
Started Apr 28 01:14:21 PM PDT 24
Finished Apr 28 01:14:46 PM PDT 24
Peak memory 205816 kb
Host smart-c782056a-187a-4e76-81ab-c8f18089d379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625889411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1625889411
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1708572333
Short name T549
Test name
Test status
Simulation time 11922818 ps
CPU time 0.69 seconds
Started Apr 28 01:14:24 PM PDT 24
Finished Apr 28 01:14:50 PM PDT 24
Peak memory 205376 kb
Host smart-069f809f-a094-4006-a7c2-67025f244744
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708572333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1708572333
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1645874233
Short name T683
Test name
Test status
Simulation time 22039646 ps
CPU time 0.72 seconds
Started Apr 28 01:14:21 PM PDT 24
Finished Apr 28 01:14:46 PM PDT 24
Peak memory 207032 kb
Host smart-5bff5939-d86e-4820-8326-dfb487772b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645874233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1645874233
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2494541815
Short name T265
Test name
Test status
Simulation time 2578507463 ps
CPU time 24.23 seconds
Started Apr 28 01:14:26 PM PDT 24
Finished Apr 28 01:15:16 PM PDT 24
Peak memory 232716 kb
Host smart-9b23757b-18f6-4e34-88ca-b57ce04a0cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494541815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2494541815
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3613655027
Short name T220
Test name
Test status
Simulation time 3722861478 ps
CPU time 10.94 seconds
Started Apr 28 01:14:27 PM PDT 24
Finished Apr 28 01:15:05 PM PDT 24
Peak memory 222784 kb
Host smart-40e1d963-8da0-49f8-a7c7-1a14a93eabc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613655027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3613655027
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2621769671
Short name T527
Test name
Test status
Simulation time 205961193 ps
CPU time 4.57 seconds
Started Apr 28 01:14:28 PM PDT 24
Finished Apr 28 01:15:00 PM PDT 24
Peak memory 222952 kb
Host smart-e31eb9f6-01c5-4512-a7e2-dc9beae35291
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2621769671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2621769671
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4052466156
Short name T370
Test name
Test status
Simulation time 52493794 ps
CPU time 1.08 seconds
Started Apr 28 01:14:25 PM PDT 24
Finished Apr 28 01:14:52 PM PDT 24
Peak memory 207308 kb
Host smart-9b8dc514-8f34-467c-8328-0e3494d2a1ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052466156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4052466156
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3448230502
Short name T386
Test name
Test status
Simulation time 1531722681 ps
CPU time 24.27 seconds
Started Apr 28 01:14:23 PM PDT 24
Finished Apr 28 01:15:13 PM PDT 24
Peak memory 216268 kb
Host smart-2d406ba1-167d-4995-be5a-56b7b98a69ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448230502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3448230502
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4246513347
Short name T455
Test name
Test status
Simulation time 7088957620 ps
CPU time 12.73 seconds
Started Apr 28 01:14:21 PM PDT 24
Finished Apr 28 01:14:58 PM PDT 24
Peak memory 216324 kb
Host smart-241417de-19c0-42a7-b96c-f0a6f542e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246513347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4246513347
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3198669845
Short name T691
Test name
Test status
Simulation time 43283210 ps
CPU time 1.07 seconds
Started Apr 28 01:14:24 PM PDT 24
Finished Apr 28 01:14:52 PM PDT 24
Peak memory 208032 kb
Host smart-0a72137a-7548-41ce-85d6-b81168c26a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198669845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3198669845
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2865079276
Short name T601
Test name
Test status
Simulation time 70228291 ps
CPU time 0.85 seconds
Started Apr 28 01:14:23 PM PDT 24
Finished Apr 28 01:14:50 PM PDT 24
Peak memory 205788 kb
Host smart-55df6127-7c63-4001-9142-b1b6973711c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865079276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2865079276
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1146720304
Short name T651
Test name
Test status
Simulation time 40702601 ps
CPU time 0.68 seconds
Started Apr 28 01:14:30 PM PDT 24
Finished Apr 28 01:15:01 PM PDT 24
Peak memory 205364 kb
Host smart-0446c75f-9807-49f6-a6cd-b069dbdce2c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146720304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1146720304
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1653003499
Short name T618
Test name
Test status
Simulation time 18416627 ps
CPU time 0.77 seconds
Started Apr 28 01:14:24 PM PDT 24
Finished Apr 28 01:14:51 PM PDT 24
Peak memory 206704 kb
Host smart-9efffeb6-064f-4155-9252-0491e4c10318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653003499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1653003499
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.312883738
Short name T313
Test name
Test status
Simulation time 7387416846 ps
CPU time 38.32 seconds
Started Apr 28 01:14:30 PM PDT 24
Finished Apr 28 01:15:39 PM PDT 24
Peak memory 254004 kb
Host smart-c64bc6e9-9c5e-4e97-af5e-ccd8cf163d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312883738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.312883738
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1698380854
Short name T229
Test name
Test status
Simulation time 14544774393 ps
CPU time 43.51 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:52 PM PDT 24
Peak memory 249116 kb
Host smart-73ad9cba-ddfb-47c9-b446-8e08fba85172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698380854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1698380854
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.659687206
Short name T262
Test name
Test status
Simulation time 73923907 ps
CPU time 2.29 seconds
Started Apr 28 01:14:25 PM PDT 24
Finished Apr 28 01:14:54 PM PDT 24
Peak memory 218476 kb
Host smart-2b5de748-e023-4334-8c00-c6ab7fed99a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659687206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.659687206
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.7450401
Short name T514
Test name
Test status
Simulation time 5047250842 ps
CPU time 5.8 seconds
Started Apr 28 01:14:27 PM PDT 24
Finished Apr 28 01:15:01 PM PDT 24
Peak memory 219080 kb
Host smart-ab57bfeb-cb7e-4791-b014-5673e690ea8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=7450401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.7450401
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2383499596
Short name T712
Test name
Test status
Simulation time 3779191548 ps
CPU time 10.28 seconds
Started Apr 28 01:14:28 PM PDT 24
Finished Apr 28 01:15:05 PM PDT 24
Peak memory 216216 kb
Host smart-025d38bc-3c5d-450a-8d73-96916bbcc7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383499596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2383499596
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3201332654
Short name T21
Test name
Test status
Simulation time 6351884283 ps
CPU time 5.76 seconds
Started Apr 28 01:14:25 PM PDT 24
Finished Apr 28 01:14:57 PM PDT 24
Peak memory 216240 kb
Host smart-07c41234-6725-4b2d-962a-8e3c6fc17ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201332654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3201332654
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.536035134
Short name T553
Test name
Test status
Simulation time 295681587 ps
CPU time 1.84 seconds
Started Apr 28 01:14:24 PM PDT 24
Finished Apr 28 01:14:51 PM PDT 24
Peak memory 216240 kb
Host smart-03cdca11-320f-4faa-9cf1-2651cac55d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536035134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.536035134
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1762595807
Short name T676
Test name
Test status
Simulation time 67077040 ps
CPU time 0.75 seconds
Started Apr 28 01:14:24 PM PDT 24
Finished Apr 28 01:14:51 PM PDT 24
Peak memory 205668 kb
Host smart-e06300d7-f7e4-4709-90a2-852a3af66949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762595807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1762595807
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1921367887
Short name T704
Test name
Test status
Simulation time 10336931654 ps
CPU time 33.69 seconds
Started Apr 28 01:14:30 PM PDT 24
Finished Apr 28 01:15:34 PM PDT 24
Peak memory 239056 kb
Host smart-d90feeeb-2492-44da-8189-43d1a721fabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921367887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1921367887
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2156856827
Short name T542
Test name
Test status
Simulation time 31619868 ps
CPU time 0.68 seconds
Started Apr 28 01:14:33 PM PDT 24
Finished Apr 28 01:15:05 PM PDT 24
Peak memory 205792 kb
Host smart-f03e3acd-04cf-4b23-b36f-c83e5c06e8e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156856827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2156856827
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1690832383
Short name T512
Test name
Test status
Simulation time 290930267 ps
CPU time 5.21 seconds
Started Apr 28 01:14:32 PM PDT 24
Finished Apr 28 01:15:10 PM PDT 24
Peak memory 223100 kb
Host smart-207ba160-166c-4936-ae46-f61729d68f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690832383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1690832383
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4035098336
Short name T619
Test name
Test status
Simulation time 91823162 ps
CPU time 0.72 seconds
Started Apr 28 01:14:31 PM PDT 24
Finished Apr 28 01:15:03 PM PDT 24
Peak memory 205988 kb
Host smart-19f3d4ff-c1ff-45b0-b731-9c79f4bf0a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035098336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4035098336
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.396544347
Short name T525
Test name
Test status
Simulation time 440790723 ps
CPU time 10.85 seconds
Started Apr 28 01:14:34 PM PDT 24
Finished Apr 28 01:15:18 PM PDT 24
Peak memory 234352 kb
Host smart-1c38cc5c-fd15-4218-9f3a-9e626b5fecf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396544347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.396544347
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2311814626
Short name T115
Test name
Test status
Simulation time 746438331 ps
CPU time 9.4 seconds
Started Apr 28 01:14:31 PM PDT 24
Finished Apr 28 01:15:11 PM PDT 24
Peak memory 232500 kb
Host smart-188877bc-5437-4ede-b9f5-33555a0ec6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311814626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2311814626
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4234404535
Short name T89
Test name
Test status
Simulation time 6572957601 ps
CPU time 75.83 seconds
Started Apr 28 01:14:30 PM PDT 24
Finished Apr 28 01:16:16 PM PDT 24
Peak memory 218536 kb
Host smart-88e578ee-bfd7-4fab-85fd-9c65f7721834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234404535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4234404535
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1966966180
Short name T640
Test name
Test status
Simulation time 78003323696 ps
CPU time 14.25 seconds
Started Apr 28 01:14:29 PM PDT 24
Finished Apr 28 01:15:13 PM PDT 24
Peak memory 224524 kb
Host smart-b20a74c8-7840-4fbf-98f9-daccb86b1ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966966180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1966966180
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.58579409
Short name T541
Test name
Test status
Simulation time 3147483166 ps
CPU time 12.26 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:20 PM PDT 24
Peak memory 219224 kb
Host smart-5e7edfd0-1dd2-455b-bf4e-d0763a26e6eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=58579409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direc
t.58579409
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.819154761
Short name T413
Test name
Test status
Simulation time 12318904434 ps
CPU time 13.63 seconds
Started Apr 28 01:14:32 PM PDT 24
Finished Apr 28 01:15:17 PM PDT 24
Peak memory 216316 kb
Host smart-b12dc694-f9ed-43d3-b5c5-9b6239581f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819154761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.819154761
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3521350972
Short name T572
Test name
Test status
Simulation time 23211295367 ps
CPU time 19.09 seconds
Started Apr 28 01:14:30 PM PDT 24
Finished Apr 28 01:15:20 PM PDT 24
Peak memory 217556 kb
Host smart-5abb66bb-febb-427b-aef7-ab4a726aea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521350972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3521350972
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2940323784
Short name T497
Test name
Test status
Simulation time 207953528 ps
CPU time 1.55 seconds
Started Apr 28 01:14:28 PM PDT 24
Finished Apr 28 01:14:58 PM PDT 24
Peak memory 216316 kb
Host smart-b34aa572-95cc-4850-8b34-9f9d47376f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940323784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2940323784
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2007592822
Short name T60
Test name
Test status
Simulation time 79021680 ps
CPU time 0.92 seconds
Started Apr 28 01:14:30 PM PDT 24
Finished Apr 28 01:15:01 PM PDT 24
Peak memory 206816 kb
Host smart-f1ba5fbe-47b4-49f5-9b82-28bcd47e47a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007592822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2007592822
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3131080546
Short name T16
Test name
Test status
Simulation time 13402564 ps
CPU time 0.7 seconds
Started Apr 28 01:14:41 PM PDT 24
Finished Apr 28 01:15:16 PM PDT 24
Peak memory 204840 kb
Host smart-fac7755d-d588-471b-a3c2-22e996f38f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131080546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3131080546
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3929053625
Short name T431
Test name
Test status
Simulation time 19379441 ps
CPU time 0.76 seconds
Started Apr 28 01:14:34 PM PDT 24
Finished Apr 28 01:15:07 PM PDT 24
Peak memory 206900 kb
Host smart-cce13d0d-7ef2-4762-a6e7-01fc7a25ebfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929053625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3929053625
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3392470362
Short name T705
Test name
Test status
Simulation time 14629935136 ps
CPU time 57.16 seconds
Started Apr 28 01:14:32 PM PDT 24
Finished Apr 28 01:16:02 PM PDT 24
Peak memory 236668 kb
Host smart-49d751ee-9e33-4610-9b7f-a26f3eca66ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392470362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3392470362
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4119241334
Short name T607
Test name
Test status
Simulation time 182365646 ps
CPU time 2.5 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:12 PM PDT 24
Peak memory 218484 kb
Host smart-24cb9d53-4508-4ca4-9373-0eeb428d9d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119241334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4119241334
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1271785927
Short name T213
Test name
Test status
Simulation time 533288781 ps
CPU time 7.17 seconds
Started Apr 28 01:14:34 PM PDT 24
Finished Apr 28 01:15:13 PM PDT 24
Peak memory 216600 kb
Host smart-ed4e326e-71ac-41d1-8d1f-068a6895441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271785927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1271785927
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3456408029
Short name T7
Test name
Test status
Simulation time 2244153248 ps
CPU time 6.9 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:15 PM PDT 24
Peak memory 223140 kb
Host smart-c0997170-20c6-48d7-b470-a3af1480e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456408029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3456408029
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2014997862
Short name T477
Test name
Test status
Simulation time 1174377777 ps
CPU time 15.95 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:25 PM PDT 24
Peak memory 220372 kb
Host smart-a28f9a9b-ae5b-421e-9a8b-d76278b9190a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2014997862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2014997862
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.553290029
Short name T403
Test name
Test status
Simulation time 910069767 ps
CPU time 13.5 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:22 PM PDT 24
Peak memory 216232 kb
Host smart-d2fbb209-e060-4b00-8115-1faf94ebfc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553290029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.553290029
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1084485487
Short name T462
Test name
Test status
Simulation time 4269814535 ps
CPU time 5.78 seconds
Started Apr 28 01:14:40 PM PDT 24
Finished Apr 28 01:15:21 PM PDT 24
Peak memory 216284 kb
Host smart-e0f630e0-0862-4e91-a4ff-096da05996d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084485487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1084485487
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2388987172
Short name T404
Test name
Test status
Simulation time 30257262 ps
CPU time 1.01 seconds
Started Apr 28 01:14:34 PM PDT 24
Finished Apr 28 01:15:07 PM PDT 24
Peak memory 207820 kb
Host smart-98ebea96-659e-4f13-8c5d-b354a87670db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388987172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2388987172
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1104454033
Short name T641
Test name
Test status
Simulation time 44343878 ps
CPU time 0.84 seconds
Started Apr 28 01:14:35 PM PDT 24
Finished Apr 28 01:15:09 PM PDT 24
Peak memory 205780 kb
Host smart-d3e82449-8bcc-43ee-ab7c-129f377e0126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104454033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1104454033
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2271404065
Short name T570
Test name
Test status
Simulation time 13723358 ps
CPU time 0.74 seconds
Started Apr 28 01:12:42 PM PDT 24
Finished Apr 28 01:12:44 PM PDT 24
Peak memory 205408 kb
Host smart-d0a7aa65-d88a-45b0-8fe2-30766697baee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271404065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
271404065
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1378975401
Short name T579
Test name
Test status
Simulation time 26515011 ps
CPU time 0.73 seconds
Started Apr 28 01:12:36 PM PDT 24
Finished Apr 28 01:12:37 PM PDT 24
Peak memory 205652 kb
Host smart-3d2f59b5-d27a-4a4b-996f-332ee9d8b539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378975401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1378975401
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3784518663
Short name T238
Test name
Test status
Simulation time 14424410891 ps
CPU time 12.6 seconds
Started Apr 28 01:12:37 PM PDT 24
Finished Apr 28 01:12:50 PM PDT 24
Peak memory 223184 kb
Host smart-dbe85992-b227-4e82-9a38-a487f3ea4b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784518663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3784518663
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4112489099
Short name T237
Test name
Test status
Simulation time 91449258 ps
CPU time 3.42 seconds
Started Apr 28 01:12:36 PM PDT 24
Finished Apr 28 01:12:41 PM PDT 24
Peak memory 222000 kb
Host smart-66e4d13c-2d18-476b-9d99-225e32edbb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112489099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4112489099
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1785564722
Short name T120
Test name
Test status
Simulation time 3867609426 ps
CPU time 20.51 seconds
Started Apr 28 01:12:44 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 219256 kb
Host smart-423d5db0-e777-469d-a883-b86595fcd4ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1785564722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1785564722
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4071144168
Short name T45
Test name
Test status
Simulation time 129976050 ps
CPU time 0.99 seconds
Started Apr 28 01:12:42 PM PDT 24
Finished Apr 28 01:12:43 PM PDT 24
Peak memory 235092 kb
Host smart-bf53e0e5-ed79-4879-8849-3b9083a2b6ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071144168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4071144168
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1501564573
Short name T681
Test name
Test status
Simulation time 35634440834 ps
CPU time 27.48 seconds
Started Apr 28 01:12:37 PM PDT 24
Finished Apr 28 01:13:05 PM PDT 24
Peak memory 216340 kb
Host smart-a48a3f19-bad6-41ad-9f3e-04275c72895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501564573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1501564573
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3189967504
Short name T519
Test name
Test status
Simulation time 470762392 ps
CPU time 3.12 seconds
Started Apr 28 01:12:36 PM PDT 24
Finished Apr 28 01:12:40 PM PDT 24
Peak memory 216144 kb
Host smart-c3b5440d-85c8-4a5a-a632-2a71d87214a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189967504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3189967504
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3632854163
Short name T654
Test name
Test status
Simulation time 32073616 ps
CPU time 0.7 seconds
Started Apr 28 01:12:39 PM PDT 24
Finished Apr 28 01:12:40 PM PDT 24
Peak memory 205788 kb
Host smart-cd038f51-a249-4b6a-bc7e-4e28732ae003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632854163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3632854163
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.133590987
Short name T564
Test name
Test status
Simulation time 62160377 ps
CPU time 0.93 seconds
Started Apr 28 01:12:35 PM PDT 24
Finished Apr 28 01:12:36 PM PDT 24
Peak memory 206820 kb
Host smart-e627bbf8-1167-4279-aa33-e6644f1b87d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133590987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.133590987
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1839042611
Short name T517
Test name
Test status
Simulation time 12638143 ps
CPU time 0.67 seconds
Started Apr 28 01:14:45 PM PDT 24
Finished Apr 28 01:15:21 PM PDT 24
Peak memory 205664 kb
Host smart-7e21f8ac-b3d4-42e0-9e97-2a9b89cc43e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839042611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1839042611
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2064485964
Short name T569
Test name
Test status
Simulation time 4654546690 ps
CPU time 8.67 seconds
Started Apr 28 01:14:41 PM PDT 24
Finished Apr 28 01:15:25 PM PDT 24
Peak memory 223068 kb
Host smart-781009ee-f9c3-4db0-896c-e0e3c115307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064485964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2064485964
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.401823648
Short name T442
Test name
Test status
Simulation time 71782546 ps
CPU time 0.78 seconds
Started Apr 28 01:14:38 PM PDT 24
Finished Apr 28 01:15:14 PM PDT 24
Peak memory 206920 kb
Host smart-de7371ba-d0c8-4a36-9c47-e19ba37eec0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401823648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.401823648
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1953622779
Short name T161
Test name
Test status
Simulation time 5194589756 ps
CPU time 4.65 seconds
Started Apr 28 01:14:39 PM PDT 24
Finished Apr 28 01:15:18 PM PDT 24
Peak memory 220528 kb
Host smart-da6eda35-5aa3-4c10-af8a-4612ff6fd835
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1953622779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1953622779
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.443696663
Short name T103
Test name
Test status
Simulation time 3067651685 ps
CPU time 9.22 seconds
Started Apr 28 01:14:40 PM PDT 24
Finished Apr 28 01:15:24 PM PDT 24
Peak memory 216508 kb
Host smart-8bf4d425-66ec-43e5-82be-274b9e8ea468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443696663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.443696663
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1282171633
Short name T678
Test name
Test status
Simulation time 790449637 ps
CPU time 5.66 seconds
Started Apr 28 01:14:40 PM PDT 24
Finished Apr 28 01:15:21 PM PDT 24
Peak memory 216200 kb
Host smart-5d5ff2da-1625-4727-ba1d-bc66607597c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282171633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1282171633
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3696977205
Short name T638
Test name
Test status
Simulation time 61361714 ps
CPU time 1.5 seconds
Started Apr 28 01:14:40 PM PDT 24
Finished Apr 28 01:15:17 PM PDT 24
Peak memory 216432 kb
Host smart-41654ec0-0fe9-413d-aca6-eaca3b053522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696977205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3696977205
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4201191803
Short name T706
Test name
Test status
Simulation time 88498513 ps
CPU time 0.69 seconds
Started Apr 28 01:14:40 PM PDT 24
Finished Apr 28 01:15:16 PM PDT 24
Peak memory 205820 kb
Host smart-8eafcd65-dd90-48ab-9e8a-7864bfc9040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201191803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4201191803
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2723665060
Short name T202
Test name
Test status
Simulation time 6382830592 ps
CPU time 11.29 seconds
Started Apr 28 01:14:40 PM PDT 24
Finished Apr 28 01:15:27 PM PDT 24
Peak memory 236388 kb
Host smart-fcb4962f-0e0f-4549-8e68-4743470f77fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723665060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2723665060
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1001272600
Short name T494
Test name
Test status
Simulation time 27288697 ps
CPU time 0.68 seconds
Started Apr 28 01:14:54 PM PDT 24
Finished Apr 28 01:15:31 PM PDT 24
Peak memory 205432 kb
Host smart-d2d5e4e4-4ce8-415d-8d9b-cdcbee8c2a3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001272600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1001272600
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1038068035
Short name T649
Test name
Test status
Simulation time 14050572 ps
CPU time 0.73 seconds
Started Apr 28 01:14:45 PM PDT 24
Finished Apr 28 01:15:21 PM PDT 24
Peak memory 205980 kb
Host smart-a373c13a-ea16-4428-9c9a-53a92f7127c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038068035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1038068035
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1743719740
Short name T353
Test name
Test status
Simulation time 553728747 ps
CPU time 6.97 seconds
Started Apr 28 01:14:43 PM PDT 24
Finished Apr 28 01:15:25 PM PDT 24
Peak memory 224464 kb
Host smart-22a96f5b-7aeb-4b2d-bc69-2af7d51f56a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743719740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1743719740
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3611297235
Short name T276
Test name
Test status
Simulation time 23091658551 ps
CPU time 28.95 seconds
Started Apr 28 01:14:44 PM PDT 24
Finished Apr 28 01:15:49 PM PDT 24
Peak memory 222056 kb
Host smart-d5c9ca25-076a-452d-b783-341e38354aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611297235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3611297235
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3963518636
Short name T3
Test name
Test status
Simulation time 933979688 ps
CPU time 11.07 seconds
Started Apr 28 01:14:50 PM PDT 24
Finished Apr 28 01:15:37 PM PDT 24
Peak memory 219288 kb
Host smart-e187b891-8e00-4993-8fb2-ba49ae179e00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3963518636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3963518636
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1391356638
Short name T686
Test name
Test status
Simulation time 34398881 ps
CPU time 0.86 seconds
Started Apr 28 01:14:55 PM PDT 24
Finished Apr 28 01:15:32 PM PDT 24
Peak memory 205512 kb
Host smart-272e4ebb-5c4c-4e09-a131-7f14415b3f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391356638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1391356638
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3075291336
Short name T436
Test name
Test status
Simulation time 1183600984 ps
CPU time 5.55 seconds
Started Apr 28 01:14:44 PM PDT 24
Finished Apr 28 01:15:24 PM PDT 24
Peak memory 216244 kb
Host smart-3402b529-dec8-4647-99b0-e30d27f8579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075291336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3075291336
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2055358555
Short name T467
Test name
Test status
Simulation time 231652863 ps
CPU time 2.23 seconds
Started Apr 28 01:14:47 PM PDT 24
Finished Apr 28 01:15:25 PM PDT 24
Peak memory 216232 kb
Host smart-779ce1d0-52ec-4867-b797-28589aa880cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055358555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2055358555
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1602122456
Short name T589
Test name
Test status
Simulation time 29728994 ps
CPU time 0.79 seconds
Started Apr 28 01:14:44 PM PDT 24
Finished Apr 28 01:15:19 PM PDT 24
Peak memory 205760 kb
Host smart-5db23a43-631e-4b55-b1f7-913e365b5502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602122456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1602122456
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2868680470
Short name T41
Test name
Test status
Simulation time 249837620 ps
CPU time 2.34 seconds
Started Apr 28 01:14:49 PM PDT 24
Finished Apr 28 01:15:28 PM PDT 24
Peak memory 216260 kb
Host smart-ffd0f427-5942-437a-89ba-6b9c6dbbf7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868680470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2868680470
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2960433545
Short name T30
Test name
Test status
Simulation time 19487058 ps
CPU time 0.69 seconds
Started Apr 28 01:15:10 PM PDT 24
Finished Apr 28 01:15:46 PM PDT 24
Peak memory 204876 kb
Host smart-a83d56fa-a27d-4610-bcf7-b7fd49b8bde8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960433545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2960433545
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.389088297
Short name T665
Test name
Test status
Simulation time 49920347 ps
CPU time 0.76 seconds
Started Apr 28 01:14:56 PM PDT 24
Finished Apr 28 01:15:33 PM PDT 24
Peak memory 207024 kb
Host smart-1839c3d4-2305-490b-af01-1a68613f22e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389088297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.389088297
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2406437557
Short name T655
Test name
Test status
Simulation time 29717107234 ps
CPU time 108.03 seconds
Started Apr 28 01:14:59 PM PDT 24
Finished Apr 28 01:17:23 PM PDT 24
Peak memory 249656 kb
Host smart-4665b1dc-111a-4233-bfc9-bfa1be208aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406437557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2406437557
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3223247968
Short name T110
Test name
Test status
Simulation time 1803740791 ps
CPU time 20.87 seconds
Started Apr 28 01:14:59 PM PDT 24
Finished Apr 28 01:15:57 PM PDT 24
Peak memory 216868 kb
Host smart-629757a8-f965-441d-970a-22e4e0159180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223247968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3223247968
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.875369662
Short name T171
Test name
Test status
Simulation time 17257690673 ps
CPU time 69.47 seconds
Started Apr 28 01:15:03 PM PDT 24
Finished Apr 28 01:16:48 PM PDT 24
Peak memory 224580 kb
Host smart-2f7be3f2-5fa8-4b8e-a051-1d9ff0cb475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875369662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.875369662
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2968893843
Short name T69
Test name
Test status
Simulation time 2958402195 ps
CPU time 9.58 seconds
Started Apr 28 01:14:54 PM PDT 24
Finished Apr 28 01:15:41 PM PDT 24
Peak memory 222720 kb
Host smart-a43c2e1e-8426-4b90-b7d0-1a1368fa1b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968893843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2968893843
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3163396388
Short name T137
Test name
Test status
Simulation time 1246906476 ps
CPU time 6 seconds
Started Apr 28 01:15:02 PM PDT 24
Finished Apr 28 01:15:44 PM PDT 24
Peak memory 222284 kb
Host smart-1dbb7951-afd7-402e-8c84-8fbddb1c732b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163396388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3163396388
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2131951933
Short name T389
Test name
Test status
Simulation time 5324104136 ps
CPU time 32.01 seconds
Started Apr 28 01:14:53 PM PDT 24
Finished Apr 28 01:16:01 PM PDT 24
Peak memory 216240 kb
Host smart-a126e5e4-ff1c-404a-9ecb-d9dcc07740d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131951933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2131951933
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1651788448
Short name T59
Test name
Test status
Simulation time 54702531 ps
CPU time 0.76 seconds
Started Apr 28 01:14:53 PM PDT 24
Finished Apr 28 01:15:30 PM PDT 24
Peak memory 205716 kb
Host smart-8b15bde1-4b4e-418f-850c-b09eddc4711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651788448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1651788448
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.854363520
Short name T600
Test name
Test status
Simulation time 33424060 ps
CPU time 0.71 seconds
Started Apr 28 01:14:54 PM PDT 24
Finished Apr 28 01:15:31 PM PDT 24
Peak memory 205768 kb
Host smart-67ab72eb-5dbc-4833-95a8-ee5d55e6c6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854363520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.854363520
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.427050332
Short name T416
Test name
Test status
Simulation time 14872303 ps
CPU time 0.7 seconds
Started Apr 28 01:15:18 PM PDT 24
Finished Apr 28 01:15:55 PM PDT 24
Peak memory 205400 kb
Host smart-cf1e33e2-1cfc-4264-826e-7fd82deea1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427050332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.427050332
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3001356427
Short name T27
Test name
Test status
Simulation time 2156436675 ps
CPU time 16.14 seconds
Started Apr 28 01:15:11 PM PDT 24
Finished Apr 28 01:16:02 PM PDT 24
Peak memory 222604 kb
Host smart-7eb8d46a-10df-49cf-afa9-1f5cd3ad292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001356427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3001356427
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2598041431
Short name T449
Test name
Test status
Simulation time 23889095 ps
CPU time 0.82 seconds
Started Apr 28 01:15:09 PM PDT 24
Finished Apr 28 01:15:46 PM PDT 24
Peak memory 206684 kb
Host smart-553968fd-9328-436c-8d5d-dbd76ac7332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598041431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2598041431
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_intercept.372980861
Short name T199
Test name
Test status
Simulation time 8008641065 ps
CPU time 10.07 seconds
Started Apr 28 01:15:15 PM PDT 24
Finished Apr 28 01:16:01 PM PDT 24
Peak memory 232072 kb
Host smart-327dee63-0ef4-489e-a6d1-0198b6d7d4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372980861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.372980861
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2244796000
Short name T501
Test name
Test status
Simulation time 167324004 ps
CPU time 4.07 seconds
Started Apr 28 01:15:10 PM PDT 24
Finished Apr 28 01:15:49 PM PDT 24
Peak memory 222952 kb
Host smart-99c860fa-99b4-4b1c-b8b2-f352da9431d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2244796000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2244796000
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.669322184
Short name T101
Test name
Test status
Simulation time 3373160797 ps
CPU time 19.11 seconds
Started Apr 28 01:15:09 PM PDT 24
Finished Apr 28 01:16:04 PM PDT 24
Peak memory 216340 kb
Host smart-f177af37-490d-4fde-858d-56d996d37ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669322184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.669322184
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1643872823
Short name T524
Test name
Test status
Simulation time 7891347799 ps
CPU time 11.47 seconds
Started Apr 28 01:15:09 PM PDT 24
Finished Apr 28 01:15:57 PM PDT 24
Peak memory 216284 kb
Host smart-e3d58640-e703-488e-900c-b3708bf6b275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643872823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1643872823
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3841456686
Short name T489
Test name
Test status
Simulation time 63684284 ps
CPU time 1.79 seconds
Started Apr 28 01:15:15 PM PDT 24
Finished Apr 28 01:15:53 PM PDT 24
Peak memory 215800 kb
Host smart-885468a1-739b-4bb0-a4dc-eaebd9e6f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841456686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3841456686
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3855696356
Short name T450
Test name
Test status
Simulation time 182646828 ps
CPU time 0.89 seconds
Started Apr 28 01:15:15 PM PDT 24
Finished Apr 28 01:15:52 PM PDT 24
Peak memory 206316 kb
Host smart-22995d43-bdd1-4c54-94f7-2cdedf46a2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855696356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3855696356
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2245457084
Short name T688
Test name
Test status
Simulation time 1268623537 ps
CPU time 6.84 seconds
Started Apr 28 01:15:10 PM PDT 24
Finished Apr 28 01:15:53 PM PDT 24
Peak memory 232668 kb
Host smart-f6f0cb81-6a0a-4e22-8fb5-90fbac574251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245457084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2245457084
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.241733806
Short name T592
Test name
Test status
Simulation time 13749740 ps
CPU time 0.69 seconds
Started Apr 28 01:15:24 PM PDT 24
Finished Apr 28 01:16:00 PM PDT 24
Peak memory 205384 kb
Host smart-2c704c57-040d-4f5a-80a1-92f97c6df11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241733806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.241733806
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.4162649492
Short name T329
Test name
Test status
Simulation time 9362478949 ps
CPU time 14.28 seconds
Started Apr 28 01:15:20 PM PDT 24
Finished Apr 28 01:16:10 PM PDT 24
Peak memory 219056 kb
Host smart-802d1c1e-518e-47ec-a965-7e9c6c484e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162649492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.4162649492
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1428732529
Short name T175
Test name
Test status
Simulation time 33237456 ps
CPU time 0.77 seconds
Started Apr 28 01:15:15 PM PDT 24
Finished Apr 28 01:15:52 PM PDT 24
Peak memory 206692 kb
Host smart-6a7104c9-8150-4cc2-99cc-f84e6665f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428732529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1428732529
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.827166555
Short name T315
Test name
Test status
Simulation time 1842875381 ps
CPU time 22.38 seconds
Started Apr 28 01:15:21 PM PDT 24
Finished Apr 28 01:16:19 PM PDT 24
Peak memory 240572 kb
Host smart-1cc0b562-a98a-49d9-b1b4-68458f4df81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827166555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.827166555
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.186477031
Short name T324
Test name
Test status
Simulation time 212239929 ps
CPU time 3.09 seconds
Started Apr 28 01:15:19 PM PDT 24
Finished Apr 28 01:15:59 PM PDT 24
Peak memory 222492 kb
Host smart-104ba3c0-331f-4816-941f-4f0fa9f5a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186477031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.186477031
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1506578220
Short name T342
Test name
Test status
Simulation time 35503189288 ps
CPU time 23.62 seconds
Started Apr 28 01:15:19 PM PDT 24
Finished Apr 28 01:16:19 PM PDT 24
Peak memory 239576 kb
Host smart-eb3671c2-593e-45ad-89f0-b9b4f97ff06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506578220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1506578220
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2140455838
Short name T285
Test name
Test status
Simulation time 8971150327 ps
CPU time 19.16 seconds
Started Apr 28 01:15:21 PM PDT 24
Finished Apr 28 01:16:16 PM PDT 24
Peak memory 223736 kb
Host smart-fe893840-beac-4b15-8fa5-548daf984781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140455838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2140455838
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2273042478
Short name T255
Test name
Test status
Simulation time 8623934604 ps
CPU time 25.64 seconds
Started Apr 28 01:15:20 PM PDT 24
Finished Apr 28 01:16:22 PM PDT 24
Peak memory 232656 kb
Host smart-d7ffceff-0419-4214-b6c6-569f879768b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273042478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2273042478
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2784217219
Short name T673
Test name
Test status
Simulation time 368092899 ps
CPU time 4.91 seconds
Started Apr 28 01:15:20 PM PDT 24
Finished Apr 28 01:16:01 PM PDT 24
Peak memory 219760 kb
Host smart-e73bdf95-9b47-4253-8076-7b0b29c9ab99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2784217219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2784217219
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.185501530
Short name T596
Test name
Test status
Simulation time 861689192 ps
CPU time 4.81 seconds
Started Apr 28 01:15:16 PM PDT 24
Finished Apr 28 01:15:57 PM PDT 24
Peak memory 216276 kb
Host smart-a2d950a5-8063-4154-8596-f9e1dea5bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185501530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.185501530
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4059550798
Short name T668
Test name
Test status
Simulation time 214668806 ps
CPU time 1.78 seconds
Started Apr 28 01:15:18 PM PDT 24
Finished Apr 28 01:15:57 PM PDT 24
Peak memory 216344 kb
Host smart-47e98178-5719-4a4b-bf17-8fe773564d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059550798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4059550798
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.400977535
Short name T555
Test name
Test status
Simulation time 43180483 ps
CPU time 0.86 seconds
Started Apr 28 01:15:17 PM PDT 24
Finished Apr 28 01:15:55 PM PDT 24
Peak memory 205788 kb
Host smart-bc2fe621-8178-4cd0-a990-cf30171cecc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400977535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.400977535
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1627167498
Short name T333
Test name
Test status
Simulation time 8729238760 ps
CPU time 9.95 seconds
Started Apr 28 01:15:19 PM PDT 24
Finished Apr 28 01:16:05 PM PDT 24
Peak memory 223124 kb
Host smart-90232471-c3e0-4256-bba5-6b70bce674b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627167498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1627167498
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4281814420
Short name T682
Test name
Test status
Simulation time 13760225 ps
CPU time 0.74 seconds
Started Apr 28 01:15:36 PM PDT 24
Finished Apr 28 01:16:11 PM PDT 24
Peak memory 205728 kb
Host smart-825744b1-dd05-40d3-9a46-86a9c91e65ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281814420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4281814420
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1883010478
Short name T424
Test name
Test status
Simulation time 260589072 ps
CPU time 0.77 seconds
Started Apr 28 01:15:25 PM PDT 24
Finished Apr 28 01:16:01 PM PDT 24
Peak memory 206644 kb
Host smart-cf103a08-dbe1-4b78-97b5-4b3863dc7906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883010478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1883010478
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.141304758
Short name T615
Test name
Test status
Simulation time 403462596 ps
CPU time 11.17 seconds
Started Apr 28 01:15:38 PM PDT 24
Finished Apr 28 01:16:23 PM PDT 24
Peak memory 232700 kb
Host smart-d2b3915c-7eaf-4ace-8590-ec2fb7415e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141304758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.141304758
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.551708243
Short name T351
Test name
Test status
Simulation time 1546114508 ps
CPU time 5.44 seconds
Started Apr 28 01:15:31 PM PDT 24
Finished Apr 28 01:16:11 PM PDT 24
Peak memory 218640 kb
Host smart-db3c456b-165e-4805-bdec-5c57ddf5ada8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551708243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.551708243
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1667149629
Short name T346
Test name
Test status
Simulation time 515255738 ps
CPU time 5.75 seconds
Started Apr 28 01:15:32 PM PDT 24
Finished Apr 28 01:16:13 PM PDT 24
Peak memory 218652 kb
Host smart-4ca3d951-fba3-4ca0-b5f4-0db4c11191c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667149629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1667149629
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2513453797
Short name T709
Test name
Test status
Simulation time 365445625 ps
CPU time 3.7 seconds
Started Apr 28 01:15:32 PM PDT 24
Finished Apr 28 01:16:11 PM PDT 24
Peak memory 218456 kb
Host smart-85dbdee3-60ec-4b41-be5c-d0bd0f203613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513453797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2513453797
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1808985635
Short name T340
Test name
Test status
Simulation time 518711208 ps
CPU time 2.41 seconds
Started Apr 28 01:15:32 PM PDT 24
Finished Apr 28 01:16:09 PM PDT 24
Peak memory 220788 kb
Host smart-b5d051b9-8974-45bd-a02c-ed24dd1202c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808985635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1808985635
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2264424016
Short name T426
Test name
Test status
Simulation time 407426868 ps
CPU time 4.9 seconds
Started Apr 28 01:15:39 PM PDT 24
Finished Apr 28 01:16:18 PM PDT 24
Peak memory 218692 kb
Host smart-037b68b9-87fd-43ec-a11b-96834f77c413
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2264424016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2264424016
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2215083875
Short name T628
Test name
Test status
Simulation time 6573514465 ps
CPU time 11.81 seconds
Started Apr 28 01:15:27 PM PDT 24
Finished Apr 28 01:16:14 PM PDT 24
Peak memory 216208 kb
Host smart-92aac0b7-1e86-498f-8bf6-871a0d557b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215083875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2215083875
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.565448454
Short name T174
Test name
Test status
Simulation time 866053456 ps
CPU time 3.72 seconds
Started Apr 28 01:15:25 PM PDT 24
Finished Apr 28 01:16:04 PM PDT 24
Peak memory 216260 kb
Host smart-c168c2e0-ec3e-447e-a0a8-3557e227bd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565448454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.565448454
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1501812144
Short name T623
Test name
Test status
Simulation time 71744696 ps
CPU time 3.27 seconds
Started Apr 28 01:15:28 PM PDT 24
Finished Apr 28 01:16:06 PM PDT 24
Peak memory 216200 kb
Host smart-b1975a78-3a1f-4d2b-b87a-f859a730fba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501812144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1501812144
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.489707340
Short name T716
Test name
Test status
Simulation time 556937059 ps
CPU time 0.9 seconds
Started Apr 28 01:15:25 PM PDT 24
Finished Apr 28 01:16:01 PM PDT 24
Peak memory 206720 kb
Host smart-8b5ed1b2-8ba3-48db-b180-0e1cb2a0190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489707340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.489707340
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2746883418
Short name T194
Test name
Test status
Simulation time 3276459496 ps
CPU time 8.21 seconds
Started Apr 28 01:15:32 PM PDT 24
Finished Apr 28 01:16:15 PM PDT 24
Peak memory 233144 kb
Host smart-fc7c4363-a0f2-400a-9c24-f0e432f3b6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746883418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2746883418
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2680399148
Short name T653
Test name
Test status
Simulation time 16961619 ps
CPU time 0.69 seconds
Started Apr 28 01:15:53 PM PDT 24
Finished Apr 28 01:16:31 PM PDT 24
Peak memory 205412 kb
Host smart-cc78adf3-4b53-46f3-86ea-224c5a002fd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680399148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2680399148
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.33317384
Short name T231
Test name
Test status
Simulation time 2319871605 ps
CPU time 7.72 seconds
Started Apr 28 01:15:42 PM PDT 24
Finished Apr 28 01:16:25 PM PDT 24
Peak memory 218764 kb
Host smart-890abb1f-6be6-4bc3-ac7a-93a8ae27bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33317384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.33317384
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1722462153
Short name T430
Test name
Test status
Simulation time 52097181 ps
CPU time 0.77 seconds
Started Apr 28 01:15:38 PM PDT 24
Finished Apr 28 01:16:14 PM PDT 24
Peak memory 206960 kb
Host smart-eaf5e004-fcb2-41c5-b541-31ce2dbd432c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722462153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1722462153
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2912272474
Short name T544
Test name
Test status
Simulation time 2866515696 ps
CPU time 12.59 seconds
Started Apr 28 01:15:43 PM PDT 24
Finished Apr 28 01:16:30 PM PDT 24
Peak memory 234584 kb
Host smart-aeb8fb07-42a2-4f12-b519-fb93e9755080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912272474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2912272474
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1445817675
Short name T363
Test name
Test status
Simulation time 145605990 ps
CPU time 3.11 seconds
Started Apr 28 01:15:44 PM PDT 24
Finished Apr 28 01:16:21 PM PDT 24
Peak memory 223328 kb
Host smart-fda3bcd0-f9c7-4cef-a55e-11f47fbb5b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445817675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1445817675
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2293623496
Short name T289
Test name
Test status
Simulation time 26227424881 ps
CPU time 114.93 seconds
Started Apr 28 01:15:43 PM PDT 24
Finished Apr 28 01:18:13 PM PDT 24
Peak memory 220744 kb
Host smart-bfaf7717-8d38-47de-934b-664c1b3cf3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293623496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2293623496
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1219864008
Short name T360
Test name
Test status
Simulation time 842257342 ps
CPU time 7.65 seconds
Started Apr 28 01:15:44 PM PDT 24
Finished Apr 28 01:16:26 PM PDT 24
Peak memory 219796 kb
Host smart-da13cf4a-5a2c-4b8c-807c-58d15bee51f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219864008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1219864008
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3273693859
Short name T193
Test name
Test status
Simulation time 9420428510 ps
CPU time 13.74 seconds
Started Apr 28 01:15:38 PM PDT 24
Finished Apr 28 01:16:26 PM PDT 24
Peak memory 227904 kb
Host smart-83ad9da0-a198-431f-b67c-a22278e53dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273693859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3273693859
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2115906635
Short name T664
Test name
Test status
Simulation time 220111804 ps
CPU time 3.86 seconds
Started Apr 28 01:15:48 PM PDT 24
Finished Apr 28 01:16:26 PM PDT 24
Peak memory 218728 kb
Host smart-48bfdc75-6f70-4f24-845e-017eebe5615c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2115906635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2115906635
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.488030988
Short name T39
Test name
Test status
Simulation time 79173386 ps
CPU time 1.16 seconds
Started Apr 28 01:15:50 PM PDT 24
Finished Apr 28 01:16:26 PM PDT 24
Peak memory 207180 kb
Host smart-782faf1a-3a58-4252-a0dc-022afe1e7421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488030988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.488030988
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1094788326
Short name T511
Test name
Test status
Simulation time 1793733486 ps
CPU time 3.89 seconds
Started Apr 28 01:15:39 PM PDT 24
Finished Apr 28 01:16:18 PM PDT 24
Peak memory 216248 kb
Host smart-f9d1d986-745a-4d96-bfd9-5c9ce257d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094788326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1094788326
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1858247958
Short name T648
Test name
Test status
Simulation time 144913257 ps
CPU time 2.14 seconds
Started Apr 28 01:15:36 PM PDT 24
Finished Apr 28 01:16:13 PM PDT 24
Peak memory 216296 kb
Host smart-49e69b82-62c3-4c8d-96a6-aecad326e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858247958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1858247958
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3133570422
Short name T703
Test name
Test status
Simulation time 31998115 ps
CPU time 0.81 seconds
Started Apr 28 01:15:36 PM PDT 24
Finished Apr 28 01:16:11 PM PDT 24
Peak memory 206788 kb
Host smart-fb35798c-c8fb-4474-9533-9f1b0e36f445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133570422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3133570422
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.717765986
Short name T551
Test name
Test status
Simulation time 25210721 ps
CPU time 0.68 seconds
Started Apr 28 01:15:55 PM PDT 24
Finished Apr 28 01:16:34 PM PDT 24
Peak memory 205736 kb
Host smart-8c597a71-72eb-4107-af94-0596e36e8b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717765986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.717765986
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.932316120
Short name T487
Test name
Test status
Simulation time 29330685 ps
CPU time 0.76 seconds
Started Apr 28 01:15:49 PM PDT 24
Finished Apr 28 01:16:25 PM PDT 24
Peak memory 206660 kb
Host smart-394f24fe-b54f-4df3-83e3-ab059697fb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932316120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.932316120
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4074494354
Short name T196
Test name
Test status
Simulation time 1742120678 ps
CPU time 18.24 seconds
Started Apr 28 01:15:53 PM PDT 24
Finished Apr 28 01:16:49 PM PDT 24
Peak memory 221248 kb
Host smart-645070fa-4f81-4242-98b8-ab7f1c6a95ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074494354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4074494354
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.631627478
Short name T246
Test name
Test status
Simulation time 2809353021 ps
CPU time 10.44 seconds
Started Apr 28 01:15:50 PM PDT 24
Finished Apr 28 01:16:36 PM PDT 24
Peak memory 222516 kb
Host smart-6c904bda-9fd2-4819-abef-e41b1b748c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631627478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.631627478
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1540047024
Short name T632
Test name
Test status
Simulation time 277711012 ps
CPU time 4.84 seconds
Started Apr 28 01:15:54 PM PDT 24
Finished Apr 28 01:16:36 PM PDT 24
Peak memory 222836 kb
Host smart-65d5e998-5e25-4599-a116-e3402b4f195c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1540047024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1540047024
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2522934174
Short name T398
Test name
Test status
Simulation time 6924485580 ps
CPU time 11.52 seconds
Started Apr 28 01:15:47 PM PDT 24
Finished Apr 28 01:16:34 PM PDT 24
Peak memory 219744 kb
Host smart-836dc9a4-38bd-476c-bf64-a2e21bb47a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522934174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2522934174
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3083271422
Short name T661
Test name
Test status
Simulation time 664176122 ps
CPU time 4.59 seconds
Started Apr 28 01:15:50 PM PDT 24
Finished Apr 28 01:16:30 PM PDT 24
Peak memory 216260 kb
Host smart-f97077bd-945e-492e-87a8-9b859c9775f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083271422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3083271422
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2252331427
Short name T491
Test name
Test status
Simulation time 294850721 ps
CPU time 1.25 seconds
Started Apr 28 01:15:49 PM PDT 24
Finished Apr 28 01:16:25 PM PDT 24
Peak memory 216172 kb
Host smart-d91fe9ca-d24e-410c-8cb1-7ef8adc31e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252331427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2252331427
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2232156575
Short name T604
Test name
Test status
Simulation time 135188480 ps
CPU time 0.77 seconds
Started Apr 28 01:15:49 PM PDT 24
Finished Apr 28 01:16:24 PM PDT 24
Peak memory 205692 kb
Host smart-6f8d1129-2e28-4de7-9a55-b2da319944ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232156575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2232156575
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4209579154
Short name T537
Test name
Test status
Simulation time 13698838 ps
CPU time 0.73 seconds
Started Apr 28 01:16:01 PM PDT 24
Finished Apr 28 01:16:43 PM PDT 24
Peak memory 204812 kb
Host smart-599f673a-057e-41ab-9d67-bfaa901b0b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209579154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4209579154
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2641800263
Short name T87
Test name
Test status
Simulation time 49467800 ps
CPU time 2.72 seconds
Started Apr 28 01:16:01 PM PDT 24
Finished Apr 28 01:16:45 PM PDT 24
Peak memory 222528 kb
Host smart-c0fbc26c-fe1a-4541-abf4-11f9cf721666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641800263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2641800263
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2482598079
Short name T595
Test name
Test status
Simulation time 66360572 ps
CPU time 0.81 seconds
Started Apr 28 01:15:57 PM PDT 24
Finished Apr 28 01:16:37 PM PDT 24
Peak memory 206696 kb
Host smart-be425ee2-f7b9-462c-a960-80dcba220c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482598079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2482598079
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3308752902
Short name T159
Test name
Test status
Simulation time 18267185297 ps
CPU time 108.43 seconds
Started Apr 28 01:16:01 PM PDT 24
Finished Apr 28 01:18:31 PM PDT 24
Peak memory 236076 kb
Host smart-b2019aed-dbe0-410c-b400-b28ab971ab77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308752902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3308752902
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1523317494
Short name T292
Test name
Test status
Simulation time 5519693734 ps
CPU time 6.45 seconds
Started Apr 28 01:16:00 PM PDT 24
Finished Apr 28 01:16:48 PM PDT 24
Peak memory 223416 kb
Host smart-b66b7af2-665f-4a96-8d76-a996db8160bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523317494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1523317494
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3345795130
Short name T242
Test name
Test status
Simulation time 1390220038 ps
CPU time 5.1 seconds
Started Apr 28 01:15:54 PM PDT 24
Finished Apr 28 01:16:37 PM PDT 24
Peak memory 223092 kb
Host smart-04add23a-a2d6-42cb-b194-d25caf43d1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345795130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3345795130
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1666077104
Short name T241
Test name
Test status
Simulation time 3349689096 ps
CPU time 11.85 seconds
Started Apr 28 01:15:55 PM PDT 24
Finished Apr 28 01:16:45 PM PDT 24
Peak memory 227508 kb
Host smart-bf069262-c478-4a0f-8b9b-8b55c5d7617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666077104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1666077104
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.545642960
Short name T662
Test name
Test status
Simulation time 4289017210 ps
CPU time 10.82 seconds
Started Apr 28 01:16:00 PM PDT 24
Finished Apr 28 01:16:52 PM PDT 24
Peak memory 220976 kb
Host smart-0f3bd650-e443-4838-b7f4-5954125486b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=545642960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.545642960
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3250783253
Short name T50
Test name
Test status
Simulation time 17860145319 ps
CPU time 41.31 seconds
Started Apr 28 01:16:00 PM PDT 24
Finished Apr 28 01:17:22 PM PDT 24
Peak memory 215896 kb
Host smart-5aa684f6-37f1-455b-883d-6cd514ba490c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250783253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3250783253
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3290655723
Short name T518
Test name
Test status
Simulation time 4370031451 ps
CPU time 13.25 seconds
Started Apr 28 01:16:00 PM PDT 24
Finished Apr 28 01:16:54 PM PDT 24
Peak memory 215972 kb
Host smart-f20743c0-25c4-4776-bde1-c6b52d814880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290655723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3290655723
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.260818599
Short name T697
Test name
Test status
Simulation time 70300080 ps
CPU time 2.04 seconds
Started Apr 28 01:15:54 PM PDT 24
Finished Apr 28 01:16:33 PM PDT 24
Peak memory 216256 kb
Host smart-003a7f0c-5891-406e-8eb1-c96e192751cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260818599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.260818599
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.905745853
Short name T533
Test name
Test status
Simulation time 65567812 ps
CPU time 0.91 seconds
Started Apr 28 01:15:59 PM PDT 24
Finished Apr 28 01:16:42 PM PDT 24
Peak memory 206724 kb
Host smart-2dcd380c-acc9-4e3b-b119-41843105522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905745853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.905745853
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.138407914
Short name T183
Test name
Test status
Simulation time 92471752 ps
CPU time 2.21 seconds
Started Apr 28 01:16:02 PM PDT 24
Finished Apr 28 01:16:47 PM PDT 24
Peak memory 218552 kb
Host smart-ac3af9b2-852f-4c1f-8bfe-f70e10507197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138407914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.138407914
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1791871030
Short name T420
Test name
Test status
Simulation time 51552551 ps
CPU time 0.74 seconds
Started Apr 28 01:16:16 PM PDT 24
Finished Apr 28 01:17:00 PM PDT 24
Peak memory 205424 kb
Host smart-84c69b24-b1dd-4704-af2a-8767479711b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791871030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1791871030
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3747719509
Short name T608
Test name
Test status
Simulation time 42426100 ps
CPU time 0.75 seconds
Started Apr 28 01:16:02 PM PDT 24
Finished Apr 28 01:16:45 PM PDT 24
Peak memory 206664 kb
Host smart-c86ef701-d9f6-4637-8d30-01ac35cb4d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747719509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3747719509
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3564062635
Short name T311
Test name
Test status
Simulation time 305803416 ps
CPU time 13.2 seconds
Started Apr 28 01:16:08 PM PDT 24
Finished Apr 28 01:17:04 PM PDT 24
Peak memory 249072 kb
Host smart-7834674a-a177-446d-b66a-d983d950c246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564062635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3564062635
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2453186753
Short name T291
Test name
Test status
Simulation time 9445687897 ps
CPU time 43.16 seconds
Started Apr 28 01:16:09 PM PDT 24
Finished Apr 28 01:17:35 PM PDT 24
Peak memory 232884 kb
Host smart-8b1adccd-99e4-4b8b-84d9-e6f7476e64e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453186753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2453186753
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3848485907
Short name T248
Test name
Test status
Simulation time 3961773364 ps
CPU time 49.09 seconds
Started Apr 28 01:16:10 PM PDT 24
Finished Apr 28 01:17:42 PM PDT 24
Peak memory 232416 kb
Host smart-5b3dfb64-d4eb-459a-a259-5de14e1a8d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848485907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3848485907
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2420003411
Short name T382
Test name
Test status
Simulation time 8615632895 ps
CPU time 23.73 seconds
Started Apr 28 01:16:09 PM PDT 24
Finished Apr 28 01:17:16 PM PDT 24
Peak memory 224312 kb
Host smart-6a34f7c8-553e-4fdf-b839-86e4ae6fb723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420003411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2420003411
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.897695021
Short name T680
Test name
Test status
Simulation time 6332721133 ps
CPU time 13.87 seconds
Started Apr 28 01:16:08 PM PDT 24
Finished Apr 28 01:17:05 PM PDT 24
Peak memory 222956 kb
Host smart-a874c7d6-143a-4b0f-9b4f-4a4fd47f8207
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=897695021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.897695021
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.118748661
Short name T392
Test name
Test status
Simulation time 5547239847 ps
CPU time 41.57 seconds
Started Apr 28 01:16:03 PM PDT 24
Finished Apr 28 01:17:27 PM PDT 24
Peak memory 216368 kb
Host smart-7bc4f53b-1a02-4f03-8f3c-a0550f3eda1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118748661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.118748661
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.694409146
Short name T482
Test name
Test status
Simulation time 1687696301 ps
CPU time 6.74 seconds
Started Apr 28 01:16:01 PM PDT 24
Finished Apr 28 01:16:49 PM PDT 24
Peak memory 216192 kb
Host smart-a7c95bc5-1a78-46ef-8bbc-a3c35ca9f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694409146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.694409146
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.734947167
Short name T13
Test name
Test status
Simulation time 204676991 ps
CPU time 1.89 seconds
Started Apr 28 01:16:01 PM PDT 24
Finished Apr 28 01:16:44 PM PDT 24
Peak memory 216252 kb
Host smart-d1fff7da-1f38-425a-9132-009d34cfc609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734947167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.734947167
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4203434849
Short name T441
Test name
Test status
Simulation time 174843997 ps
CPU time 0.8 seconds
Started Apr 28 01:16:00 PM PDT 24
Finished Apr 28 01:16:43 PM PDT 24
Peak memory 205716 kb
Host smart-5479b3f9-ea7a-4d0a-aa19-583ccaba9fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203434849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4203434849
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.716959567
Short name T383
Test name
Test status
Simulation time 4404443295 ps
CPU time 3.14 seconds
Started Apr 28 01:16:09 PM PDT 24
Finished Apr 28 01:16:56 PM PDT 24
Peak memory 218708 kb
Host smart-ec21acb7-f9da-4034-b582-362d4845d5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716959567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.716959567
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1113576367
Short name T515
Test name
Test status
Simulation time 38237831 ps
CPU time 0.7 seconds
Started Apr 28 01:12:51 PM PDT 24
Finished Apr 28 01:12:52 PM PDT 24
Peak memory 205756 kb
Host smart-7bde2e01-d51c-4864-b5ca-bad65f9300b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113576367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
113576367
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2257184062
Short name T475
Test name
Test status
Simulation time 16704958 ps
CPU time 0.77 seconds
Started Apr 28 01:12:42 PM PDT 24
Finished Apr 28 01:12:44 PM PDT 24
Peak memory 206668 kb
Host smart-029b063b-23aa-4109-add4-4d6c023c3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257184062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2257184062
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1494796471
Short name T323
Test name
Test status
Simulation time 191989347 ps
CPU time 11.73 seconds
Started Apr 28 01:12:41 PM PDT 24
Finished Apr 28 01:12:54 PM PDT 24
Peak memory 240912 kb
Host smart-b968f3af-9882-42bb-9090-fce8a3a4594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494796471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1494796471
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1553884955
Short name T42
Test name
Test status
Simulation time 594865315 ps
CPU time 3.84 seconds
Started Apr 28 01:12:41 PM PDT 24
Finished Apr 28 01:12:46 PM PDT 24
Peak memory 222944 kb
Host smart-c080bb00-097f-4cd8-a4ba-a6cf4e3dbf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553884955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1553884955
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2226562788
Short name T380
Test name
Test status
Simulation time 7024156702 ps
CPU time 6.72 seconds
Started Apr 28 01:12:41 PM PDT 24
Finished Apr 28 01:12:48 PM PDT 24
Peak memory 218964 kb
Host smart-87f5d3ba-483d-4029-91dc-425066e63124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226562788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2226562788
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1687509318
Short name T568
Test name
Test status
Simulation time 119702909 ps
CPU time 4.4 seconds
Started Apr 28 01:12:43 PM PDT 24
Finished Apr 28 01:12:48 PM PDT 24
Peak memory 222420 kb
Host smart-28ce7957-04f1-41e6-b097-860efe48cd8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1687509318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1687509318
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1870990218
Short name T47
Test name
Test status
Simulation time 119053713 ps
CPU time 1.02 seconds
Started Apr 28 01:12:44 PM PDT 24
Finished Apr 28 01:12:46 PM PDT 24
Peak memory 235032 kb
Host smart-e19743ee-fb90-4f51-849d-d99d4710c357
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870990218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1870990218
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2540492961
Short name T410
Test name
Test status
Simulation time 5699936819 ps
CPU time 9.28 seconds
Started Apr 28 01:12:43 PM PDT 24
Finished Apr 28 01:12:53 PM PDT 24
Peak memory 216304 kb
Host smart-8ce56fff-8b44-4cc5-ae8b-7b0616017fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540492961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2540492961
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4238360001
Short name T486
Test name
Test status
Simulation time 11945155675 ps
CPU time 31.74 seconds
Started Apr 28 01:12:46 PM PDT 24
Finished Apr 28 01:13:18 PM PDT 24
Peak memory 216388 kb
Host smart-110d11fe-7e06-40ac-83e9-74e702a886a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238360001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4238360001
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.921193780
Short name T510
Test name
Test status
Simulation time 113725343 ps
CPU time 1.83 seconds
Started Apr 28 01:12:41 PM PDT 24
Finished Apr 28 01:12:43 PM PDT 24
Peak memory 216228 kb
Host smart-56f75c2a-6fd1-482c-95a1-64242934ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921193780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.921193780
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4136630457
Short name T478
Test name
Test status
Simulation time 150089209 ps
CPU time 1.05 seconds
Started Apr 28 01:12:39 PM PDT 24
Finished Apr 28 01:12:41 PM PDT 24
Peak memory 206792 kb
Host smart-72cd59db-2a58-4a41-9a05-cc009f00133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136630457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4136630457
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.199058794
Short name T490
Test name
Test status
Simulation time 36944832 ps
CPU time 0.7 seconds
Started Apr 28 01:16:26 PM PDT 24
Finished Apr 28 01:17:13 PM PDT 24
Peak memory 205396 kb
Host smart-889f2250-ab9c-41e7-8e78-8ca35ed7c6d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199058794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.199058794
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1575959150
Short name T567
Test name
Test status
Simulation time 22547460 ps
CPU time 0.72 seconds
Started Apr 28 01:16:14 PM PDT 24
Finished Apr 28 01:16:58 PM PDT 24
Peak memory 207032 kb
Host smart-eb48ac64-1840-4728-b837-fcb2eed69d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575959150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1575959150
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1067738738
Short name T108
Test name
Test status
Simulation time 9582621102 ps
CPU time 19.02 seconds
Started Apr 28 01:16:21 PM PDT 24
Finished Apr 28 01:17:25 PM PDT 24
Peak memory 249768 kb
Host smart-d2a6a216-0464-4823-a35d-4fff4e515375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067738738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1067738738
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3175142146
Short name T677
Test name
Test status
Simulation time 164124450 ps
CPU time 4 seconds
Started Apr 28 01:16:20 PM PDT 24
Finished Apr 28 01:17:08 PM PDT 24
Peak memory 222232 kb
Host smart-deb39dfb-e66b-45e9-bfe6-a3dd72cf8977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175142146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3175142146
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1046979908
Short name T217
Test name
Test status
Simulation time 1299259249 ps
CPU time 3.39 seconds
Started Apr 28 01:16:14 PM PDT 24
Finished Apr 28 01:17:00 PM PDT 24
Peak memory 223648 kb
Host smart-77b1445a-8808-47d5-8329-e73cc65affe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046979908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1046979908
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.611043870
Short name T556
Test name
Test status
Simulation time 8429309262 ps
CPU time 8.32 seconds
Started Apr 28 01:16:20 PM PDT 24
Finished Apr 28 01:17:12 PM PDT 24
Peak memory 223084 kb
Host smart-6280cb89-ef92-464e-9cae-c639a62a197b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611043870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.611043870
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.329040521
Short name T399
Test name
Test status
Simulation time 16929875075 ps
CPU time 29.3 seconds
Started Apr 28 01:16:15 PM PDT 24
Finished Apr 28 01:17:27 PM PDT 24
Peak memory 216364 kb
Host smart-b6403c60-46cb-431a-92d8-363cbfbf6f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329040521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.329040521
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3286262798
Short name T584
Test name
Test status
Simulation time 974853769 ps
CPU time 5.63 seconds
Started Apr 28 01:16:15 PM PDT 24
Finished Apr 28 01:17:03 PM PDT 24
Peak memory 216192 kb
Host smart-359614f9-ff45-42eb-9c32-2bb40e46ab35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286262798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3286262798
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3845273203
Short name T448
Test name
Test status
Simulation time 133256486 ps
CPU time 1.85 seconds
Started Apr 28 01:16:13 PM PDT 24
Finished Apr 28 01:16:58 PM PDT 24
Peak memory 216292 kb
Host smart-89f145cf-e232-4751-8efa-3836045ea63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845273203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3845273203
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.141878172
Short name T468
Test name
Test status
Simulation time 46838880 ps
CPU time 0.85 seconds
Started Apr 28 01:16:16 PM PDT 24
Finished Apr 28 01:17:00 PM PDT 24
Peak memory 205712 kb
Host smart-342b3fc6-56e1-464e-8dd7-57b5a4cadf50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141878172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.141878172
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3147973511
Short name T429
Test name
Test status
Simulation time 36161588 ps
CPU time 0.71 seconds
Started Apr 28 01:16:41 PM PDT 24
Finished Apr 28 01:17:27 PM PDT 24
Peak memory 205364 kb
Host smart-e099cd7a-bc9e-47f3-bb4e-154be38ffe60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147973511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3147973511
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2559240162
Short name T598
Test name
Test status
Simulation time 48289209 ps
CPU time 0.74 seconds
Started Apr 28 01:16:26 PM PDT 24
Finished Apr 28 01:17:13 PM PDT 24
Peak memory 206692 kb
Host smart-1aa1196e-f40c-4285-a3b8-40b13e9f7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559240162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2559240162
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.25507850
Short name T322
Test name
Test status
Simulation time 4144243814 ps
CPU time 25.05 seconds
Started Apr 28 01:16:33 PM PDT 24
Finished Apr 28 01:17:44 PM PDT 24
Peak memory 224528 kb
Host smart-0d69eb42-0e8a-460c-b045-31900862a86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25507850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.25507850
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4168012922
Short name T117
Test name
Test status
Simulation time 1386256481 ps
CPU time 4.12 seconds
Started Apr 28 01:16:37 PM PDT 24
Finished Apr 28 01:17:27 PM PDT 24
Peak memory 220036 kb
Host smart-bc7c8f8f-42d8-4f3e-868e-147f0901c85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168012922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4168012922
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.35030886
Short name T209
Test name
Test status
Simulation time 7061078900 ps
CPU time 7.84 seconds
Started Apr 28 01:16:30 PM PDT 24
Finished Apr 28 01:17:25 PM PDT 24
Peak memory 219272 kb
Host smart-335771c2-2cd6-447d-beb6-276f2cc0d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35030886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.35030886
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3028397681
Short name T652
Test name
Test status
Simulation time 3502274121 ps
CPU time 7.37 seconds
Started Apr 28 01:16:31 PM PDT 24
Finished Apr 28 01:17:25 PM PDT 24
Peak memory 222272 kb
Host smart-97169e82-3484-4ab4-a06c-c9b478cf77a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3028397681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3028397681
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.147489673
Short name T405
Test name
Test status
Simulation time 393208561 ps
CPU time 6.39 seconds
Started Apr 28 01:16:32 PM PDT 24
Finished Apr 28 01:17:24 PM PDT 24
Peak memory 216380 kb
Host smart-c9bf5d39-b03a-4dcf-a1b1-7cb6d3406611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147489673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.147489673
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2668547460
Short name T458
Test name
Test status
Simulation time 3706778870 ps
CPU time 9.89 seconds
Started Apr 28 01:16:25 PM PDT 24
Finished Apr 28 01:17:22 PM PDT 24
Peak memory 216392 kb
Host smart-6da1f57b-ca82-437b-b776-4553a63e6c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668547460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2668547460
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.671370050
Short name T476
Test name
Test status
Simulation time 35915716 ps
CPU time 1.22 seconds
Started Apr 28 01:16:29 PM PDT 24
Finished Apr 28 01:17:18 PM PDT 24
Peak memory 208008 kb
Host smart-efd5a08a-5edf-498d-bbe8-b1d2cd62d977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671370050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.671370050
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.436585864
Short name T715
Test name
Test status
Simulation time 107526381 ps
CPU time 1.02 seconds
Started Apr 28 01:16:30 PM PDT 24
Finished Apr 28 01:17:18 PM PDT 24
Peak memory 206768 kb
Host smart-9cb8c4d8-be4d-4326-8883-105515bac058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436585864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.436585864
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4028347596
Short name T437
Test name
Test status
Simulation time 48709321 ps
CPU time 0.69 seconds
Started Apr 28 01:16:48 PM PDT 24
Finished Apr 28 01:17:36 PM PDT 24
Peak memory 205636 kb
Host smart-d8384855-57f4-4adb-9d86-45bdcf536c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028347596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4028347596
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2618834791
Short name T204
Test name
Test status
Simulation time 3083964115 ps
CPU time 5.73 seconds
Started Apr 28 01:16:41 PM PDT 24
Finished Apr 28 01:17:32 PM PDT 24
Peak memory 218528 kb
Host smart-6a254edf-5ff9-4867-9253-a20811b6eb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618834791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2618834791
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2657638453
Short name T474
Test name
Test status
Simulation time 20179489 ps
CPU time 0.72 seconds
Started Apr 28 01:16:36 PM PDT 24
Finished Apr 28 01:17:23 PM PDT 24
Peak memory 206968 kb
Host smart-67fd084e-5d29-4b42-9a00-912483cf7ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657638453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2657638453
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.820749493
Short name T5
Test name
Test status
Simulation time 8586038127 ps
CPU time 99.08 seconds
Started Apr 28 01:16:40 PM PDT 24
Finished Apr 28 01:19:05 PM PDT 24
Peak memory 249592 kb
Host smart-f00ddd03-24ae-4215-8583-7f8c11ed25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820749493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.820749493
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3418144911
Short name T257
Test name
Test status
Simulation time 361116188 ps
CPU time 5.2 seconds
Started Apr 28 01:16:35 PM PDT 24
Finished Apr 28 01:17:27 PM PDT 24
Peak memory 222528 kb
Host smart-1478fce9-01a2-453a-ac58-55ae659c51d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418144911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3418144911
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1830239018
Short name T343
Test name
Test status
Simulation time 4588769048 ps
CPU time 18.55 seconds
Started Apr 28 01:16:40 PM PDT 24
Finished Apr 28 01:17:44 PM PDT 24
Peak memory 223564 kb
Host smart-cc2e788f-5008-42db-8838-ccfa3bd1bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830239018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1830239018
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2032448325
Short name T295
Test name
Test status
Simulation time 283298984 ps
CPU time 4.49 seconds
Started Apr 28 01:16:41 PM PDT 24
Finished Apr 28 01:17:31 PM PDT 24
Peak memory 220268 kb
Host smart-430bc04e-da16-4cd5-bd88-70d8c9b60cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032448325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2032448325
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.604428487
Short name T581
Test name
Test status
Simulation time 1111137759 ps
CPU time 5.15 seconds
Started Apr 28 01:16:40 PM PDT 24
Finished Apr 28 01:17:31 PM PDT 24
Peak memory 219012 kb
Host smart-3087f6e4-63cc-4cd5-b58a-5bfec0b3af7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=604428487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.604428487
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4062754079
Short name T402
Test name
Test status
Simulation time 34480650034 ps
CPU time 25.05 seconds
Started Apr 28 01:16:35 PM PDT 24
Finished Apr 28 01:17:47 PM PDT 24
Peak memory 216436 kb
Host smart-988d77c3-6aae-4a25-9aad-55a575b80ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062754079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4062754079
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1971922759
Short name T503
Test name
Test status
Simulation time 1122224782 ps
CPU time 5.92 seconds
Started Apr 28 01:16:37 PM PDT 24
Finished Apr 28 01:17:29 PM PDT 24
Peak memory 216292 kb
Host smart-5654ba3e-74cf-484a-9793-fe15116882d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971922759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1971922759
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.949505691
Short name T616
Test name
Test status
Simulation time 152352337 ps
CPU time 2.07 seconds
Started Apr 28 01:16:35 PM PDT 24
Finished Apr 28 01:17:24 PM PDT 24
Peak memory 216256 kb
Host smart-27371ba9-6b4d-4add-a1ff-53035ff0a78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949505691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.949505691
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.901239479
Short name T509
Test name
Test status
Simulation time 88083955 ps
CPU time 0.8 seconds
Started Apr 28 01:16:38 PM PDT 24
Finished Apr 28 01:17:25 PM PDT 24
Peak memory 205736 kb
Host smart-ae92ab82-93ac-4fb4-ad06-8d71e788c1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901239479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.901239479
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1941786680
Short name T582
Test name
Test status
Simulation time 19088247 ps
CPU time 0.66 seconds
Started Apr 28 01:16:52 PM PDT 24
Finished Apr 28 01:17:40 PM PDT 24
Peak memory 204828 kb
Host smart-92fe9711-7ea6-4452-9dd2-4069309024a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941786680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1941786680
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2558795155
Short name T57
Test name
Test status
Simulation time 56525254 ps
CPU time 0.75 seconds
Started Apr 28 01:16:47 PM PDT 24
Finished Apr 28 01:17:34 PM PDT 24
Peak memory 206644 kb
Host smart-4f3a914a-80f8-4977-930d-be5bcce4dbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558795155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2558795155
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3939108498
Short name T301
Test name
Test status
Simulation time 46730699504 ps
CPU time 127.51 seconds
Started Apr 28 01:16:52 PM PDT 24
Finished Apr 28 01:19:47 PM PDT 24
Peak memory 249116 kb
Host smart-24f33828-5ba3-4a9c-8181-5d0250cc419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939108498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3939108498
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1556272019
Short name T190
Test name
Test status
Simulation time 10837657146 ps
CPU time 10.58 seconds
Started Apr 28 01:16:47 PM PDT 24
Finished Apr 28 01:17:44 PM PDT 24
Peak memory 222592 kb
Host smart-cdb5bef5-b677-41d3-8adb-ea7ce6ec93b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556272019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1556272019
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1427230894
Short name T530
Test name
Test status
Simulation time 1361067751 ps
CPU time 12.28 seconds
Started Apr 28 01:16:52 PM PDT 24
Finished Apr 28 01:17:52 PM PDT 24
Peak memory 222896 kb
Host smart-20ce99f0-79b8-4c78-a51b-1904c1b7ce74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1427230894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1427230894
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.251244973
Short name T408
Test name
Test status
Simulation time 26861918498 ps
CPU time 45.67 seconds
Started Apr 28 01:16:47 PM PDT 24
Finished Apr 28 01:18:20 PM PDT 24
Peak memory 216328 kb
Host smart-1fecb028-bdfb-46d7-b6ea-f449a3935d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251244973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.251244973
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3300172229
Short name T531
Test name
Test status
Simulation time 3636402004 ps
CPU time 12.43 seconds
Started Apr 28 01:16:47 PM PDT 24
Finished Apr 28 01:17:46 PM PDT 24
Peak memory 216408 kb
Host smart-56faf87d-8318-48f4-b23a-f51b74aea77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300172229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3300172229
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1185168567
Short name T526
Test name
Test status
Simulation time 58809445 ps
CPU time 0.74 seconds
Started Apr 28 01:16:48 PM PDT 24
Finished Apr 28 01:17:35 PM PDT 24
Peak memory 205820 kb
Host smart-38553508-c262-4c95-8129-d6f0f96b6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185168567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1185168567
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2868856170
Short name T643
Test name
Test status
Simulation time 1146479842 ps
CPU time 4.22 seconds
Started Apr 28 01:16:54 PM PDT 24
Finished Apr 28 01:17:45 PM PDT 24
Peak memory 223360 kb
Host smart-70017bd5-640a-4549-a466-634361398309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868856170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2868856170
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4181711671
Short name T445
Test name
Test status
Simulation time 14284979 ps
CPU time 0.78 seconds
Started Apr 28 01:17:03 PM PDT 24
Finished Apr 28 01:17:50 PM PDT 24
Peak memory 205268 kb
Host smart-821d36d2-dd1d-4b63-9894-bde942738b48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181711671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4181711671
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3223629066
Short name T558
Test name
Test status
Simulation time 55664676 ps
CPU time 0.71 seconds
Started Apr 28 01:16:52 PM PDT 24
Finished Apr 28 01:17:40 PM PDT 24
Peak memory 205872 kb
Host smart-5e671799-5f14-41c5-9ef2-ce36f89ad058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223629066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3223629066
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2573728636
Short name T109
Test name
Test status
Simulation time 60793964430 ps
CPU time 98.15 seconds
Started Apr 28 01:17:02 PM PDT 24
Finished Apr 28 01:19:26 PM PDT 24
Peak memory 252228 kb
Host smart-dcefe9ef-4fc5-43fc-80eb-e73cf3f3696e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573728636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2573728636
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2241065701
Short name T119
Test name
Test status
Simulation time 73849172 ps
CPU time 2.74 seconds
Started Apr 28 01:16:58 PM PDT 24
Finished Apr 28 01:17:47 PM PDT 24
Peak memory 222720 kb
Host smart-b34d5ed7-afc9-44af-a305-69c0afd97ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241065701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2241065701
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3428651043
Short name T349
Test name
Test status
Simulation time 21359391686 ps
CPU time 21.09 seconds
Started Apr 28 01:16:59 PM PDT 24
Finished Apr 28 01:18:06 PM PDT 24
Peak memory 234320 kb
Host smart-83c4ade5-6e63-4bc8-8bc0-07172cb0cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428651043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3428651043
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2221268629
Short name T562
Test name
Test status
Simulation time 2265683443 ps
CPU time 6.32 seconds
Started Apr 28 01:17:05 PM PDT 24
Finished Apr 28 01:17:57 PM PDT 24
Peak memory 220148 kb
Host smart-ff3ca007-5126-4418-94d7-780f8b0ca6a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2221268629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2221268629
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.503680164
Short name T31
Test name
Test status
Simulation time 44551897 ps
CPU time 1.02 seconds
Started Apr 28 01:17:03 PM PDT 24
Finished Apr 28 01:17:51 PM PDT 24
Peak memory 207292 kb
Host smart-c6a3ecfe-f793-4855-b5dd-a6bc85c7d6e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503680164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.503680164
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3250779453
Short name T513
Test name
Test status
Simulation time 6967393400 ps
CPU time 18.49 seconds
Started Apr 28 01:16:54 PM PDT 24
Finished Apr 28 01:17:59 PM PDT 24
Peak memory 216260 kb
Host smart-beafe8c9-ac6a-49de-8a62-9abf79fc7851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250779453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3250779453
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3430736641
Short name T617
Test name
Test status
Simulation time 197813309 ps
CPU time 2.88 seconds
Started Apr 28 01:17:00 PM PDT 24
Finished Apr 28 01:17:49 PM PDT 24
Peak memory 216120 kb
Host smart-dd4432b4-da15-4ca4-bab0-76d798272d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430736641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3430736641
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1509237942
Short name T545
Test name
Test status
Simulation time 28863623 ps
CPU time 0.76 seconds
Started Apr 28 01:16:59 PM PDT 24
Finished Apr 28 01:17:46 PM PDT 24
Peak memory 205744 kb
Host smart-b2363210-bc08-4c7b-9310-07325f0e08ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509237942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1509237942
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2318324682
Short name T586
Test name
Test status
Simulation time 14160036 ps
CPU time 0.69 seconds
Started Apr 28 01:17:16 PM PDT 24
Finished Apr 28 01:17:59 PM PDT 24
Peak memory 205316 kb
Host smart-3ef9eafd-dc8a-4e6c-a49f-f535633c51f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318324682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2318324682
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1786125397
Short name T642
Test name
Test status
Simulation time 16299228 ps
CPU time 0.75 seconds
Started Apr 28 01:17:04 PM PDT 24
Finished Apr 28 01:17:51 PM PDT 24
Peak memory 206584 kb
Host smart-c0994356-a574-454e-bc01-4e2b4507a090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786125397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1786125397
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3797211713
Short name T317
Test name
Test status
Simulation time 2124958877 ps
CPU time 35.5 seconds
Started Apr 28 01:17:10 PM PDT 24
Finished Apr 28 01:18:29 PM PDT 24
Peak memory 240852 kb
Host smart-3f4118f2-3ea1-4394-bfbc-846f62dd471e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797211713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3797211713
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1309300709
Short name T181
Test name
Test status
Simulation time 1287874860 ps
CPU time 4.75 seconds
Started Apr 28 01:17:10 PM PDT 24
Finished Apr 28 01:17:58 PM PDT 24
Peak memory 218696 kb
Host smart-cca8f436-6d9c-4ba1-90b8-3b0a461cb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309300709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1309300709
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.937808379
Short name T173
Test name
Test status
Simulation time 438587561 ps
CPU time 3.44 seconds
Started Apr 28 01:17:09 PM PDT 24
Finished Apr 28 01:17:56 PM PDT 24
Peak memory 219220 kb
Host smart-d1e54044-6d4b-4ecc-8e9a-1843c495d472
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937808379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.937808379
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.493876134
Short name T369
Test name
Test status
Simulation time 394335802 ps
CPU time 0.96 seconds
Started Apr 28 01:17:15 PM PDT 24
Finished Apr 28 01:17:58 PM PDT 24
Peak memory 206632 kb
Host smart-aa1c2223-4ad2-4819-beef-0f955c35335b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493876134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.493876134
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3935427252
Short name T105
Test name
Test status
Simulation time 5305211562 ps
CPU time 19.46 seconds
Started Apr 28 01:17:06 PM PDT 24
Finished Apr 28 01:18:10 PM PDT 24
Peak memory 216272 kb
Host smart-31445cdb-68cd-44eb-b202-4a0b036df6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935427252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3935427252
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4293748653
Short name T504
Test name
Test status
Simulation time 32646314 ps
CPU time 1.07 seconds
Started Apr 28 01:17:04 PM PDT 24
Finished Apr 28 01:17:51 PM PDT 24
Peak memory 207756 kb
Host smart-837af2ed-ec0f-4498-a7d2-404e132d324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293748653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4293748653
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1372655862
Short name T585
Test name
Test status
Simulation time 144303930 ps
CPU time 0.77 seconds
Started Apr 28 01:17:05 PM PDT 24
Finished Apr 28 01:17:51 PM PDT 24
Peak memory 205748 kb
Host smart-d07b9d47-77ae-45fa-9d15-51720b68c8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372655862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1372655862
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.868197624
Short name T294
Test name
Test status
Simulation time 825174282 ps
CPU time 3.23 seconds
Started Apr 28 01:17:09 PM PDT 24
Finished Apr 28 01:17:56 PM PDT 24
Peak memory 218824 kb
Host smart-da136ff7-0bea-4f98-a7eb-f580126cd684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868197624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.868197624
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.331675608
Short name T573
Test name
Test status
Simulation time 13369960 ps
CPU time 0.7 seconds
Started Apr 28 01:17:22 PM PDT 24
Finished Apr 28 01:18:06 PM PDT 24
Peak memory 205368 kb
Host smart-b839ca25-0d65-4f93-b072-8b312bd9d948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331675608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.331675608
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3228775840
Short name T684
Test name
Test status
Simulation time 14030877 ps
CPU time 0.75 seconds
Started Apr 28 01:17:14 PM PDT 24
Finished Apr 28 01:17:57 PM PDT 24
Peak memory 206916 kb
Host smart-54f07085-f840-45f4-97a9-ba3711015c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228775840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3228775840
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.845370217
Short name T160
Test name
Test status
Simulation time 18958927252 ps
CPU time 115.58 seconds
Started Apr 28 01:17:22 PM PDT 24
Finished Apr 28 01:20:01 PM PDT 24
Peak memory 238876 kb
Host smart-23103ae7-8084-4665-97ab-0ee885f6589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845370217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.845370217
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1405936314
Short name T227
Test name
Test status
Simulation time 202792645 ps
CPU time 2.99 seconds
Started Apr 28 01:17:23 PM PDT 24
Finished Apr 28 01:18:09 PM PDT 24
Peak memory 222320 kb
Host smart-2ae1a699-2af1-43ae-8647-d06c3ecf9724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405936314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1405936314
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1058372244
Short name T576
Test name
Test status
Simulation time 1860071418 ps
CPU time 10.73 seconds
Started Apr 28 01:17:22 PM PDT 24
Finished Apr 28 01:18:16 PM PDT 24
Peak memory 220056 kb
Host smart-df860729-6f4a-49fb-a1e2-27f154a00649
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1058372244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1058372244
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1875265394
Short name T409
Test name
Test status
Simulation time 6883230871 ps
CPU time 33.11 seconds
Started Apr 28 01:17:17 PM PDT 24
Finished Apr 28 01:18:31 PM PDT 24
Peak memory 216364 kb
Host smart-57151619-a7fb-4687-b994-dc835c28a276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875265394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1875265394
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2729569638
Short name T49
Test name
Test status
Simulation time 1089417535 ps
CPU time 4.2 seconds
Started Apr 28 01:17:15 PM PDT 24
Finished Apr 28 01:18:01 PM PDT 24
Peak memory 216136 kb
Host smart-e60dd130-386d-42d2-9077-7de68e05e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729569638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2729569638
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1348714407
Short name T702
Test name
Test status
Simulation time 587707315 ps
CPU time 2.86 seconds
Started Apr 28 01:17:15 PM PDT 24
Finished Apr 28 01:18:00 PM PDT 24
Peak memory 216320 kb
Host smart-0538413a-5bfb-4982-a5b7-537f2b7dcba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348714407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1348714407
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4188164124
Short name T493
Test name
Test status
Simulation time 197065459 ps
CPU time 1.02 seconds
Started Apr 28 01:17:15 PM PDT 24
Finished Apr 28 01:17:58 PM PDT 24
Peak memory 206840 kb
Host smart-00ff2abe-09bc-44fc-b924-d5a6d63103d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188164124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4188164124
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2712900291
Short name T224
Test name
Test status
Simulation time 3583533587 ps
CPU time 2.33 seconds
Started Apr 28 01:17:21 PM PDT 24
Finished Apr 28 01:18:07 PM PDT 24
Peak memory 216436 kb
Host smart-035a3760-7ff8-4cb7-bff7-5710378da41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712900291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2712900291
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2417770806
Short name T520
Test name
Test status
Simulation time 38788133 ps
CPU time 0.72 seconds
Started Apr 28 01:17:40 PM PDT 24
Finished Apr 28 01:18:24 PM PDT 24
Peak memory 205708 kb
Host smart-aeb6c17d-9e42-43f5-9f8c-877ce6f458c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417770806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2417770806
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3852864125
Short name T439
Test name
Test status
Simulation time 18232448 ps
CPU time 0.72 seconds
Started Apr 28 01:17:26 PM PDT 24
Finished Apr 28 01:18:09 PM PDT 24
Peak memory 205968 kb
Host smart-74570c55-7bf4-42a0-bce4-d27bd7c27679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852864125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3852864125
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3132546470
Short name T320
Test name
Test status
Simulation time 5474990852 ps
CPU time 41.08 seconds
Started Apr 28 01:17:31 PM PDT 24
Finished Apr 28 01:18:56 PM PDT 24
Peak memory 253924 kb
Host smart-30c9bab7-aa43-465e-9774-e5d670172310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132546470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3132546470
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2409573228
Short name T272
Test name
Test status
Simulation time 267309860 ps
CPU time 2.71 seconds
Started Apr 28 01:17:32 PM PDT 24
Finished Apr 28 01:18:20 PM PDT 24
Peak memory 222872 kb
Host smart-9f1da2d1-c4ff-462e-9314-7596d5875da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409573228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2409573228
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3717320549
Short name T56
Test name
Test status
Simulation time 3475290654 ps
CPU time 18.55 seconds
Started Apr 28 01:17:32 PM PDT 24
Finished Apr 28 01:18:35 PM PDT 24
Peak memory 247072 kb
Host smart-1563725d-9466-4f92-92f2-dd37bfba2e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717320549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3717320549
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1861569848
Short name T302
Test name
Test status
Simulation time 500226820 ps
CPU time 5.19 seconds
Started Apr 28 01:17:25 PM PDT 24
Finished Apr 28 01:18:13 PM PDT 24
Peak memory 219516 kb
Host smart-3727902c-30a1-4c05-a994-e0839add8852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861569848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1861569848
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.449327441
Short name T663
Test name
Test status
Simulation time 1022962893 ps
CPU time 6.16 seconds
Started Apr 28 01:17:32 PM PDT 24
Finished Apr 28 01:18:23 PM PDT 24
Peak memory 222608 kb
Host smart-990e74f7-af96-4053-8910-8c413e174f43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=449327441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.449327441
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2814154917
Short name T566
Test name
Test status
Simulation time 1728815199 ps
CPU time 8.96 seconds
Started Apr 28 01:17:27 PM PDT 24
Finished Apr 28 01:18:18 PM PDT 24
Peak memory 216420 kb
Host smart-c45bfa5b-10c7-425e-8689-078c170f31d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814154917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2814154917
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.955689562
Short name T540
Test name
Test status
Simulation time 1799733539 ps
CPU time 5.78 seconds
Started Apr 28 01:17:27 PM PDT 24
Finished Apr 28 01:18:15 PM PDT 24
Peak memory 216272 kb
Host smart-bbeb3d21-24bd-4971-a50e-ee0b03a79a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955689562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.955689562
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1945257691
Short name T578
Test name
Test status
Simulation time 82180991 ps
CPU time 1.26 seconds
Started Apr 28 01:17:25 PM PDT 24
Finished Apr 28 01:18:09 PM PDT 24
Peak memory 216196 kb
Host smart-4eb121db-1247-4163-81b9-9cd8c167abc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945257691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1945257691
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2727601586
Short name T53
Test name
Test status
Simulation time 560268832 ps
CPU time 1.14 seconds
Started Apr 28 01:17:28 PM PDT 24
Finished Apr 28 01:18:12 PM PDT 24
Peak memory 206840 kb
Host smart-d35aca8a-1c80-478e-8323-e489fd3640bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727601586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2727601586
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.689005216
Short name T422
Test name
Test status
Simulation time 35993717 ps
CPU time 0.73 seconds
Started Apr 28 01:17:53 PM PDT 24
Finished Apr 28 01:18:33 PM PDT 24
Peak memory 204864 kb
Host smart-760be774-3fff-4124-829a-7d31898d6a3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689005216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.689005216
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3321189773
Short name T483
Test name
Test status
Simulation time 18331337 ps
CPU time 0.77 seconds
Started Apr 28 01:17:37 PM PDT 24
Finished Apr 28 01:18:22 PM PDT 24
Peak memory 206604 kb
Host smart-ebfd7236-c922-4568-a058-98fe8537e1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321189773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3321189773
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1981713665
Short name T470
Test name
Test status
Simulation time 591770217 ps
CPU time 16.39 seconds
Started Apr 28 01:17:48 PM PDT 24
Finished Apr 28 01:18:46 PM PDT 24
Peak memory 240912 kb
Host smart-e1d9bdfa-9770-4388-8436-6cfcc16d2bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981713665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1981713665
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3344198976
Short name T672
Test name
Test status
Simulation time 2886512904 ps
CPU time 14.9 seconds
Started Apr 28 01:17:48 PM PDT 24
Finished Apr 28 01:18:44 PM PDT 24
Peak memory 223192 kb
Host smart-0245e5c4-e3c1-4341-9fa9-fd8ef9ff615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344198976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3344198976
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3996834261
Short name T659
Test name
Test status
Simulation time 578532023 ps
CPU time 5.76 seconds
Started Apr 28 01:17:49 PM PDT 24
Finished Apr 28 01:18:36 PM PDT 24
Peak memory 222512 kb
Host smart-166be5ee-3d3d-415b-a208-78bec504943f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996834261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3996834261
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1524956478
Short name T699
Test name
Test status
Simulation time 4701502652 ps
CPU time 30.48 seconds
Started Apr 28 01:17:42 PM PDT 24
Finished Apr 28 01:18:55 PM PDT 24
Peak memory 216256 kb
Host smart-816027a2-05ba-4a02-8cdd-8f353dc0591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524956478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1524956478
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2196871978
Short name T432
Test name
Test status
Simulation time 995995407 ps
CPU time 5.99 seconds
Started Apr 28 01:17:43 PM PDT 24
Finished Apr 28 01:18:33 PM PDT 24
Peak memory 216284 kb
Host smart-a7c9448b-46f5-4374-b3ea-e53b6387361c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196871978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2196871978
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.21701409
Short name T62
Test name
Test status
Simulation time 36566816 ps
CPU time 1.07 seconds
Started Apr 28 01:17:41 PM PDT 24
Finished Apr 28 01:18:26 PM PDT 24
Peak memory 207860 kb
Host smart-4de7a929-ca4a-4bbf-98fd-1eba7e2e21ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21701409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.21701409
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1521260602
Short name T427
Test name
Test status
Simulation time 883063254 ps
CPU time 0.87 seconds
Started Apr 28 01:17:43 PM PDT 24
Finished Apr 28 01:18:26 PM PDT 24
Peak memory 206828 kb
Host smart-fb594e13-5177-4d38-a9c6-5f385136b5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521260602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1521260602
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.622131427
Short name T332
Test name
Test status
Simulation time 40030446882 ps
CPU time 34.69 seconds
Started Apr 28 01:17:51 PM PDT 24
Finished Apr 28 01:19:06 PM PDT 24
Peak memory 236628 kb
Host smart-00632a7e-413e-434a-b186-54d88a5860b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622131427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.622131427
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2644534696
Short name T454
Test name
Test status
Simulation time 21484574 ps
CPU time 0.68 seconds
Started Apr 28 01:18:04 PM PDT 24
Finished Apr 28 01:18:40 PM PDT 24
Peak memory 205768 kb
Host smart-07b02395-d9b1-48f0-abef-9c97691e5748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644534696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2644534696
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.754573422
Short name T528
Test name
Test status
Simulation time 46346093 ps
CPU time 0.78 seconds
Started Apr 28 01:17:53 PM PDT 24
Finished Apr 28 01:18:33 PM PDT 24
Peak memory 206736 kb
Host smart-6bc1802d-83dc-43e2-9a4c-dc50f1f3e922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754573422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.754573422
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1253514895
Short name T84
Test name
Test status
Simulation time 10900770728 ps
CPU time 45.05 seconds
Started Apr 28 01:18:04 PM PDT 24
Finished Apr 28 01:19:24 PM PDT 24
Peak memory 240948 kb
Host smart-f874efe2-0f35-4a1b-8166-9c67b17a6a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253514895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1253514895
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3677454918
Short name T198
Test name
Test status
Simulation time 101536276 ps
CPU time 3.34 seconds
Started Apr 28 01:17:58 PM PDT 24
Finished Apr 28 01:18:39 PM PDT 24
Peak memory 222952 kb
Host smart-12fe9490-9393-44d1-a5b3-f508c7a471ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677454918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3677454918
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.787811782
Short name T261
Test name
Test status
Simulation time 155068835 ps
CPU time 2.1 seconds
Started Apr 28 01:18:04 PM PDT 24
Finished Apr 28 01:18:41 PM PDT 24
Peak memory 218408 kb
Host smart-d8673fee-1086-4ed1-949f-f47cd9e1b631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787811782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.787811782
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4212288168
Short name T465
Test name
Test status
Simulation time 635339499 ps
CPU time 4.78 seconds
Started Apr 28 01:17:59 PM PDT 24
Finished Apr 28 01:18:41 PM PDT 24
Peak memory 222928 kb
Host smart-76b9fe74-d4ce-496f-af05-1e81a36bf189
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4212288168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4212288168
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4015417806
Short name T414
Test name
Test status
Simulation time 9340408193 ps
CPU time 12.01 seconds
Started Apr 28 01:17:53 PM PDT 24
Finished Apr 28 01:18:44 PM PDT 24
Peak memory 216232 kb
Host smart-e0f86247-8fe5-4d81-9025-3bd14c62ec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015417806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4015417806
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2082491653
Short name T459
Test name
Test status
Simulation time 827025036 ps
CPU time 4.69 seconds
Started Apr 28 01:17:55 PM PDT 24
Finished Apr 28 01:18:38 PM PDT 24
Peak memory 216232 kb
Host smart-e1967048-f19c-4655-baa7-61dc14808862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082491653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2082491653
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2105722142
Short name T18
Test name
Test status
Simulation time 95944788 ps
CPU time 0.79 seconds
Started Apr 28 01:18:00 PM PDT 24
Finished Apr 28 01:18:37 PM PDT 24
Peak memory 205764 kb
Host smart-ef4c8257-968a-4a56-8d60-6e94085545c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105722142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2105722142
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.625926435
Short name T694
Test name
Test status
Simulation time 296703335 ps
CPU time 1.12 seconds
Started Apr 28 01:17:59 PM PDT 24
Finished Apr 28 01:18:37 PM PDT 24
Peak memory 206780 kb
Host smart-44f28285-f5cb-4e0d-aa6b-af354e06527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625926435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.625926435
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3252285913
Short name T214
Test name
Test status
Simulation time 248355442 ps
CPU time 3.09 seconds
Started Apr 28 01:17:58 PM PDT 24
Finished Apr 28 01:18:39 PM PDT 24
Peak memory 222680 kb
Host smart-a616fc1a-ddb7-4a9a-a880-a2ddb6f9e7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252285913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3252285913
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2693570652
Short name T633
Test name
Test status
Simulation time 12300835 ps
CPU time 0.72 seconds
Started Apr 28 01:12:50 PM PDT 24
Finished Apr 28 01:12:52 PM PDT 24
Peak memory 205408 kb
Host smart-b14c75c3-38aa-4a48-964d-2645f9352b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693570652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
693570652
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2513362698
Short name T636
Test name
Test status
Simulation time 18005667 ps
CPU time 0.76 seconds
Started Apr 28 01:12:46 PM PDT 24
Finished Apr 28 01:12:48 PM PDT 24
Peak memory 205636 kb
Host smart-7c6ab0c6-37f8-495f-acd6-4c2d56ffbefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513362698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2513362698
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1882333518
Short name T367
Test name
Test status
Simulation time 47549138584 ps
CPU time 143.06 seconds
Started Apr 28 01:12:47 PM PDT 24
Finished Apr 28 01:15:11 PM PDT 24
Peak memory 255164 kb
Host smart-4c7a8b78-b18f-413d-a644-96b1ce43c34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882333518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1882333518
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2096751180
Short name T278
Test name
Test status
Simulation time 1481862055 ps
CPU time 5.96 seconds
Started Apr 28 01:12:48 PM PDT 24
Finished Apr 28 01:12:55 PM PDT 24
Peak memory 224104 kb
Host smart-e9457553-fbf9-483b-a712-e93c63a87e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096751180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2096751180
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2563620490
Short name T331
Test name
Test status
Simulation time 2449128656 ps
CPU time 30.13 seconds
Started Apr 28 01:12:47 PM PDT 24
Finished Apr 28 01:13:18 PM PDT 24
Peak memory 222140 kb
Host smart-ee6ea7b1-df7a-417f-9e86-c12ccabd2095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563620490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2563620490
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4194899197
Short name T670
Test name
Test status
Simulation time 1081457317 ps
CPU time 4.24 seconds
Started Apr 28 01:12:44 PM PDT 24
Finished Apr 28 01:12:50 PM PDT 24
Peak memory 220740 kb
Host smart-2d30d2a5-6707-4d3a-a650-f7aa117755cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4194899197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4194899197
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1641947451
Short name T394
Test name
Test status
Simulation time 15988232046 ps
CPU time 9.61 seconds
Started Apr 28 01:12:47 PM PDT 24
Finished Apr 28 01:12:57 PM PDT 24
Peak memory 216312 kb
Host smart-b66e3fd1-fe86-4602-bf4f-98f7f1799d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641947451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1641947451
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4068945826
Short name T603
Test name
Test status
Simulation time 3650193910 ps
CPU time 12.41 seconds
Started Apr 28 01:12:49 PM PDT 24
Finished Apr 28 01:13:02 PM PDT 24
Peak memory 216372 kb
Host smart-e17c97cc-6af1-4e9d-b765-032d87019037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068945826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4068945826
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3191785892
Short name T546
Test name
Test status
Simulation time 44703593 ps
CPU time 1.28 seconds
Started Apr 28 01:12:46 PM PDT 24
Finished Apr 28 01:12:48 PM PDT 24
Peak memory 216248 kb
Host smart-2bf7da9c-99fe-4912-a09d-7149c8bf26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191785892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3191785892
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2436173141
Short name T473
Test name
Test status
Simulation time 170196398 ps
CPU time 0.76 seconds
Started Apr 28 01:12:45 PM PDT 24
Finished Apr 28 01:12:47 PM PDT 24
Peak memory 205796 kb
Host smart-dab3eb98-9d10-40a5-8614-710df019f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436173141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2436173141
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1225359173
Short name T264
Test name
Test status
Simulation time 3594146278 ps
CPU time 14.58 seconds
Started Apr 28 01:13:08 PM PDT 24
Finished Apr 28 01:13:24 PM PDT 24
Peak memory 217560 kb
Host smart-1fb764b2-bde8-4dd8-a9d5-d7ef2ef24c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225359173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1225359173
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3215843263
Short name T557
Test name
Test status
Simulation time 23118582 ps
CPU time 0.68 seconds
Started Apr 28 01:12:52 PM PDT 24
Finished Apr 28 01:12:53 PM PDT 24
Peak memory 205336 kb
Host smart-3478c4df-eca6-41f5-8caa-b05112765cc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215843263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
215843263
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1150989254
Short name T591
Test name
Test status
Simulation time 68621630 ps
CPU time 0.78 seconds
Started Apr 28 01:12:53 PM PDT 24
Finished Apr 28 01:12:54 PM PDT 24
Peak memory 205680 kb
Host smart-027705ed-040f-4782-a540-5f69087edf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150989254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1150989254
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1980216310
Short name T321
Test name
Test status
Simulation time 6563076270 ps
CPU time 24.32 seconds
Started Apr 28 01:12:51 PM PDT 24
Finished Apr 28 01:13:16 PM PDT 24
Peak memory 240896 kb
Host smart-713a52c8-1250-4fff-b131-cd0002c79825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980216310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1980216310
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4056789399
Short name T296
Test name
Test status
Simulation time 229844247 ps
CPU time 6.16 seconds
Started Apr 28 01:12:54 PM PDT 24
Finished Apr 28 01:13:01 PM PDT 24
Peak memory 218836 kb
Host smart-c87d6dcd-d493-4fbf-8e1e-5c4688b3b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056789399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4056789399
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1924830060
Short name T674
Test name
Test status
Simulation time 1436169887 ps
CPU time 8.01 seconds
Started Apr 28 01:12:55 PM PDT 24
Finished Apr 28 01:13:05 PM PDT 24
Peak memory 221152 kb
Host smart-3e96aa88-37b1-4c56-89b0-058b3329d9fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1924830060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1924830060
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.259397843
Short name T464
Test name
Test status
Simulation time 457734884 ps
CPU time 3.36 seconds
Started Apr 28 01:12:50 PM PDT 24
Finished Apr 28 01:12:54 PM PDT 24
Peak memory 216352 kb
Host smart-daebb192-f61e-404a-b6f1-f1073bdfa11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259397843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.259397843
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.518456663
Short name T610
Test name
Test status
Simulation time 150436635 ps
CPU time 0.82 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:00 PM PDT 24
Peak memory 205764 kb
Host smart-6a8bbd28-a8f3-44bf-8a9d-db3413221274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518456663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.518456663
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1013252316
Short name T629
Test name
Test status
Simulation time 118591510 ps
CPU time 0.98 seconds
Started Apr 28 01:12:50 PM PDT 24
Finished Apr 28 01:12:52 PM PDT 24
Peak memory 207144 kb
Host smart-cf8ac535-1713-4ec5-944b-f497711d8559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013252316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1013252316
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.486968369
Short name T334
Test name
Test status
Simulation time 3652943973 ps
CPU time 16.52 seconds
Started Apr 28 01:12:51 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 232704 kb
Host smart-87b6f13e-4417-474a-8016-8bb930cb9366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486968369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.486968369
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2905662428
Short name T597
Test name
Test status
Simulation time 15644961 ps
CPU time 0.71 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:00 PM PDT 24
Peak memory 205752 kb
Host smart-6c15733d-75af-4dd5-8f79-e16319c66b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905662428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
905662428
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4176397721
Short name T463
Test name
Test status
Simulation time 17559025 ps
CPU time 0.74 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:12:58 PM PDT 24
Peak memory 206680 kb
Host smart-d3dd2bfe-fe39-4a1f-8231-a0a9eb2e7c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176397721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4176397721
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2352976683
Short name T307
Test name
Test status
Simulation time 2691735122 ps
CPU time 47.01 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:46 PM PDT 24
Peak memory 240480 kb
Host smart-c5cc9135-a13d-4ba8-91bb-aa961810fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352976683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2352976683
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3567346720
Short name T352
Test name
Test status
Simulation time 231196956 ps
CPU time 4.25 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:04 PM PDT 24
Peak memory 216748 kb
Host smart-399f1bdd-5531-4042-80a4-15398b5e9ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567346720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3567346720
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2578227306
Short name T639
Test name
Test status
Simulation time 1311067781 ps
CPU time 8.49 seconds
Started Apr 28 01:12:55 PM PDT 24
Finished Apr 28 01:13:05 PM PDT 24
Peak memory 220272 kb
Host smart-c4fc7f24-4c38-4dde-8fd0-deda47f08ef6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2578227306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2578227306
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1927421512
Short name T22
Test name
Test status
Simulation time 6073994853 ps
CPU time 17.54 seconds
Started Apr 28 01:12:50 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 216204 kb
Host smart-cbff82c3-0418-4a32-a988-5a3e14c14e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927421512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1927421512
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4012690551
Short name T516
Test name
Test status
Simulation time 19401262855 ps
CPU time 15.44 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:15 PM PDT 24
Peak memory 216296 kb
Host smart-6b0fe9d9-c26f-473f-9c9b-e43a817d4b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012690551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4012690551
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1697393738
Short name T647
Test name
Test status
Simulation time 348759342 ps
CPU time 1.36 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:12:59 PM PDT 24
Peak memory 216164 kb
Host smart-6cfcafea-c755-4f13-8353-1a161ab6599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697393738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1697393738
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2052515644
Short name T451
Test name
Test status
Simulation time 204357118 ps
CPU time 0.83 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:12:58 PM PDT 24
Peak memory 205772 kb
Host smart-3fc3d2b6-7c94-45f4-8293-2be8d9f7543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052515644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2052515644
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.813531546
Short name T85
Test name
Test status
Simulation time 23749092717 ps
CPU time 8.53 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:13:07 PM PDT 24
Peak memory 216340 kb
Host smart-d70f9f28-47ae-4e9e-81f4-1c2ab1ee233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813531546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.813531546
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.393295730
Short name T505
Test name
Test status
Simulation time 43369565 ps
CPU time 0.68 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:12:58 PM PDT 24
Peak memory 205360 kb
Host smart-62d162a2-7926-40d6-aa5d-fa6f0d4eb132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393295730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.393295730
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3483505922
Short name T583
Test name
Test status
Simulation time 64888731 ps
CPU time 0.77 seconds
Started Apr 28 01:12:55 PM PDT 24
Finished Apr 28 01:12:58 PM PDT 24
Peak memory 207004 kb
Host smart-3ec1d7fb-cb7d-44da-999e-8fc86e45077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483505922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3483505922
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3209868932
Short name T180
Test name
Test status
Simulation time 1676273149 ps
CPU time 14.66 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:14 PM PDT 24
Peak memory 216536 kb
Host smart-f374479e-079b-480f-83ab-3f8c8b44f375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209868932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3209868932
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1756274399
Short name T6
Test name
Test status
Simulation time 8559443294 ps
CPU time 62.8 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:14:02 PM PDT 24
Peak memory 222588 kb
Host smart-a6a2fad7-92d8-44f7-811c-6dd664afeaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756274399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1756274399
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3478885765
Short name T622
Test name
Test status
Simulation time 4077908483 ps
CPU time 7.93 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:08 PM PDT 24
Peak memory 222216 kb
Host smart-ab15d9ec-cd96-4870-bff6-a96e5080b231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478885765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3478885765
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2024614182
Short name T667
Test name
Test status
Simulation time 1002388009 ps
CPU time 4.02 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:03 PM PDT 24
Peak memory 222440 kb
Host smart-71d8db91-982b-40fc-a220-149b7dbd2959
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2024614182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2024614182
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.739126061
Short name T104
Test name
Test status
Simulation time 1514279360 ps
CPU time 5.13 seconds
Started Apr 28 01:12:59 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 216284 kb
Host smart-d62acf14-b707-4b9a-944e-ae06754bef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739126061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.739126061
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3578167891
Short name T685
Test name
Test status
Simulation time 72124093 ps
CPU time 1.03 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:13:00 PM PDT 24
Peak memory 207908 kb
Host smart-1b7cec5b-f572-4a66-9899-e13ec7b0890f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578167891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3578167891
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1540035671
Short name T711
Test name
Test status
Simulation time 346698765 ps
CPU time 1 seconds
Started Apr 28 01:12:56 PM PDT 24
Finished Apr 28 01:13:00 PM PDT 24
Peak memory 206828 kb
Host smart-04be76ae-99fe-4f1d-a7d2-05b34a82c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540035671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1540035671
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3859752250
Short name T507
Test name
Test status
Simulation time 18589218 ps
CPU time 0.7 seconds
Started Apr 28 01:13:02 PM PDT 24
Finished Apr 28 01:13:04 PM PDT 24
Peak memory 205668 kb
Host smart-010b7f1e-2216-4cf2-b8d2-d4919e82e238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859752250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
859752250
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3916103664
Short name T574
Test name
Test status
Simulation time 19287584 ps
CPU time 0.76 seconds
Started Apr 28 01:13:00 PM PDT 24
Finished Apr 28 01:13:03 PM PDT 24
Peak memory 206020 kb
Host smart-27060088-99e5-4a48-9016-b17efeb21d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916103664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3916103664
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_intercept.991615278
Short name T571
Test name
Test status
Simulation time 117945174 ps
CPU time 2.44 seconds
Started Apr 28 01:13:00 PM PDT 24
Finished Apr 28 01:13:04 PM PDT 24
Peak memory 221948 kb
Host smart-2405dc1f-1b05-42a3-8652-f4b09995768e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991615278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.991615278
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4013410111
Short name T222
Test name
Test status
Simulation time 2492223991 ps
CPU time 15.03 seconds
Started Apr 28 01:13:01 PM PDT 24
Finished Apr 28 01:13:18 PM PDT 24
Peak memory 246664 kb
Host smart-9ad9fa4d-d538-4eff-92b7-656c180436b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013410111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4013410111
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3119349837
Short name T692
Test name
Test status
Simulation time 158672233 ps
CPU time 2.95 seconds
Started Apr 28 01:12:58 PM PDT 24
Finished Apr 28 01:13:03 PM PDT 24
Peak memory 222612 kb
Host smart-ac14c2ea-4ffa-4bfe-876a-d4426235e687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119349837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3119349837
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3555706652
Short name T82
Test name
Test status
Simulation time 318942112 ps
CPU time 3.84 seconds
Started Apr 28 01:13:00 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 220172 kb
Host smart-47913d64-7de4-4f71-8c5a-e115d5ec6876
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3555706652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3555706652
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.559450131
Short name T523
Test name
Test status
Simulation time 5851910448 ps
CPU time 10.7 seconds
Started Apr 28 01:13:00 PM PDT 24
Finished Apr 28 01:13:12 PM PDT 24
Peak memory 216332 kb
Host smart-48cde696-7c99-4112-9a0e-72d6a4cda3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559450131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.559450131
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1991889963
Short name T58
Test name
Test status
Simulation time 501538919 ps
CPU time 2.15 seconds
Started Apr 28 01:12:57 PM PDT 24
Finished Apr 28 01:13:01 PM PDT 24
Peak memory 216352 kb
Host smart-4631fa54-b1fe-4e52-8b22-ec6330a1dc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991889963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1991889963
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2709559343
Short name T522
Test name
Test status
Simulation time 202138564 ps
CPU time 1.01 seconds
Started Apr 28 01:12:55 PM PDT 24
Finished Apr 28 01:12:57 PM PDT 24
Peak memory 206792 kb
Host smart-4acd1124-9cd0-4abb-884f-c739d97deecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709559343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2709559343
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2437627312
Short name T267
Test name
Test status
Simulation time 571558691 ps
CPU time 2.67 seconds
Started Apr 28 01:13:02 PM PDT 24
Finished Apr 28 01:13:06 PM PDT 24
Peak memory 222216 kb
Host smart-ea270bfc-8618-46b6-963b-64fe47b2dacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437627312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2437627312
Directory /workspace/9.spi_device_upload/latest
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