Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1447636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1586389

1

T1

172

T2

898

T3

2312

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2347067	1			T1	1610		T2	7		T3	6727
values[0x0]	342652	1			T1	84		T2	436		T3	1130
values[0x1]	344306	1			T1	78		T2	460		T3	1152

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1095081	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1938944

1

T1

710

T2

900

T3

4437

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13863	1			T1	2		T2	8		T13	7
valid_sources[0x01]	10498	1			T1	2		T2	2		T4	9
valid_sources[0x02]	9474	1			T1	4		T2	5		T13	6
valid_sources[0x03]	119497	1			T1	2		T2	4		T4	6
valid_sources[0x04]	11104	1			T2	2		T3	2		T4	3
valid_sources[0x05]	17105	1			T3	299		T4	10		T19	2
valid_sources[0x06]	10470	1			T1	8		T2	3		T3	83
valid_sources[0x07]	26996	1			T2	3		T4	6		T13	6
valid_sources[0x08]	10306	1			T1	3		T2	2		T4	2
valid_sources[0x09]	12061	1			T1	22		T2	3		T4	3
valid_sources[0x0a]	9126	1			T1	7		T2	2		T4	1
valid_sources[0x0b]	9645	1			T1	12		T2	5		T3	20
valid_sources[0x0c]	13976	1			T1	3		T2	6		T4	2
valid_sources[0x0d]	10144	1			T1	10		T2	1		T4	1
valid_sources[0x0e]	10096	1			T1	6		T2	2		T3	637
valid_sources[0x0f]	15794	1			T1	17		T2	3		T3	5
valid_sources[0x10]	10108	1			T1	5		T2	5		T13	6
valid_sources[0x11]	23777	1			T1	14		T2	3		T4	5
valid_sources[0x12]	10293	1			T1	5		T2	6		T13	1
valid_sources[0x13]	11372	1			T1	3		T2	2		T13	3
valid_sources[0x14]	9715	1			T1	9		T2	2		T4	9
valid_sources[0x15]	10365	1			T1	10		T2	1		T3	2
valid_sources[0x16]	14918	1			T2	3		T4	1		T13	8
valid_sources[0x17]	10512	1			T3	47		T4	7		T13	2
valid_sources[0x18]	9601	1			T2	3		T3	4		T4	4
valid_sources[0x19]	13210	1			T1	1		T2	2		T3	2
valid_sources[0x1a]	12970	1			T1	5		T2	1		T3	294
valid_sources[0x1b]	9342	1			T1	6		T2	2		T4	1
valid_sources[0x1c]	12635	1			T2	4		T4	2		T13	8
valid_sources[0x1d]	12016	1			T1	17		T2	4		T3	358
valid_sources[0x1e]	15354	1			T1	2		T2	2		T3	101
valid_sources[0x1f]	9673	1			T1	41		T2	5		T3	1
valid_sources[0x20]	10671	1			T1	3		T3	138		T4	9
valid_sources[0x21]	12119	1			T1	7		T2	1		T3	329
valid_sources[0x22]	9010	1			T2	3		T13	5		T18	1
valid_sources[0x23]	10539	1			T1	3		T2	3		T4	2
valid_sources[0x24]	11426	1			T1	4		T2	2		T3	101
valid_sources[0x25]	14393	1			T2	7		T4	3		T13	6
valid_sources[0x26]	10174	1			T1	5		T2	3		T13	5
valid_sources[0x27]	12014	1			T1	4		T2	8		T4	3
valid_sources[0x28]	10309	1			T2	4		T13	4		T6	48
valid_sources[0x29]	9869	1			T1	3		T2	3		T4	9
valid_sources[0x2a]	10875	1			T1	4		T2	4		T4	3
valid_sources[0x2b]	9984	1			T1	3		T2	6		T3	2
valid_sources[0x2c]	10031	1			T1	5		T2	4		T13	2
valid_sources[0x2d]	9682	1			T1	5		T2	2		T3	4
valid_sources[0x2e]	11796	1			T2	5		T4	2		T13	4
valid_sources[0x2f]	14965	1			T1	10		T3	20		T13	5
valid_sources[0x30]	9619	1			T2	5		T13	6		T18	1
valid_sources[0x31]	8838	1			T2	4		T13	12		T14	1
valid_sources[0x32]	8834	1			T1	5		T2	2		T4	8
valid_sources[0x33]	12933	1			T1	4		T2	4		T3	10
valid_sources[0x34]	10620	1			T1	5		T2	6		T13	4
valid_sources[0x35]	10242	1			T1	1		T2	4		T4	6
valid_sources[0x36]	9306	1			T2	5		T16	4		T19	2
valid_sources[0x37]	9250	1			T1	1		T2	5		T4	4
valid_sources[0x38]	9020	1			T1	4		T2	4		T3	1
valid_sources[0x39]	9626	1			T1	5		T2	3		T4	13
valid_sources[0x3a]	13012	1			T1	2		T2	2		T4	6
valid_sources[0x3b]	12870	1			T1	16		T2	2		T3	47
valid_sources[0x3c]	11025	1			T1	4		T2	6		T13	4
valid_sources[0x3d]	10612	1			T1	19		T2	6		T4	3
valid_sources[0x3e]	10290	1			T1	3		T2	4		T4	10
valid_sources[0x3f]	9930	1			T1	9		T2	4		T4	3
valid_sources[0x40]	9804	1			T1	3		T2	2		T4	6
valid_sources[0x41]	9732	1			T1	9		T2	4		T4	3
valid_sources[0x42]	10246	1			T1	2		T2	5		T3	649
valid_sources[0x43]	12419	1			T1	4		T2	8		T4	1
valid_sources[0x44]	9592	1			T1	30		T2	7		T3	211
valid_sources[0x45]	10378	1			T1	8		T3	937		T4	1
valid_sources[0x46]	11308	1			T1	7		T2	2		T4	5
valid_sources[0x47]	9372	1			T2	7		T4	7		T13	7
valid_sources[0x48]	10118	1			T1	15		T2	5		T13	5
valid_sources[0x49]	9567	1			T1	8		T2	1		T13	11
valid_sources[0x4a]	10435	1			T1	18		T2	4		T4	7
valid_sources[0x4b]	9477	1			T1	4		T2	1		T13	2
valid_sources[0x4c]	10792	1			T1	3		T2	5		T4	8
valid_sources[0x4d]	11042	1			T1	2		T2	5		T4	15
valid_sources[0x4e]	9577	1			T1	9		T2	2		T4	6
valid_sources[0x4f]	10103	1			T1	4		T2	8		T13	5
valid_sources[0x50]	13035	1			T1	7		T2	5		T4	1
valid_sources[0x51]	10456	1			T1	16		T2	3		T3	3
valid_sources[0x52]	10499	1			T2	3		T4	1		T13	9
valid_sources[0x53]	11160	1			T1	7		T2	4		T13	4
valid_sources[0x54]	10316	1			T1	8		T2	2		T13	13
valid_sources[0x55]	11698	1			T1	21		T2	3		T4	14
valid_sources[0x56]	13401	1			T1	14		T3	24		T4	2
valid_sources[0x57]	8888	1			T2	5		T13	7		T14	1
valid_sources[0x58]	10694	1			T1	11		T2	7		T13	6
valid_sources[0x59]	8650	1			T1	9		T2	4		T4	10
valid_sources[0x5a]	10969	1			T1	2		T2	2		T4	4
valid_sources[0x5b]	11669	1			T1	1		T2	6		T4	6
valid_sources[0x5c]	12969	1			T1	9		T2	2		T13	3
valid_sources[0x5d]	11983	1			T1	13		T2	2		T4	5
valid_sources[0x5e]	9159	1			T1	6		T2	5		T3	578
valid_sources[0x5f]	9319	1			T1	17		T2	4		T3	34
valid_sources[0x60]	12743	1			T1	6		T2	4		T3	4
valid_sources[0x61]	9672	1			T1	7		T2	2		T4	2
valid_sources[0x62]	9947	1			T1	5		T2	5		T4	5
valid_sources[0x63]	9153	1			T2	4		T3	148		T4	3
valid_sources[0x64]	9769	1			T1	1		T2	4		T3	560
valid_sources[0x65]	11225	1			T1	7		T2	6		T4	8
valid_sources[0x66]	9061	1			T1	13		T2	4		T4	6
valid_sources[0x67]	8944	1			T1	5		T2	2		T13	7
valid_sources[0x68]	9486	1			T1	23		T2	1		T3	1
valid_sources[0x69]	16726	1			T1	7		T2	3		T13	5
valid_sources[0x6a]	11070	1			T1	8		T2	4		T4	2
valid_sources[0x6b]	9722	1			T1	7		T2	1		T4	11
valid_sources[0x6c]	12362	1			T1	18		T2	2		T4	6
valid_sources[0x6d]	10784	1			T1	2		T13	11		T6	54
valid_sources[0x6e]	10218	1			T1	17		T2	4		T13	11
valid_sources[0x6f]	13952	1			T1	10		T3	3		T13	18
valid_sources[0x70]	10696	1			T1	8		T2	2		T4	15
valid_sources[0x71]	14543	1			T1	2		T2	3		T4	7
valid_sources[0x72]	10884	1			T1	2		T2	4		T4	4
valid_sources[0x73]	10147	1			T2	3		T4	2		T13	3
valid_sources[0x74]	11393	1			T1	15		T2	4		T4	3
valid_sources[0x75]	9897	1			T1	5		T2	3		T4	12
valid_sources[0x76]	12718	1			T1	12		T2	5		T13	11
valid_sources[0x77]	10315	1			T2	7		T4	7		T13	6
valid_sources[0x78]	10262	1			T1	3		T2	3		T4	2
valid_sources[0x79]	9391	1			T1	6		T2	2		T4	7
valid_sources[0x7a]	12756	1			T1	9		T2	6		T4	2
valid_sources[0x7b]	17064	1			T1	8		T2	3		T4	1
valid_sources[0x7c]	11596	1			T2	10		T4	6		T6	54
valid_sources[0x7d]	11503	1			T1	5		T2	3		T13	5
valid_sources[0x7e]	10308	1			T1	7		T2	4		T4	1
valid_sources[0x7f]	9246	1			T1	10		T2	3		T3	102
valid_sources[0x80]	9898	1			T1	9		T2	6		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

965705

1

T1

68

T2

4

T3

659

values[0x0]

all_enables

biggest_size

313416

1

T1

56

T2

435

T3

840

values[0x1]

all_enables

biggest_size

307268

1

T1

48

T2

459

T3

813