Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1468392

1

T1

1600

T2

5

T3

6697

full_word

1587617

1

T1

172

T2

898

T3

2312

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3055589	1			T1	1772		T2	903		T3	9009
auto[TlIntgErrCmd]	151	1			T115	8		T116	2		T118	1
auto[TlIntgErrData]	129	1			T115	15		T116	5		T118	4
auto[TlIntgErrBoth]	140	1			T115	7		T116	3		T118	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2350508

1

T1

1610

T2

7

T3

6727

auto[1]

705501

1

T1

162

T2

896

T3

2282

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1384331	1			T1	1542		T2	3		T3	6068
auto[TlIntgErrNone]	partial	auto[1]	83678	1			T1	58		T2	2		T3	629
auto[TlIntgErrNone]	full_word	auto[0]	965967	1			T1	68		T2	4		T3	659
auto[TlIntgErrNone]	full_word	auto[1]	621613	1			T1	104		T2	894		T3	1653
auto[TlIntgErrCmd]	partial	auto[0]	70	1			T115	5		T116	1		T141	5
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T115	3		T116	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T379	1		T133	1		T381	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T379	1		T133	3		T382	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T115	5		T116	2		T118	3
auto[TlIntgErrData]	partial	auto[1]	57	1			T115	7		T116	3		T118	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T115	2		T141	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T115	1		T133	2		T381	1
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T115	2		T116	1		T118	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T115	3		T116	2		T118	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T115	1		T379	1		T383	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T115	1		T376	1		T133	1