Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.42	90.27	80.39	96.94		78.12	86.36	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	671	671	0	0
OutputsKnown_A	124978824	124920409	0	0
gen_no_flops.OutputDelay_A	124978824	124920409	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671	671	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124978824	124920409	0	0
T1	35181	35094	0	0
T2	230504	230417	0	0
T3	565457	565400	0	0
T4	72704	72615	0	0
T13	8920	8864	0	0
T14	3752	3694	0	0
T15	20070	19984	0	0
T16	4292	4208	0	0
T18	1218	1119	0	0
T19	4412	4333	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124978824	124920409	0	0
T1	35181	35094	0	0
T2	230504	230417	0	0
T3	565457	565400	0	0
T4	72704	72615	0	0
T13	8920	8864	0	0
T14	3752	3694	0	0
T15	20070	19984	0	0
T16	4292	4208	0	0
T18	1218	1119	0	0
T19	4412	4333	0	0