Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	164960445	572399	0	0
gen_wmask[1].MaskCheckPortA_A	164960445	572399	0	0
gen_wmask[2].MaskCheckPortA_A	164960445	572399	0	0
gen_wmask[3].MaskCheckPortA_A	164960445	572399	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164960445	572399	0	0
T1	40703	329	0	0
T2	286509	832	0	0
T3	634014	2848	0	0
T4	141599	832	0	0
T5	95484	2368	0	0
T6	0	6198	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	11488	114	0	0
T14	4408	19	0	0
T15	21987	0	0	0
T16	5084	0	0	0
T17	153188	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164960445	572399	0	0
T1	40703	329	0	0
T2	286509	832	0	0
T3	634014	2848	0	0
T4	141599	832	0	0
T5	95484	2368	0	0
T6	0	6198	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	11488	114	0	0
T14	4408	19	0	0
T15	21987	0	0	0
T16	5084	0	0	0
T17	153188	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164960445	572399	0	0
T1	40703	329	0	0
T2	286509	832	0	0
T3	634014	2848	0	0
T4	141599	832	0	0
T5	95484	2368	0	0
T6	0	6198	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	11488	114	0	0
T14	4408	19	0	0
T15	21987	0	0	0
T16	5084	0	0	0
T17	153188	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	164960445	572399	0	0
T1	40703	329	0	0
T2	286509	832	0	0
T3	634014	2848	0	0
T4	141599	832	0	0
T5	95484	2368	0	0
T6	0	6198	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	11488	114	0	0
T14	4408	19	0	0
T15	21987	0	0	0
T16	5084	0	0	0
T17	153188	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	124978824	418981	0	0
gen_wmask[1].MaskCheckPortA_A	124978824	418981	0	0
gen_wmask[2].MaskCheckPortA_A	124978824	418981	0	0
gen_wmask[3].MaskCheckPortA_A	124978824	418981	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124978824	418981	0	0
T1	35181	78	0	0
T2	230504	832	0	0
T3	565457	765	0	0
T4	72704	832	0	0
T5	0	2368	0	0
T6	0	2754	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	8920	48	0	0
T14	3752	16	0	0
T15	20070	0	0	0
T16	4292	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124978824	418981	0	0
T1	35181	78	0	0
T2	230504	832	0	0
T3	565457	765	0	0
T4	72704	832	0	0
T5	0	2368	0	0
T6	0	2754	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	8920	48	0	0
T14	3752	16	0	0
T15	20070	0	0	0
T16	4292	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124978824	418981	0	0
T1	35181	78	0	0
T2	230504	832	0	0
T3	565457	765	0	0
T4	72704	832	0	0
T5	0	2368	0	0
T6	0	2754	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	8920	48	0	0
T14	3752	16	0	0
T15	20070	0	0	0
T16	4292	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	124978824	418981	0	0
T1	35181	78	0	0
T2	230504	832	0	0
T3	565457	765	0	0
T4	72704	832	0	0
T5	0	2368	0	0
T6	0	2754	0	0
T7	0	832	0	0
T8	0	832	0	0
T13	8920	48	0	0
T14	3752	16	0	0
T15	20070	0	0	0
T16	4292	0	0	0
T18	1218	0	0	0
T19	4412	0	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	39981621	153418	0	0
gen_wmask[1].MaskCheckPortA_A	39981621	153418	0	0
gen_wmask[2].MaskCheckPortA_A	39981621	153418	0	0
gen_wmask[3].MaskCheckPortA_A	39981621	153418	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39981621	153418	0	0
T1	5522	251	0	0
T2	56005	0	0	0
T3	68557	2083	0	0
T4	68895	0	0	0
T5	95484	0	0	0
T6	0	3444	0	0
T13	2568	66	0	0
T14	656	3	0	0
T15	1917	0	0	0
T16	792	0	0	0
T17	153188	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39981621	153418	0	0
T1	5522	251	0	0
T2	56005	0	0	0
T3	68557	2083	0	0
T4	68895	0	0	0
T5	95484	0	0	0
T6	0	3444	0	0
T13	2568	66	0	0
T14	656	3	0	0
T15	1917	0	0	0
T16	792	0	0	0
T17	153188	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39981621	153418	0	0
T1	5522	251	0	0
T2	56005	0	0	0
T3	68557	2083	0	0
T4	68895	0	0	0
T5	95484	0	0	0
T6	0	3444	0	0
T13	2568	66	0	0
T14	656	3	0	0
T15	1917	0	0	0
T16	792	0	0	0
T17	153188	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39981621	153418	0	0
T1	5522	251	0	0
T2	56005	0	0	0
T3	68557	2083	0	0
T4	68895	0	0	0
T5	95484	0	0	0
T6	0	3444	0	0
T13	2568	66	0	0
T14	656	3	0	0
T15	1917	0	0	0
T16	792	0	0	0
T17	153188	0	0	0
T20	0	324	0	0
T21	0	582	0	0
T22	0	76	0	0
T23	0	1769	0	0
T24	0	296	0	0