Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3727 |
0 |
0 |
T38 |
2191 |
5 |
0 |
0 |
T39 |
3120 |
119 |
0 |
0 |
T40 |
5311 |
8 |
0 |
0 |
T115 |
91029 |
5 |
0 |
0 |
T116 |
35197 |
1 |
0 |
0 |
T117 |
18291 |
273 |
0 |
0 |
T118 |
33435 |
3 |
0 |
0 |
T123 |
7984 |
89 |
0 |
0 |
T128 |
3402 |
95 |
0 |
0 |
T140 |
4496 |
3 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1721 |
0 |
0 |
T115 |
91029 |
57 |
0 |
0 |
T116 |
35197 |
43 |
0 |
0 |
T118 |
33435 |
41 |
0 |
0 |
T134 |
7129 |
5 |
0 |
0 |
T152 |
181711 |
454 |
0 |
0 |
T156 |
18546 |
24 |
0 |
0 |
T158 |
64981 |
91 |
0 |
0 |
T159 |
9968 |
14 |
0 |
0 |
T160 |
21147 |
65 |
0 |
0 |
T161 |
14411 |
7 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1789 |
0 |
0 |
T115 |
91029 |
84 |
0 |
0 |
T116 |
35197 |
58 |
0 |
0 |
T118 |
33435 |
39 |
0 |
0 |
T134 |
7129 |
8 |
0 |
0 |
T152 |
181711 |
463 |
0 |
0 |
T156 |
18546 |
22 |
0 |
0 |
T158 |
64981 |
58 |
0 |
0 |
T159 |
9968 |
4 |
0 |
0 |
T160 |
21147 |
86 |
0 |
0 |
T161 |
14411 |
30 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
2009 |
0 |
0 |
T115 |
91029 |
120 |
0 |
0 |
T116 |
35197 |
56 |
0 |
0 |
T118 |
33435 |
102 |
0 |
0 |
T134 |
7129 |
7 |
0 |
0 |
T152 |
181711 |
428 |
0 |
0 |
T156 |
18546 |
75 |
0 |
0 |
T158 |
64981 |
129 |
0 |
0 |
T159 |
9968 |
21 |
0 |
0 |
T160 |
21147 |
66 |
0 |
0 |
T161 |
14411 |
49 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
5832 |
0 |
0 |
T115 |
91029 |
747 |
0 |
0 |
T116 |
35197 |
861 |
0 |
0 |
T118 |
33435 |
666 |
0 |
0 |
T134 |
7129 |
25 |
0 |
0 |
T152 |
181711 |
469 |
0 |
0 |
T156 |
18546 |
28 |
0 |
0 |
T158 |
64981 |
884 |
0 |
0 |
T159 |
9968 |
123 |
0 |
0 |
T160 |
21147 |
108 |
0 |
0 |
T161 |
14411 |
352 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
6865 |
0 |
0 |
T115 |
91029 |
1100 |
0 |
0 |
T116 |
35197 |
911 |
0 |
0 |
T118 |
33435 |
496 |
0 |
0 |
T134 |
7129 |
8 |
0 |
0 |
T152 |
181711 |
490 |
0 |
0 |
T156 |
18546 |
46 |
0 |
0 |
T158 |
64981 |
1502 |
0 |
0 |
T159 |
9968 |
78 |
0 |
0 |
T160 |
21147 |
88 |
0 |
0 |
T161 |
14411 |
144 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
4765 |
0 |
0 |
T115 |
91029 |
1033 |
0 |
0 |
T116 |
35197 |
491 |
0 |
0 |
T118 |
33435 |
444 |
0 |
0 |
T134 |
7129 |
8 |
0 |
0 |
T152 |
181711 |
441 |
0 |
0 |
T156 |
18546 |
9 |
0 |
0 |
T158 |
64981 |
898 |
0 |
0 |
T159 |
9968 |
3 |
0 |
0 |
T160 |
21147 |
68 |
0 |
0 |
T161 |
14411 |
33 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
5149 |
0 |
0 |
T115 |
91029 |
784 |
0 |
0 |
T116 |
35197 |
571 |
0 |
0 |
T118 |
33435 |
383 |
0 |
0 |
T134 |
7129 |
28 |
0 |
0 |
T152 |
181711 |
448 |
0 |
0 |
T156 |
18546 |
20 |
0 |
0 |
T158 |
64981 |
951 |
0 |
0 |
T159 |
9968 |
78 |
0 |
0 |
T160 |
21147 |
67 |
0 |
0 |
T161 |
14411 |
135 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
5876 |
0 |
0 |
T115 |
91029 |
926 |
0 |
0 |
T116 |
35197 |
798 |
0 |
0 |
T118 |
33435 |
710 |
0 |
0 |
T134 |
7129 |
13 |
0 |
0 |
T152 |
181711 |
410 |
0 |
0 |
T156 |
18546 |
36 |
0 |
0 |
T158 |
64981 |
997 |
0 |
0 |
T159 |
9968 |
65 |
0 |
0 |
T160 |
21147 |
65 |
0 |
0 |
T161 |
14411 |
124 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
5390 |
0 |
0 |
T115 |
91029 |
968 |
0 |
0 |
T116 |
35197 |
464 |
0 |
0 |
T118 |
33435 |
518 |
0 |
0 |
T134 |
7129 |
7 |
0 |
0 |
T152 |
181711 |
446 |
0 |
0 |
T156 |
18546 |
36 |
0 |
0 |
T158 |
64981 |
1066 |
0 |
0 |
T159 |
9968 |
158 |
0 |
0 |
T160 |
21147 |
45 |
0 |
0 |
T161 |
14411 |
108 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
5678 |
0 |
0 |
T115 |
91029 |
1229 |
0 |
0 |
T116 |
35197 |
596 |
0 |
0 |
T118 |
33435 |
212 |
0 |
0 |
T152 |
181711 |
406 |
0 |
0 |
T156 |
18546 |
33 |
0 |
0 |
T158 |
64981 |
1318 |
0 |
0 |
T159 |
9968 |
12 |
0 |
0 |
T160 |
21147 |
113 |
0 |
0 |
T161 |
14411 |
137 |
0 |
0 |
T162 |
6579 |
2 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
6678 |
0 |
0 |
T115 |
91029 |
1014 |
0 |
0 |
T116 |
35197 |
449 |
0 |
0 |
T118 |
33435 |
691 |
0 |
0 |
T134 |
7129 |
27 |
0 |
0 |
T152 |
181711 |
466 |
0 |
0 |
T156 |
18546 |
36 |
0 |
0 |
T158 |
64981 |
1669 |
0 |
0 |
T159 |
9968 |
77 |
0 |
0 |
T160 |
21147 |
64 |
0 |
0 |
T161 |
14411 |
216 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3216 |
0 |
0 |
T115 |
91029 |
483 |
0 |
0 |
T116 |
35197 |
202 |
0 |
0 |
T118 |
33435 |
334 |
0 |
0 |
T134 |
7129 |
63 |
0 |
0 |
T152 |
181711 |
434 |
0 |
0 |
T156 |
18546 |
39 |
0 |
0 |
T158 |
64981 |
379 |
0 |
0 |
T159 |
9968 |
29 |
0 |
0 |
T160 |
21147 |
52 |
0 |
0 |
T161 |
14411 |
108 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3391 |
0 |
0 |
T115 |
91029 |
489 |
0 |
0 |
T116 |
35197 |
161 |
0 |
0 |
T118 |
33435 |
171 |
0 |
0 |
T134 |
7129 |
46 |
0 |
0 |
T152 |
181711 |
513 |
0 |
0 |
T156 |
18546 |
13 |
0 |
0 |
T158 |
64981 |
520 |
0 |
0 |
T159 |
9968 |
5 |
0 |
0 |
T160 |
21147 |
104 |
0 |
0 |
T161 |
14411 |
145 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3291 |
0 |
0 |
T115 |
91029 |
410 |
0 |
0 |
T116 |
35197 |
291 |
0 |
0 |
T118 |
33435 |
285 |
0 |
0 |
T134 |
7129 |
10 |
0 |
0 |
T152 |
181711 |
395 |
0 |
0 |
T156 |
18546 |
43 |
0 |
0 |
T158 |
64981 |
524 |
0 |
0 |
T159 |
9968 |
18 |
0 |
0 |
T160 |
21147 |
25 |
0 |
0 |
T161 |
14411 |
59 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3797 |
0 |
0 |
T115 |
91029 |
561 |
0 |
0 |
T116 |
35197 |
158 |
0 |
0 |
T118 |
33435 |
396 |
0 |
0 |
T134 |
7129 |
25 |
0 |
0 |
T152 |
181711 |
394 |
0 |
0 |
T156 |
18546 |
66 |
0 |
0 |
T158 |
64981 |
810 |
0 |
0 |
T159 |
9968 |
35 |
0 |
0 |
T160 |
21147 |
77 |
0 |
0 |
T161 |
14411 |
62 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3870 |
0 |
0 |
T115 |
91029 |
409 |
0 |
0 |
T116 |
35197 |
387 |
0 |
0 |
T118 |
33435 |
225 |
0 |
0 |
T134 |
7129 |
14 |
0 |
0 |
T152 |
181711 |
450 |
0 |
0 |
T156 |
18546 |
24 |
0 |
0 |
T158 |
64981 |
578 |
0 |
0 |
T159 |
9968 |
30 |
0 |
0 |
T160 |
21147 |
71 |
0 |
0 |
T161 |
14411 |
150 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
4025 |
0 |
0 |
T115 |
91029 |
419 |
0 |
0 |
T116 |
35197 |
309 |
0 |
0 |
T118 |
33435 |
397 |
0 |
0 |
T134 |
7129 |
17 |
0 |
0 |
T152 |
181711 |
488 |
0 |
0 |
T156 |
18546 |
37 |
0 |
0 |
T158 |
64981 |
797 |
0 |
0 |
T159 |
9968 |
58 |
0 |
0 |
T160 |
21147 |
49 |
0 |
0 |
T161 |
14411 |
129 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3456 |
0 |
0 |
T115 |
91029 |
344 |
0 |
0 |
T116 |
35197 |
260 |
0 |
0 |
T118 |
33435 |
356 |
0 |
0 |
T134 |
7129 |
5 |
0 |
0 |
T152 |
181711 |
467 |
0 |
0 |
T156 |
18546 |
39 |
0 |
0 |
T158 |
64981 |
520 |
0 |
0 |
T159 |
9968 |
55 |
0 |
0 |
T160 |
21147 |
60 |
0 |
0 |
T161 |
14411 |
123 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3023 |
0 |
0 |
T115 |
91029 |
433 |
0 |
0 |
T116 |
35197 |
178 |
0 |
0 |
T118 |
33435 |
266 |
0 |
0 |
T134 |
7129 |
52 |
0 |
0 |
T152 |
181711 |
419 |
0 |
0 |
T156 |
18546 |
46 |
0 |
0 |
T158 |
64981 |
281 |
0 |
0 |
T159 |
9968 |
19 |
0 |
0 |
T160 |
21147 |
59 |
0 |
0 |
T161 |
14411 |
84 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3310 |
0 |
0 |
T115 |
91029 |
333 |
0 |
0 |
T116 |
35197 |
253 |
0 |
0 |
T118 |
33435 |
345 |
0 |
0 |
T134 |
7129 |
29 |
0 |
0 |
T152 |
181711 |
456 |
0 |
0 |
T156 |
18546 |
14 |
0 |
0 |
T158 |
64981 |
504 |
0 |
0 |
T159 |
9968 |
27 |
0 |
0 |
T160 |
21147 |
81 |
0 |
0 |
T161 |
14411 |
79 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3347 |
0 |
0 |
T115 |
91029 |
480 |
0 |
0 |
T116 |
35197 |
250 |
0 |
0 |
T118 |
33435 |
302 |
0 |
0 |
T134 |
7129 |
36 |
0 |
0 |
T152 |
181711 |
466 |
0 |
0 |
T156 |
18546 |
38 |
0 |
0 |
T158 |
64981 |
391 |
0 |
0 |
T159 |
9968 |
35 |
0 |
0 |
T160 |
21147 |
79 |
0 |
0 |
T161 |
14411 |
75 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3634 |
0 |
0 |
T115 |
91029 |
488 |
0 |
0 |
T116 |
35197 |
280 |
0 |
0 |
T118 |
33435 |
358 |
0 |
0 |
T134 |
7129 |
5 |
0 |
0 |
T152 |
181711 |
488 |
0 |
0 |
T156 |
18546 |
44 |
0 |
0 |
T158 |
64981 |
605 |
0 |
0 |
T159 |
9968 |
10 |
0 |
0 |
T160 |
21147 |
61 |
0 |
0 |
T161 |
14411 |
62 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3094 |
0 |
0 |
T115 |
91029 |
440 |
0 |
0 |
T116 |
35197 |
173 |
0 |
0 |
T118 |
33435 |
206 |
0 |
0 |
T152 |
181711 |
430 |
0 |
0 |
T156 |
18546 |
5 |
0 |
0 |
T158 |
64981 |
578 |
0 |
0 |
T159 |
9968 |
42 |
0 |
0 |
T160 |
21147 |
36 |
0 |
0 |
T161 |
14411 |
41 |
0 |
0 |
T162 |
6579 |
9 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3645 |
0 |
0 |
T115 |
91029 |
435 |
0 |
0 |
T116 |
35197 |
356 |
0 |
0 |
T118 |
33435 |
247 |
0 |
0 |
T134 |
7129 |
37 |
0 |
0 |
T152 |
181711 |
491 |
0 |
0 |
T156 |
18546 |
42 |
0 |
0 |
T158 |
64981 |
421 |
0 |
0 |
T159 |
9968 |
28 |
0 |
0 |
T160 |
21147 |
60 |
0 |
0 |
T161 |
14411 |
144 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3731 |
0 |
0 |
T115 |
91029 |
555 |
0 |
0 |
T116 |
35197 |
345 |
0 |
0 |
T118 |
33435 |
275 |
0 |
0 |
T134 |
7129 |
25 |
0 |
0 |
T152 |
181711 |
446 |
0 |
0 |
T156 |
18546 |
35 |
0 |
0 |
T158 |
64981 |
615 |
0 |
0 |
T159 |
9968 |
9 |
0 |
0 |
T160 |
21147 |
57 |
0 |
0 |
T161 |
14411 |
91 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3476 |
0 |
0 |
T115 |
91029 |
535 |
0 |
0 |
T116 |
35197 |
45 |
0 |
0 |
T118 |
33435 |
348 |
0 |
0 |
T134 |
7129 |
1 |
0 |
0 |
T152 |
181711 |
469 |
0 |
0 |
T156 |
18546 |
45 |
0 |
0 |
T158 |
64981 |
454 |
0 |
0 |
T159 |
9968 |
43 |
0 |
0 |
T160 |
21147 |
72 |
0 |
0 |
T161 |
14411 |
56 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3378 |
0 |
0 |
T115 |
91029 |
549 |
0 |
0 |
T116 |
35197 |
262 |
0 |
0 |
T118 |
33435 |
228 |
0 |
0 |
T134 |
7129 |
18 |
0 |
0 |
T152 |
181711 |
428 |
0 |
0 |
T156 |
18546 |
52 |
0 |
0 |
T158 |
64981 |
438 |
0 |
0 |
T159 |
9968 |
4 |
0 |
0 |
T160 |
21147 |
49 |
0 |
0 |
T161 |
14411 |
68 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3565 |
0 |
0 |
T115 |
91029 |
433 |
0 |
0 |
T116 |
35197 |
286 |
0 |
0 |
T118 |
33435 |
233 |
0 |
0 |
T134 |
7129 |
26 |
0 |
0 |
T152 |
181711 |
483 |
0 |
0 |
T156 |
18546 |
40 |
0 |
0 |
T158 |
64981 |
576 |
0 |
0 |
T159 |
9968 |
73 |
0 |
0 |
T160 |
21147 |
43 |
0 |
0 |
T161 |
14411 |
83 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3095 |
0 |
0 |
T115 |
91029 |
446 |
0 |
0 |
T116 |
35197 |
225 |
0 |
0 |
T118 |
33435 |
212 |
0 |
0 |
T134 |
7129 |
55 |
0 |
0 |
T152 |
181711 |
420 |
0 |
0 |
T156 |
18546 |
38 |
0 |
0 |
T158 |
64981 |
450 |
0 |
0 |
T159 |
9968 |
13 |
0 |
0 |
T160 |
21147 |
59 |
0 |
0 |
T161 |
14411 |
73 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3613 |
0 |
0 |
T115 |
91029 |
478 |
0 |
0 |
T116 |
35197 |
224 |
0 |
0 |
T118 |
33435 |
328 |
0 |
0 |
T134 |
7129 |
24 |
0 |
0 |
T152 |
181711 |
495 |
0 |
0 |
T156 |
18546 |
45 |
0 |
0 |
T158 |
64981 |
476 |
0 |
0 |
T159 |
9968 |
39 |
0 |
0 |
T160 |
21147 |
42 |
0 |
0 |
T161 |
14411 |
55 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3160 |
0 |
0 |
T115 |
91029 |
425 |
0 |
0 |
T116 |
35197 |
331 |
0 |
0 |
T118 |
33435 |
248 |
0 |
0 |
T152 |
181711 |
419 |
0 |
0 |
T156 |
18546 |
37 |
0 |
0 |
T158 |
64981 |
480 |
0 |
0 |
T159 |
9968 |
33 |
0 |
0 |
T160 |
21147 |
93 |
0 |
0 |
T161 |
14411 |
22 |
0 |
0 |
T162 |
6579 |
1 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3326 |
0 |
0 |
T115 |
91029 |
303 |
0 |
0 |
T116 |
35197 |
220 |
0 |
0 |
T118 |
33435 |
422 |
0 |
0 |
T134 |
7129 |
37 |
0 |
0 |
T152 |
181711 |
433 |
0 |
0 |
T156 |
18546 |
35 |
0 |
0 |
T158 |
64981 |
383 |
0 |
0 |
T159 |
9968 |
58 |
0 |
0 |
T160 |
21147 |
36 |
0 |
0 |
T161 |
14411 |
100 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3518 |
0 |
0 |
T115 |
91029 |
433 |
0 |
0 |
T116 |
35197 |
188 |
0 |
0 |
T118 |
33435 |
303 |
0 |
0 |
T134 |
7129 |
27 |
0 |
0 |
T152 |
181711 |
458 |
0 |
0 |
T156 |
18546 |
38 |
0 |
0 |
T158 |
64981 |
619 |
0 |
0 |
T159 |
9968 |
50 |
0 |
0 |
T160 |
21147 |
98 |
0 |
0 |
T161 |
14411 |
50 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3496 |
0 |
0 |
T115 |
91029 |
598 |
0 |
0 |
T116 |
35197 |
260 |
0 |
0 |
T118 |
33435 |
277 |
0 |
0 |
T134 |
7129 |
31 |
0 |
0 |
T152 |
181711 |
458 |
0 |
0 |
T156 |
18546 |
46 |
0 |
0 |
T158 |
64981 |
434 |
0 |
0 |
T159 |
9968 |
8 |
0 |
0 |
T160 |
21147 |
29 |
0 |
0 |
T161 |
14411 |
124 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3336 |
0 |
0 |
T115 |
91029 |
403 |
0 |
0 |
T116 |
35197 |
177 |
0 |
0 |
T118 |
33435 |
229 |
0 |
0 |
T123 |
7984 |
8 |
0 |
0 |
T134 |
7129 |
33 |
0 |
0 |
T152 |
181711 |
456 |
0 |
0 |
T156 |
18546 |
44 |
0 |
0 |
T158 |
64981 |
573 |
0 |
0 |
T159 |
9968 |
23 |
0 |
0 |
T160 |
21147 |
58 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1901 |
0 |
0 |
T115 |
91029 |
88 |
0 |
0 |
T116 |
35197 |
50 |
0 |
0 |
T118 |
33435 |
76 |
0 |
0 |
T134 |
7129 |
19 |
0 |
0 |
T152 |
181711 |
426 |
0 |
0 |
T156 |
18546 |
11 |
0 |
0 |
T158 |
64981 |
151 |
0 |
0 |
T159 |
9968 |
22 |
0 |
0 |
T160 |
21147 |
69 |
0 |
0 |
T161 |
14411 |
32 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1894 |
0 |
0 |
T115 |
91029 |
109 |
0 |
0 |
T116 |
35197 |
59 |
0 |
0 |
T118 |
33435 |
43 |
0 |
0 |
T134 |
7129 |
23 |
0 |
0 |
T152 |
181711 |
445 |
0 |
0 |
T156 |
18546 |
18 |
0 |
0 |
T158 |
64981 |
107 |
0 |
0 |
T159 |
9968 |
23 |
0 |
0 |
T160 |
21147 |
48 |
0 |
0 |
T161 |
14411 |
21 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1904 |
0 |
0 |
T115 |
91029 |
81 |
0 |
0 |
T116 |
35197 |
59 |
0 |
0 |
T118 |
33435 |
45 |
0 |
0 |
T134 |
7129 |
26 |
0 |
0 |
T152 |
181711 |
453 |
0 |
0 |
T156 |
18546 |
29 |
0 |
0 |
T158 |
64981 |
114 |
0 |
0 |
T159 |
9968 |
8 |
0 |
0 |
T160 |
21147 |
56 |
0 |
0 |
T161 |
14411 |
44 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1894 |
0 |
0 |
T115 |
91029 |
94 |
0 |
0 |
T116 |
35197 |
63 |
0 |
0 |
T118 |
33435 |
70 |
0 |
0 |
T134 |
7129 |
12 |
0 |
0 |
T152 |
181711 |
436 |
0 |
0 |
T156 |
18546 |
13 |
0 |
0 |
T158 |
64981 |
103 |
0 |
0 |
T159 |
9968 |
14 |
0 |
0 |
T160 |
21147 |
131 |
0 |
0 |
T161 |
14411 |
14 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
2298 |
0 |
0 |
T115 |
91029 |
219 |
0 |
0 |
T116 |
35197 |
97 |
0 |
0 |
T118 |
33435 |
98 |
0 |
0 |
T134 |
7129 |
31 |
0 |
0 |
T152 |
181711 |
470 |
0 |
0 |
T156 |
18546 |
31 |
0 |
0 |
T158 |
64981 |
176 |
0 |
0 |
T159 |
9968 |
17 |
0 |
0 |
T160 |
21147 |
17 |
0 |
0 |
T161 |
14411 |
22 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
3221 |
0 |
0 |
T37 |
4742 |
42 |
0 |
0 |
T69 |
104777 |
0 |
0 |
0 |
T115 |
0 |
333 |
0 |
0 |
T116 |
0 |
155 |
0 |
0 |
T134 |
0 |
36 |
0 |
0 |
T163 |
0 |
4 |
0 |
0 |
T164 |
0 |
105 |
0 |
0 |
T165 |
0 |
81 |
0 |
0 |
T166 |
0 |
12 |
0 |
0 |
T167 |
0 |
8 |
0 |
0 |
T168 |
0 |
23 |
0 |
0 |
T169 |
1224 |
0 |
0 |
0 |
T170 |
109498 |
0 |
0 |
0 |
T171 |
1183 |
0 |
0 |
0 |
T172 |
1599 |
0 |
0 |
0 |
T173 |
337908 |
0 |
0 |
0 |
T174 |
2915 |
0 |
0 |
0 |
T175 |
43717 |
0 |
0 |
0 |
T176 |
98353 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1785 |
0 |
0 |
T115 |
91029 |
57 |
0 |
0 |
T116 |
35197 |
70 |
0 |
0 |
T118 |
33435 |
46 |
0 |
0 |
T134 |
7129 |
12 |
0 |
0 |
T152 |
181711 |
436 |
0 |
0 |
T156 |
18546 |
11 |
0 |
0 |
T158 |
64981 |
138 |
0 |
0 |
T159 |
9968 |
9 |
0 |
0 |
T160 |
21147 |
63 |
0 |
0 |
T161 |
14411 |
27 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1857 |
0 |
0 |
T115 |
91029 |
72 |
0 |
0 |
T116 |
35197 |
49 |
0 |
0 |
T118 |
33435 |
58 |
0 |
0 |
T134 |
7129 |
16 |
0 |
0 |
T152 |
181711 |
442 |
0 |
0 |
T156 |
18546 |
34 |
0 |
0 |
T158 |
64981 |
145 |
0 |
0 |
T159 |
9968 |
1 |
0 |
0 |
T160 |
21147 |
69 |
0 |
0 |
T161 |
14411 |
22 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1864 |
0 |
0 |
T115 |
91029 |
53 |
0 |
0 |
T116 |
35197 |
46 |
0 |
0 |
T118 |
33435 |
44 |
0 |
0 |
T134 |
7129 |
38 |
0 |
0 |
T152 |
181711 |
476 |
0 |
0 |
T156 |
18546 |
8 |
0 |
0 |
T158 |
64981 |
82 |
0 |
0 |
T159 |
9968 |
3 |
0 |
0 |
T160 |
21147 |
70 |
0 |
0 |
T161 |
14411 |
27 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1808 |
0 |
0 |
T115 |
91029 |
84 |
0 |
0 |
T116 |
35197 |
34 |
0 |
0 |
T118 |
33435 |
43 |
0 |
0 |
T134 |
7129 |
22 |
0 |
0 |
T152 |
181711 |
465 |
0 |
0 |
T156 |
18546 |
30 |
0 |
0 |
T158 |
64981 |
66 |
0 |
0 |
T159 |
9968 |
8 |
0 |
0 |
T160 |
21147 |
63 |
0 |
0 |
T161 |
14411 |
13 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1769 |
0 |
0 |
T115 |
91029 |
77 |
0 |
0 |
T116 |
35197 |
58 |
0 |
0 |
T118 |
33435 |
54 |
0 |
0 |
T134 |
7129 |
17 |
0 |
0 |
T152 |
181711 |
422 |
0 |
0 |
T156 |
18546 |
19 |
0 |
0 |
T158 |
64981 |
79 |
0 |
0 |
T159 |
9968 |
4 |
0 |
0 |
T160 |
21147 |
77 |
0 |
0 |
T161 |
14411 |
20 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1781 |
0 |
0 |
T115 |
91029 |
39 |
0 |
0 |
T116 |
35197 |
48 |
0 |
0 |
T118 |
33435 |
61 |
0 |
0 |
T134 |
7129 |
36 |
0 |
0 |
T152 |
181711 |
503 |
0 |
0 |
T156 |
18546 |
40 |
0 |
0 |
T158 |
64981 |
57 |
0 |
0 |
T159 |
9968 |
4 |
0 |
0 |
T160 |
21147 |
87 |
0 |
0 |
T161 |
14411 |
7 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
2188 |
0 |
0 |
T115 |
91029 |
116 |
0 |
0 |
T116 |
35197 |
101 |
0 |
0 |
T118 |
33435 |
70 |
0 |
0 |
T134 |
7129 |
27 |
0 |
0 |
T152 |
181711 |
421 |
0 |
0 |
T156 |
18546 |
51 |
0 |
0 |
T158 |
64981 |
214 |
0 |
0 |
T159 |
9968 |
18 |
0 |
0 |
T160 |
21147 |
66 |
0 |
0 |
T161 |
14411 |
40 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1819 |
0 |
0 |
T115 |
91029 |
36 |
0 |
0 |
T116 |
35197 |
48 |
0 |
0 |
T118 |
33435 |
32 |
0 |
0 |
T134 |
7129 |
7 |
0 |
0 |
T152 |
181711 |
463 |
0 |
0 |
T156 |
18546 |
16 |
0 |
0 |
T158 |
64981 |
88 |
0 |
0 |
T159 |
9968 |
11 |
0 |
0 |
T160 |
21147 |
78 |
0 |
0 |
T161 |
14411 |
22 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
2383 |
0 |
0 |
T115 |
91029 |
142 |
0 |
0 |
T116 |
35197 |
105 |
0 |
0 |
T118 |
33435 |
148 |
0 |
0 |
T134 |
7129 |
25 |
0 |
0 |
T152 |
181711 |
446 |
0 |
0 |
T156 |
18546 |
48 |
0 |
0 |
T158 |
64981 |
299 |
0 |
0 |
T159 |
9968 |
22 |
0 |
0 |
T160 |
21147 |
83 |
0 |
0 |
T161 |
14411 |
53 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1813 |
0 |
0 |
T115 |
91029 |
100 |
0 |
0 |
T116 |
35197 |
58 |
0 |
0 |
T118 |
33435 |
60 |
0 |
0 |
T134 |
7129 |
16 |
0 |
0 |
T152 |
181711 |
456 |
0 |
0 |
T156 |
18546 |
23 |
0 |
0 |
T158 |
64981 |
105 |
0 |
0 |
T159 |
9968 |
11 |
0 |
0 |
T160 |
21147 |
54 |
0 |
0 |
T161 |
14411 |
30 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1614 |
0 |
0 |
T115 |
91029 |
56 |
0 |
0 |
T116 |
35197 |
30 |
0 |
0 |
T118 |
33435 |
43 |
0 |
0 |
T134 |
7129 |
7 |
0 |
0 |
T152 |
181711 |
443 |
0 |
0 |
T156 |
18546 |
20 |
0 |
0 |
T158 |
64981 |
102 |
0 |
0 |
T159 |
9968 |
10 |
0 |
0 |
T160 |
21147 |
41 |
0 |
0 |
T161 |
14411 |
11 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1599 |
0 |
0 |
T115 |
91029 |
77 |
0 |
0 |
T116 |
35197 |
28 |
0 |
0 |
T118 |
33435 |
47 |
0 |
0 |
T134 |
7129 |
1 |
0 |
0 |
T152 |
181711 |
416 |
0 |
0 |
T156 |
18546 |
3 |
0 |
0 |
T158 |
64981 |
69 |
0 |
0 |
T159 |
9968 |
5 |
0 |
0 |
T160 |
21147 |
36 |
0 |
0 |
T161 |
14411 |
17 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1759 |
0 |
0 |
T115 |
91029 |
73 |
0 |
0 |
T116 |
35197 |
28 |
0 |
0 |
T118 |
33435 |
29 |
0 |
0 |
T134 |
7129 |
2 |
0 |
0 |
T152 |
181711 |
438 |
0 |
0 |
T156 |
18546 |
67 |
0 |
0 |
T158 |
64981 |
79 |
0 |
0 |
T159 |
9968 |
8 |
0 |
0 |
T160 |
21147 |
95 |
0 |
0 |
T161 |
14411 |
16 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1774 |
0 |
0 |
T115 |
91029 |
52 |
0 |
0 |
T116 |
35197 |
41 |
0 |
0 |
T118 |
33435 |
46 |
0 |
0 |
T134 |
7129 |
15 |
0 |
0 |
T152 |
181711 |
468 |
0 |
0 |
T156 |
18546 |
17 |
0 |
0 |
T158 |
64981 |
80 |
0 |
0 |
T160 |
21147 |
89 |
0 |
0 |
T161 |
14411 |
27 |
0 |
0 |
T162 |
6579 |
16 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1787 |
0 |
0 |
T115 |
91029 |
73 |
0 |
0 |
T116 |
35197 |
39 |
0 |
0 |
T118 |
33435 |
38 |
0 |
0 |
T134 |
7129 |
8 |
0 |
0 |
T152 |
181711 |
462 |
0 |
0 |
T156 |
18546 |
79 |
0 |
0 |
T158 |
64981 |
101 |
0 |
0 |
T159 |
9968 |
3 |
0 |
0 |
T160 |
21147 |
83 |
0 |
0 |
T161 |
14411 |
11 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
127414472 |
1790 |
0 |
0 |
T115 |
91029 |
47 |
0 |
0 |
T116 |
35197 |
27 |
0 |
0 |
T118 |
33435 |
23 |
0 |
0 |
T134 |
7129 |
12 |
0 |
0 |
T152 |
181711 |
458 |
0 |
0 |
T156 |
18546 |
41 |
0 |
0 |
T158 |
64981 |
61 |
0 |
0 |
T159 |
9968 |
3 |
0 |
0 |
T160 |
21147 |
83 |
0 |
0 |
T161 |
14411 |
13 |
0 |
0 |