Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1507990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1613550

1

T1

1081

T2

1487

T3

96

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2475196	1			T1	364		T2	1192		T3	988
values[0x0]	322551	1			T1	472		T2	452		T3	50
values[0x1]	323793	1			T1	447		T2	438		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1143029	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1978511

1

T1

1120

T2

1603

T3

438

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15387	1			T2	2		T3	4		T4	1
valid_sources[0x01]	8620	1			T2	13		T3	3		T4	4
valid_sources[0x02]	13635	1			T2	10		T3	8		T4	5
valid_sources[0x03]	11879	1			T2	8		T3	5		T4	2
valid_sources[0x04]	10828	1			T2	8		T3	3		T4	2
valid_sources[0x05]	9906	1			T2	8		T3	2		T4	2
valid_sources[0x06]	9638	1			T2	4		T3	3		T4	6
valid_sources[0x07]	8540	1			T2	14		T3	8		T4	3
valid_sources[0x08]	14403	1			T2	9		T3	2		T4	5
valid_sources[0x09]	15827	1			T2	7		T3	4		T4	5
valid_sources[0x0a]	9380	1			T2	7		T3	3		T4	4
valid_sources[0x0b]	10469	1			T2	15		T3	1		T4	2
valid_sources[0x0c]	9551	1			T2	10		T3	4		T4	2
valid_sources[0x0d]	9879	1			T2	6		T3	4		T4	2
valid_sources[0x0e]	10280	1			T2	2		T3	2		T4	4
valid_sources[0x0f]	10464	1			T2	4		T3	3		T4	3
valid_sources[0x10]	11714	1			T2	6		T3	5		T4	2
valid_sources[0x11]	10950	1			T2	4		T3	8		T4	2
valid_sources[0x12]	9159	1			T2	7		T3	7		T4	2
valid_sources[0x13]	107580	1			T2	11		T3	5		T4	1
valid_sources[0x14]	8899	1			T2	11		T3	4		T4	4
valid_sources[0x15]	9022	1			T2	6		T3	4		T4	3
valid_sources[0x16]	10126	1			T1	27		T2	11		T3	7
valid_sources[0x17]	24385	1			T2	3		T3	3		T4	5
valid_sources[0x18]	10384	1			T1	68		T2	9		T3	4
valid_sources[0x19]	11730	1			T2	4		T3	3		T4	2
valid_sources[0x1a]	22406	1			T2	11		T3	4		T4	5
valid_sources[0x1b]	9045	1			T1	16		T2	6		T3	2
valid_sources[0x1c]	16142	1			T2	18		T3	3		T4	1
valid_sources[0x1d]	10290	1			T2	8		T3	2		T4	5
valid_sources[0x1e]	11412	1			T2	15		T3	2		T4	6
valid_sources[0x1f]	9407	1			T2	7		T3	6		T4	5
valid_sources[0x20]	9607	1			T2	8		T3	4		T4	4
valid_sources[0x21]	54510	1			T2	8		T3	2		T4	3
valid_sources[0x22]	21165	1			T2	4		T3	6		T4	7
valid_sources[0x23]	9812	1			T2	6		T3	6		T4	2
valid_sources[0x24]	10183	1			T2	6		T3	1		T4	2
valid_sources[0x25]	8820	1			T2	7		T3	2		T4	6
valid_sources[0x26]	10828	1			T2	17		T3	3		T4	6
valid_sources[0x27]	9136	1			T2	11		T3	8		T4	3
valid_sources[0x28]	9249	1			T1	12		T2	7		T3	3
valid_sources[0x29]	10046	1			T2	8		T3	4		T4	2
valid_sources[0x2a]	9092	1			T1	24		T2	13		T3	5
valid_sources[0x2b]	8751	1			T2	7		T3	3		T4	3
valid_sources[0x2c]	11443	1			T2	11		T3	5		T4	3
valid_sources[0x2d]	10610	1			T2	9		T3	1		T4	7
valid_sources[0x2e]	9546	1			T2	6		T3	4		T4	2
valid_sources[0x2f]	8635	1			T2	7		T3	4		T4	6
valid_sources[0x30]	11306	1			T2	13		T3	5		T4	3
valid_sources[0x31]	9620	1			T2	8		T3	3		T4	5
valid_sources[0x32]	8911	1			T2	9		T3	6		T4	3
valid_sources[0x33]	11347	1			T2	6		T3	3		T4	8
valid_sources[0x34]	11569	1			T2	6		T3	6		T4	3
valid_sources[0x35]	9091	1			T2	12		T3	6		T4	1
valid_sources[0x36]	11888	1			T2	13		T3	4		T4	7
valid_sources[0x37]	10912	1			T1	30		T2	13		T3	3
valid_sources[0x38]	8856	1			T2	7		T3	2		T4	5
valid_sources[0x39]	10138	1			T2	3		T3	6		T4	1
valid_sources[0x3a]	10477	1			T1	32		T2	8		T3	6
valid_sources[0x3b]	12056	1			T2	9		T3	4		T4	1
valid_sources[0x3c]	15099	1			T2	7		T3	3		T4	6
valid_sources[0x3d]	10734	1			T2	7		T3	2		T4	4
valid_sources[0x3e]	9442	1			T2	6		T3	3		T4	2
valid_sources[0x3f]	9359	1			T2	8		T3	7		T4	4
valid_sources[0x40]	10693	1			T2	5		T3	4		T4	3
valid_sources[0x41]	9416	1			T2	7		T3	4		T4	4
valid_sources[0x42]	11246	1			T2	8		T3	5		T4	3
valid_sources[0x43]	9480	1			T2	7		T3	4		T4	3
valid_sources[0x44]	13268	1			T2	5		T3	4		T4	1
valid_sources[0x45]	15236	1			T2	7		T3	2		T4	5
valid_sources[0x46]	10428	1			T2	10		T3	5		T5	3
valid_sources[0x47]	19640	1			T2	8		T3	2		T4	5
valid_sources[0x48]	9581	1			T2	11		T3	4		T4	3
valid_sources[0x49]	12838	1			T2	7		T3	2		T4	3
valid_sources[0x4a]	9838	1			T2	12		T3	2		T4	6
valid_sources[0x4b]	8448	1			T2	17		T4	2		T5	2
valid_sources[0x4c]	9996	1			T2	7		T3	2		T4	5
valid_sources[0x4d]	9340	1			T2	9		T3	5		T4	3
valid_sources[0x4e]	10745	1			T2	5		T3	4		T4	1
valid_sources[0x4f]	8866	1			T1	24		T2	4		T3	3
valid_sources[0x50]	14562	1			T2	6		T3	3		T5	2
valid_sources[0x51]	11037	1			T2	13		T3	3		T4	4
valid_sources[0x52]	9947	1			T2	8		T3	5		T4	2
valid_sources[0x53]	9204	1			T1	8		T2	5		T3	7
valid_sources[0x54]	10252	1			T1	20		T2	7		T3	8
valid_sources[0x55]	9330	1			T2	8		T3	6		T4	5
valid_sources[0x56]	8658	1			T2	5		T3	9		T4	10
valid_sources[0x57]	9175	1			T2	11		T3	1		T4	4
valid_sources[0x58]	17832	1			T2	8		T3	2		T4	5
valid_sources[0x59]	8943	1			T2	8		T3	3		T4	7
valid_sources[0x5a]	10492	1			T2	11		T3	3		T4	1
valid_sources[0x5b]	10293	1			T2	12		T3	6		T4	1
valid_sources[0x5c]	9906	1			T1	107		T2	7		T3	8
valid_sources[0x5d]	13004	1			T2	4		T3	2		T4	4
valid_sources[0x5e]	10832	1			T2	7		T3	6		T4	4
valid_sources[0x5f]	9493	1			T2	4		T3	3		T4	7
valid_sources[0x60]	10556	1			T2	8		T3	2		T4	7
valid_sources[0x61]	8824	1			T2	12		T3	2		T4	4
valid_sources[0x62]	11168	1			T2	8		T3	2		T4	8
valid_sources[0x63]	12277	1			T2	11		T3	4		T4	5
valid_sources[0x64]	9270	1			T2	10		T3	10		T4	4
valid_sources[0x65]	8756	1			T2	9		T3	4		T4	1
valid_sources[0x66]	11608	1			T1	32		T2	12		T3	2
valid_sources[0x67]	22289	1			T1	24		T2	6		T3	3
valid_sources[0x68]	17333	1			T1	54		T2	10		T3	12
valid_sources[0x69]	9741	1			T2	4		T3	1		T4	3
valid_sources[0x6a]	13211	1			T2	5		T3	8		T4	4
valid_sources[0x6b]	15689	1			T2	9		T3	5		T5	5
valid_sources[0x6c]	8939	1			T1	19		T2	10		T3	10
valid_sources[0x6d]	12474	1			T2	4		T3	3		T4	4
valid_sources[0x6e]	12259	1			T2	6		T3	4		T4	4
valid_sources[0x6f]	9086	1			T2	3		T3	5		T4	4
valid_sources[0x70]	13298	1			T2	12		T3	2		T4	5
valid_sources[0x71]	9838	1			T2	8		T3	5		T4	2
valid_sources[0x72]	9915	1			T2	7		T3	6		T4	4
valid_sources[0x73]	11199	1			T2	5		T3	2		T4	1
valid_sources[0x74]	22597	1			T1	18		T2	1		T3	2
valid_sources[0x75]	9572	1			T2	15		T3	2		T4	2
valid_sources[0x76]	9259	1			T2	6		T3	4		T4	4
valid_sources[0x77]	9806	1			T2	9		T3	6		T4	1
valid_sources[0x78]	8291	1			T2	10		T3	5		T4	6
valid_sources[0x79]	11690	1			T1	7		T2	12		T3	5
valid_sources[0x7a]	9152	1			T2	6		T3	11		T4	3
valid_sources[0x7b]	27578	1			T2	11		T3	5		T4	3
valid_sources[0x7c]	9403	1			T2	4		T3	5		T4	6
valid_sources[0x7d]	9755	1			T2	12		T3	8		T4	4
valid_sources[0x7e]	9798	1			T1	32		T2	12		T3	3
valid_sources[0x7f]	12559	1			T2	4		T3	7		T4	3
valid_sources[0x80]	10154	1			T2	11		T3	3		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1028619

1

T1

170

T2

605

T3

44

values[0x0]

all_enables

biggest_size

295401

1

T1

472

T2

449

T3

31

values[0x1]

all_enables

biggest_size

289530

1

T1

439

T2

433

T3

21