Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1530025

1

T1

202

T2

595

T3

977

full_word

1614848

1

T1

1081

T2

1487

T3

96

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3144453	1			T1	1283		T2	2082		T3	1073
auto[TlIntgErrCmd]	149	1			T115	5		T116	9		T123	4
auto[TlIntgErrData]	132	1			T115	9		T116	7		T123	4
auto[TlIntgErrBoth]	139	1			T115	6		T116	4		T123	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2478955

1

T1

364

T2

1192

T3

988

auto[1]

665918

1

T1

919

T2

890

T3

85

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1449815	1			T1	194		T2	587		T3	944
auto[TlIntgErrNone]	partial	auto[1]	79826	1			T1	8		T2	8		T3	33
auto[TlIntgErrNone]	full_word	auto[0]	1028937	1			T1	170		T2	605		T3	44
auto[TlIntgErrNone]	full_word	auto[1]	585875	1			T1	911		T2	882		T3	52
auto[TlIntgErrCmd]	partial	auto[0]	63	1			T115	3		T116	3		T123	1
auto[TlIntgErrCmd]	partial	auto[1]	72	1			T115	1		T116	6		T123	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T115	1		T383	1		T387	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T385	1		T383	1		T384	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T115	5		T116	4		T123	3
auto[TlIntgErrData]	partial	auto[1]	54	1			T115	4		T116	2		T123	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T116	1		T384	1		T388	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T162	1		T385	2		T383	1
auto[TlIntgErrBoth]	partial	auto[0]	61	1			T115	4		T116	1		T123	1
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T115	2		T116	3		T162	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T123	1		T383	1		T384	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T389	1		T390	1		T391	1