Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.34	100.00	70.37			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	55.51	86.36	44.44			60.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.51	86.36	44.44			60.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
55.51	86.36

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T3,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Unreachable
1	1	Covered	T3,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
55.51	44.44

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	200397224	160844674	0	0
CheckNGreaterZero_A	1989	1989	0	0
GntImpliesReady_A	200397224	671154	0	0
GntImpliesValid_A	200397224	671154	0	0
GrantKnown_A	200397224	160844674	0	0
IdxKnown_A	200397224	160844674	0	0
IndexIsCorrect_A	200397224	671154	0	0
LockArbDecision_A	200397224	0	0	0
NoReadyValidNoGrant_A	200397224	0	0	0
ReadyAndValidImplyGrant_A	200397224	671154	0	0
ReqAndReadyImplyGrant_A	200397224	671154	0	0
ReqImpliesValid_A	200397224	671154	0	0
ReqStaysHighUntilGranted0_M	200397224	0	0	0
RoundRobin_A	200397224	0	0	663
ValidKnown_A	200397224	160844674	0	0
gen_data_port_assertion.DataFlow_A	200397224	671154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	160844674	0	0
T1	45664	44438	0	0
T2	87789	87252	0	0
T3	23252	19641	0	0
T4	557048	337074	0	0
T5	3814	3675	0	0
T6	1039045	866323	0	0
T7	12488	12379	0	0
T8	96	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	52873	46745	0	0
T13	978627	775146	0	0
T14	13900	12203	0	0
T15	1645	1475	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1989	1989	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T12	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0
T15	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	671154	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	20076	238	0	0
T4	337295	832	0	0
T5	3726	832	0	0
T6	866373	832	0	0
T7	12488	832	0	0
T8	96	832	0	0
T12	47091	489	0	0
T13	784181	10318	0	0
T14	12695	0	0	0
T15	1573	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	671154	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	20076	238	0	0
T4	337295	832	0	0
T5	3726	832	0	0
T6	866373	832	0	0
T7	12488	832	0	0
T8	96	832	0	0
T12	47091	489	0	0
T13	784181	10318	0	0
T14	12695	0	0	0
T15	1573	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	160844674	0	0
T1	45664	44438	0	0
T2	87789	87252	0	0
T3	23252	19641	0	0
T4	557048	337074	0	0
T5	3814	3675	0	0
T6	1039045	866323	0	0
T7	12488	12379	0	0
T8	96	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	52873	46745	0	0
T13	978627	775146	0	0
T14	13900	12203	0	0
T15	1645	1475	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	160844674	0	0
T1	45664	44438	0	0
T2	87789	87252	0	0
T3	23252	19641	0	0
T4	557048	337074	0	0
T5	3814	3675	0	0
T6	1039045	866323	0	0
T7	12488	12379	0	0
T8	96	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	52873	46745	0	0
T13	978627	775146	0	0
T14	13900	12203	0	0
T15	1645	1475	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	671154	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	20076	238	0	0
T4	337295	832	0	0
T5	3726	832	0	0
T6	866373	832	0	0
T7	12488	832	0	0
T8	96	832	0	0
T12	47091	489	0	0
T13	784181	10318	0	0
T14	12695	0	0	0
T15	1573	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	671154	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	20076	238	0	0
T4	337295	832	0	0
T5	3726	832	0	0
T6	866373	832	0	0
T7	12488	832	0	0
T8	96	832	0	0
T12	47091	489	0	0
T13	784181	10318	0	0
T14	12695	0	0	0
T15	1573	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	671154	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	20076	238	0	0
T4	337295	832	0	0
T5	3726	832	0	0
T6	866373	832	0	0
T7	12488	832	0	0
T8	96	832	0	0
T12	47091	489	0	0
T13	784181	10318	0	0
T14	12695	0	0	0
T15	1573	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	671154	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	20076	238	0	0
T4	337295	832	0	0
T5	3726	832	0	0
T6	866373	832	0	0
T7	12488	832	0	0
T8	96	832	0	0
T12	47091	489	0	0
T13	784181	10318	0	0
T14	12695	0	0	0
T15	1573	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	0	0	663

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	160844674	0	0
T1	45664	44438	0	0
T2	87789	87252	0	0
T3	23252	19641	0	0
T4	557048	337074	0	0
T5	3814	3675	0	0
T6	1039045	866323	0	0
T7	12488	12379	0	0
T8	96	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	52873	46745	0	0
T13	978627	775146	0	0
T14	13900	12203	0	0
T15	1645	1475	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200397224	671154	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	20076	238	0	0
T4	337295	832	0	0
T5	3726	832	0	0
T6	866373	832	0	0
T7	12488	832	0	0
T8	96	832	0	0
T12	47091	489	0	0
T13	784181	10318	0	0
T14	12695	0	0	0
T15	1573	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	19	86.36
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	3	75.00
ALWAYS	124	4	3	75.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	0	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	0	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	4	44.44
Logical	9	4	44.44
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	1	50.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	38957083	25211660	0	0
CheckNGreaterZero_A	663	663	0	0
GntImpliesReady_A	38957083	0	0	0
GntImpliesValid_A	38957083	0	0	0
GrantKnown_A	38957083	25211660	0	0
IdxKnown_A	38957083	25211660	0	0
IndexIsCorrect_A	38957083	0	0	0
LockArbDecision_A	38957083	0	0	0
NoReadyValidNoGrant_A	38957083	0	0	0
ReadyAndValidImplyGrant_A	38957083	0	0	0
ReqAndReadyImplyGrant_A	38957083	0	0	0
ReqImpliesValid_A	38957083	0	0	0
ReqStaysHighUntilGranted0_M	38957083	0	0	0
RoundRobin_A	38957083	0	0	0
ValidKnown_A	38957083	25211660	0	0
gen_data_port_assertion.DataFlow_A	38957083	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	25211660	0	0
T1	25302	24176	0	0
T2	10305	9818	0	0
T3	3176	0	0	0
T4	219753	219610	0	0
T5	88	88	0	0
T6	172672	172672	0	0
T7	0	12379	0	0
T8	0	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	5782	0	0	0
T13	194446	0	0	0
T14	1205	0	0	0
T15	72	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	25211660	0	0
T1	25302	24176	0	0
T2	10305	9818	0	0
T3	3176	0	0	0
T4	219753	219610	0	0
T5	88	88	0	0
T6	172672	172672	0	0
T7	0	12379	0	0
T8	0	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	5782	0	0	0
T13	194446	0	0	0
T14	1205	0	0	0
T15	72	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	25211660	0	0
T1	25302	24176	0	0
T2	10305	9818	0	0
T3	3176	0	0	0
T4	219753	219610	0	0
T5	88	88	0	0
T6	172672	172672	0	0
T7	0	12379	0	0
T8	0	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	5782	0	0	0
T13	194446	0	0	0
T14	1205	0	0	0
T15	72	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	25211660	0	0
T1	25302	24176	0	0
T2	10305	9818	0	0
T3	3176	0	0	0
T4	219753	219610	0	0
T5	88	88	0	0
T6	172672	172672	0	0
T7	0	12379	0	0
T8	0	96	0	0
T9	0	70410	0	0
T10	0	15022	0	0
T11	0	157110	0	0
T12	5782	0	0	0
T13	194446	0	0	0
T14	1205	0	0	0
T15	72	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T3,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T13
1	0	Unreachable
1	1	Covered	T3,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T3,T12,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	38957083	13205272	0	0
CheckNGreaterZero_A	663	663	0	0
GntImpliesReady_A	38957083	222727	0	0
GntImpliesValid_A	38957083	222727	0	0
GrantKnown_A	38957083	13205272	0	0
IdxKnown_A	38957083	13205272	0	0
IndexIsCorrect_A	38957083	222727	0	0
LockArbDecision_A	38957083	0	0	0
NoReadyValidNoGrant_A	38957083	0	0	0
ReadyAndValidImplyGrant_A	38957083	222727	0	0
ReqAndReadyImplyGrant_A	38957083	222727	0	0
ReqImpliesValid_A	38957083	222727	0	0
ReqStaysHighUntilGranted0_M	38957083	0	0	0
RoundRobin_A	38957083	0	0	0
ValidKnown_A	38957083	13205272	0	0
gen_data_port_assertion.DataFlow_A	38957083	222727	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	13205272	0	0
T3	3176	2824	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	5528	0	0
T13	194446	185504	0	0
T14	1205	792	0	0
T15	72	72	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	222727	0	0
T3	3176	170	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	342	0	0
T13	194446	6831	0	0
T14	1205	0	0	0
T15	72	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	222727	0	0
T3	3176	170	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	342	0	0
T13	194446	6831	0	0
T14	1205	0	0	0
T15	72	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	13205272	0	0
T3	3176	2824	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	5528	0	0
T13	194446	185504	0	0
T14	1205	792	0	0
T15	72	72	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	13205272	0	0
T3	3176	2824	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	5528	0	0
T13	194446	185504	0	0
T14	1205	792	0	0
T15	72	72	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	222727	0	0
T3	3176	170	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	342	0	0
T13	194446	6831	0	0
T14	1205	0	0	0
T15	72	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	222727	0	0
T3	3176	170	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	342	0	0
T13	194446	6831	0	0
T14	1205	0	0	0
T15	72	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	222727	0	0
T3	3176	170	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	342	0	0
T13	194446	6831	0	0
T14	1205	0	0	0
T15	72	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	222727	0	0
T3	3176	170	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	342	0	0
T13	194446	6831	0	0
T14	1205	0	0	0
T15	72	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	13205272	0	0
T3	3176	2824	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	5528	0	0
T13	194446	185504	0	0
T14	1205	792	0	0
T15	72	72	0	0
T16	0	45960	0	0
T17	0	159936	0	0
T18	0	19552	0	0
T19	0	7936	0	0
T21	0	360	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38957083	222727	0	0
T3	3176	170	0	0
T4	219753	0	0	0
T5	88	0	0	0
T6	172672	0	0	0
T7	12488	0	0	0
T8	96	0	0	0
T12	5782	342	0	0
T13	194446	6831	0	0
T14	1205	0	0	0
T15	72	0	0	0
T17	0	5675	0	0
T18	0	750	0	0
T19	0	188	0	0
T59	0	6286	0	0
T60	0	312	0	0
T61	0	1418	0	0
T62	0	91	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T12,T13
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	122483058	122427742	0	0
CheckNGreaterZero_A	663	663	0	0
GntImpliesReady_A	122483058	448427	0	0
GntImpliesValid_A	122483058	448427	0	0
GrantKnown_A	122483058	122427742	0	0
IdxKnown_A	122483058	122427742	0	0
IndexIsCorrect_A	122483058	448427	0	0
LockArbDecision_A	122483058	0	0	0
NoReadyValidNoGrant_A	122483058	0	0	0
ReadyAndValidImplyGrant_A	122483058	448427	0	0
ReqAndReadyImplyGrant_A	122483058	448427	0	0
ReqImpliesValid_A	122483058	448427	0	0
ReqStaysHighUntilGranted0_M	122483058	0	0	0
RoundRobin_A	122483058	0	0	663
ValidKnown_A	122483058	122427742	0	0
gen_data_port_assertion.DataFlow_A	122483058	448427	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	122427742	0	0
T1	20362	20262	0	0
T2	77484	77434	0	0
T3	16900	16817	0	0
T4	117542	117464	0	0
T5	3638	3587	0	0
T6	693701	693651	0	0
T12	41309	41217	0	0
T13	589735	589642	0	0
T14	11490	11411	0	0
T15	1501	1403	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663	663	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	448427	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	16900	68	0	0
T4	117542	832	0	0
T5	3638	832	0	0
T6	693701	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T12	41309	147	0	0
T13	589735	3487	0	0
T14	11490	0	0	0
T15	1501	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	448427	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	16900	68	0	0
T4	117542	832	0	0
T5	3638	832	0	0
T6	693701	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T12	41309	147	0	0
T13	589735	3487	0	0
T14	11490	0	0	0
T15	1501	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	122427742	0	0
T1	20362	20262	0	0
T2	77484	77434	0	0
T3	16900	16817	0	0
T4	117542	117464	0	0
T5	3638	3587	0	0
T6	693701	693651	0	0
T12	41309	41217	0	0
T13	589735	589642	0	0
T14	11490	11411	0	0
T15	1501	1403	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	122427742	0	0
T1	20362	20262	0	0
T2	77484	77434	0	0
T3	16900	16817	0	0
T4	117542	117464	0	0
T5	3638	3587	0	0
T6	693701	693651	0	0
T12	41309	41217	0	0
T13	589735	589642	0	0
T14	11490	11411	0	0
T15	1501	1403	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	448427	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	16900	68	0	0
T4	117542	832	0	0
T5	3638	832	0	0
T6	693701	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T12	41309	147	0	0
T13	589735	3487	0	0
T14	11490	0	0	0
T15	1501	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	448427	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	16900	68	0	0
T4	117542	832	0	0
T5	3638	832	0	0
T6	693701	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T12	41309	147	0	0
T13	589735	3487	0	0
T14	11490	0	0	0
T15	1501	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	448427	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	16900	68	0	0
T4	117542	832	0	0
T5	3638	832	0	0
T6	693701	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T12	41309	147	0	0
T13	589735	3487	0	0
T14	11490	0	0	0
T15	1501	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	448427	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	16900	68	0	0
T4	117542	832	0	0
T5	3638	832	0	0
T6	693701	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T12	41309	147	0	0
T13	589735	3487	0	0
T14	11490	0	0	0
T15	1501	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	0	0	663

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	122427742	0	0
T1	20362	20262	0	0
T2	77484	77434	0	0
T3	16900	16817	0	0
T4	117542	117464	0	0
T5	3638	3587	0	0
T6	693701	693651	0	0
T12	41309	41217	0	0
T13	589735	589642	0	0
T14	11490	11411	0	0
T15	1501	1403	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122483058	448427	0	0
T1	20362	832	0	0
T2	77484	832	0	0
T3	16900	68	0	0
T4	117542	832	0	0
T5	3638	832	0	0
T6	693701	832	0	0
T7	0	832	0	0
T8	0	832	0	0
T12	41309	147	0	0
T13	589735	3487	0	0
T14	11490	0	0	0
T15	1501	0	0	0