Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4041 |
0 |
0 |
T35 |
5124 |
6 |
0 |
0 |
T36 |
9426 |
3 |
0 |
0 |
T37 |
5337 |
21 |
0 |
0 |
T115 |
67306 |
1 |
0 |
0 |
T116 |
19405 |
3 |
0 |
0 |
T117 |
5254 |
3 |
0 |
0 |
T118 |
6058 |
263 |
0 |
0 |
T119 |
7324 |
326 |
0 |
0 |
T135 |
8966 |
4 |
0 |
0 |
T136 |
8534 |
5 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1898 |
0 |
0 |
T115 |
67306 |
85 |
0 |
0 |
T123 |
30956 |
48 |
0 |
0 |
T134 |
15520 |
27 |
0 |
0 |
T144 |
71972 |
430 |
0 |
0 |
T152 |
8720 |
7 |
0 |
0 |
T153 |
8696 |
4 |
0 |
0 |
T159 |
180367 |
475 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
36 |
0 |
0 |
T162 |
36054 |
28 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1736 |
0 |
0 |
T115 |
67306 |
71 |
0 |
0 |
T123 |
30956 |
18 |
0 |
0 |
T134 |
15520 |
18 |
0 |
0 |
T144 |
71972 |
450 |
0 |
0 |
T152 |
8720 |
3 |
0 |
0 |
T153 |
8696 |
10 |
0 |
0 |
T159 |
180367 |
424 |
0 |
0 |
T160 |
2093 |
2 |
0 |
0 |
T161 |
13913 |
19 |
0 |
0 |
T162 |
36054 |
42 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2594 |
0 |
0 |
T115 |
67306 |
152 |
0 |
0 |
T117 |
5254 |
14 |
0 |
0 |
T123 |
30956 |
100 |
0 |
0 |
T134 |
15520 |
40 |
0 |
0 |
T144 |
71972 |
459 |
0 |
0 |
T152 |
8720 |
34 |
0 |
0 |
T153 |
8696 |
34 |
0 |
0 |
T159 |
180367 |
454 |
0 |
0 |
T161 |
13913 |
40 |
0 |
0 |
T162 |
36054 |
72 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
9982 |
0 |
0 |
T115 |
67306 |
1246 |
0 |
0 |
T117 |
5254 |
78 |
0 |
0 |
T123 |
30956 |
670 |
0 |
0 |
T134 |
15520 |
141 |
0 |
0 |
T152 |
8720 |
263 |
0 |
0 |
T153 |
8696 |
302 |
0 |
0 |
T159 |
180367 |
430 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
43 |
0 |
0 |
T162 |
36054 |
677 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
9604 |
0 |
0 |
T115 |
67306 |
1340 |
0 |
0 |
T117 |
5254 |
38 |
0 |
0 |
T123 |
30956 |
37 |
0 |
0 |
T134 |
15520 |
249 |
0 |
0 |
T152 |
8720 |
240 |
0 |
0 |
T153 |
8696 |
242 |
0 |
0 |
T159 |
180367 |
473 |
0 |
0 |
T160 |
2093 |
2 |
0 |
0 |
T161 |
13913 |
52 |
0 |
0 |
T162 |
36054 |
743 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
10941 |
0 |
0 |
T115 |
67306 |
1009 |
0 |
0 |
T117 |
5254 |
75 |
0 |
0 |
T123 |
30956 |
777 |
0 |
0 |
T134 |
15520 |
161 |
0 |
0 |
T152 |
8720 |
153 |
0 |
0 |
T153 |
8696 |
127 |
0 |
0 |
T159 |
180367 |
449 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
38 |
0 |
0 |
T162 |
36054 |
806 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
9186 |
0 |
0 |
T115 |
67306 |
1114 |
0 |
0 |
T117 |
5254 |
56 |
0 |
0 |
T123 |
30956 |
523 |
0 |
0 |
T134 |
15520 |
17 |
0 |
0 |
T152 |
8720 |
89 |
0 |
0 |
T153 |
8696 |
12 |
0 |
0 |
T159 |
180367 |
476 |
0 |
0 |
T160 |
2093 |
10 |
0 |
0 |
T161 |
13913 |
52 |
0 |
0 |
T162 |
36054 |
718 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
10244 |
0 |
0 |
T115 |
67306 |
1197 |
0 |
0 |
T117 |
5254 |
7 |
0 |
0 |
T123 |
30956 |
967 |
0 |
0 |
T134 |
15520 |
252 |
0 |
0 |
T152 |
8720 |
111 |
0 |
0 |
T153 |
8696 |
152 |
0 |
0 |
T159 |
180367 |
393 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
30 |
0 |
0 |
T162 |
36054 |
843 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
9208 |
0 |
0 |
T115 |
67306 |
1680 |
0 |
0 |
T117 |
5254 |
73 |
0 |
0 |
T123 |
30956 |
243 |
0 |
0 |
T134 |
15520 |
163 |
0 |
0 |
T152 |
8720 |
144 |
0 |
0 |
T153 |
8696 |
145 |
0 |
0 |
T159 |
180367 |
457 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
53 |
0 |
0 |
T162 |
36054 |
701 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
9225 |
0 |
0 |
T115 |
67306 |
1067 |
0 |
0 |
T117 |
5254 |
7 |
0 |
0 |
T123 |
30956 |
141 |
0 |
0 |
T134 |
15520 |
173 |
0 |
0 |
T152 |
8720 |
281 |
0 |
0 |
T153 |
8696 |
125 |
0 |
0 |
T159 |
180367 |
472 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
49 |
0 |
0 |
T162 |
36054 |
681 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
10294 |
0 |
0 |
T115 |
67306 |
1701 |
0 |
0 |
T117 |
5254 |
84 |
0 |
0 |
T123 |
30956 |
423 |
0 |
0 |
T134 |
15520 |
398 |
0 |
0 |
T152 |
8720 |
113 |
0 |
0 |
T153 |
8696 |
132 |
0 |
0 |
T159 |
180367 |
478 |
0 |
0 |
T160 |
2093 |
2 |
0 |
0 |
T161 |
13913 |
14 |
0 |
0 |
T162 |
36054 |
649 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4679 |
0 |
0 |
T115 |
67306 |
539 |
0 |
0 |
T117 |
5254 |
6 |
0 |
0 |
T123 |
30956 |
204 |
0 |
0 |
T134 |
15520 |
28 |
0 |
0 |
T152 |
8720 |
113 |
0 |
0 |
T153 |
8696 |
50 |
0 |
0 |
T159 |
180367 |
426 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
53 |
0 |
0 |
T162 |
36054 |
146 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5018 |
0 |
0 |
T115 |
67306 |
512 |
0 |
0 |
T117 |
5254 |
27 |
0 |
0 |
T123 |
30956 |
154 |
0 |
0 |
T134 |
15520 |
97 |
0 |
0 |
T152 |
8720 |
45 |
0 |
0 |
T153 |
8696 |
49 |
0 |
0 |
T159 |
180367 |
453 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
44 |
0 |
0 |
T162 |
36054 |
284 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5146 |
0 |
0 |
T115 |
67306 |
491 |
0 |
0 |
T117 |
5254 |
4 |
0 |
0 |
T123 |
30956 |
246 |
0 |
0 |
T134 |
15520 |
64 |
0 |
0 |
T152 |
8720 |
61 |
0 |
0 |
T153 |
8696 |
89 |
0 |
0 |
T159 |
180367 |
459 |
0 |
0 |
T160 |
2093 |
7 |
0 |
0 |
T161 |
13913 |
80 |
0 |
0 |
T162 |
36054 |
385 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5170 |
0 |
0 |
T115 |
67306 |
504 |
0 |
0 |
T117 |
5254 |
8 |
0 |
0 |
T123 |
30956 |
240 |
0 |
0 |
T134 |
15520 |
103 |
0 |
0 |
T152 |
8720 |
49 |
0 |
0 |
T153 |
8696 |
82 |
0 |
0 |
T159 |
180367 |
431 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
43 |
0 |
0 |
T162 |
36054 |
210 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5436 |
0 |
0 |
T115 |
67306 |
610 |
0 |
0 |
T117 |
5254 |
30 |
0 |
0 |
T123 |
30956 |
240 |
0 |
0 |
T134 |
15520 |
95 |
0 |
0 |
T152 |
8720 |
53 |
0 |
0 |
T153 |
8696 |
100 |
0 |
0 |
T159 |
180367 |
495 |
0 |
0 |
T160 |
2093 |
8 |
0 |
0 |
T161 |
13913 |
30 |
0 |
0 |
T162 |
36054 |
227 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5264 |
0 |
0 |
T115 |
67306 |
703 |
0 |
0 |
T123 |
30956 |
156 |
0 |
0 |
T134 |
15520 |
8 |
0 |
0 |
T144 |
71972 |
419 |
0 |
0 |
T152 |
8720 |
108 |
0 |
0 |
T153 |
8696 |
92 |
0 |
0 |
T159 |
180367 |
429 |
0 |
0 |
T160 |
2093 |
6 |
0 |
0 |
T161 |
13913 |
69 |
0 |
0 |
T162 |
36054 |
218 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5329 |
0 |
0 |
T115 |
67306 |
448 |
0 |
0 |
T117 |
5254 |
6 |
0 |
0 |
T123 |
30956 |
377 |
0 |
0 |
T134 |
15520 |
104 |
0 |
0 |
T152 |
8720 |
59 |
0 |
0 |
T153 |
8696 |
55 |
0 |
0 |
T159 |
180367 |
467 |
0 |
0 |
T160 |
2093 |
6 |
0 |
0 |
T161 |
13913 |
92 |
0 |
0 |
T162 |
36054 |
352 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5364 |
0 |
0 |
T115 |
67306 |
695 |
0 |
0 |
T117 |
5254 |
2 |
0 |
0 |
T123 |
30956 |
265 |
0 |
0 |
T134 |
15520 |
165 |
0 |
0 |
T152 |
8720 |
9 |
0 |
0 |
T153 |
8696 |
10 |
0 |
0 |
T159 |
180367 |
432 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
61 |
0 |
0 |
T162 |
36054 |
304 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5141 |
0 |
0 |
T115 |
67306 |
602 |
0 |
0 |
T123 |
30956 |
247 |
0 |
0 |
T134 |
15520 |
132 |
0 |
0 |
T144 |
71972 |
492 |
0 |
0 |
T152 |
8720 |
60 |
0 |
0 |
T153 |
8696 |
58 |
0 |
0 |
T159 |
180367 |
437 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
64 |
0 |
0 |
T162 |
36054 |
304 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5251 |
0 |
0 |
T115 |
67306 |
582 |
0 |
0 |
T117 |
5254 |
2 |
0 |
0 |
T123 |
30956 |
202 |
0 |
0 |
T134 |
15520 |
157 |
0 |
0 |
T152 |
8720 |
82 |
0 |
0 |
T153 |
8696 |
41 |
0 |
0 |
T159 |
180367 |
445 |
0 |
0 |
T160 |
2093 |
7 |
0 |
0 |
T161 |
13913 |
52 |
0 |
0 |
T162 |
36054 |
289 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4980 |
0 |
0 |
T115 |
67306 |
624 |
0 |
0 |
T117 |
5254 |
31 |
0 |
0 |
T123 |
30956 |
258 |
0 |
0 |
T134 |
15520 |
114 |
0 |
0 |
T152 |
8720 |
94 |
0 |
0 |
T153 |
8696 |
5 |
0 |
0 |
T159 |
180367 |
445 |
0 |
0 |
T160 |
2093 |
3 |
0 |
0 |
T161 |
13913 |
62 |
0 |
0 |
T162 |
36054 |
183 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4740 |
0 |
0 |
T115 |
67306 |
427 |
0 |
0 |
T117 |
5254 |
11 |
0 |
0 |
T123 |
30956 |
351 |
0 |
0 |
T134 |
15520 |
29 |
0 |
0 |
T152 |
8720 |
66 |
0 |
0 |
T153 |
8696 |
10 |
0 |
0 |
T159 |
180367 |
447 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
51 |
0 |
0 |
T162 |
36054 |
286 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5013 |
0 |
0 |
T115 |
67306 |
627 |
0 |
0 |
T123 |
30956 |
171 |
0 |
0 |
T134 |
15520 |
99 |
0 |
0 |
T144 |
71972 |
539 |
0 |
0 |
T152 |
8720 |
1 |
0 |
0 |
T153 |
8696 |
28 |
0 |
0 |
T159 |
180367 |
429 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
30 |
0 |
0 |
T162 |
36054 |
197 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4534 |
0 |
0 |
T115 |
67306 |
280 |
0 |
0 |
T117 |
5254 |
27 |
0 |
0 |
T123 |
30956 |
206 |
0 |
0 |
T134 |
15520 |
18 |
0 |
0 |
T152 |
8720 |
4 |
0 |
0 |
T153 |
8696 |
39 |
0 |
0 |
T159 |
180367 |
467 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
34 |
0 |
0 |
T162 |
36054 |
396 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5144 |
0 |
0 |
T115 |
67306 |
516 |
0 |
0 |
T117 |
5254 |
28 |
0 |
0 |
T123 |
30956 |
207 |
0 |
0 |
T134 |
15520 |
80 |
0 |
0 |
T152 |
8720 |
74 |
0 |
0 |
T153 |
8696 |
67 |
0 |
0 |
T159 |
180367 |
417 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
40 |
0 |
0 |
T162 |
36054 |
321 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4659 |
0 |
0 |
T115 |
67306 |
417 |
0 |
0 |
T117 |
5254 |
3 |
0 |
0 |
T123 |
30956 |
375 |
0 |
0 |
T134 |
15520 |
152 |
0 |
0 |
T152 |
8720 |
70 |
0 |
0 |
T153 |
8696 |
63 |
0 |
0 |
T159 |
180367 |
462 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
75 |
0 |
0 |
T162 |
36054 |
71 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4774 |
0 |
0 |
T115 |
67306 |
408 |
0 |
0 |
T117 |
5254 |
21 |
0 |
0 |
T123 |
30956 |
294 |
0 |
0 |
T134 |
15520 |
105 |
0 |
0 |
T152 |
8720 |
16 |
0 |
0 |
T153 |
8696 |
110 |
0 |
0 |
T159 |
180367 |
465 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
33 |
0 |
0 |
T162 |
36054 |
340 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5265 |
0 |
0 |
T115 |
67306 |
395 |
0 |
0 |
T117 |
5254 |
26 |
0 |
0 |
T123 |
30956 |
240 |
0 |
0 |
T134 |
15520 |
11 |
0 |
0 |
T152 |
8720 |
7 |
0 |
0 |
T153 |
8696 |
71 |
0 |
0 |
T159 |
180367 |
408 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
37 |
0 |
0 |
T162 |
36054 |
492 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5001 |
0 |
0 |
T115 |
67306 |
677 |
0 |
0 |
T117 |
5254 |
7 |
0 |
0 |
T123 |
30956 |
147 |
0 |
0 |
T134 |
15520 |
61 |
0 |
0 |
T152 |
8720 |
69 |
0 |
0 |
T153 |
8696 |
103 |
0 |
0 |
T159 |
180367 |
466 |
0 |
0 |
T160 |
2093 |
6 |
0 |
0 |
T161 |
13913 |
18 |
0 |
0 |
T162 |
36054 |
172 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4898 |
0 |
0 |
T115 |
67306 |
356 |
0 |
0 |
T123 |
30956 |
295 |
0 |
0 |
T134 |
15520 |
115 |
0 |
0 |
T144 |
71972 |
487 |
0 |
0 |
T152 |
8720 |
4 |
0 |
0 |
T153 |
8696 |
57 |
0 |
0 |
T159 |
180367 |
428 |
0 |
0 |
T160 |
2093 |
2 |
0 |
0 |
T161 |
13913 |
34 |
0 |
0 |
T162 |
36054 |
374 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4573 |
0 |
0 |
T115 |
67306 |
597 |
0 |
0 |
T123 |
30956 |
183 |
0 |
0 |
T134 |
15520 |
155 |
0 |
0 |
T144 |
71972 |
482 |
0 |
0 |
T152 |
8720 |
8 |
0 |
0 |
T153 |
8696 |
35 |
0 |
0 |
T159 |
180367 |
454 |
0 |
0 |
T160 |
2093 |
7 |
0 |
0 |
T161 |
13913 |
32 |
0 |
0 |
T162 |
36054 |
100 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4965 |
0 |
0 |
T115 |
67306 |
656 |
0 |
0 |
T117 |
5254 |
9 |
0 |
0 |
T123 |
30956 |
318 |
0 |
0 |
T134 |
15520 |
42 |
0 |
0 |
T144 |
71972 |
519 |
0 |
0 |
T152 |
8720 |
116 |
0 |
0 |
T153 |
8696 |
104 |
0 |
0 |
T159 |
180367 |
464 |
0 |
0 |
T161 |
13913 |
56 |
0 |
0 |
T162 |
36054 |
243 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
4923 |
0 |
0 |
T115 |
67306 |
518 |
0 |
0 |
T117 |
5254 |
30 |
0 |
0 |
T123 |
30956 |
260 |
0 |
0 |
T134 |
15520 |
105 |
0 |
0 |
T152 |
8720 |
10 |
0 |
0 |
T153 |
8696 |
7 |
0 |
0 |
T159 |
180367 |
434 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
49 |
0 |
0 |
T162 |
36054 |
274 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
5074 |
0 |
0 |
T115 |
67306 |
436 |
0 |
0 |
T117 |
5254 |
32 |
0 |
0 |
T123 |
30956 |
249 |
0 |
0 |
T134 |
15520 |
123 |
0 |
0 |
T152 |
8720 |
48 |
0 |
0 |
T153 |
8696 |
112 |
0 |
0 |
T159 |
180367 |
453 |
0 |
0 |
T160 |
2093 |
3 |
0 |
0 |
T161 |
13913 |
20 |
0 |
0 |
T162 |
36054 |
307 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2097 |
0 |
0 |
T115 |
67306 |
117 |
0 |
0 |
T117 |
5254 |
3 |
0 |
0 |
T123 |
30956 |
76 |
0 |
0 |
T134 |
15520 |
32 |
0 |
0 |
T144 |
71972 |
462 |
0 |
0 |
T152 |
8720 |
10 |
0 |
0 |
T153 |
8696 |
6 |
0 |
0 |
T159 |
180367 |
450 |
0 |
0 |
T161 |
13913 |
37 |
0 |
0 |
T162 |
36054 |
61 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1934 |
0 |
0 |
T115 |
67306 |
81 |
0 |
0 |
T117 |
5254 |
10 |
0 |
0 |
T123 |
30956 |
32 |
0 |
0 |
T134 |
15520 |
22 |
0 |
0 |
T152 |
8720 |
7 |
0 |
0 |
T153 |
8696 |
4 |
0 |
0 |
T159 |
180367 |
438 |
0 |
0 |
T160 |
2093 |
8 |
0 |
0 |
T161 |
13913 |
30 |
0 |
0 |
T162 |
36054 |
65 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2024 |
0 |
0 |
T115 |
67306 |
133 |
0 |
0 |
T117 |
5254 |
10 |
0 |
0 |
T123 |
30956 |
40 |
0 |
0 |
T134 |
15520 |
29 |
0 |
0 |
T152 |
8720 |
8 |
0 |
0 |
T153 |
8696 |
9 |
0 |
0 |
T159 |
180367 |
424 |
0 |
0 |
T160 |
2093 |
8 |
0 |
0 |
T161 |
13913 |
33 |
0 |
0 |
T162 |
36054 |
47 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2351 |
0 |
0 |
T115 |
67306 |
117 |
0 |
0 |
T123 |
30956 |
69 |
0 |
0 |
T134 |
15520 |
39 |
0 |
0 |
T144 |
71972 |
440 |
0 |
0 |
T152 |
8720 |
10 |
0 |
0 |
T153 |
8696 |
13 |
0 |
0 |
T159 |
180367 |
500 |
0 |
0 |
T161 |
13913 |
53 |
0 |
0 |
T162 |
36054 |
84 |
0 |
0 |
T163 |
10756 |
15 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2710 |
0 |
0 |
T115 |
67306 |
193 |
0 |
0 |
T117 |
5254 |
18 |
0 |
0 |
T123 |
30956 |
129 |
0 |
0 |
T134 |
15520 |
47 |
0 |
0 |
T152 |
8720 |
8 |
0 |
0 |
T153 |
8696 |
27 |
0 |
0 |
T159 |
180367 |
412 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
72 |
0 |
0 |
T162 |
36054 |
111 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
3866 |
0 |
0 |
T41 |
6897 |
32 |
0 |
0 |
T111 |
200168 |
0 |
0 |
0 |
T115 |
0 |
398 |
0 |
0 |
T117 |
0 |
5 |
0 |
0 |
T159 |
0 |
483 |
0 |
0 |
T160 |
0 |
4 |
0 |
0 |
T164 |
0 |
8 |
0 |
0 |
T165 |
0 |
74 |
0 |
0 |
T166 |
0 |
30 |
0 |
0 |
T167 |
0 |
3 |
0 |
0 |
T168 |
0 |
17 |
0 |
0 |
T169 |
8671 |
0 |
0 |
0 |
T170 |
88763 |
0 |
0 |
0 |
T171 |
71824 |
0 |
0 |
0 |
T172 |
1290 |
0 |
0 |
0 |
T173 |
289821 |
0 |
0 |
0 |
T174 |
738 |
0 |
0 |
0 |
T175 |
449375 |
0 |
0 |
0 |
T176 |
106035 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2028 |
0 |
0 |
T115 |
67306 |
121 |
0 |
0 |
T117 |
5254 |
1 |
0 |
0 |
T123 |
30956 |
64 |
0 |
0 |
T134 |
15520 |
23 |
0 |
0 |
T152 |
8720 |
11 |
0 |
0 |
T153 |
8696 |
12 |
0 |
0 |
T159 |
180367 |
385 |
0 |
0 |
T160 |
2093 |
2 |
0 |
0 |
T161 |
13913 |
47 |
0 |
0 |
T162 |
36054 |
70 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2248 |
0 |
0 |
T115 |
67306 |
136 |
0 |
0 |
T117 |
5254 |
7 |
0 |
0 |
T123 |
30956 |
47 |
0 |
0 |
T134 |
15520 |
23 |
0 |
0 |
T152 |
8720 |
4 |
0 |
0 |
T153 |
8696 |
20 |
0 |
0 |
T159 |
180367 |
459 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
70 |
0 |
0 |
T162 |
36054 |
68 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1928 |
0 |
0 |
T115 |
67306 |
73 |
0 |
0 |
T117 |
5254 |
1 |
0 |
0 |
T123 |
30956 |
31 |
0 |
0 |
T134 |
15520 |
25 |
0 |
0 |
T152 |
8720 |
8 |
0 |
0 |
T153 |
8696 |
6 |
0 |
0 |
T159 |
180367 |
460 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
57 |
0 |
0 |
T162 |
36054 |
29 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1943 |
0 |
0 |
T115 |
67306 |
94 |
0 |
0 |
T117 |
5254 |
3 |
0 |
0 |
T123 |
30956 |
37 |
0 |
0 |
T134 |
15520 |
25 |
0 |
0 |
T144 |
71972 |
446 |
0 |
0 |
T153 |
8696 |
13 |
0 |
0 |
T159 |
180367 |
415 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
27 |
0 |
0 |
T162 |
36054 |
48 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1882 |
0 |
0 |
T115 |
67306 |
92 |
0 |
0 |
T117 |
5254 |
1 |
0 |
0 |
T123 |
30956 |
32 |
0 |
0 |
T134 |
15520 |
22 |
0 |
0 |
T144 |
71972 |
455 |
0 |
0 |
T152 |
8720 |
5 |
0 |
0 |
T153 |
8696 |
10 |
0 |
0 |
T159 |
180367 |
423 |
0 |
0 |
T161 |
13913 |
88 |
0 |
0 |
T162 |
36054 |
45 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1889 |
0 |
0 |
T115 |
67306 |
72 |
0 |
0 |
T123 |
30956 |
40 |
0 |
0 |
T134 |
15520 |
19 |
0 |
0 |
T144 |
71972 |
469 |
0 |
0 |
T152 |
8720 |
6 |
0 |
0 |
T153 |
8696 |
6 |
0 |
0 |
T159 |
180367 |
478 |
0 |
0 |
T160 |
2093 |
2 |
0 |
0 |
T161 |
13913 |
26 |
0 |
0 |
T162 |
36054 |
42 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2657 |
0 |
0 |
T115 |
67306 |
140 |
0 |
0 |
T117 |
5254 |
14 |
0 |
0 |
T123 |
30956 |
71 |
0 |
0 |
T134 |
15520 |
20 |
0 |
0 |
T144 |
71972 |
399 |
0 |
0 |
T152 |
8720 |
16 |
0 |
0 |
T153 |
8696 |
27 |
0 |
0 |
T159 |
180367 |
386 |
0 |
0 |
T161 |
13913 |
63 |
0 |
0 |
T162 |
36054 |
116 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1856 |
0 |
0 |
T115 |
67306 |
75 |
0 |
0 |
T117 |
5254 |
2 |
0 |
0 |
T123 |
30956 |
30 |
0 |
0 |
T134 |
15520 |
32 |
0 |
0 |
T152 |
8720 |
10 |
0 |
0 |
T153 |
8696 |
4 |
0 |
0 |
T159 |
180367 |
420 |
0 |
0 |
T160 |
2093 |
5 |
0 |
0 |
T161 |
13913 |
54 |
0 |
0 |
T162 |
36054 |
47 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2889 |
0 |
0 |
T115 |
67306 |
271 |
0 |
0 |
T117 |
5254 |
7 |
0 |
0 |
T123 |
30956 |
85 |
0 |
0 |
T134 |
15520 |
11 |
0 |
0 |
T152 |
8720 |
41 |
0 |
0 |
T153 |
8696 |
27 |
0 |
0 |
T159 |
180367 |
429 |
0 |
0 |
T160 |
2093 |
6 |
0 |
0 |
T161 |
13913 |
51 |
0 |
0 |
T162 |
36054 |
103 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2019 |
0 |
0 |
T115 |
67306 |
129 |
0 |
0 |
T123 |
30956 |
42 |
0 |
0 |
T134 |
15520 |
30 |
0 |
0 |
T144 |
71972 |
463 |
0 |
0 |
T152 |
8720 |
9 |
0 |
0 |
T153 |
8696 |
10 |
0 |
0 |
T159 |
180367 |
388 |
0 |
0 |
T160 |
2093 |
2 |
0 |
0 |
T161 |
13913 |
37 |
0 |
0 |
T162 |
36054 |
73 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1868 |
0 |
0 |
T115 |
67306 |
81 |
0 |
0 |
T117 |
5254 |
2 |
0 |
0 |
T123 |
30956 |
30 |
0 |
0 |
T134 |
15520 |
20 |
0 |
0 |
T152 |
8720 |
9 |
0 |
0 |
T153 |
8696 |
13 |
0 |
0 |
T159 |
180367 |
414 |
0 |
0 |
T160 |
2093 |
6 |
0 |
0 |
T161 |
13913 |
96 |
0 |
0 |
T162 |
36054 |
33 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1859 |
0 |
0 |
T115 |
67306 |
72 |
0 |
0 |
T117 |
5254 |
4 |
0 |
0 |
T123 |
30956 |
30 |
0 |
0 |
T134 |
15520 |
23 |
0 |
0 |
T152 |
8720 |
9 |
0 |
0 |
T153 |
8696 |
1 |
0 |
0 |
T159 |
180367 |
456 |
0 |
0 |
T160 |
2093 |
1 |
0 |
0 |
T161 |
13913 |
53 |
0 |
0 |
T162 |
36054 |
41 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1917 |
0 |
0 |
T115 |
67306 |
62 |
0 |
0 |
T123 |
30956 |
42 |
0 |
0 |
T134 |
15520 |
13 |
0 |
0 |
T144 |
71972 |
541 |
0 |
0 |
T152 |
8720 |
13 |
0 |
0 |
T153 |
8696 |
15 |
0 |
0 |
T159 |
180367 |
435 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
46 |
0 |
0 |
T162 |
36054 |
41 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1809 |
0 |
0 |
T115 |
67306 |
73 |
0 |
0 |
T123 |
30956 |
30 |
0 |
0 |
T134 |
15520 |
24 |
0 |
0 |
T144 |
71972 |
487 |
0 |
0 |
T152 |
8720 |
12 |
0 |
0 |
T153 |
8696 |
8 |
0 |
0 |
T159 |
180367 |
434 |
0 |
0 |
T161 |
13913 |
30 |
0 |
0 |
T162 |
36054 |
32 |
0 |
0 |
T163 |
10756 |
18 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
2047 |
0 |
0 |
T115 |
67306 |
92 |
0 |
0 |
T117 |
5254 |
6 |
0 |
0 |
T123 |
30956 |
39 |
0 |
0 |
T134 |
15520 |
32 |
0 |
0 |
T152 |
8720 |
14 |
0 |
0 |
T153 |
8696 |
9 |
0 |
0 |
T159 |
180367 |
471 |
0 |
0 |
T160 |
2093 |
7 |
0 |
0 |
T161 |
13913 |
66 |
0 |
0 |
T162 |
36054 |
55 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
124641562 |
1904 |
0 |
0 |
T115 |
67306 |
76 |
0 |
0 |
T123 |
30956 |
52 |
0 |
0 |
T134 |
15520 |
8 |
0 |
0 |
T144 |
71972 |
488 |
0 |
0 |
T152 |
8720 |
1 |
0 |
0 |
T153 |
8696 |
11 |
0 |
0 |
T159 |
180367 |
464 |
0 |
0 |
T160 |
2093 |
4 |
0 |
0 |
T161 |
13913 |
21 |
0 |
0 |
T162 |
36054 |
39 |
0 |
0 |