Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1558615	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1660636

1

T1

2008

T2

4

T3

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2523470	1			T1	2268		T2	1		T3	110
values[0x0]	346848	1			T1	444		T2	4		T3	27
values[0x1]	348933	1			T1	455		T2	3		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1176930	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2042321

1

T1

2259

T2

5

T3

78

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15218	1			T1	28		T14	2		T5	17
valid_sources[0x01]	11523	1			T1	15		T4	5		T14	1
valid_sources[0x02]	9674	1			T1	7		T4	8		T5	11
valid_sources[0x03]	10810	1			T1	18		T4	18		T14	2
valid_sources[0x04]	10178	1			T1	9		T4	15		T14	1
valid_sources[0x05]	18989	1			T1	21		T4	10		T14	4
valid_sources[0x06]	9939	1			T1	6		T3	2		T4	17
valid_sources[0x07]	20574	1			T1	24		T3	1		T4	28
valid_sources[0x08]	10025	1			T1	4		T4	5		T5	15
valid_sources[0x09]	10910	1			T1	28		T4	32		T14	1
valid_sources[0x0a]	9951	1			T1	31		T4	17		T5	11
valid_sources[0x0b]	11821	1			T1	3		T4	12		T14	1
valid_sources[0x0c]	10674	1			T1	18		T3	5		T4	24
valid_sources[0x0d]	10867	1			T1	14		T4	9		T5	9
valid_sources[0x0e]	9590	1			T1	12		T4	1		T14	2
valid_sources[0x0f]	16778	1			T1	15		T4	23		T5	8
valid_sources[0x10]	10617	1			T4	31		T5	10		T6	9
valid_sources[0x11]	11645	1			T1	11		T3	13		T4	14
valid_sources[0x12]	13269	1			T1	15		T2	1		T3	1
valid_sources[0x13]	66511	1			T1	13		T4	35		T14	4
valid_sources[0x14]	17073	1			T4	40		T14	1		T5	17
valid_sources[0x15]	9585	1			T1	37		T4	25		T14	2
valid_sources[0x16]	11265	1			T1	6		T4	32		T14	2
valid_sources[0x17]	12411	1			T1	20		T4	19		T14	3
valid_sources[0x18]	14169	1			T1	25		T3	11		T4	18
valid_sources[0x19]	21310	1			T1	11		T2	1		T4	18
valid_sources[0x1a]	12257	1			T4	36		T14	2		T5	8
valid_sources[0x1b]	10376	1			T1	12		T2	1		T4	25
valid_sources[0x1c]	24888	1			T1	12		T4	15		T14	2
valid_sources[0x1d]	9248	1			T1	1		T4	5		T14	1
valid_sources[0x1e]	17877	1			T1	6		T4	21		T14	1
valid_sources[0x1f]	13251	1			T1	4		T4	10		T5	16
valid_sources[0x20]	10719	1			T3	2		T4	15		T14	6
valid_sources[0x21]	10443	1			T1	24		T4	14		T14	2
valid_sources[0x22]	11377	1			T1	26		T4	12		T14	3
valid_sources[0x23]	9600	1			T1	2		T4	8		T14	1
valid_sources[0x24]	11045	1			T1	1		T4	39		T14	5
valid_sources[0x25]	13190	1			T1	23		T4	27		T14	2
valid_sources[0x26]	16012	1			T1	14		T4	15		T5	15
valid_sources[0x27]	10371	1			T1	16		T2	1		T4	2
valid_sources[0x28]	11552	1			T1	13		T3	2		T4	14
valid_sources[0x29]	14901	1			T1	15		T4	48		T5	18
valid_sources[0x2a]	11198	1			T1	20		T3	1		T4	1
valid_sources[0x2b]	10921	1			T1	13		T4	18		T14	1
valid_sources[0x2c]	11927	1			T1	24		T4	13		T5	13
valid_sources[0x2d]	13230	1			T1	9		T14	2		T5	14
valid_sources[0x2e]	10493	1			T1	18		T4	7		T14	1
valid_sources[0x2f]	16243	1			T1	7		T4	16		T14	1
valid_sources[0x30]	14458	1			T1	2		T4	16		T5	7
valid_sources[0x31]	10408	1			T1	4		T4	10		T14	4
valid_sources[0x32]	10788	1			T1	1		T4	7		T14	2
valid_sources[0x33]	58260	1			T1	2		T4	18		T14	2
valid_sources[0x34]	13266	1			T1	11		T4	35		T14	1
valid_sources[0x35]	10014	1			T1	8		T4	8		T5	14
valid_sources[0x36]	10036	1			T1	19		T4	37		T14	1
valid_sources[0x37]	10658	1			T1	10		T4	13		T14	2
valid_sources[0x38]	11318	1			T1	14		T4	24		T14	3
valid_sources[0x39]	11012	1			T1	5		T3	2		T4	8
valid_sources[0x3a]	10441	1			T4	42		T14	4		T5	11
valid_sources[0x3b]	10381	1			T1	7		T4	36		T14	2
valid_sources[0x3c]	10799	1			T1	1		T3	1		T4	6
valid_sources[0x3d]	14404	1			T4	22		T14	3		T5	9
valid_sources[0x3e]	10672	1			T1	51		T4	5		T14	2
valid_sources[0x3f]	12610	1			T1	25		T2	1		T4	31
valid_sources[0x40]	13290	1			T4	4		T14	3		T5	12
valid_sources[0x41]	10451	1			T4	8		T14	3		T5	13
valid_sources[0x42]	13824	1			T1	9		T4	28		T14	2
valid_sources[0x43]	13971	1			T1	11		T4	27		T14	1
valid_sources[0x44]	9272	1			T1	3		T4	33		T14	1
valid_sources[0x45]	12390	1			T1	2		T3	3		T4	9
valid_sources[0x46]	10764	1			T1	3		T4	25		T5	17
valid_sources[0x47]	11561	1			T1	8		T4	15		T14	2
valid_sources[0x48]	12146	1			T1	15		T4	24		T14	2
valid_sources[0x49]	10204	1			T4	27		T14	2		T5	20
valid_sources[0x4a]	12457	1			T1	1		T4	21		T14	5
valid_sources[0x4b]	10254	1			T1	10		T4	15		T14	1
valid_sources[0x4c]	16188	1			T1	25		T14	1		T5	13
valid_sources[0x4d]	10164	1			T1	29		T4	13		T5	16
valid_sources[0x4e]	11367	1			T1	7		T4	3		T14	2
valid_sources[0x4f]	11690	1			T1	3		T3	1		T4	2
valid_sources[0x50]	11139	1			T1	4		T4	12		T5	17
valid_sources[0x51]	12577	1			T1	8		T3	9		T4	17
valid_sources[0x52]	10505	1			T1	31		T3	3		T4	7
valid_sources[0x53]	11956	1			T4	11		T14	3		T5	19
valid_sources[0x54]	10052	1			T1	29		T4	19		T14	1
valid_sources[0x55]	10066	1			T1	29		T4	8		T14	2
valid_sources[0x56]	29227	1			T1	5		T4	37		T14	1
valid_sources[0x57]	9686	1			T1	10		T4	4		T14	3
valid_sources[0x58]	10230	1			T1	18		T4	5		T14	1
valid_sources[0x59]	10841	1			T1	15		T4	31		T5	15
valid_sources[0x5a]	10007	1			T1	10		T4	16		T14	1
valid_sources[0x5b]	10279	1			T1	10		T4	5		T14	2
valid_sources[0x5c]	10754	1			T1	1		T3	4		T4	3
valid_sources[0x5d]	18281	1			T1	3		T4	18		T14	3
valid_sources[0x5e]	9906	1			T4	4		T14	1		T5	13
valid_sources[0x5f]	9824	1			T1	19		T4	25		T14	1
valid_sources[0x60]	10985	1			T4	4		T14	4		T5	11
valid_sources[0x61]	9992	1			T4	25		T14	2		T5	20
valid_sources[0x62]	11960	1			T1	40		T4	18		T14	1
valid_sources[0x63]	11715	1			T4	32		T14	3		T5	12
valid_sources[0x64]	11028	1			T1	17		T4	20		T14	3
valid_sources[0x65]	13994	1			T1	14		T4	18		T14	1
valid_sources[0x66]	10980	1			T1	2		T4	36		T14	1
valid_sources[0x67]	11270	1			T1	4		T4	5		T14	1
valid_sources[0x68]	11133	1			T1	20		T4	21		T14	3
valid_sources[0x69]	10174	1			T1	6		T3	10		T4	29
valid_sources[0x6a]	10780	1			T3	5		T4	23		T14	1
valid_sources[0x6b]	10918	1			T1	6		T4	20		T5	15
valid_sources[0x6c]	10896	1			T1	3		T4	25		T5	11
valid_sources[0x6d]	10179	1			T1	9		T4	22		T14	1
valid_sources[0x6e]	10639	1			T1	14		T3	3		T4	14
valid_sources[0x6f]	10314	1			T1	22		T14	4		T5	18
valid_sources[0x70]	11133	1			T1	3		T4	12		T5	12
valid_sources[0x71]	10562	1			T1	16		T4	9		T14	2
valid_sources[0x72]	9709	1			T1	17		T4	22		T14	2
valid_sources[0x73]	10013	1			T1	7		T3	6		T4	11
valid_sources[0x74]	10416	1			T1	34		T4	2		T14	2
valid_sources[0x75]	10065	1			T1	7		T4	17		T14	1
valid_sources[0x76]	10559	1			T1	22		T4	22		T14	4
valid_sources[0x77]	10410	1			T1	2		T4	12		T14	2
valid_sources[0x78]	10209	1			T1	3		T4	10		T14	2
valid_sources[0x79]	13913	1			T1	6		T4	28		T14	1
valid_sources[0x7a]	12327	1			T1	21		T4	11		T5	19
valid_sources[0x7b]	11682	1			T1	23		T4	14		T14	2
valid_sources[0x7c]	10533	1			T1	1		T4	21		T14	2
valid_sources[0x7d]	13687	1			T1	7		T4	20		T14	4
valid_sources[0x7e]	9899	1			T1	12		T4	11		T5	15
valid_sources[0x7f]	9818	1			T1	33		T4	39		T14	2
valid_sources[0x80]	14484	1			T4	5		T14	1		T5	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1031641

1

T1

1112

T3

14

T4

1442

values[0x0]

all_enables

biggest_size

317173

1

T1

443

T2

3

T3

22

values[0x1]

all_enables

biggest_size

311822

1

T1

453

T2

1

T3

15