SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[spi_device_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 2810739 | 1 | T1 | 2335 | T2 | 8 | T3 | 149 | ||||
auto[1] | 430184 | 1 | T1 | 832 | T3 | 11 | T4 | 1856 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3240599 | 1 | T1 | 3167 | T2 | 8 | T3 | 160 | ||||
values[1] | 36 | 1 | T37 | 3 | T119 | 3 | T141 | 3 | ||||
values[2] | 10 | 1 | T119 | 1 | T120 | 1 | T141 | 1 | ||||
values[3] | 161 | 1 | T37 | 7 | T119 | 7 | T120 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 3240605 | 1 | T1 | 3167 | T2 | 8 | T3 | 160 | ||||
values[1] | 34 | 1 | T37 | 2 | T119 | 1 | T141 | 3 | ||||
values[2] | 7 | 1 | T120 | 1 | T142 | 2 | T375 | 1 | ||||
values[3] | 165 | 1 | T37 | 7 | T119 | 9 | T120 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 3240453 | 1 | T1 | 3167 | T2 | 8 | T3 | 160 | ||||
auto[TlIntgErrCmd] | 152 | 1 | T37 | 8 | T119 | 7 | T120 | 3 | ||||
auto[TlIntgErrData] | 146 | 1 | T37 | 11 | T119 | 12 | T120 | 4 | ||||
auto[TlIntgErrBoth] | 172 | 1 | T37 | 11 | T119 | 11 | T120 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |