Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
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Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_cgs_wrap[spi_device_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_cgs_wrap[spi_device_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_cgs_wrap[spi_device_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00


Variables for Group Instance tl_intg_err_cgs_wrap[spi_device_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_is_mem 2 0 2 100.00 100 1 1 2
cp_num_cmd_err_bits 4 0 4 100.00 100 1 1 0
cp_num_data_err_bits 4 0 4 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0


Summary for Variable cp_is_mem

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_mem

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2810739 1 T1 2335 T2 8 T3 149
auto[1] 430184 1 T1 832 T3 11 T4 1856



Summary for Variable cp_num_cmd_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_cmd_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3240599 1 T1 3167 T2 8 T3 160
values[1] 36 1 T37 3 T119 3 T141 3
values[2] 10 1 T119 1 T120 1 T141 1
values[3] 161 1 T37 7 T119 7 T120 2



Summary for Variable cp_num_data_err_bits

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_num_data_err_bits

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3240605 1 T1 3167 T2 8 T3 160
values[1] 34 1 T37 2 T119 1 T141 3
values[2] 7 1 T120 1 T142 2 T375 1
values[3] 165 1 T37 7 T119 9 T120 4



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3240453 1 T1 3167 T2 8 T3 160
auto[TlIntgErrCmd] 152 1 T37 8 T119 7 T120 3
auto[TlIntgErrData] 146 1 T37 11 T119 12 T120 4
auto[TlIntgErrBoth] 172 1 T37 11 T119 11 T120 3

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