Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1579073

1

T1

1159

T2

4

T3

109

full_word

1661850

1

T1

2008

T2

4

T3

51

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3240453	1			T1	3167		T2	8		T3	160
auto[TlIntgErrCmd]	152	1			T37	8		T119	7		T120	3
auto[TlIntgErrData]	146	1			T37	11		T119	12		T120	4
auto[TlIntgErrBoth]	172	1			T37	11		T119	11		T120	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2526791

1

T1

2268

T2

1

T3

110

auto[1]

714132

1

T1

899

T2

7

T3

50

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1494677	1			T1	1156		T2	1		T3	96
auto[TlIntgErrNone]	partial	auto[1]	83963	1			T1	3		T2	3		T3	13
auto[TlIntgErrNone]	full_word	auto[0]	1031902	1			T1	1112		T3	14		T4	1442
auto[TlIntgErrNone]	full_word	auto[1]	629911	1			T1	896		T2	4		T3	37
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T37	1		T119	2		T120	1
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T37	7		T119	5		T120	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T376	1		T377	1		T378	2
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T142	1		T379	1		T375	1
auto[TlIntgErrData]	partial	auto[0]	70	1			T37	7		T119	2		T120	1
auto[TlIntgErrData]	partial	auto[1]	60	1			T37	3		T119	5		T120	2
auto[TlIntgErrData]	full_word	auto[0]	7	1			T119	2		T120	1		T376	1
auto[TlIntgErrData]	full_word	auto[1]	9	1			T37	1		T119	3		T142	1
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T37	5		T119	7		T120	2
auto[TlIntgErrBoth]	partial	auto[1]	97	1			T37	6		T119	4		T120	1
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T141	1		T142	1		T379	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T142	1		T375	1		T380	1