Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	160488885	607179	0	0
gen_wmask[1].MaskCheckPortA_A	160488885	607179	0	0
gen_wmask[2].MaskCheckPortA_A	160488885	607179	0	0
gen_wmask[3].MaskCheckPortA_A	160488885	607179	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160488885	607179	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	74	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	21	0	0
T16	1144	55	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160488885	607179	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	74	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	21	0	0
T16	1144	55	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160488885	607179	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	74	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	21	0	0
T16	1144	55	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160488885	607179	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	74	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	21	0	0
T16	1144	55	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	121474548	441133	0	0
gen_wmask[1].MaskCheckPortA_A	121474548	441133	0	0
gen_wmask[2].MaskCheckPortA_A	121474548	441133	0	0
gen_wmask[3].MaskCheckPortA_A	121474548	441133	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	441133	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	33	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	10	0	0
T16	0	18	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	441133	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	33	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	10	0	0
T16	0	18	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	441133	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	33	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	10	0	0
T16	0	18	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	441133	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	33	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	10	0	0
T16	0	18	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	39014337	166046	0	0
gen_wmask[1].MaskCheckPortA_A	39014337	166046	0	0
gen_wmask[2].MaskCheckPortA_A	39014337	166046	0	0
gen_wmask[3].MaskCheckPortA_A	39014337	166046	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	166046	0	0
T3	1760	41	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	11	0	0
T16	1144	37	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	166046	0	0
T3	1760	41	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	11	0	0
T16	1144	37	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	166046	0	0
T3	1760	41	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	11	0	0
T16	1144	37	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	166046	0	0
T3	1760	41	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	11	0	0
T16	1144	37	0	0
T19	0	2832	0	0
T55	0	135	0	0
T57	0	3074	0	0
T60	0	76	0	0
T62	0	4318	0	0
T63	0	39	0	0
T64	0	62	0	0