Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 10 | 62.50 |
Logical | 16 | 10 | 62.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T15,T16 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T15,T16 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T15,T16 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T15,T16 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T15,T16 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T15,T16 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T15,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
43029 |
0 |
0 |
T3 |
4799 |
11 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
10 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T62 |
0 |
1117 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
43029 |
0 |
0 |
T3 |
4799 |
11 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
10 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T62 |
0 |
1117 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 18 | 75.00 |
Logical | 24 | 18 | 75.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T16,T60 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T15,T16 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T15,T16 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T3,T16,T60 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T15,T16 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T15,T16 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T15,T16 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T16,T60 |
1 | 0 | Covered | T3,T15,T16 |
1 | 1 | Covered | T1,T2,T3 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T15,T16 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
9 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T15,T16 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T15,T16 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T15,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
80411 |
0 |
0 |
T3 |
4799 |
60 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
39 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
91 |
0 |
0 |
T62 |
0 |
5030 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
80411 |
0 |
0 |
T3 |
4799 |
60 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
39 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
91 |
0 |
0 |
T62 |
0 |
5030 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
| Total | Covered | Percent |
Conditions | 16 | 9 | 56.25 |
Logical | 16 | 9 | 56.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T15,T16 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T15,T16 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T15,T16 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T15,T16 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T15,T16 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T15,T16 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.u_req_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
43029 |
0 |
0 |
T3 |
4799 |
11 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
10 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T62 |
0 |
1117 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
121414305 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
121474548 |
43029 |
0 |
0 |
T3 |
4799 |
11 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
10 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T62 |
0 |
1117 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
3782819 |
0 |
0 |
T1 |
57235 |
4013 |
0 |
0 |
T2 |
1549 |
8 |
0 |
0 |
T3 |
4799 |
160 |
0 |
0 |
T4 |
88191 |
6598 |
0 |
0 |
T5 |
51612 |
3388 |
0 |
0 |
T6 |
101513 |
897 |
0 |
0 |
T8 |
631962 |
2637 |
0 |
0 |
T9 |
131405 |
1740 |
0 |
0 |
T10 |
305106 |
20817 |
0 |
0 |
T14 |
87494 |
469 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
834 |
834 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
6324881 |
0 |
0 |
T1 |
57235 |
11255 |
0 |
0 |
T2 |
1549 |
8 |
0 |
0 |
T3 |
4799 |
723 |
0 |
0 |
T4 |
88191 |
14101 |
0 |
0 |
T5 |
51612 |
3385 |
0 |
0 |
T6 |
101513 |
897 |
0 |
0 |
T8 |
631962 |
1805 |
0 |
0 |
T9 |
131405 |
1166 |
0 |
0 |
T10 |
305106 |
44589 |
0 |
0 |
T14 |
87494 |
469 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
834 |
834 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
615597 |
0 |
0 |
T1 |
57235 |
1665 |
0 |
0 |
T2 |
1549 |
0 |
0 |
0 |
T3 |
4799 |
0 |
0 |
0 |
T4 |
88191 |
3714 |
0 |
0 |
T5 |
51612 |
832 |
0 |
0 |
T6 |
101513 |
832 |
0 |
0 |
T8 |
631962 |
1663 |
0 |
0 |
T9 |
131405 |
1667 |
0 |
0 |
T10 |
305106 |
8509 |
0 |
0 |
T11 |
0 |
4218 |
0 |
0 |
T12 |
0 |
1670 |
0 |
0 |
T13 |
0 |
832 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
834 |
834 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
537603 |
0 |
0 |
T1 |
57235 |
834 |
0 |
0 |
T2 |
1549 |
0 |
0 |
0 |
T3 |
4799 |
0 |
0 |
0 |
T4 |
88191 |
1863 |
0 |
0 |
T5 |
51612 |
832 |
0 |
0 |
T6 |
101513 |
832 |
0 |
0 |
T8 |
631962 |
832 |
0 |
0 |
T9 |
131405 |
836 |
0 |
0 |
T10 |
305106 |
6329 |
0 |
0 |
T11 |
0 |
2112 |
0 |
0 |
T12 |
0 |
840 |
0 |
0 |
T13 |
0 |
2611 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
834 |
834 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
54896 |
0 |
0 |
T3 |
4799 |
11 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
10 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
20 |
0 |
0 |
T62 |
0 |
1117 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
834 |
834 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
94266 |
0 |
0 |
T3 |
4799 |
60 |
0 |
0 |
T4 |
88191 |
0 |
0 |
0 |
T5 |
51612 |
0 |
0 |
0 |
T6 |
101513 |
0 |
0 |
0 |
T8 |
631962 |
0 |
0 |
0 |
T9 |
131405 |
0 |
0 |
0 |
T10 |
305106 |
0 |
0 |
0 |
T14 |
87494 |
0 |
0 |
0 |
T15 |
1092 |
4 |
0 |
0 |
T16 |
3661 |
39 |
0 |
0 |
T19 |
0 |
731 |
0 |
0 |
T55 |
0 |
36 |
0 |
0 |
T57 |
0 |
792 |
0 |
0 |
T60 |
0 |
91 |
0 |
0 |
T62 |
0 |
5030 |
0 |
0 |
T63 |
0 |
12 |
0 |
0 |
T64 |
0 |
16 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
123414033 |
123304124 |
0 |
0 |
T1 |
57235 |
57163 |
0 |
0 |
T2 |
1549 |
1492 |
0 |
0 |
T3 |
4799 |
4707 |
0 |
0 |
T4 |
88191 |
88095 |
0 |
0 |
T5 |
51612 |
51540 |
0 |
0 |
T6 |
101513 |
101508 |
0 |
0 |
T8 |
631962 |
631864 |
0 |
0 |
T9 |
131405 |
131316 |
0 |
0 |
T10 |
305106 |
305012 |
0 |
0 |
T14 |
87494 |
87395 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
834 |
834 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |