Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	123414033	3092219	0	0
DepthKnown_A	123414033	123304124	0	0
RvalidKnown_A	123414033	123304124	0	0
WreadyKnown_A	123414033	123304124	0	0
gen_passthru_fifo.paramCheckPass	834	834	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	3092219	0	0
T1	57235	2348	0	0
T2	1549	8	0	0
T3	4799	149	0	0
T4	88191	2873	0	0
T5	51612	2556	0	0
T6	101513	65	0	0
T8	631962	973	0	0
T9	131405	73	0	0
T10	305106	12276	0	0
T14	87494	469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	123304124	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	123304124	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	123304124	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	834	834	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	123414033	5693012	0	0
DepthKnown_A	123414033	123304124	0	0
RvalidKnown_A	123414033	123304124	0	0
WreadyKnown_A	123414033	123304124	0	0
gen_passthru_fifo.paramCheckPass	834	834	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	5693012	0	0
T1	57235	10421	0	0
T2	1549	8	0	0
T3	4799	663	0	0
T4	88191	12238	0	0
T5	51612	2553	0	0
T6	101513	65	0	0
T8	631962	973	0	0
T9	131405	330	0	0
T10	305106	38260	0	0
T14	87494	469	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	123304124	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	123304124	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	123414033	123304124	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	834	834	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0