Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.27	100.00	74.07			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	65.57	95.45	55.56			80.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
65.57	95.45

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T16
1	0	Covered	T3,T15,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Unreachable
1	1	Covered	T3,T15,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
65.57	55.56

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T15,T19

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	199503222	159845537	0	0
CheckNGreaterZero_A	1977	1977	0	0
GntImpliesReady_A	199503222	733081	0	0
GntImpliesValid_A	199503222	733081	0	0
GrantKnown_A	199503222	159845537	0	0
IdxKnown_A	199503222	159845537	0	0
IndexIsCorrect_A	199503222	733081	0	0
LockArbDecision_A	199503222	0	0	0
NoReadyValidNoGrant_A	199503222	0	0	0
ReadyAndValidImplyGrant_A	199503222	733081	0	0
ReqAndReadyImplyGrant_A	199503222	733081	0	0
ReqImpliesValid_A	199503222	733081	0	0
ReqStaysHighUntilGranted0_M	199503222	0	0	0
RoundRobin_A	199503222	0	0	659
ValidKnown_A	199503222	159845537	0	0
gen_data_port_assertion.DataFlow_A	199503222	733081	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	159845537	0	0
T1	217397	217325	0	0
T2	1837	1636	0	0
T3	8319	6467	0	0
T4	253225	170139	0	0
T5	193768	121318	0	0
T6	504709	303106	0	0
T8	840698	735872	0	0
T9	382829	256838	0	0
T10	423086	364002	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	357750	217707	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1977	1977	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T14	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	733081	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	119	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	36	0	0
T16	1144	83	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	733081	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	119	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	36	0	0
T16	1144	83	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	159845537	0	0
T1	217397	217325	0	0
T2	1837	1636	0	0
T3	8319	6467	0	0
T4	253225	170139	0	0
T5	193768	121318	0	0
T6	504709	303106	0	0
T8	840698	735872	0	0
T9	382829	256838	0	0
T10	423086	364002	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	357750	217707	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	159845537	0	0
T1	217397	217325	0	0
T2	1837	1636	0	0
T3	8319	6467	0	0
T4	253225	170139	0	0
T5	193768	121318	0	0
T6	504709	303106	0	0
T8	840698	735872	0	0
T9	382829	256838	0	0
T10	423086	364002	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	357750	217707	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	733081	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	119	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	36	0	0
T16	1144	83	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	733081	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	119	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	36	0	0
T16	1144	83	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	733081	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	119	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	36	0	0
T16	1144	83	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	733081	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	119	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	36	0	0
T16	1144	83	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	0	0	659

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	159845537	0	0
T1	217397	217325	0	0
T2	1837	1636	0	0
T3	8319	6467	0	0
T4	253225	170139	0	0
T5	193768	121318	0	0
T6	504709	303106	0	0
T8	840698	735872	0	0
T9	382829	256838	0	0
T10	423086	364002	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	357750	217707	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	199503222	733081	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	6559	119	0	0
T4	170708	1856	0	0
T5	122690	832	0	0
T6	303111	832	0	0
T8	736330	832	0	0
T9	257117	832	0	0
T10	364096	4672	0	0
T14	222622	0	0	0
T15	704	36	0	0
T16	1144	83	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	21	95.45
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	8	80.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	39014337	25666160	0	0
CheckNGreaterZero_A	659	659	0	0
GntImpliesReady_A	39014337	0	0	0
GntImpliesValid_A	39014337	0	0	0
GrantKnown_A	39014337	25666160	0	0
IdxKnown_A	39014337	25666160	0	0
IndexIsCorrect_A	39014337	0	0	0
LockArbDecision_A	39014337	0	0	0
NoReadyValidNoGrant_A	39014337	0	0	0
ReadyAndValidImplyGrant_A	39014337	0	0	0
ReqAndReadyImplyGrant_A	39014337	0	0	0
ReqImpliesValid_A	39014337	0	0	0
ReqStaysHighUntilGranted0_M	39014337	0	0	0
RoundRobin_A	39014337	0	0	0
ValidKnown_A	39014337	25666160	0	0
gen_data_port_assertion.DataFlow_A	39014337	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	25666160	0	0
T1	160162	160162	0	0
T2	144	0	0	0
T3	1760	0	0	0
T4	82517	82044	0	0
T5	71078	69778	0	0
T6	201598	201598	0	0
T8	104368	104008	0	0
T9	125712	125522	0	0
T10	58990	58990	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	135128	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	25666160	0	0
T1	160162	160162	0	0
T2	144	0	0	0
T3	1760	0	0	0
T4	82517	82044	0	0
T5	71078	69778	0	0
T6	201598	201598	0	0
T8	104368	104008	0	0
T9	125712	125522	0	0
T10	58990	58990	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	135128	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	25666160	0	0
T1	160162	160162	0	0
T2	144	0	0	0
T3	1760	0	0	0
T4	82517	82044	0	0
T5	71078	69778	0	0
T6	201598	201598	0	0
T8	104368	104008	0	0
T9	125712	125522	0	0
T10	58990	58990	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	135128	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	25666160	0	0
T1	160162	160162	0	0
T2	144	0	0	0
T3	1760	0	0	0
T4	82517	82044	0	0
T5	71078	69778	0	0
T6	201598	201598	0	0
T8	104368	104008	0	0
T9	125712	125522	0	0
T10	58990	58990	0	0
T11	0	165608	0	0
T12	0	158784	0	0
T13	0	12949	0	0
T14	135128	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T16
1	0	Covered	T3,T15,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T14
1	0	Unreachable
1	1	Covered	T3,T15,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T15,T16
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	39014337	12765072	0	0
CheckNGreaterZero_A	659	659	0	0
GntImpliesReady_A	39014337	248919	0	0
GntImpliesValid_A	39014337	248919	0	0
GrantKnown_A	39014337	12765072	0	0
IdxKnown_A	39014337	12765072	0	0
IndexIsCorrect_A	39014337	248919	0	0
LockArbDecision_A	39014337	0	0	0
NoReadyValidNoGrant_A	39014337	0	0	0
ReadyAndValidImplyGrant_A	39014337	248919	0	0
ReqAndReadyImplyGrant_A	39014337	248919	0	0
ReqImpliesValid_A	39014337	248919	0	0
ReqStaysHighUntilGranted0_M	39014337	0	0	0
RoundRobin_A	39014337	0	0	0
ValidKnown_A	39014337	12765072	0	0
gen_data_port_assertion.DataFlow_A	39014337	248919	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	12765072	0	0
T2	144	144	0	0
T3	1760	1760	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	130312	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	248919	0	0
T3	1760	75	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	22	0	0
T16	1144	55	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	248919	0	0
T3	1760	75	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	22	0	0
T16	1144	55	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	12765072	0	0
T2	144	144	0	0
T3	1760	1760	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	130312	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	12765072	0	0
T2	144	144	0	0
T3	1760	1760	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	130312	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	248919	0	0
T3	1760	75	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	22	0	0
T16	1144	55	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	248919	0	0
T3	1760	75	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	22	0	0
T16	1144	55	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	248919	0	0
T3	1760	75	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	22	0	0
T16	1144	55	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	248919	0	0
T3	1760	75	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	22	0	0
T16	1144	55	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	12765072	0	0
T2	144	144	0	0
T3	1760	1760	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	130312	0	0
T15	704	704	0	0
T16	0	1144	0	0
T19	0	86904	0	0
T21	0	8600	0	0
T60	0	1488	0	0
T61	0	101936	0	0
T62	0	179560	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39014337	248919	0	0
T3	1760	75	0	0
T4	82517	0	0	0
T5	71078	0	0	0
T6	201598	0	0	0
T8	104368	0	0	0
T9	125712	0	0	0
T10	58990	0	0	0
T14	135128	0	0	0
T15	704	22	0	0
T16	1144	55	0	0
T19	0	4141	0	0
T55	0	169	0	0
T57	0	4810	0	0
T60	0	98	0	0
T62	0	6305	0	0
T63	0	52	0	0
T64	0	62	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T15,T19

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T16
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	121474548	121414305	0	0
CheckNGreaterZero_A	659	659	0	0
GntImpliesReady_A	121474548	484162	0	0
GntImpliesValid_A	121474548	484162	0	0
GrantKnown_A	121474548	121414305	0	0
IdxKnown_A	121474548	121414305	0	0
IndexIsCorrect_A	121474548	484162	0	0
LockArbDecision_A	121474548	0	0	0
NoReadyValidNoGrant_A	121474548	0	0	0
ReadyAndValidImplyGrant_A	121474548	484162	0	0
ReqAndReadyImplyGrant_A	121474548	484162	0	0
ReqImpliesValid_A	121474548	484162	0	0
ReqStaysHighUntilGranted0_M	121474548	0	0	0
RoundRobin_A	121474548	0	0	659
ValidKnown_A	121474548	121414305	0	0
gen_data_port_assertion.DataFlow_A	121474548	484162	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	659	659	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	484162	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	44	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	14	0	0
T16	0	28	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	484162	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	44	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	14	0	0
T16	0	28	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	484162	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	44	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	14	0	0
T16	0	28	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	484162	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	44	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	14	0	0
T16	0	28	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	484162	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	44	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	14	0	0
T16	0	28	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	484162	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	44	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	14	0	0
T16	0	28	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	0	0	659

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	121414305	0	0
T1	57235	57163	0	0
T2	1549	1492	0	0
T3	4799	4707	0	0
T4	88191	88095	0	0
T5	51612	51540	0	0
T6	101513	101508	0	0
T8	631962	631864	0	0
T9	131405	131316	0	0
T10	305106	305012	0	0
T14	87494	87395	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121474548	484162	0	0
T1	57235	832	0	0
T2	1549	0	0	0
T3	4799	44	0	0
T4	88191	1856	0	0
T5	51612	832	0	0
T6	101513	832	0	0
T8	631962	832	0	0
T9	131405	832	0	0
T10	305106	4672	0	0
T14	87494	0	0	0
T15	0	14	0	0
T16	0	28	0	0