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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.12 97.61 92.93 98.61 80.85 96.01 90.94 87.88


Total test records in report: 834
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T128 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1523495262 May 05 01:41:09 PM PDT 24 May 05 01:41:12 PM PDT 24 176216976 ps
T761 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3579936156 May 05 01:41:15 PM PDT 24 May 05 01:41:19 PM PDT 24 229843659 ps
T762 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.216863220 May 05 01:41:15 PM PDT 24 May 05 01:41:18 PM PDT 24 95721538 ps
T763 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3151393273 May 05 01:40:58 PM PDT 24 May 05 01:40:59 PM PDT 24 18381915 ps
T764 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.274492925 May 05 01:41:14 PM PDT 24 May 05 01:41:16 PM PDT 24 14105331 ps
T765 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1949358342 May 05 01:41:16 PM PDT 24 May 05 01:41:18 PM PDT 24 308904498 ps
T766 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2201258584 May 05 01:41:03 PM PDT 24 May 05 01:41:21 PM PDT 24 584117908 ps
T132 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3384158674 May 05 01:41:01 PM PDT 24 May 05 01:41:05 PM PDT 24 260261185 ps
T767 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.570164957 May 05 01:41:10 PM PDT 24 May 05 01:41:12 PM PDT 24 29717530 ps
T768 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2462903247 May 05 01:41:02 PM PDT 24 May 05 01:41:03 PM PDT 24 39792267 ps
T769 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1111380436 May 05 01:41:14 PM PDT 24 May 05 01:41:17 PM PDT 24 90255796 ps
T770 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.424462494 May 05 01:41:09 PM PDT 24 May 05 01:41:10 PM PDT 24 18532871 ps
T771 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3174082620 May 05 01:40:52 PM PDT 24 May 05 01:40:53 PM PDT 24 13741031 ps
T772 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1608520043 May 05 01:41:14 PM PDT 24 May 05 01:41:25 PM PDT 24 191317448 ps
T134 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1427909742 May 05 01:40:59 PM PDT 24 May 05 01:41:03 PM PDT 24 255387148 ps
T773 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3001537276 May 05 01:41:22 PM PDT 24 May 05 01:41:23 PM PDT 24 51385233 ps
T774 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1812523585 May 05 01:41:16 PM PDT 24 May 05 01:41:20 PM PDT 24 299382464 ps
T775 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3476766968 May 05 01:41:21 PM PDT 24 May 05 01:41:22 PM PDT 24 15480501 ps
T776 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.48644160 May 05 01:40:49 PM PDT 24 May 05 01:40:50 PM PDT 24 14053423 ps
T126 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.513470784 May 05 01:41:00 PM PDT 24 May 05 01:41:05 PM PDT 24 414684807 ps
T777 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2388011841 May 05 01:40:56 PM PDT 24 May 05 01:40:59 PM PDT 24 137172594 ps
T778 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2343758350 May 05 01:41:25 PM PDT 24 May 05 01:41:26 PM PDT 24 22938704 ps
T779 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2200967120 May 05 01:40:52 PM PDT 24 May 05 01:40:56 PM PDT 24 215465015 ps
T780 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1469693189 May 05 01:40:58 PM PDT 24 May 05 01:41:00 PM PDT 24 20440266 ps
T781 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3211274430 May 05 01:40:56 PM PDT 24 May 05 01:41:20 PM PDT 24 3329978404 ps
T782 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1813884229 May 05 01:40:47 PM PDT 24 May 05 01:40:48 PM PDT 24 38170850 ps
T783 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3892626894 May 05 01:41:18 PM PDT 24 May 05 01:41:20 PM PDT 24 89893104 ps
T784 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3812934583 May 05 01:41:05 PM PDT 24 May 05 01:41:08 PM PDT 24 27156208 ps
T785 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1469876307 May 05 01:40:46 PM PDT 24 May 05 01:40:47 PM PDT 24 17090293 ps
T786 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3738617663 May 05 01:41:24 PM PDT 24 May 05 01:41:25 PM PDT 24 12680001 ps
T787 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3815117731 May 05 01:41:11 PM PDT 24 May 05 01:41:13 PM PDT 24 71806728 ps
T788 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.260183193 May 05 01:41:15 PM PDT 24 May 05 01:41:18 PM PDT 24 167647130 ps
T789 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1262781235 May 05 01:40:56 PM PDT 24 May 05 01:41:08 PM PDT 24 184607953 ps
T790 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1356454840 May 05 01:41:04 PM PDT 24 May 05 01:41:05 PM PDT 24 23383459 ps
T791 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.239021478 May 05 01:41:18 PM PDT 24 May 05 01:41:19 PM PDT 24 19507402 ps
T792 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1629503275 May 05 01:40:59 PM PDT 24 May 05 01:41:01 PM PDT 24 29024589 ps
T793 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3654899995 May 05 01:41:23 PM PDT 24 May 05 01:41:24 PM PDT 24 17021437 ps
T794 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2627496033 May 05 01:41:12 PM PDT 24 May 05 01:41:15 PM PDT 24 180599368 ps
T795 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1834071931 May 05 01:41:04 PM PDT 24 May 05 01:41:09 PM PDT 24 238925207 ps
T796 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2409941162 May 05 01:41:10 PM PDT 24 May 05 01:41:30 PM PDT 24 2451853069 ps
T797 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3238555289 May 05 01:41:14 PM PDT 24 May 05 01:41:15 PM PDT 24 13072667 ps
T798 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3471969885 May 05 01:41:19 PM PDT 24 May 05 01:41:38 PM PDT 24 5786462254 ps
T799 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1585040603 May 05 01:41:26 PM PDT 24 May 05 01:41:27 PM PDT 24 20817691 ps
T130 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2075042737 May 05 01:40:57 PM PDT 24 May 05 01:40:59 PM PDT 24 30094878 ps
T800 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2521001784 May 05 01:41:24 PM PDT 24 May 05 01:41:26 PM PDT 24 16527767 ps
T135 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1479991845 May 05 01:41:15 PM PDT 24 May 05 01:41:20 PM PDT 24 177904155 ps
T801 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2060651359 May 05 01:41:29 PM PDT 24 May 05 01:41:30 PM PDT 24 39075663 ps
T802 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1672521502 May 05 01:40:52 PM PDT 24 May 05 01:41:04 PM PDT 24 182978749 ps
T803 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1733400438 May 05 01:41:20 PM PDT 24 May 05 01:41:21 PM PDT 24 14877427 ps
T804 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1740515517 May 05 01:41:03 PM PDT 24 May 05 01:41:06 PM PDT 24 133777653 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.619613861 May 05 01:40:48 PM PDT 24 May 05 01:40:52 PM PDT 24 1187257867 ps
T805 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.47724055 May 05 01:41:23 PM PDT 24 May 05 01:41:24 PM PDT 24 12244119 ps
T806 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3081340687 May 05 01:40:51 PM PDT 24 May 05 01:40:54 PM PDT 24 712991609 ps
T807 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.903536434 May 05 01:41:28 PM PDT 24 May 05 01:41:29 PM PDT 24 16576005 ps
T808 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2384297537 May 05 01:41:19 PM PDT 24 May 05 01:41:22 PM PDT 24 47055794 ps
T94 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1825145330 May 05 01:40:51 PM PDT 24 May 05 01:40:53 PM PDT 24 39047425 ps
T809 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3083951956 May 05 01:41:09 PM PDT 24 May 05 01:41:11 PM PDT 24 190137279 ps
T810 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3656606448 May 05 01:40:58 PM PDT 24 May 05 01:41:02 PM PDT 24 664795656 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2796367254 May 05 01:40:53 PM PDT 24 May 05 01:40:55 PM PDT 24 125180546 ps
T811 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3109196530 May 05 01:40:46 PM PDT 24 May 05 01:40:47 PM PDT 24 42897717 ps
T812 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1174448800 May 05 01:41:33 PM PDT 24 May 05 01:41:34 PM PDT 24 12479022 ps
T813 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.409442789 May 05 01:41:14 PM PDT 24 May 05 01:41:16 PM PDT 24 36278402 ps
T374 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.878353552 May 05 01:41:10 PM PDT 24 May 05 01:41:15 PM PDT 24 232939543 ps
T814 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2106552595 May 05 01:40:50 PM PDT 24 May 05 01:40:52 PM PDT 24 69688776 ps
T815 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3207036713 May 05 01:41:26 PM PDT 24 May 05 01:41:28 PM PDT 24 40120104 ps
T816 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2678444249 May 05 01:40:46 PM PDT 24 May 05 01:40:49 PM PDT 24 293368281 ps
T817 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3856596317 May 05 01:41:19 PM PDT 24 May 05 01:41:20 PM PDT 24 37453132 ps
T818 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2570963183 May 05 01:40:48 PM PDT 24 May 05 01:40:50 PM PDT 24 230805390 ps
T819 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2864736111 May 05 01:41:21 PM PDT 24 May 05 01:41:22 PM PDT 24 53352278 ps
T820 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.595771359 May 05 01:41:06 PM PDT 24 May 05 01:41:24 PM PDT 24 1179113893 ps
T821 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1266465065 May 05 01:40:58 PM PDT 24 May 05 01:41:18 PM PDT 24 4720376835 ps
T822 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4213431062 May 05 01:41:13 PM PDT 24 May 05 01:41:18 PM PDT 24 1270732311 ps
T823 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2877526387 May 05 01:40:59 PM PDT 24 May 05 01:41:03 PM PDT 24 274703291 ps
T824 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3662191486 May 05 01:41:21 PM PDT 24 May 05 01:41:22 PM PDT 24 50105700 ps
T825 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1059828026 May 05 01:41:22 PM PDT 24 May 05 01:41:23 PM PDT 24 48366149 ps
T826 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.112867934 May 05 01:41:21 PM PDT 24 May 05 01:41:22 PM PDT 24 13138181 ps
T827 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.752210722 May 05 01:40:46 PM PDT 24 May 05 01:40:48 PM PDT 24 611353744 ps
T828 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3086102806 May 05 01:40:50 PM PDT 24 May 05 01:40:52 PM PDT 24 71205532 ps
T829 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3923198505 May 05 01:41:11 PM PDT 24 May 05 01:41:12 PM PDT 24 47168117 ps
T830 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.798059147 May 05 01:40:50 PM PDT 24 May 05 01:40:52 PM PDT 24 87872213 ps
T831 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.539242454 May 05 01:41:26 PM PDT 24 May 05 01:41:27 PM PDT 24 15537476 ps
T832 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.254117288 May 05 01:41:19 PM PDT 24 May 05 01:41:22 PM PDT 24 379216599 ps
T833 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1622418666 May 05 01:41:22 PM PDT 24 May 05 01:41:27 PM PDT 24 82756731 ps
T834 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2358393917 May 05 01:40:49 PM PDT 24 May 05 01:40:57 PM PDT 24 110592147 ps

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3000453608
Short name T6
Test name
Test status
Simulation time 101513532752 ps
CPU time 29.72 seconds
Started May 05 01:57:13 PM PDT 24
Finished May 05 01:57:43 PM PDT 24
Peak memory 226696 kb
Host smart-216e85c2-5d97-439d-a651-cfbef6e79df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000453608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3000453608
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1793315009
Short name T19
Test name
Test status
Simulation time 6643183147 ps
CPU time 34.9 seconds
Started May 05 01:58:16 PM PDT 24
Finished May 05 01:58:51 PM PDT 24
Peak memory 216304 kb
Host smart-ed15be8c-53f9-4cfa-a91e-98d49a0bb7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793315009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1793315009
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_upload.721342391
Short name T8
Test name
Test status
Simulation time 6319653311 ps
CPU time 20.86 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:23 PM PDT 24
Peak memory 223264 kb
Host smart-244a95ca-5f6b-41a0-a213-e89b3643e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721342391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.721342391
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.15712486
Short name T38
Test name
Test status
Simulation time 412129255 ps
CPU time 2.86 seconds
Started May 05 01:40:56 PM PDT 24
Finished May 05 01:40:59 PM PDT 24
Peak memory 216148 kb
Host smart-b83702d8-9b31-4e61-b089-4f3bb5fc9fe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15712486 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.15712486
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1812007601
Short name T62
Test name
Test status
Simulation time 25511856837 ps
CPU time 34.52 seconds
Started May 05 01:57:42 PM PDT 24
Finished May 05 01:58:17 PM PDT 24
Peak memory 216632 kb
Host smart-353dbb27-7f37-4b92-9c77-8cca8b70505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812007601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1812007601
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2421876094
Short name T118
Test name
Test status
Simulation time 613881501 ps
CPU time 10.99 seconds
Started May 05 01:55:57 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 223412 kb
Host smart-a432f85d-47af-4080-a58d-85f56bd3880f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421876094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2421876094
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1561919715
Short name T33
Test name
Test status
Simulation time 254855014 ps
CPU time 1.2 seconds
Started May 05 01:56:17 PM PDT 24
Finished May 05 01:56:19 PM PDT 24
Peak memory 208008 kb
Host smart-6b016533-83d1-41b8-a625-dc2920d83297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561919715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1561919715
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4169524238
Short name T66
Test name
Test status
Simulation time 4907707268 ps
CPU time 18.26 seconds
Started May 05 01:57:52 PM PDT 24
Finished May 05 01:58:10 PM PDT 24
Peak memory 224452 kb
Host smart-15476e10-dc5f-482b-a0a1-6e0c8d0e1343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169524238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4169524238
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3310597702
Short name T98
Test name
Test status
Simulation time 31887402011 ps
CPU time 77.77 seconds
Started May 05 01:57:11 PM PDT 24
Finished May 05 01:58:29 PM PDT 24
Peak memory 216352 kb
Host smart-17c72c18-d74b-4467-922c-81d7c4764ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310597702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3310597702
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1754135899
Short name T5
Test name
Test status
Simulation time 516148614 ps
CPU time 9.67 seconds
Started May 05 01:58:27 PM PDT 24
Finished May 05 01:58:37 PM PDT 24
Peak memory 218696 kb
Host smart-e6df0821-f428-428a-a1ee-a95ace3a89ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754135899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1754135899
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1382314261
Short name T116
Test name
Test status
Simulation time 10045856308 ps
CPU time 30.71 seconds
Started May 05 01:56:11 PM PDT 24
Finished May 05 01:56:43 PM PDT 24
Peak memory 216856 kb
Host smart-2a258d34-09b4-47c2-b841-241509330bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382314261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1382314261
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2920642224
Short name T103
Test name
Test status
Simulation time 11965404069 ps
CPU time 59.36 seconds
Started May 05 01:58:09 PM PDT 24
Finished May 05 01:59:09 PM PDT 24
Peak memory 216328 kb
Host smart-55707d79-7fd5-4111-bc23-95956ce5ac3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920642224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2920642224
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1453076456
Short name T43
Test name
Test status
Simulation time 73924489 ps
CPU time 0.73 seconds
Started May 05 01:55:47 PM PDT 24
Finished May 05 01:55:48 PM PDT 24
Peak memory 216200 kb
Host smart-aaf7d73b-0b84-4902-8559-24c86ddabf85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453076456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1453076456
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.855487644
Short name T22
Test name
Test status
Simulation time 572526644 ps
CPU time 4.32 seconds
Started May 05 01:57:12 PM PDT 24
Finished May 05 01:57:16 PM PDT 24
Peak memory 218648 kb
Host smart-d2dc31a5-45ec-43f0-b4fb-0c2c898a7ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855487644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.855487644
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.63201962
Short name T10
Test name
Test status
Simulation time 3632320392 ps
CPU time 49.72 seconds
Started May 05 01:56:58 PM PDT 24
Finished May 05 01:57:48 PM PDT 24
Peak memory 224572 kb
Host smart-c7e2fe6f-964e-485c-8065-b1a349fccde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63201962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.63201962
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2505052123
Short name T34
Test name
Test status
Simulation time 250094967 ps
CPU time 1.06 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:55:56 PM PDT 24
Peak memory 235028 kb
Host smart-df430fee-dec9-451e-90d5-aa758235e8ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505052123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2505052123
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/6.spi_device_upload.2403792679
Short name T28
Test name
Test status
Simulation time 18485876016 ps
CPU time 20.15 seconds
Started May 05 01:56:01 PM PDT 24
Finished May 05 01:56:22 PM PDT 24
Peak memory 238152 kb
Host smart-39abd6b5-b429-489e-9e21-09cd024878c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403792679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2403792679
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.279435479
Short name T53
Test name
Test status
Simulation time 1685739228 ps
CPU time 9.84 seconds
Started May 05 01:56:43 PM PDT 24
Finished May 05 01:56:54 PM PDT 24
Peak memory 220732 kb
Host smart-0d71fd4a-c533-4df3-a424-2915e86c8202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279435479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.279435479
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3862393569
Short name T214
Test name
Test status
Simulation time 3290927165 ps
CPU time 17.21 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 229796 kb
Host smart-fdf0cf91-281e-423f-beff-c140ecb99f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862393569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3862393569
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2301691290
Short name T279
Test name
Test status
Simulation time 2901338952 ps
CPU time 8.54 seconds
Started May 05 01:56:12 PM PDT 24
Finished May 05 01:56:22 PM PDT 24
Peak memory 218652 kb
Host smart-e80f1daf-4863-4861-b7af-08370cbcb5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301691290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2301691290
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.558263018
Short name T142
Test name
Test status
Simulation time 2254803515 ps
CPU time 13.54 seconds
Started May 05 01:41:10 PM PDT 24
Finished May 05 01:41:24 PM PDT 24
Peak memory 215572 kb
Host smart-d58fa6c8-0226-4d47-8729-215998692633
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558263018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.558263018
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2958066921
Short name T102
Test name
Test status
Simulation time 10558283417 ps
CPU time 40.38 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:56:32 PM PDT 24
Peak memory 216372 kb
Host smart-7c5ba781-adfc-4f9e-95bc-4f084baa0237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958066921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2958066921
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.86532662
Short name T39
Test name
Test status
Simulation time 555530996 ps
CPU time 2.48 seconds
Started May 05 01:40:54 PM PDT 24
Finished May 05 01:40:57 PM PDT 24
Peak memory 206892 kb
Host smart-a5c157ea-0999-49a5-a52f-09781938dac6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86532662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.86532662
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.603244347
Short name T51
Test name
Test status
Simulation time 5116360303 ps
CPU time 15.56 seconds
Started May 05 01:55:50 PM PDT 24
Finished May 05 01:56:06 PM PDT 24
Peak memory 218488 kb
Host smart-dd33eccc-0799-41ec-822c-4d4d6243a035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603244347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
603244347
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_upload.439830625
Short name T243
Test name
Test status
Simulation time 1462779865 ps
CPU time 11.04 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 216404 kb
Host smart-3f00752c-2641-480f-b84a-f5d1486dca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439830625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.439830625
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1571408557
Short name T77
Test name
Test status
Simulation time 4890532276 ps
CPU time 17.17 seconds
Started May 05 01:57:30 PM PDT 24
Finished May 05 01:57:48 PM PDT 24
Peak memory 222600 kb
Host smart-20a0ac94-dee6-48f5-b313-77160f2407f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571408557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1571408557
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4217636475
Short name T14
Test name
Test status
Simulation time 3499850923 ps
CPU time 7.86 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:25 PM PDT 24
Peak memory 216260 kb
Host smart-2c1afe1e-0a9a-443e-a8a9-9fc7c3abba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217636475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4217636475
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4262878660
Short name T129
Test name
Test status
Simulation time 261018199 ps
CPU time 4.29 seconds
Started May 05 01:41:05 PM PDT 24
Finished May 05 01:41:10 PM PDT 24
Peak memory 215364 kb
Host smart-3bd5edb2-4853-4625-9c7a-5ce7f8e56ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262878660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4262878660
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2337499281
Short name T273
Test name
Test status
Simulation time 27120731533 ps
CPU time 15.4 seconds
Started May 05 01:56:38 PM PDT 24
Finished May 05 01:56:54 PM PDT 24
Peak memory 218836 kb
Host smart-d424868b-f314-4fd1-813c-2400dfd6b8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337499281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2337499281
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3107207524
Short name T266
Test name
Test status
Simulation time 71357250253 ps
CPU time 161.06 seconds
Started May 05 01:57:22 PM PDT 24
Finished May 05 02:00:03 PM PDT 24
Peak memory 246708 kb
Host smart-b27db61f-0717-4a60-b8b5-84a4b501e59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107207524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3107207524
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2199316457
Short name T73
Test name
Test status
Simulation time 1031681638 ps
CPU time 3.27 seconds
Started May 05 01:57:48 PM PDT 24
Finished May 05 01:57:52 PM PDT 24
Peak memory 222956 kb
Host smart-9eb00a78-bbd2-425a-a1f1-44664b4df159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199316457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2199316457
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.470135468
Short name T297
Test name
Test status
Simulation time 5837005314 ps
CPU time 55.53 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:56:49 PM PDT 24
Peak memory 251384 kb
Host smart-0bb81975-c519-451f-9cb6-7e78af33be18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470135468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.470135468
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1518753592
Short name T230
Test name
Test status
Simulation time 1229338024 ps
CPU time 7.32 seconds
Started May 05 01:56:07 PM PDT 24
Finished May 05 01:56:15 PM PDT 24
Peak memory 221424 kb
Host smart-58b9d42c-7c14-4d3f-9e28-cf93ebd759fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518753592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1518753592
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2218846195
Short name T242
Test name
Test status
Simulation time 7612570060 ps
CPU time 13.6 seconds
Started May 05 01:57:16 PM PDT 24
Finished May 05 01:57:29 PM PDT 24
Peak memory 237388 kb
Host smart-eadc4f6c-5d4f-4c86-bae7-e2bc85bf1efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218846195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2218846195
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2556799630
Short name T117
Test name
Test status
Simulation time 2288206072 ps
CPU time 32.2 seconds
Started May 05 01:58:13 PM PDT 24
Finished May 05 01:58:45 PM PDT 24
Peak memory 228764 kb
Host smart-0c54b09b-64d7-4593-b7fc-7e93bdb5b3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556799630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2556799630
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1979869336
Short name T282
Test name
Test status
Simulation time 11788645318 ps
CPU time 14.74 seconds
Started May 05 01:55:57 PM PDT 24
Finished May 05 01:56:12 PM PDT 24
Peak memory 224012 kb
Host smart-cfe3cf3c-2584-4368-bbb6-f9b7faf0c98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979869336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1979869336
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2294135654
Short name T260
Test name
Test status
Simulation time 1556915351 ps
CPU time 15.25 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:57:03 PM PDT 24
Peak memory 217344 kb
Host smart-f381b37b-ffdd-4dae-b0f4-3d07dfde4978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294135654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2294135654
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2698419170
Short name T278
Test name
Test status
Simulation time 990340756 ps
CPU time 13.81 seconds
Started May 05 01:55:55 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 224476 kb
Host smart-e226a5fb-1ee6-459b-9589-6ee73c562814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698419170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2698419170
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1070649143
Short name T398
Test name
Test status
Simulation time 5920418724 ps
CPU time 37.71 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:41 PM PDT 24
Peak memory 216332 kb
Host smart-0a30fe5f-80b4-4976-9137-237ab8ca3e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070649143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1070649143
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1714753903
Short name T188
Test name
Test status
Simulation time 625240040 ps
CPU time 8.35 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:23 PM PDT 24
Peak memory 232668 kb
Host smart-2ff1cbc6-9171-49a9-8cb9-894c87940799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714753903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1714753903
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_upload.3330614411
Short name T294
Test name
Test status
Simulation time 11916728213 ps
CPU time 37.87 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:57:23 PM PDT 24
Peak memory 226300 kb
Host smart-312c7441-b850-4ff1-91f9-d73f5449b32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330614411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3330614411
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1342784311
Short name T171
Test name
Test status
Simulation time 1182218771 ps
CPU time 5.67 seconds
Started May 05 01:56:42 PM PDT 24
Finished May 05 01:56:48 PM PDT 24
Peak memory 222348 kb
Host smart-066879e6-4149-4d19-9c95-803035d635cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342784311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1342784311
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2675646269
Short name T264
Test name
Test status
Simulation time 442041104 ps
CPU time 4.17 seconds
Started May 05 01:58:09 PM PDT 24
Finished May 05 01:58:14 PM PDT 24
Peak memory 221156 kb
Host smart-806a6888-17f8-4b2e-b53f-38d75991ee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675646269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2675646269
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_upload.367792725
Short name T7
Test name
Test status
Simulation time 2169243872 ps
CPU time 4.23 seconds
Started May 05 01:57:47 PM PDT 24
Finished May 05 01:57:51 PM PDT 24
Peak memory 234912 kb
Host smart-5eede7e4-5bad-4a14-b305-293c9580d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367792725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.367792725
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2718668069
Short name T1
Test name
Test status
Simulation time 1100721010 ps
CPU time 13 seconds
Started May 05 01:57:12 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 238172 kb
Host smart-4771d0f5-1db2-4f74-82cb-0f14c686f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718668069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2718668069
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2152848717
Short name T299
Test name
Test status
Simulation time 40632344023 ps
CPU time 53.03 seconds
Started May 05 01:57:39 PM PDT 24
Finished May 05 01:58:33 PM PDT 24
Peak memory 240924 kb
Host smart-30534780-18d8-4a6e-bfd2-de26395e1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152848717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2152848717
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3712176249
Short name T405
Test name
Test status
Simulation time 16294351 ps
CPU time 0.75 seconds
Started May 05 01:56:08 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 205396 kb
Host smart-7eb20fa1-87d9-4d6d-8434-92e633c8216d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712176249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3712176249
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1099011536
Short name T182
Test name
Test status
Simulation time 763175980 ps
CPU time 6.39 seconds
Started May 05 01:56:29 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 221852 kb
Host smart-27c7cf58-0ccd-403f-befb-98fcdd5957cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099011536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1099011536
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.830874610
Short name T641
Test name
Test status
Simulation time 6860036147 ps
CPU time 12.88 seconds
Started May 05 01:56:21 PM PDT 24
Finished May 05 01:56:34 PM PDT 24
Peak memory 223472 kb
Host smart-24ab17d6-5b61-4720-8479-2165a82d5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830874610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.830874610
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.582762254
Short name T227
Test name
Test status
Simulation time 12564290013 ps
CPU time 17.49 seconds
Started May 05 01:56:44 PM PDT 24
Finished May 05 01:57:03 PM PDT 24
Peak memory 216684 kb
Host smart-cfd3a0a3-d826-43c3-85a3-ef3bd95fd777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582762254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.582762254
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3150003344
Short name T290
Test name
Test status
Simulation time 4814673526 ps
CPU time 8.24 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 218516 kb
Host smart-cc74e1a0-abcd-4b68-aebc-de70e008e975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150003344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3150003344
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_upload.1695295687
Short name T26
Test name
Test status
Simulation time 529219044 ps
CPU time 5.68 seconds
Started May 05 01:57:41 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 220644 kb
Host smart-05f668d1-c477-4cec-b44d-7536c5d2f643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695295687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1695295687
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.878353552
Short name T374
Test name
Test status
Simulation time 232939543 ps
CPU time 5.11 seconds
Started May 05 01:41:10 PM PDT 24
Finished May 05 01:41:15 PM PDT 24
Peak memory 215416 kb
Host smart-53e0798c-d686-4b7c-8c01-162925870bf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878353552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.878353552
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3987610011
Short name T389
Test name
Test status
Simulation time 5128138361 ps
CPU time 29.72 seconds
Started May 05 01:56:04 PM PDT 24
Finished May 05 01:56:34 PM PDT 24
Peak memory 216688 kb
Host smart-a2841316-57de-4258-9cc9-34d081f638ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987610011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3987610011
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3988351197
Short name T305
Test name
Test status
Simulation time 4057803763 ps
CPU time 52.06 seconds
Started May 05 01:56:06 PM PDT 24
Finished May 05 01:56:59 PM PDT 24
Peak memory 232744 kb
Host smart-cc677d37-d656-4837-9b71-e4e7ab9573f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988351197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3988351197
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3232152956
Short name T210
Test name
Test status
Simulation time 628595970 ps
CPU time 5.34 seconds
Started May 05 01:56:30 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 216752 kb
Host smart-4712b978-8ae0-4680-87e3-b26cbe2dc874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232152956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3232152956
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intercept.680113179
Short name T208
Test name
Test status
Simulation time 417677786 ps
CPU time 2.34 seconds
Started May 05 01:56:39 PM PDT 24
Finished May 05 01:56:42 PM PDT 24
Peak memory 216736 kb
Host smart-9b707ec8-1fce-4795-8fe4-7725fdf57e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680113179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.680113179
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1421448124
Short name T579
Test name
Test status
Simulation time 832490480 ps
CPU time 1.05 seconds
Started May 05 01:56:43 PM PDT 24
Finished May 05 01:56:44 PM PDT 24
Peak memory 207364 kb
Host smart-d512e8a6-f233-43d7-af6a-f2ceade90795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421448124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1421448124
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2142926636
Short name T347
Test name
Test status
Simulation time 13306542496 ps
CPU time 10.06 seconds
Started May 05 01:56:44 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 222976 kb
Host smart-8473d033-89da-4bc5-9643-74e594b5d4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142926636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2142926636
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2645314942
Short name T75
Test name
Test status
Simulation time 26677454696 ps
CPU time 8.57 seconds
Started May 05 01:57:12 PM PDT 24
Finished May 05 01:57:21 PM PDT 24
Peak memory 218764 kb
Host smart-9ed4954b-9534-44c6-b9f6-7601a0e22b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645314942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2645314942
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.924454261
Short name T69
Test name
Test status
Simulation time 841820411 ps
CPU time 9.41 seconds
Started May 05 01:57:19 PM PDT 24
Finished May 05 01:57:29 PM PDT 24
Peak memory 240080 kb
Host smart-c93eab2b-1869-409c-beeb-5925d94839bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924454261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.924454261
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2411352301
Short name T354
Test name
Test status
Simulation time 16246666858 ps
CPU time 48.4 seconds
Started May 05 01:57:27 PM PDT 24
Finished May 05 01:58:16 PM PDT 24
Peak memory 231108 kb
Host smart-2cb8adae-60ce-4e76-9e5a-273c6d19fc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411352301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2411352301
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2957332153
Short name T220
Test name
Test status
Simulation time 8416598699 ps
CPU time 62.65 seconds
Started May 05 01:57:38 PM PDT 24
Finished May 05 01:58:42 PM PDT 24
Peak memory 224552 kb
Host smart-cb07d5d8-e345-4f9e-ac8b-036a3871e2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957332153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2957332153
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2393722402
Short name T283
Test name
Test status
Simulation time 4347639154 ps
CPU time 32.53 seconds
Started May 05 01:57:47 PM PDT 24
Finished May 05 01:58:21 PM PDT 24
Peak memory 232752 kb
Host smart-849bbd49-d19f-4410-9dd3-3dd2ccc80187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393722402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2393722402
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.314971741
Short name T255
Test name
Test status
Simulation time 625239732 ps
CPU time 2.75 seconds
Started May 05 01:58:06 PM PDT 24
Finished May 05 01:58:09 PM PDT 24
Peak memory 223112 kb
Host smart-ef155417-f01a-4622-8e0c-3702b2e7ef7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314971741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.314971741
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1255865572
Short name T376
Test name
Test status
Simulation time 1300074735 ps
CPU time 14.15 seconds
Started May 05 01:41:16 PM PDT 24
Finished May 05 01:41:31 PM PDT 24
Peak memory 215460 kb
Host smart-ddbb158d-0e82-4e6e-824d-88dc87e85035
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255865572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1255865572
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2340306308
Short name T70
Test name
Test status
Simulation time 28596082392 ps
CPU time 18.62 seconds
Started May 05 01:56:17 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 224444 kb
Host smart-feeb7dcf-6d9c-4907-9646-888f91d2b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340306308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2340306308
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3032709846
Short name T67
Test name
Test status
Simulation time 10219826762 ps
CPU time 10.83 seconds
Started May 05 01:56:17 PM PDT 24
Finished May 05 01:56:28 PM PDT 24
Peak memory 235384 kb
Host smart-5fa2d2d5-6670-45d2-999f-13c5f1869d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032709846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3032709846
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.673823056
Short name T362
Test name
Test status
Simulation time 2482807091 ps
CPU time 32.71 seconds
Started May 05 01:56:38 PM PDT 24
Finished May 05 01:57:11 PM PDT 24
Peak memory 218860 kb
Host smart-51ba9798-5849-4e33-aee9-f0210dc13e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673823056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.673823056
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.732443264
Short name T271
Test name
Test status
Simulation time 9349368076 ps
CPU time 26.77 seconds
Started May 05 01:56:40 PM PDT 24
Finished May 05 01:57:07 PM PDT 24
Peak memory 239056 kb
Host smart-52afed73-e086-4512-aaf4-57defbe9fec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732443264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.732443264
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2818261374
Short name T196
Test name
Test status
Simulation time 4679487678 ps
CPU time 19.86 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:57:08 PM PDT 24
Peak memory 218848 kb
Host smart-858b15be-82e8-4f72-b359-434983218c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818261374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2818261374
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_upload.2216875017
Short name T268
Test name
Test status
Simulation time 1380126708 ps
CPU time 5.69 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:54 PM PDT 24
Peak memory 219116 kb
Host smart-6c2332ac-0db8-4a15-8d3e-e80d2a0c0be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216875017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2216875017
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2434666283
Short name T89
Test name
Test status
Simulation time 22151703504 ps
CPU time 58.18 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:57:44 PM PDT 24
Peak memory 232724 kb
Host smart-d960a7fe-fa7e-4198-a0aa-cd83e3de2d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434666283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2434666283
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1773997534
Short name T235
Test name
Test status
Simulation time 3508630760 ps
CPU time 8.59 seconds
Started May 05 01:56:54 PM PDT 24
Finished May 05 01:57:03 PM PDT 24
Peak memory 216856 kb
Host smart-c188c200-d829-4703-b93f-15fa6241ff3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773997534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1773997534
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3052053390
Short name T225
Test name
Test status
Simulation time 67129501846 ps
CPU time 39.47 seconds
Started May 05 01:57:14 PM PDT 24
Finished May 05 01:57:54 PM PDT 24
Peak memory 232936 kb
Host smart-4a2f1b98-149a-46c5-b517-a989b0b034b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052053390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3052053390
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1190433012
Short name T234
Test name
Test status
Simulation time 208671949 ps
CPU time 3.61 seconds
Started May 05 01:57:55 PM PDT 24
Finished May 05 01:57:59 PM PDT 24
Peak memory 218156 kb
Host smart-5e1746a7-60e3-4a85-8863-f232300a9c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190433012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1190433012
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2718271692
Short name T12
Test name
Test status
Simulation time 5407803153 ps
CPU time 8.07 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:09 PM PDT 24
Peak memory 235992 kb
Host smart-84ff007c-15a0-415d-889c-f69d7859d480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718271692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2718271692
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2253998135
Short name T46
Test name
Test status
Simulation time 2468491888 ps
CPU time 25.28 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:25 PM PDT 24
Peak memory 232728 kb
Host smart-828f29de-4e13-430f-a09b-026c3c913aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253998135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2253998135
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1477232228
Short name T307
Test name
Test status
Simulation time 521905356 ps
CPU time 17.23 seconds
Started May 05 01:56:05 PM PDT 24
Finished May 05 01:56:23 PM PDT 24
Peak memory 238440 kb
Host smart-655b86ea-2947-4f32-8e22-5244f6df43f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477232228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1477232228
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_upload.106515117
Short name T250
Test name
Test status
Simulation time 96140447 ps
CPU time 2.61 seconds
Started May 05 01:56:05 PM PDT 24
Finished May 05 01:56:08 PM PDT 24
Peak memory 222460 kb
Host smart-de1ff9bf-39bf-4bba-a093-7f76ec21cf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106515117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.106515117
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1900424672
Short name T78
Test name
Test status
Simulation time 2116889130 ps
CPU time 3.19 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:18 PM PDT 24
Peak memory 218204 kb
Host smart-5712dd02-564f-4c2c-9edf-2c390d572509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900424672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1900424672
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4031545485
Short name T195
Test name
Test status
Simulation time 241518253 ps
CPU time 3.81 seconds
Started May 05 01:56:15 PM PDT 24
Finished May 05 01:56:20 PM PDT 24
Peak memory 223580 kb
Host smart-ad02539c-4112-4c2c-9f08-17984e7d003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031545485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4031545485
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1048601274
Short name T710
Test name
Test status
Simulation time 4687281931 ps
CPU time 24.29 seconds
Started May 05 01:56:30 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 220212 kb
Host smart-e80d4c1f-b6e5-4f03-bac3-5c1414547765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048601274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1048601274
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_upload.3771682440
Short name T201
Test name
Test status
Simulation time 10775690858 ps
CPU time 29.61 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:56:23 PM PDT 24
Peak memory 226056 kb
Host smart-2cad1663-0a95-4e69-b27e-648cfb350066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771682440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3771682440
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1143821530
Short name T325
Test name
Test status
Simulation time 5774809541 ps
CPU time 33.34 seconds
Started May 05 01:56:36 PM PDT 24
Finished May 05 01:57:10 PM PDT 24
Peak memory 224480 kb
Host smart-39cc20a2-8ee9-444a-9a6d-c167f4fb4a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143821530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1143821530
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4215775163
Short name T314
Test name
Test status
Simulation time 5764253018 ps
CPU time 9 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 223852 kb
Host smart-c0963db0-3842-4329-bc5e-bd0febbfc0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215775163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4215775163
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2749808221
Short name T357
Test name
Test status
Simulation time 38118197762 ps
CPU time 102.99 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:58:29 PM PDT 24
Peak memory 224512 kb
Host smart-57c8b19f-e5af-4d78-822a-d59d793f7dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749808221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2749808221
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4170796259
Short name T292
Test name
Test status
Simulation time 7210126567 ps
CPU time 22.68 seconds
Started May 05 01:56:50 PM PDT 24
Finished May 05 01:57:13 PM PDT 24
Peak memory 234444 kb
Host smart-cd5f7625-b009-418e-b95d-967d886ac866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170796259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4170796259
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4210267558
Short name T74
Test name
Test status
Simulation time 8344873158 ps
CPU time 10.36 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:59 PM PDT 24
Peak memory 224436 kb
Host smart-f6f770b6-1b2a-4087-afd7-4827847d8f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210267558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4210267558
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3433004057
Short name T346
Test name
Test status
Simulation time 2505680498 ps
CPU time 8.29 seconds
Started May 05 01:56:56 PM PDT 24
Finished May 05 01:57:05 PM PDT 24
Peak memory 218664 kb
Host smart-f1805d29-5842-4787-80fa-53913b2ed297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433004057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3433004057
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3741545117
Short name T361
Test name
Test status
Simulation time 2193830610 ps
CPU time 22.02 seconds
Started May 05 01:57:02 PM PDT 24
Finished May 05 01:57:24 PM PDT 24
Peak memory 224748 kb
Host smart-28da92a1-7b14-436c-b93d-541e988f00cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741545117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3741545117
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.392420885
Short name T231
Test name
Test status
Simulation time 14424911235 ps
CPU time 13.92 seconds
Started May 05 01:57:08 PM PDT 24
Finished May 05 01:57:22 PM PDT 24
Peak memory 233624 kb
Host smart-26b62b49-d0f6-49e7-ab3a-ad3801e31871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392420885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.392420885
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2307193445
Short name T203
Test name
Test status
Simulation time 887700351 ps
CPU time 3.4 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:57:41 PM PDT 24
Peak memory 216720 kb
Host smart-90011d2d-3fa2-4895-be3b-c1d8a8a41be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307193445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2307193445
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3011815002
Short name T301
Test name
Test status
Simulation time 6449402845 ps
CPU time 32.42 seconds
Started May 05 01:57:48 PM PDT 24
Finished May 05 01:58:20 PM PDT 24
Peak memory 233724 kb
Host smart-5c88ea8d-acd4-43e5-8a0c-114d200bde65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011815002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3011815002
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1323530060
Short name T72
Test name
Test status
Simulation time 1476449284 ps
CPU time 8.08 seconds
Started May 05 01:57:56 PM PDT 24
Finished May 05 01:58:05 PM PDT 24
Peak memory 224308 kb
Host smart-4783ccc7-1d4e-4168-959b-7d45ac73987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323530060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1323530060
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3931954054
Short name T245
Test name
Test status
Simulation time 8127067746 ps
CPU time 24.65 seconds
Started May 05 01:58:14 PM PDT 24
Finished May 05 01:58:39 PM PDT 24
Peak memory 222724 kb
Host smart-578eac77-0cad-4ab5-8dc3-5800b1535837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931954054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3931954054
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3059933181
Short name T215
Test name
Test status
Simulation time 7657069807 ps
CPU time 10.59 seconds
Started May 05 01:58:18 PM PDT 24
Finished May 05 01:58:29 PM PDT 24
Peak memory 232732 kb
Host smart-a96edd3c-38ec-427b-bc4d-3d73caf89ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059933181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3059933181
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3032461986
Short name T385
Test name
Test status
Simulation time 15151602601 ps
CPU time 63.49 seconds
Started May 05 01:56:09 PM PDT 24
Finished May 05 01:57:13 PM PDT 24
Peak memory 216392 kb
Host smart-ec5ae751-56ee-468a-8442-36be23363ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032461986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3032461986
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3122757384
Short name T76
Test name
Test status
Simulation time 1634670257 ps
CPU time 7.17 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:10 PM PDT 24
Peak memory 232640 kb
Host smart-cc41abdb-bcc1-4974-8001-d71f9b1c39b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122757384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3122757384
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3106969015
Short name T338
Test name
Test status
Simulation time 131115424 ps
CPU time 2.26 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:51 PM PDT 24
Peak memory 219096 kb
Host smart-4f79a305-8333-4638-9b62-1f306cede8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106969015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3106969015
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4213431062
Short name T822
Test name
Test status
Simulation time 1270732311 ps
CPU time 4.79 seconds
Started May 05 01:41:13 PM PDT 24
Finished May 05 01:41:18 PM PDT 24
Peak memory 215296 kb
Host smart-d2f34935-7939-436b-9df9-ac379a315579
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213431062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4213431062
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2607765093
Short name T267
Test name
Test status
Simulation time 887636348 ps
CPU time 2.96 seconds
Started May 05 01:55:56 PM PDT 24
Finished May 05 01:56:04 PM PDT 24
Peak memory 218948 kb
Host smart-2e37aabe-557c-479b-bdab-aab45a164a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607765093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2607765093
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.519987584
Short name T199
Test name
Test status
Simulation time 2261255995 ps
CPU time 2.73 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:55:58 PM PDT 24
Peak memory 222824 kb
Host smart-dff21dd2-23f2-4924-9543-a964abb424f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519987584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.519987584
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2622538063
Short name T257
Test name
Test status
Simulation time 135265337636 ps
CPU time 141.55 seconds
Started May 05 01:56:04 PM PDT 24
Finished May 05 01:58:31 PM PDT 24
Peak memory 231644 kb
Host smart-a0cbcebe-de3a-44b0-9350-717b100100f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622538063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2622538063
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1199907732
Short name T288
Test name
Test status
Simulation time 11268356318 ps
CPU time 11.7 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:14 PM PDT 24
Peak memory 223816 kb
Host smart-994089b3-4b1b-4996-a6da-e075f7bb2498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199907732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1199907732
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_upload.3076904929
Short name T79
Test name
Test status
Simulation time 156623028 ps
CPU time 3.21 seconds
Started May 05 01:56:11 PM PDT 24
Finished May 05 01:56:15 PM PDT 24
Peak memory 232412 kb
Host smart-edb4baa5-5494-4b93-9b3e-3581c92cd9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076904929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3076904929
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2506489474
Short name T45
Test name
Test status
Simulation time 2631446025 ps
CPU time 12.73 seconds
Started May 05 01:56:24 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 232560 kb
Host smart-1c8620e5-aabe-466d-9b87-407b9650c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506489474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2506489474
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3994314870
Short name T348
Test name
Test status
Simulation time 14948021041 ps
CPU time 14.02 seconds
Started May 05 01:56:36 PM PDT 24
Finished May 05 01:56:51 PM PDT 24
Peak memory 218696 kb
Host smart-ff786c49-9c35-4263-98ac-0e5ed8de278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994314870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3994314870
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1159953880
Short name T289
Test name
Test status
Simulation time 5728604926 ps
CPU time 8.19 seconds
Started May 05 01:56:30 PM PDT 24
Finished May 05 01:56:39 PM PDT 24
Peak memory 232720 kb
Host smart-848eb61e-7164-4abc-89a2-426248ae86a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159953880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1159953880
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1378617301
Short name T703
Test name
Test status
Simulation time 4883086299 ps
CPU time 32.07 seconds
Started May 05 01:56:31 PM PDT 24
Finished May 05 01:57:04 PM PDT 24
Peak memory 216268 kb
Host smart-bdb18f62-018f-4a6d-843c-3d74e76009d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378617301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1378617301
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_upload.687524653
Short name T312
Test name
Test status
Simulation time 11330443752 ps
CPU time 21.11 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:56:56 PM PDT 24
Peak memory 220184 kb
Host smart-dd19666d-5f86-47c5-9e12-bc7b599427f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687524653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.687524653
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.372440103
Short name T229
Test name
Test status
Simulation time 4054836783 ps
CPU time 20.41 seconds
Started May 05 01:56:41 PM PDT 24
Finished May 05 01:57:02 PM PDT 24
Peak memory 236024 kb
Host smart-b7ce954d-ce85-41cf-8914-19dba83c73f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372440103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.372440103
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2920518155
Short name T276
Test name
Test status
Simulation time 366667725 ps
CPU time 4.22 seconds
Started May 05 01:56:36 PM PDT 24
Finished May 05 01:56:41 PM PDT 24
Peak memory 224684 kb
Host smart-86fcf19a-4084-435d-8e3a-54b2d35ce9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920518155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2920518155
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_upload.3362132346
Short name T212
Test name
Test status
Simulation time 240129251 ps
CPU time 2.89 seconds
Started May 05 01:56:44 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 222432 kb
Host smart-bd836338-ab9d-483a-afe4-ceb8032fd0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362132346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3362132346
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2479328575
Short name T249
Test name
Test status
Simulation time 2416938594 ps
CPU time 8.6 seconds
Started May 05 01:56:49 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 223544 kb
Host smart-112d142b-31f3-4a02-bb53-bb3fa76f7d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479328575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2479328575
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3835957574
Short name T322
Test name
Test status
Simulation time 1739624289 ps
CPU time 4.75 seconds
Started May 05 01:56:50 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 218912 kb
Host smart-dee12d01-5716-4f78-a571-3b09f0e60fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835957574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3835957574
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1623820981
Short name T304
Test name
Test status
Simulation time 6721448115 ps
CPU time 30.3 seconds
Started May 05 01:56:54 PM PDT 24
Finished May 05 01:57:25 PM PDT 24
Peak memory 250528 kb
Host smart-2975a74e-acd8-46e7-a417-381c73c5e541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623820981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1623820981
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_upload.342707064
Short name T219
Test name
Test status
Simulation time 21741982560 ps
CPU time 19.09 seconds
Started May 05 01:56:54 PM PDT 24
Finished May 05 01:57:13 PM PDT 24
Peak memory 234672 kb
Host smart-28ca9e0e-b04f-4067-99da-ddd56e2fd54e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342707064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.342707064
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1928900964
Short name T291
Test name
Test status
Simulation time 676013469 ps
CPU time 6.19 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:04 PM PDT 24
Peak memory 222712 kb
Host smart-77d175cf-1be8-418e-b7b7-11d3666c98e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928900964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1928900964
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1384253027
Short name T345
Test name
Test status
Simulation time 308732155 ps
CPU time 2.53 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 222784 kb
Host smart-0770480e-de76-4457-b26b-8c2a12f996d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384253027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1384253027
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.783936331
Short name T185
Test name
Test status
Simulation time 1640355157 ps
CPU time 10.53 seconds
Started May 05 01:57:11 PM PDT 24
Finished May 05 01:57:22 PM PDT 24
Peak memory 234444 kb
Host smart-6402e7e6-1d16-4069-adaa-7d747616558f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783936331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.783936331
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2578139332
Short name T335
Test name
Test status
Simulation time 356399091 ps
CPU time 5.07 seconds
Started May 05 01:57:08 PM PDT 24
Finished May 05 01:57:14 PM PDT 24
Peak memory 216908 kb
Host smart-c51bc569-6679-4be3-9432-2aabcca1f165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578139332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2578139332
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_upload.4219649126
Short name T317
Test name
Test status
Simulation time 946264471 ps
CPU time 3.16 seconds
Started May 05 01:55:47 PM PDT 24
Finished May 05 01:55:51 PM PDT 24
Peak memory 218852 kb
Host smart-a4baa994-6440-4480-92e2-ecc53a435453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219649126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.4219649126
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4094318722
Short name T200
Test name
Test status
Simulation time 1578170301 ps
CPU time 18.55 seconds
Started May 05 01:57:11 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 232716 kb
Host smart-52bdb2cf-1945-4f69-af21-1719021e3977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094318722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4094318722
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2968811290
Short name T240
Test name
Test status
Simulation time 11439365720 ps
CPU time 28.45 seconds
Started May 05 01:57:24 PM PDT 24
Finished May 05 01:57:53 PM PDT 24
Peak memory 218488 kb
Host smart-b3ab1c43-d62c-463e-8c87-3cdc89413ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968811290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2968811290
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_upload.3909098219
Short name T332
Test name
Test status
Simulation time 13428589431 ps
CPU time 10.95 seconds
Started May 05 01:57:26 PM PDT 24
Finished May 05 01:57:37 PM PDT 24
Peak memory 232648 kb
Host smart-801a8481-118c-4238-9a8b-c97f75611e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909098219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3909098219
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1345206365
Short name T303
Test name
Test status
Simulation time 467717736 ps
CPU time 16.88 seconds
Started May 05 01:57:30 PM PDT 24
Finished May 05 01:57:48 PM PDT 24
Peak memory 233720 kb
Host smart-67ea670a-f4fc-4db0-9811-a636e07b2209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345206365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1345206365
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_upload.2483244874
Short name T339
Test name
Test status
Simulation time 7758078838 ps
CPU time 9.14 seconds
Started May 05 01:57:36 PM PDT 24
Finished May 05 01:57:46 PM PDT 24
Peak memory 223412 kb
Host smart-005a7768-4069-4b39-a899-6efcf794fd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483244874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2483244874
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2835624710
Short name T349
Test name
Test status
Simulation time 726101656 ps
CPU time 11.96 seconds
Started May 05 01:57:30 PM PDT 24
Finished May 05 01:57:43 PM PDT 24
Peak memory 232268 kb
Host smart-14a8b692-8703-4e8e-899e-5e3d3d66409c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835624710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2835624710
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1443798345
Short name T187
Test name
Test status
Simulation time 470127860 ps
CPU time 5.34 seconds
Started May 05 01:57:34 PM PDT 24
Finished May 05 01:57:40 PM PDT 24
Peak memory 216668 kb
Host smart-f832c84b-4496-4771-af2e-f121062971da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443798345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1443798345
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2422689942
Short name T333
Test name
Test status
Simulation time 507773306 ps
CPU time 7.62 seconds
Started May 05 01:57:41 PM PDT 24
Finished May 05 01:57:49 PM PDT 24
Peak memory 218820 kb
Host smart-4d703957-1edc-4640-96a1-959182d0c046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422689942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2422689942
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.960478757
Short name T259
Test name
Test status
Simulation time 2278034495 ps
CPU time 5.05 seconds
Started May 05 01:56:01 PM PDT 24
Finished May 05 01:56:07 PM PDT 24
Peak memory 222996 kb
Host smart-1caaa8ba-164c-4b13-8f12-29d020828041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960478757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
960478757
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.923252832
Short name T326
Test name
Test status
Simulation time 2571791385 ps
CPU time 4.56 seconds
Started May 05 01:57:42 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 219864 kb
Host smart-3dcb2ae6-413f-4f93-bde9-6450ce815d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923252832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.923252832
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.550225164
Short name T272
Test name
Test status
Simulation time 2381847027 ps
CPU time 8.5 seconds
Started May 05 01:57:47 PM PDT 24
Finished May 05 01:57:56 PM PDT 24
Peak memory 222928 kb
Host smart-ecbf6a2a-3d53-4086-8c76-8f1f18339461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550225164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.550225164
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2910600279
Short name T328
Test name
Test status
Simulation time 9788158904 ps
CPU time 12.24 seconds
Started May 05 01:57:55 PM PDT 24
Finished May 05 01:58:08 PM PDT 24
Peak memory 239988 kb
Host smart-f0780531-a83d-44c5-a2f4-5fd6bf40010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910600279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2910600279
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.731302312
Short name T247
Test name
Test status
Simulation time 790064484 ps
CPU time 4.85 seconds
Started May 05 01:58:05 PM PDT 24
Finished May 05 01:58:10 PM PDT 24
Peak memory 223224 kb
Host smart-f921c2db-55db-498d-b030-33c9772f7da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731302312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.731302312
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.141547075
Short name T352
Test name
Test status
Simulation time 190330312 ps
CPU time 2.43 seconds
Started May 05 01:58:09 PM PDT 24
Finished May 05 01:58:12 PM PDT 24
Peak memory 218920 kb
Host smart-80ab712e-b2fb-42ff-8dcb-7149e7915572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141547075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.141547075
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2829953687
Short name T217
Test name
Test status
Simulation time 434682568 ps
CPU time 2.37 seconds
Started May 05 01:58:10 PM PDT 24
Finished May 05 01:58:13 PM PDT 24
Peak memory 220240 kb
Host smart-d8986dcc-0c90-4058-891b-33b3232c1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829953687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2829953687
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1036368211
Short name T248
Test name
Test status
Simulation time 5673346020 ps
CPU time 15.53 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:56:08 PM PDT 24
Peak memory 222712 kb
Host smart-0332e10f-90f4-4726-890e-14f0798b897f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036368211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1036368211
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2373487134
Short name T351
Test name
Test status
Simulation time 2194710998 ps
CPU time 2.29 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 219880 kb
Host smart-a331007d-ae6e-4697-a03d-b01e0edba6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373487134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2373487134
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.207329745
Short name T207
Test name
Test status
Simulation time 365242300 ps
CPU time 6.69 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 237120 kb
Host smart-e8aae18e-19d3-42c8-8eef-9c82d5bacb99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207329745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
207329745
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.666511958
Short name T285
Test name
Test status
Simulation time 1480947275 ps
CPU time 27.02 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:42 PM PDT 24
Peak memory 248828 kb
Host smart-408abd1d-2051-4e0c-b640-de7d3864dbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666511958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.666511958
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.342282941
Short name T112
Test name
Test status
Simulation time 1327877659 ps
CPU time 5.06 seconds
Started May 05 01:56:12 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 221684 kb
Host smart-0c8dda42-c995-487d-a75f-b14ee01cc118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342282941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.342282941
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1060025193
Short name T93
Test name
Test status
Simulation time 59194887 ps
CPU time 1.14 seconds
Started May 05 01:40:47 PM PDT 24
Finished May 05 01:40:49 PM PDT 24
Peak memory 206912 kb
Host smart-ef9d586e-91b3-4a47-809c-ddd6a7e32af4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060025193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1060025193
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1523495262
Short name T128
Test name
Test status
Simulation time 176216976 ps
CPU time 2.55 seconds
Started May 05 01:41:09 PM PDT 24
Finished May 05 01:41:12 PM PDT 24
Peak memory 216296 kb
Host smart-64f1ca3b-de8e-4f1d-b982-35116ddc0cb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523495262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1523495262
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.573420725
Short name T83
Test name
Test status
Simulation time 2075260034 ps
CPU time 3.51 seconds
Started May 05 01:57:52 PM PDT 24
Finished May 05 01:57:56 PM PDT 24
Peak memory 218888 kb
Host smart-afde391b-dcce-491b-9109-d620f6da9270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573420725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.573420725
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2358393917
Short name T834
Test name
Test status
Simulation time 110592147 ps
CPU time 7.66 seconds
Started May 05 01:40:49 PM PDT 24
Finished May 05 01:40:57 PM PDT 24
Peak memory 215072 kb
Host smart-7953ef4e-e600-45e4-860f-9bd949034cd4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358393917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2358393917
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.919133952
Short name T749
Test name
Test status
Simulation time 220614840 ps
CPU time 11.67 seconds
Started May 05 01:40:47 PM PDT 24
Finished May 05 01:40:59 PM PDT 24
Peak memory 207176 kb
Host smart-6c3a8b38-35ec-4667-8bc7-f1bb594b4eba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919133952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.919133952
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2958363491
Short name T138
Test name
Test status
Simulation time 57594091 ps
CPU time 1.71 seconds
Started May 05 01:40:47 PM PDT 24
Finished May 05 01:40:49 PM PDT 24
Peak memory 215268 kb
Host smart-887aca96-0678-4e08-bb37-1502e6423e2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958363491 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2958363491
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.569490010
Short name T155
Test name
Test status
Simulation time 44835606 ps
CPU time 1.66 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:40:48 PM PDT 24
Peak memory 215160 kb
Host smart-6dda3d42-8f10-43ad-a391-c0549d15a037
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569490010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.569490010
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1813884229
Short name T782
Test name
Test status
Simulation time 38170850 ps
CPU time 0.7 seconds
Started May 05 01:40:47 PM PDT 24
Finished May 05 01:40:48 PM PDT 24
Peak memory 203980 kb
Host smart-1d5db47e-7a40-4321-9bdd-1468db327391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813884229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
813884229
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2570963183
Short name T818
Test name
Test status
Simulation time 230805390 ps
CPU time 2.04 seconds
Started May 05 01:40:48 PM PDT 24
Finished May 05 01:40:50 PM PDT 24
Peak memory 215108 kb
Host smart-4af9961c-0bd6-44b3-acf6-456aa4666a48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570963183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2570963183
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1469876307
Short name T785
Test name
Test status
Simulation time 17090293 ps
CPU time 0.66 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:40:47 PM PDT 24
Peak memory 203452 kb
Host smart-1b9fa60c-5a38-4ed4-bc61-323bcfd1b692
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469876307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1469876307
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3650589514
Short name T41
Test name
Test status
Simulation time 154007688 ps
CPU time 3.89 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:40:51 PM PDT 24
Peak memory 215084 kb
Host smart-32bbddde-f8cc-4592-90b5-05677963d477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650589514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3650589514
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2678444249
Short name T816
Test name
Test status
Simulation time 293368281 ps
CPU time 2.37 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:40:49 PM PDT 24
Peak memory 215304 kb
Host smart-454adbd7-d5db-4ca0-a88a-a1c59723578b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678444249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
678444249
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1890348900
Short name T141
Test name
Test status
Simulation time 417495923 ps
CPU time 11.71 seconds
Started May 05 01:40:45 PM PDT 24
Finished May 05 01:40:57 PM PDT 24
Peak memory 215072 kb
Host smart-b6ab4c80-b124-49ab-b2fc-74c9a0a3985d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890348900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1890348900
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.688596900
Short name T145
Test name
Test status
Simulation time 1295605101 ps
CPU time 20.49 seconds
Started May 05 01:40:48 PM PDT 24
Finished May 05 01:41:09 PM PDT 24
Peak memory 207004 kb
Host smart-3e813858-c8c6-4183-a0a2-7f029e494e80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688596900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.688596900
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1723705798
Short name T147
Test name
Test status
Simulation time 371187582 ps
CPU time 22.84 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:41:09 PM PDT 24
Peak memory 215100 kb
Host smart-e4c1261f-5db0-4957-8ca5-d0e29e88f98d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723705798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1723705798
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1825145330
Short name T94
Test name
Test status
Simulation time 39047425 ps
CPU time 1.21 seconds
Started May 05 01:40:51 PM PDT 24
Finished May 05 01:40:53 PM PDT 24
Peak memory 216340 kb
Host smart-d7ce981c-be91-460b-9681-a2507b3b9271
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825145330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1825145330
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.752210722
Short name T827
Test name
Test status
Simulation time 611353744 ps
CPU time 1.7 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:40:48 PM PDT 24
Peak memory 215208 kb
Host smart-e5234fcd-a10d-4771-a209-21c1cd7aad38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752210722 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.752210722
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2423761222
Short name T750
Test name
Test status
Simulation time 336089964 ps
CPU time 1.31 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:40:48 PM PDT 24
Peak memory 206992 kb
Host smart-d9cd4506-df18-4e3b-b027-7dd315f5d28b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423761222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
423761222
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3109196530
Short name T811
Test name
Test status
Simulation time 42897717 ps
CPU time 0.69 seconds
Started May 05 01:40:46 PM PDT 24
Finished May 05 01:40:47 PM PDT 24
Peak memory 203936 kb
Host smart-870827db-dd5a-469f-bf65-c7e091b5ee3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109196530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
109196530
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2918953797
Short name T148
Test name
Test status
Simulation time 383851381 ps
CPU time 1.25 seconds
Started May 05 01:40:49 PM PDT 24
Finished May 05 01:40:50 PM PDT 24
Peak memory 215236 kb
Host smart-3c91b7d2-0b1d-4b44-aee3-dc6b974449bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918953797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2918953797
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.162902421
Short name T741
Test name
Test status
Simulation time 13161196 ps
CPU time 0.64 seconds
Started May 05 01:40:48 PM PDT 24
Finished May 05 01:40:50 PM PDT 24
Peak memory 203492 kb
Host smart-3be4d25c-fe2c-4a8d-b949-83e603a43fd7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162902421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.162902421
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.580123229
Short name T745
Test name
Test status
Simulation time 204751708 ps
CPU time 4.08 seconds
Started May 05 01:40:49 PM PDT 24
Finished May 05 01:40:53 PM PDT 24
Peak memory 215188 kb
Host smart-7bd8a726-25db-46ec-946b-45321741e573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580123229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.580123229
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.619613861
Short name T136
Test name
Test status
Simulation time 1187257867 ps
CPU time 3.99 seconds
Started May 05 01:40:48 PM PDT 24
Finished May 05 01:40:52 PM PDT 24
Peak memory 215312 kb
Host smart-cf666ac9-e7ff-41eb-9dae-2d88130ab3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619613861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.619613861
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.215695188
Short name T119
Test name
Test status
Simulation time 302285189 ps
CPU time 18.85 seconds
Started May 05 01:40:48 PM PDT 24
Finished May 05 01:41:07 PM PDT 24
Peak memory 215248 kb
Host smart-cda2c3d5-e501-4af0-930e-3b5bb6fbf45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215695188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.215695188
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.444025581
Short name T131
Test name
Test status
Simulation time 52304191 ps
CPU time 1.71 seconds
Started May 05 01:41:07 PM PDT 24
Finished May 05 01:41:09 PM PDT 24
Peak memory 215392 kb
Host smart-539e2a8f-e5d0-4a95-a06a-c982d24dd2db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444025581 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.444025581
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1756753375
Short name T156
Test name
Test status
Simulation time 175194680 ps
CPU time 1.4 seconds
Started May 05 01:41:04 PM PDT 24
Finished May 05 01:41:06 PM PDT 24
Peak memory 215132 kb
Host smart-35f5b9c0-bc50-4435-a276-b670189fe366
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756753375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1756753375
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1446386291
Short name T167
Test name
Test status
Simulation time 46144334 ps
CPU time 0.68 seconds
Started May 05 01:41:04 PM PDT 24
Finished May 05 01:41:06 PM PDT 24
Peak memory 203608 kb
Host smart-515c9e32-8491-4d8f-8c82-0828c2594a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446386291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1446386291
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1834071931
Short name T795
Test name
Test status
Simulation time 238925207 ps
CPU time 4.06 seconds
Started May 05 01:41:04 PM PDT 24
Finished May 05 01:41:09 PM PDT 24
Peak memory 215180 kb
Host smart-023bd48c-577b-45dc-a086-cd5c97616b28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834071931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1834071931
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3357338828
Short name T115
Test name
Test status
Simulation time 166064484 ps
CPU time 2.69 seconds
Started May 05 01:41:05 PM PDT 24
Finished May 05 01:41:08 PM PDT 24
Peak memory 215372 kb
Host smart-16c9880a-108c-4c43-bf17-73de7acfb517
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357338828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3357338828
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.457272882
Short name T379
Test name
Test status
Simulation time 624570714 ps
CPU time 19.25 seconds
Started May 05 01:41:03 PM PDT 24
Finished May 05 01:41:23 PM PDT 24
Peak memory 215148 kb
Host smart-40687256-5eb1-42c7-9f43-d520ea064104
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457272882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.457272882
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1591974984
Short name T139
Test name
Test status
Simulation time 128820523 ps
CPU time 3.31 seconds
Started May 05 01:41:13 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 216916 kb
Host smart-6809f330-7b45-4c43-a973-05e097f1b9eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591974984 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1591974984
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3102213143
Short name T165
Test name
Test status
Simulation time 86535757 ps
CPU time 2.19 seconds
Started May 05 01:41:13 PM PDT 24
Finished May 05 01:41:15 PM PDT 24
Peak memory 215152 kb
Host smart-cb3b228b-c914-4288-88f6-f0964f80b420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102213143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3102213143
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1639011355
Short name T748
Test name
Test status
Simulation time 19596907 ps
CPU time 0.7 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:17 PM PDT 24
Peak memory 203640 kb
Host smart-72a4b274-f03f-4c7b-8541-847fabd90e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639011355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1639011355
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2175217393
Short name T159
Test name
Test status
Simulation time 48385862 ps
CPU time 2.86 seconds
Started May 05 01:41:11 PM PDT 24
Finished May 05 01:41:14 PM PDT 24
Peak memory 215056 kb
Host smart-bd0a12ad-4dfe-49bc-99f9-9e31376f70a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175217393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2175217393
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.595771359
Short name T820
Test name
Test status
Simulation time 1179113893 ps
CPU time 17.35 seconds
Started May 05 01:41:06 PM PDT 24
Finished May 05 01:41:24 PM PDT 24
Peak memory 215128 kb
Host smart-abb91b84-e9c8-403c-85a2-be71cdc6c0e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595771359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.595771359
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3083951956
Short name T809
Test name
Test status
Simulation time 190137279 ps
CPU time 1.69 seconds
Started May 05 01:41:09 PM PDT 24
Finished May 05 01:41:11 PM PDT 24
Peak memory 215216 kb
Host smart-38d70913-558c-4daa-b509-b40ef42781b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083951956 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3083951956
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.570164957
Short name T767
Test name
Test status
Simulation time 29717530 ps
CPU time 1.82 seconds
Started May 05 01:41:10 PM PDT 24
Finished May 05 01:41:12 PM PDT 24
Peak memory 206972 kb
Host smart-0261cf14-7791-4b80-9a0d-19830a084dad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570164957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.570164957
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3795497418
Short name T170
Test name
Test status
Simulation time 18043836 ps
CPU time 0.78 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 203864 kb
Host smart-a3329038-0d7c-4954-8755-9f272a1bfad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795497418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3795497418
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3815117731
Short name T787
Test name
Test status
Simulation time 71806728 ps
CPU time 1.86 seconds
Started May 05 01:41:11 PM PDT 24
Finished May 05 01:41:13 PM PDT 24
Peak memory 215084 kb
Host smart-8f4f2bff-426f-450a-81a4-b2e1a523cd8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815117731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3815117731
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1807752428
Short name T377
Test name
Test status
Simulation time 377159300 ps
CPU time 8.24 seconds
Started May 05 01:41:11 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 215416 kb
Host smart-426ca494-d165-47d9-81d7-eeb9705b6fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807752428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1807752428
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.216863220
Short name T762
Test name
Test status
Simulation time 95721538 ps
CPU time 2.57 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:18 PM PDT 24
Peak memory 216796 kb
Host smart-12b33bf8-ae88-4d07-94e5-5ae94b06fa51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216863220 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.216863220
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1126472729
Short name T153
Test name
Test status
Simulation time 60117553 ps
CPU time 1.97 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:17 PM PDT 24
Peak memory 206824 kb
Host smart-8fdf0ec1-9943-4033-aa14-baa6c8b3bd44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126472729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1126472729
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3923198505
Short name T829
Test name
Test status
Simulation time 47168117 ps
CPU time 0.66 seconds
Started May 05 01:41:11 PM PDT 24
Finished May 05 01:41:12 PM PDT 24
Peak memory 203944 kb
Host smart-fb16cb9d-8b69-45ef-a9ff-c859e357f797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923198505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3923198505
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1812523585
Short name T774
Test name
Test status
Simulation time 299382464 ps
CPU time 4.03 seconds
Started May 05 01:41:16 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 215120 kb
Host smart-eaa7984a-3783-4c17-b740-8ac509a34f19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812523585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1812523585
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3825522903
Short name T127
Test name
Test status
Simulation time 54835282 ps
CPU time 3.69 seconds
Started May 05 01:41:08 PM PDT 24
Finished May 05 01:41:12 PM PDT 24
Peak memory 216216 kb
Host smart-7da9b5ac-0e66-4688-bab7-d3cf0cdc73a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825522903 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3825522903
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.424462494
Short name T770
Test name
Test status
Simulation time 18532871 ps
CPU time 1.21 seconds
Started May 05 01:41:09 PM PDT 24
Finished May 05 01:41:10 PM PDT 24
Peak memory 215100 kb
Host smart-f85625f7-b190-4942-b5b4-3bf139c3be26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424462494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.424462494
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.431339200
Short name T752
Test name
Test status
Simulation time 65015471 ps
CPU time 0.75 seconds
Started May 05 01:41:11 PM PDT 24
Finished May 05 01:41:12 PM PDT 24
Peak memory 203584 kb
Host smart-a125dbd8-a9c3-4878-b4da-382d112533e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431339200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.431339200
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2627496033
Short name T794
Test name
Test status
Simulation time 180599368 ps
CPU time 3.06 seconds
Started May 05 01:41:12 PM PDT 24
Finished May 05 01:41:15 PM PDT 24
Peak memory 215152 kb
Host smart-320c354d-d9d4-463d-8944-321bf25c197c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627496033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2627496033
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2409941162
Short name T796
Test name
Test status
Simulation time 2451853069 ps
CPU time 19.27 seconds
Started May 05 01:41:10 PM PDT 24
Finished May 05 01:41:30 PM PDT 24
Peak memory 223600 kb
Host smart-f3a49fd6-e7a0-4750-9385-155d4ea46a21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409941162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2409941162
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1872159336
Short name T164
Test name
Test status
Simulation time 140949852 ps
CPU time 3.31 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:18 PM PDT 24
Peak memory 216880 kb
Host smart-3a5bcec8-72d3-40ff-8871-baa7b7396302
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872159336 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1872159336
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1111380436
Short name T769
Test name
Test status
Simulation time 90255796 ps
CPU time 2.56 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:17 PM PDT 24
Peak memory 207016 kb
Host smart-1f8a0879-0706-4ab0-9138-39a78a87d0a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111380436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1111380436
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3404600377
Short name T742
Test name
Test status
Simulation time 10533872 ps
CPU time 0.7 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:17 PM PDT 24
Peak memory 203896 kb
Host smart-e11186a6-1adc-4463-a818-13c88c1e279f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404600377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3404600377
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3579936156
Short name T761
Test name
Test status
Simulation time 229843659 ps
CPU time 3.75 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:19 PM PDT 24
Peak memory 215176 kb
Host smart-bf982d94-6081-471c-a6da-42a09469119a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579936156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3579936156
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1479991845
Short name T135
Test name
Test status
Simulation time 177904155 ps
CPU time 4.25 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 216172 kb
Host smart-15fe5411-54a9-44d7-be5e-04afc9400b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479991845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1479991845
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.962226939
Short name T758
Test name
Test status
Simulation time 1204858640 ps
CPU time 2.63 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:17 PM PDT 24
Peak memory 216476 kb
Host smart-e2237ec4-d3a4-4153-9278-f79e0ac0e9fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962226939 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.962226939
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.409442789
Short name T813
Test name
Test status
Simulation time 36278402 ps
CPU time 1.79 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 215136 kb
Host smart-529d0c18-69d1-49ad-94c6-1d2ced4e7013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409442789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.409442789
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1800041159
Short name T725
Test name
Test status
Simulation time 28121143 ps
CPU time 0.69 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 203616 kb
Host smart-bf47ac1e-bf8b-4c3f-bfb6-6e7eaf5aa093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800041159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1800041159
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3910570490
Short name T754
Test name
Test status
Simulation time 58233299 ps
CPU time 1.69 seconds
Started May 05 01:41:17 PM PDT 24
Finished May 05 01:41:19 PM PDT 24
Peak memory 215508 kb
Host smart-d1dd61e7-8d05-4939-85b6-7491d7971011
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910570490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3910570490
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1048837637
Short name T133
Test name
Test status
Simulation time 85040520 ps
CPU time 1.52 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:15 PM PDT 24
Peak memory 216244 kb
Host smart-6d7fa5fc-8fbb-43b6-9508-4f8329bed96c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048837637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1048837637
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1608520043
Short name T772
Test name
Test status
Simulation time 191317448 ps
CPU time 10.89 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:25 PM PDT 24
Peak memory 215124 kb
Host smart-6aded0be-3dbc-43ea-9fe1-a7f1d994f6df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608520043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1608520043
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3818348393
Short name T121
Test name
Test status
Simulation time 68136858 ps
CPU time 3.5 seconds
Started May 05 01:41:16 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 217956 kb
Host smart-43d14423-6876-4704-81a3-8e85574a06f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818348393 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3818348393
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1472810890
Short name T743
Test name
Test status
Simulation time 28156074 ps
CPU time 1.83 seconds
Started May 05 01:41:17 PM PDT 24
Finished May 05 01:41:19 PM PDT 24
Peak memory 206904 kb
Host smart-391c5706-ceab-4879-920e-cfda80ad7a42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472810890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1472810890
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.274492925
Short name T764
Test name
Test status
Simulation time 14105331 ps
CPU time 0.7 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 203916 kb
Host smart-90618360-f313-4086-9d27-4476276228a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274492925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.274492925
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1949358342
Short name T765
Test name
Test status
Simulation time 308904498 ps
CPU time 1.73 seconds
Started May 05 01:41:16 PM PDT 24
Finished May 05 01:41:18 PM PDT 24
Peak memory 215160 kb
Host smart-2c60f8b6-94b7-4aaf-af61-9cf5c9227051
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949358342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1949358342
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.260183193
Short name T788
Test name
Test status
Simulation time 167647130 ps
CPU time 2.26 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:18 PM PDT 24
Peak memory 215308 kb
Host smart-99f3a6c8-278a-42ab-a07f-86b147042530
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260183193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.260183193
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2619041361
Short name T375
Test name
Test status
Simulation time 303781641 ps
CPU time 18.58 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:34 PM PDT 24
Peak memory 215116 kb
Host smart-a81aaf3c-a05f-4608-92c0-94f1d1a87b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619041361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2619041361
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.254117288
Short name T832
Test name
Test status
Simulation time 379216599 ps
CPU time 2.42 seconds
Started May 05 01:41:19 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 216208 kb
Host smart-4b201641-25c7-4fab-9ccf-2d8446271532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254117288 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.254117288
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3702016980
Short name T40
Test name
Test status
Simulation time 520093560 ps
CPU time 2.88 seconds
Started May 05 01:41:21 PM PDT 24
Finished May 05 01:41:25 PM PDT 24
Peak memory 215128 kb
Host smart-65d37c79-d642-4c0a-8f6a-968685c0d10d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702016980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3702016980
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3238555289
Short name T797
Test name
Test status
Simulation time 13072667 ps
CPU time 0.74 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:15 PM PDT 24
Peak memory 203944 kb
Host smart-058aa440-7793-4b6c-9d7b-53f24b927b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238555289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3238555289
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3892626894
Short name T783
Test name
Test status
Simulation time 89893104 ps
CPU time 1.78 seconds
Started May 05 01:41:18 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 215228 kb
Host smart-517db6a7-9e48-48f5-973b-17b91215480b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892626894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3892626894
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1066735199
Short name T114
Test name
Test status
Simulation time 74025258 ps
CPU time 2.16 seconds
Started May 05 01:41:14 PM PDT 24
Finished May 05 01:41:16 PM PDT 24
Peak memory 215272 kb
Host smart-9a05083d-e134-4c95-984f-e3bf2c9ee56e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066735199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1066735199
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3320896312
Short name T746
Test name
Test status
Simulation time 12082946225 ps
CPU time 23.63 seconds
Started May 05 01:41:15 PM PDT 24
Finished May 05 01:41:39 PM PDT 24
Peak memory 215224 kb
Host smart-9a6c2fb3-c295-4d60-88e1-ceb0f8e6e204
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320896312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3320896312
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1898558497
Short name T733
Test name
Test status
Simulation time 150953337 ps
CPU time 2.49 seconds
Started May 05 01:41:20 PM PDT 24
Finished May 05 01:41:23 PM PDT 24
Peak memory 216284 kb
Host smart-5c7ad44b-c226-410e-bc28-2bccf585b1d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898558497 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1898558497
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1094168759
Short name T157
Test name
Test status
Simulation time 56808003 ps
CPU time 1.23 seconds
Started May 05 01:41:21 PM PDT 24
Finished May 05 01:41:23 PM PDT 24
Peak memory 206972 kb
Host smart-3fb1dc4a-bbde-4fed-9e4e-0de99072345b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094168759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1094168759
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.112867934
Short name T826
Test name
Test status
Simulation time 13138181 ps
CPU time 0.72 seconds
Started May 05 01:41:21 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 203624 kb
Host smart-a3ddccf5-30ad-4cf5-b157-06de222ba285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112867934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.112867934
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2384297537
Short name T808
Test name
Test status
Simulation time 47055794 ps
CPU time 2.65 seconds
Started May 05 01:41:19 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 215208 kb
Host smart-7689ba03-50f1-47ec-9bec-d47b7ee3c74c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384297537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2384297537
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1622418666
Short name T833
Test name
Test status
Simulation time 82756731 ps
CPU time 5.27 seconds
Started May 05 01:41:22 PM PDT 24
Finished May 05 01:41:27 PM PDT 24
Peak memory 215356 kb
Host smart-fa05cc6e-12e3-4bbd-8bb6-e23ed9a74fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622418666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1622418666
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3471969885
Short name T798
Test name
Test status
Simulation time 5786462254 ps
CPU time 18.81 seconds
Started May 05 01:41:19 PM PDT 24
Finished May 05 01:41:38 PM PDT 24
Peak memory 215224 kb
Host smart-19dd38d0-803c-4665-ab7e-c01a8a494064
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471969885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3471969885
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.533422162
Short name T150
Test name
Test status
Simulation time 607904716 ps
CPU time 15.37 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:41:08 PM PDT 24
Peak memory 206992 kb
Host smart-732065d6-cd0a-4564-bd63-09e4ad78b578
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533422162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.533422162
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1672521502
Short name T802
Test name
Test status
Simulation time 182978749 ps
CPU time 11.57 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:41:04 PM PDT 24
Peak memory 206972 kb
Host smart-65a60fd3-c40f-45a6-bb73-904ccda524d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672521502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1672521502
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.798059147
Short name T830
Test name
Test status
Simulation time 87872213 ps
CPU time 0.92 seconds
Started May 05 01:40:50 PM PDT 24
Finished May 05 01:40:52 PM PDT 24
Peak memory 206808 kb
Host smart-416cd2aa-8e5f-4437-a8fe-998b5b525b2a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798059147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.798059147
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2200967120
Short name T779
Test name
Test status
Simulation time 215465015 ps
CPU time 3.39 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:40:56 PM PDT 24
Peak memory 216520 kb
Host smart-11cc28df-62ea-4c2f-bfd2-2527606e23af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200967120 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2200967120
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3086102806
Short name T828
Test name
Test status
Simulation time 71205532 ps
CPU time 2.37 seconds
Started May 05 01:40:50 PM PDT 24
Finished May 05 01:40:52 PM PDT 24
Peak memory 215124 kb
Host smart-512af430-fe2e-49b8-95a4-29b328fba98b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086102806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
086102806
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.48644160
Short name T776
Test name
Test status
Simulation time 14053423 ps
CPU time 0.72 seconds
Started May 05 01:40:49 PM PDT 24
Finished May 05 01:40:50 PM PDT 24
Peak memory 203540 kb
Host smart-23fb4e3d-3d37-4e42-978e-9830f4fde7b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48644160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.48644160
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.103226454
Short name T146
Test name
Test status
Simulation time 67694089 ps
CPU time 2.07 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:40:55 PM PDT 24
Peak memory 215212 kb
Host smart-fefe3c8e-3376-4827-82b3-6f61a8d2ad66
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103226454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.103226454
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3174082620
Short name T771
Test name
Test status
Simulation time 13741031 ps
CPU time 0.65 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:40:53 PM PDT 24
Peak memory 203524 kb
Host smart-35082df0-ea71-49c4-9610-0b3573c64860
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174082620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3174082620
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1598124898
Short name T739
Test name
Test status
Simulation time 115538512 ps
CPU time 1.73 seconds
Started May 05 01:40:51 PM PDT 24
Finished May 05 01:40:53 PM PDT 24
Peak memory 215120 kb
Host smart-ef1ea71c-6d3f-4d98-91f2-4ee3343d9674
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598124898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1598124898
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2106552595
Short name T814
Test name
Test status
Simulation time 69688776 ps
CPU time 2.15 seconds
Started May 05 01:40:50 PM PDT 24
Finished May 05 01:40:52 PM PDT 24
Peak memory 215280 kb
Host smart-b26c81ff-fb92-465c-8a0f-1f6fef4631a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106552595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
106552595
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2924950012
Short name T380
Test name
Test status
Simulation time 2236305751 ps
CPU time 14.95 seconds
Started May 05 01:40:48 PM PDT 24
Finished May 05 01:41:04 PM PDT 24
Peak memory 215160 kb
Host smart-0889bc50-9292-4b33-ac91-d7fc8ff8f595
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924950012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2924950012
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1733400438
Short name T803
Test name
Test status
Simulation time 14877427 ps
CPU time 0.75 seconds
Started May 05 01:41:20 PM PDT 24
Finished May 05 01:41:21 PM PDT 24
Peak memory 203888 kb
Host smart-1ae0a234-abd9-435c-a36d-194841f0870a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733400438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1733400438
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1820129001
Short name T753
Test name
Test status
Simulation time 50646523 ps
CPU time 0.73 seconds
Started May 05 01:41:19 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 203580 kb
Host smart-d8b9a112-e71a-4fc5-98e0-eb1e71a039b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820129001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1820129001
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1324715328
Short name T727
Test name
Test status
Simulation time 138550682 ps
CPU time 0.72 seconds
Started May 05 01:41:20 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 203860 kb
Host smart-9769c625-4b24-4487-9edc-c7b4a4a1db06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324715328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1324715328
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1478803397
Short name T740
Test name
Test status
Simulation time 13783109 ps
CPU time 0.72 seconds
Started May 05 01:41:19 PM PDT 24
Finished May 05 01:41:21 PM PDT 24
Peak memory 203940 kb
Host smart-af38d464-6a06-4d92-9579-48bfd6751046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478803397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1478803397
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.47724055
Short name T805
Test name
Test status
Simulation time 12244119 ps
CPU time 0.71 seconds
Started May 05 01:41:23 PM PDT 24
Finished May 05 01:41:24 PM PDT 24
Peak memory 203536 kb
Host smart-17a2b574-98e1-454c-8baa-202e441003b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47724055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.47724055
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4006764178
Short name T760
Test name
Test status
Simulation time 13073539 ps
CPU time 0.69 seconds
Started May 05 01:41:21 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 203628 kb
Host smart-338ef8e5-ceb8-488c-a591-ffdfc77bd6b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006764178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4006764178
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.76892167
Short name T730
Test name
Test status
Simulation time 50455834 ps
CPU time 0.73 seconds
Started May 05 01:41:18 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 203588 kb
Host smart-b7ada80d-6d1e-4b8b-9e72-c3528bb175ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76892167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.76892167
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3662191486
Short name T824
Test name
Test status
Simulation time 50105700 ps
CPU time 0.71 seconds
Started May 05 01:41:21 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 203564 kb
Host smart-fa734f00-ae13-4c2b-8a4b-45a3129d5de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662191486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3662191486
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.239021478
Short name T791
Test name
Test status
Simulation time 19507402 ps
CPU time 0.77 seconds
Started May 05 01:41:18 PM PDT 24
Finished May 05 01:41:19 PM PDT 24
Peak memory 203556 kb
Host smart-800da822-40d2-4fb7-b721-7124779e5250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239021478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.239021478
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3314096083
Short name T732
Test name
Test status
Simulation time 15788897 ps
CPU time 0.73 seconds
Started May 05 01:41:18 PM PDT 24
Finished May 05 01:41:19 PM PDT 24
Peak memory 203644 kb
Host smart-3ac26990-a8dd-4da5-99c5-c4664d001a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314096083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3314096083
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1571567792
Short name T163
Test name
Test status
Simulation time 872604644 ps
CPU time 16.72 seconds
Started May 05 01:40:55 PM PDT 24
Finished May 05 01:41:12 PM PDT 24
Peak memory 206996 kb
Host smart-21f8ca06-5d3a-4d0e-bc41-59dee92f7c43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571567792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1571567792
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1262781235
Short name T789
Test name
Test status
Simulation time 184607953 ps
CPU time 11.21 seconds
Started May 05 01:40:56 PM PDT 24
Finished May 05 01:41:08 PM PDT 24
Peak memory 206952 kb
Host smart-a09ae8a2-ae6c-4829-b8e9-249a586807e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262781235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1262781235
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2796367254
Short name T95
Test name
Test status
Simulation time 125180546 ps
CPU time 1.42 seconds
Started May 05 01:40:53 PM PDT 24
Finished May 05 01:40:55 PM PDT 24
Peak memory 206872 kb
Host smart-81e8a009-4a7e-4468-8fa3-776980423f69
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796367254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2796367254
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2032206783
Short name T140
Test name
Test status
Simulation time 663910257 ps
CPU time 3.91 seconds
Started May 05 01:40:56 PM PDT 24
Finished May 05 01:41:00 PM PDT 24
Peak memory 216824 kb
Host smart-f7eb3b84-0225-49d5-bb02-006d232dd37a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032206783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2032206783
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.172960823
Short name T728
Test name
Test status
Simulation time 14981291 ps
CPU time 0.72 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:40:54 PM PDT 24
Peak memory 203580 kb
Host smart-7913a74d-5ef5-4737-8d97-2dd65a00457f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172960823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.172960823
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3557509595
Short name T151
Test name
Test status
Simulation time 575616329 ps
CPU time 2.24 seconds
Started May 05 01:40:49 PM PDT 24
Finished May 05 01:40:51 PM PDT 24
Peak memory 215224 kb
Host smart-236a11b2-9c6b-408a-b1d9-29c39f73749b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557509595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3557509595
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3807966889
Short name T747
Test name
Test status
Simulation time 10216068 ps
CPU time 0.63 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:40:53 PM PDT 24
Peak memory 203484 kb
Host smart-999ae42f-afa3-4b0f-958d-52a87f563e11
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807966889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3807966889
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2877526387
Short name T823
Test name
Test status
Simulation time 274703291 ps
CPU time 3.03 seconds
Started May 05 01:40:59 PM PDT 24
Finished May 05 01:41:03 PM PDT 24
Peak memory 215148 kb
Host smart-e29695f7-56b7-43b4-bd00-670a14fdd22c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877526387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2877526387
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3081340687
Short name T806
Test name
Test status
Simulation time 712991609 ps
CPU time 3.3 seconds
Started May 05 01:40:51 PM PDT 24
Finished May 05 01:40:54 PM PDT 24
Peak memory 216236 kb
Host smart-713c1b2b-f532-4dc1-9ec6-fde92bef61ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081340687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
081340687
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.445966751
Short name T179
Test name
Test status
Simulation time 1529155687 ps
CPU time 8.04 seconds
Started May 05 01:40:52 PM PDT 24
Finished May 05 01:41:01 PM PDT 24
Peak memory 215096 kb
Host smart-066d3cba-2c86-4144-b7af-52b06ea59b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445966751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.445966751
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2864736111
Short name T819
Test name
Test status
Simulation time 53352278 ps
CPU time 0.74 seconds
Started May 05 01:41:21 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 203940 kb
Host smart-a12cbe28-2b8e-47f1-8adf-8161e3f84ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864736111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2864736111
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3654899995
Short name T793
Test name
Test status
Simulation time 17021437 ps
CPU time 0.74 seconds
Started May 05 01:41:23 PM PDT 24
Finished May 05 01:41:24 PM PDT 24
Peak memory 203564 kb
Host smart-b4741076-f3cc-4e7e-b78e-754d918db4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654899995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3654899995
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3476766968
Short name T775
Test name
Test status
Simulation time 15480501 ps
CPU time 0.75 seconds
Started May 05 01:41:21 PM PDT 24
Finished May 05 01:41:22 PM PDT 24
Peak memory 203944 kb
Host smart-c4b4f4cc-1cad-48b4-91d9-1f9282284177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476766968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3476766968
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3856596317
Short name T817
Test name
Test status
Simulation time 37453132 ps
CPU time 0.75 seconds
Started May 05 01:41:19 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 203588 kb
Host smart-1ff0cf74-1c3d-4b97-8a63-369943c654e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856596317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3856596317
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1059828026
Short name T825
Test name
Test status
Simulation time 48366149 ps
CPU time 0.82 seconds
Started May 05 01:41:22 PM PDT 24
Finished May 05 01:41:23 PM PDT 24
Peak memory 203640 kb
Host smart-12a534ef-cd56-49ec-b699-c1691a52123a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059828026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1059828026
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3001537276
Short name T773
Test name
Test status
Simulation time 51385233 ps
CPU time 0.73 seconds
Started May 05 01:41:22 PM PDT 24
Finished May 05 01:41:23 PM PDT 24
Peak memory 203640 kb
Host smart-119e43aa-8f2a-4b49-976f-3d978a3137b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001537276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3001537276
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2521001784
Short name T800
Test name
Test status
Simulation time 16527767 ps
CPU time 0.77 seconds
Started May 05 01:41:24 PM PDT 24
Finished May 05 01:41:26 PM PDT 24
Peak memory 203616 kb
Host smart-63edd7f4-3896-4ee4-973e-c02cdc61c19a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521001784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2521001784
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2824106493
Short name T729
Test name
Test status
Simulation time 46779994 ps
CPU time 0.69 seconds
Started May 05 01:41:26 PM PDT 24
Finished May 05 01:41:28 PM PDT 24
Peak memory 203572 kb
Host smart-c5bc1bfe-54b2-4bb9-8457-92da00a9a195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824106493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2824106493
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.539242454
Short name T831
Test name
Test status
Simulation time 15537476 ps
CPU time 0.75 seconds
Started May 05 01:41:26 PM PDT 24
Finished May 05 01:41:27 PM PDT 24
Peak memory 203916 kb
Host smart-208eaaf1-9a23-4a8e-acbd-63aed6aa8293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539242454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.539242454
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.903536434
Short name T807
Test name
Test status
Simulation time 16576005 ps
CPU time 0.73 seconds
Started May 05 01:41:28 PM PDT 24
Finished May 05 01:41:29 PM PDT 24
Peak memory 203868 kb
Host smart-372e6b53-8feb-498c-a074-0a68c3814253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903536434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.903536434
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2826440867
Short name T734
Test name
Test status
Simulation time 258751755 ps
CPU time 8.03 seconds
Started May 05 01:40:58 PM PDT 24
Finished May 05 01:41:07 PM PDT 24
Peak memory 206932 kb
Host smart-fdeb1541-c043-4342-b332-1220c283be90
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826440867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2826440867
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3211274430
Short name T781
Test name
Test status
Simulation time 3329978404 ps
CPU time 23.69 seconds
Started May 05 01:40:56 PM PDT 24
Finished May 05 01:41:20 PM PDT 24
Peak memory 207100 kb
Host smart-47fce2d4-e1db-4c94-8115-20f018ec52bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211274430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3211274430
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4043289111
Short name T92
Test name
Test status
Simulation time 50341992 ps
CPU time 0.96 seconds
Started May 05 01:40:57 PM PDT 24
Finished May 05 01:40:58 PM PDT 24
Peak memory 206824 kb
Host smart-f4c172b9-3ba0-455c-b885-b2a32023c27e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043289111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4043289111
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.557760483
Short name T149
Test name
Test status
Simulation time 51372742 ps
CPU time 1.72 seconds
Started May 05 01:40:58 PM PDT 24
Finished May 05 01:41:00 PM PDT 24
Peak memory 215092 kb
Host smart-5c6792fd-3fba-4e16-b007-ed2bcd80d742
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557760483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.557760483
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1469693189
Short name T780
Test name
Test status
Simulation time 20440266 ps
CPU time 0.74 seconds
Started May 05 01:40:58 PM PDT 24
Finished May 05 01:41:00 PM PDT 24
Peak memory 203964 kb
Host smart-2a7c95c8-76a3-4f3b-aa0a-716a6fb5c8a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469693189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
469693189
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2388011841
Short name T777
Test name
Test status
Simulation time 137172594 ps
CPU time 2.43 seconds
Started May 05 01:40:56 PM PDT 24
Finished May 05 01:40:59 PM PDT 24
Peak memory 215212 kb
Host smart-951131d3-c86b-4f31-83f9-2b663ceb35e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388011841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2388011841
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3868777252
Short name T756
Test name
Test status
Simulation time 14129563 ps
CPU time 0.66 seconds
Started May 05 01:40:59 PM PDT 24
Finished May 05 01:41:00 PM PDT 24
Peak memory 203480 kb
Host smart-5d66e15b-3e09-406e-8bb7-794b6748ebae
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868777252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3868777252
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1629503275
Short name T792
Test name
Test status
Simulation time 29024589 ps
CPU time 1.7 seconds
Started May 05 01:40:59 PM PDT 24
Finished May 05 01:41:01 PM PDT 24
Peak memory 215104 kb
Host smart-c96b1e34-bedc-4009-9cfd-e6da05ef1e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629503275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1629503275
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2075042737
Short name T130
Test name
Test status
Simulation time 30094878 ps
CPU time 1.88 seconds
Started May 05 01:40:57 PM PDT 24
Finished May 05 01:40:59 PM PDT 24
Peak memory 215344 kb
Host smart-07c8d77b-8624-4315-a02f-e6002f8af961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075042737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
075042737
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3916877009
Short name T378
Test name
Test status
Simulation time 336004233 ps
CPU time 18.87 seconds
Started May 05 01:40:55 PM PDT 24
Finished May 05 01:41:14 PM PDT 24
Peak memory 215172 kb
Host smart-672a2ee8-919f-4e53-b87d-6d3916b52d92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916877009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3916877009
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2060651359
Short name T801
Test name
Test status
Simulation time 39075663 ps
CPU time 0.67 seconds
Started May 05 01:41:29 PM PDT 24
Finished May 05 01:41:30 PM PDT 24
Peak memory 203596 kb
Host smart-57834310-3942-43bb-8f3b-ffcccea79c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060651359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2060651359
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2308288724
Short name T168
Test name
Test status
Simulation time 13754980 ps
CPU time 0.69 seconds
Started May 05 01:41:26 PM PDT 24
Finished May 05 01:41:27 PM PDT 24
Peak memory 203556 kb
Host smart-218561e0-6d3b-42f2-b204-53ef70ba77e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308288724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2308288724
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1264946298
Short name T731
Test name
Test status
Simulation time 14171646 ps
CPU time 0.73 seconds
Started May 05 01:41:25 PM PDT 24
Finished May 05 01:41:26 PM PDT 24
Peak memory 203644 kb
Host smart-0ea3da42-c36d-4c04-800d-4f523d9ae525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264946298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1264946298
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1585040603
Short name T799
Test name
Test status
Simulation time 20817691 ps
CPU time 0.7 seconds
Started May 05 01:41:26 PM PDT 24
Finished May 05 01:41:27 PM PDT 24
Peak memory 203632 kb
Host smart-e214944d-d26f-4051-a347-6fcd6e6da476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585040603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1585040603
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3207036713
Short name T815
Test name
Test status
Simulation time 40120104 ps
CPU time 0.71 seconds
Started May 05 01:41:26 PM PDT 24
Finished May 05 01:41:28 PM PDT 24
Peak memory 203896 kb
Host smart-122910dd-852b-43c1-b6e8-c4d5a350001d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207036713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3207036713
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3951950895
Short name T755
Test name
Test status
Simulation time 38359313 ps
CPU time 0.69 seconds
Started May 05 01:41:28 PM PDT 24
Finished May 05 01:41:29 PM PDT 24
Peak memory 203892 kb
Host smart-a090d9eb-1d43-4752-a76e-29c591b097da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951950895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3951950895
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2343758350
Short name T778
Test name
Test status
Simulation time 22938704 ps
CPU time 0.69 seconds
Started May 05 01:41:25 PM PDT 24
Finished May 05 01:41:26 PM PDT 24
Peak memory 203624 kb
Host smart-bca9c155-d14a-4033-8ad9-6e42d6c11ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343758350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2343758350
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1174448800
Short name T812
Test name
Test status
Simulation time 12479022 ps
CPU time 0.72 seconds
Started May 05 01:41:33 PM PDT 24
Finished May 05 01:41:34 PM PDT 24
Peak memory 203784 kb
Host smart-cd1cab2b-5d89-4ba2-b74b-966562246eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174448800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1174448800
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3738617663
Short name T786
Test name
Test status
Simulation time 12680001 ps
CPU time 0.72 seconds
Started May 05 01:41:24 PM PDT 24
Finished May 05 01:41:25 PM PDT 24
Peak memory 203580 kb
Host smart-6a401a8b-9a80-4044-8924-70da5fc7a637
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738617663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3738617663
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2707805545
Short name T726
Test name
Test status
Simulation time 19017780 ps
CPU time 0.7 seconds
Started May 05 01:41:25 PM PDT 24
Finished May 05 01:41:26 PM PDT 24
Peak memory 203620 kb
Host smart-a0d950df-61b9-4d6d-8a60-10a071e54a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707805545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2707805545
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1757044531
Short name T137
Test name
Test status
Simulation time 363763978 ps
CPU time 2.91 seconds
Started May 05 01:40:58 PM PDT 24
Finished May 05 01:41:01 PM PDT 24
Peak memory 217704 kb
Host smart-fd4acff2-024f-4f12-9cdc-1839b60b36e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757044531 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1757044531
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2493631803
Short name T144
Test name
Test status
Simulation time 77292429 ps
CPU time 1.75 seconds
Started May 05 01:40:56 PM PDT 24
Finished May 05 01:40:58 PM PDT 24
Peak memory 215056 kb
Host smart-d3e39fda-58b2-4496-992a-8db1e18de131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493631803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
493631803
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3151393273
Short name T763
Test name
Test status
Simulation time 18381915 ps
CPU time 0.66 seconds
Started May 05 01:40:58 PM PDT 24
Finished May 05 01:40:59 PM PDT 24
Peak memory 203568 kb
Host smart-dc02a3da-fc91-4b60-b768-1c4a26fe8d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151393273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
151393273
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.541951439
Short name T158
Test name
Test status
Simulation time 152520974 ps
CPU time 1.95 seconds
Started May 05 01:40:59 PM PDT 24
Finished May 05 01:41:01 PM PDT 24
Peak memory 206896 kb
Host smart-00c72787-4148-4983-b02f-43204dfcd7b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541951439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.541951439
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1427909742
Short name T134
Test name
Test status
Simulation time 255387148 ps
CPU time 3.24 seconds
Started May 05 01:40:59 PM PDT 24
Finished May 05 01:41:03 PM PDT 24
Peak memory 215296 kb
Host smart-a604935a-83a5-482a-8f8c-b2ba5d4edf92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427909742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
427909742
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1266465065
Short name T821
Test name
Test status
Simulation time 4720376835 ps
CPU time 19.01 seconds
Started May 05 01:40:58 PM PDT 24
Finished May 05 01:41:18 PM PDT 24
Peak memory 215264 kb
Host smart-37dbb230-f477-495f-a82b-b60a62649814
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266465065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1266465065
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.984395039
Short name T738
Test name
Test status
Simulation time 208405449 ps
CPU time 3.65 seconds
Started May 05 01:41:04 PM PDT 24
Finished May 05 01:41:08 PM PDT 24
Peak memory 216716 kb
Host smart-e12fd400-fda3-45a9-97de-fbe59344d7af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984395039 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.984395039
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1740515517
Short name T804
Test name
Test status
Simulation time 133777653 ps
CPU time 1.88 seconds
Started May 05 01:41:03 PM PDT 24
Finished May 05 01:41:06 PM PDT 24
Peak memory 215156 kb
Host smart-ca7d8994-3f47-42f7-8969-274a6cb8d818
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740515517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
740515517
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.253381581
Short name T759
Test name
Test status
Simulation time 14404005 ps
CPU time 0.74 seconds
Started May 05 01:41:00 PM PDT 24
Finished May 05 01:41:02 PM PDT 24
Peak memory 203592 kb
Host smart-5a30e37c-bce4-4682-b206-f13ad994126b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253381581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.253381581
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3656606448
Short name T810
Test name
Test status
Simulation time 664795656 ps
CPU time 2.89 seconds
Started May 05 01:40:58 PM PDT 24
Finished May 05 01:41:02 PM PDT 24
Peak memory 215172 kb
Host smart-bf1174c6-6793-4ffb-a9a9-ae485742a90e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656606448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3656606448
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.513470784
Short name T126
Test name
Test status
Simulation time 414684807 ps
CPU time 4.65 seconds
Started May 05 01:41:00 PM PDT 24
Finished May 05 01:41:05 PM PDT 24
Peak memory 215296 kb
Host smart-2daeb56a-b89a-4c2e-9da2-b897fe3854e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513470784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.513470784
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2340638866
Short name T737
Test name
Test status
Simulation time 472773770 ps
CPU time 6.28 seconds
Started May 05 01:41:00 PM PDT 24
Finished May 05 01:41:07 PM PDT 24
Peak memory 215140 kb
Host smart-95b0e4b5-2d34-4668-9bfc-ce06e2720cb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340638866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2340638866
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1241009606
Short name T744
Test name
Test status
Simulation time 41043241 ps
CPU time 2.91 seconds
Started May 05 01:41:00 PM PDT 24
Finished May 05 01:41:03 PM PDT 24
Peak memory 217692 kb
Host smart-fdf3b026-362c-4a16-9065-05309f6f8361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241009606 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1241009606
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1564804497
Short name T152
Test name
Test status
Simulation time 72633039 ps
CPU time 1.31 seconds
Started May 05 01:41:01 PM PDT 24
Finished May 05 01:41:03 PM PDT 24
Peak memory 206908 kb
Host smart-cae7d420-3f68-4ccd-83c9-b0dabd151199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564804497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
564804497
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1675043360
Short name T169
Test name
Test status
Simulation time 60241445 ps
CPU time 0.75 seconds
Started May 05 01:40:59 PM PDT 24
Finished May 05 01:41:00 PM PDT 24
Peak memory 203672 kb
Host smart-a767b537-89db-4624-9fda-ba2d2a566607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675043360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
675043360
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.407142242
Short name T735
Test name
Test status
Simulation time 245736469 ps
CPU time 2.05 seconds
Started May 05 01:41:00 PM PDT 24
Finished May 05 01:41:02 PM PDT 24
Peak memory 206896 kb
Host smart-d95ad7fa-d999-4926-bb18-3dc849a90e90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407142242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.407142242
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.453264952
Short name T36
Test name
Test status
Simulation time 65205963 ps
CPU time 1.39 seconds
Started May 05 01:41:01 PM PDT 24
Finished May 05 01:41:03 PM PDT 24
Peak memory 215308 kb
Host smart-2921de7e-9375-4ba2-909d-8ce5f4b6fda7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453264952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.453264952
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.526457693
Short name T120
Test name
Test status
Simulation time 113642393 ps
CPU time 6.22 seconds
Started May 05 01:41:02 PM PDT 24
Finished May 05 01:41:08 PM PDT 24
Peak memory 215156 kb
Host smart-439f2e45-302b-455f-94fe-cba37c5b0007
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526457693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.526457693
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.698131641
Short name T736
Test name
Test status
Simulation time 104596226 ps
CPU time 1.84 seconds
Started May 05 01:41:02 PM PDT 24
Finished May 05 01:41:04 PM PDT 24
Peak memory 215240 kb
Host smart-105fb830-63fc-41ea-9781-844f1f5096c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698131641 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.698131641
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.829581308
Short name T751
Test name
Test status
Simulation time 51062968 ps
CPU time 1.45 seconds
Started May 05 01:41:01 PM PDT 24
Finished May 05 01:41:02 PM PDT 24
Peak memory 206944 kb
Host smart-bb7909d6-cd2f-4b8a-a11d-ec3ad69010eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829581308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.829581308
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2462903247
Short name T768
Test name
Test status
Simulation time 39792267 ps
CPU time 0.71 seconds
Started May 05 01:41:02 PM PDT 24
Finished May 05 01:41:03 PM PDT 24
Peak memory 203664 kb
Host smart-97b22ac9-b2fe-4e82-86a8-fd2cd0a9d955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462903247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
462903247
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.931621937
Short name T757
Test name
Test status
Simulation time 158259995 ps
CPU time 3.99 seconds
Started May 05 01:40:59 PM PDT 24
Finished May 05 01:41:04 PM PDT 24
Peak memory 215136 kb
Host smart-a18fbe68-4802-4e3b-b7b6-2a11494f4706
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931621937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.931621937
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3384158674
Short name T132
Test name
Test status
Simulation time 260261185 ps
CPU time 3.73 seconds
Started May 05 01:41:01 PM PDT 24
Finished May 05 01:41:05 PM PDT 24
Peak memory 215272 kb
Host smart-ae9b209f-9a8c-488d-92c1-26159e4a6211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384158674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
384158674
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2201258584
Short name T766
Test name
Test status
Simulation time 584117908 ps
CPU time 17.47 seconds
Started May 05 01:41:03 PM PDT 24
Finished May 05 01:41:21 PM PDT 24
Peak memory 215140 kb
Host smart-3ee153ba-58c2-45bb-aae0-eb7fa3fc2b47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201258584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2201258584
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3812934583
Short name T784
Test name
Test status
Simulation time 27156208 ps
CPU time 1.97 seconds
Started May 05 01:41:05 PM PDT 24
Finished May 05 01:41:08 PM PDT 24
Peak memory 216240 kb
Host smart-a35aa306-efcd-478d-aecf-889ce0eeafa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812934583 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3812934583
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.740392700
Short name T154
Test name
Test status
Simulation time 384574854 ps
CPU time 2.56 seconds
Started May 05 01:41:07 PM PDT 24
Finished May 05 01:41:10 PM PDT 24
Peak memory 215044 kb
Host smart-8bbaa73f-261c-4d9f-a9c1-cef4beb7b77d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740392700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.740392700
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1356454840
Short name T790
Test name
Test status
Simulation time 23383459 ps
CPU time 0.72 seconds
Started May 05 01:41:04 PM PDT 24
Finished May 05 01:41:05 PM PDT 24
Peak memory 203632 kb
Host smart-ee516a5a-9e72-45a3-9a5f-4cdffd9d2673
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356454840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
356454840
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3548821051
Short name T160
Test name
Test status
Simulation time 143089490 ps
CPU time 1.72 seconds
Started May 05 01:41:07 PM PDT 24
Finished May 05 01:41:10 PM PDT 24
Peak memory 215032 kb
Host smart-005bd90d-22d7-44d6-97cf-34519e7a933d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548821051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3548821051
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1588395077
Short name T125
Test name
Test status
Simulation time 197818500 ps
CPU time 2.73 seconds
Started May 05 01:41:05 PM PDT 24
Finished May 05 01:41:08 PM PDT 24
Peak memory 216288 kb
Host smart-36609a24-d6dc-4ed0-b966-5a4625ff700b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588395077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
588395077
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.396445571
Short name T37
Test name
Test status
Simulation time 3210016490 ps
CPU time 20.55 seconds
Started May 05 01:41:07 PM PDT 24
Finished May 05 01:41:28 PM PDT 24
Peak memory 215472 kb
Host smart-647ef49f-29c8-4a92-8f80-502591592ab7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396445571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.396445571
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4150616247
Short name T581
Test name
Test status
Simulation time 14797466 ps
CPU time 0.79 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:55:53 PM PDT 24
Peak memory 205432 kb
Host smart-7a86c12b-4aa2-43aa-b691-8bf03ec78665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150616247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
150616247
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.844953530
Short name T716
Test name
Test status
Simulation time 44925459 ps
CPU time 0.74 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 206628 kb
Host smart-cd7230a6-bdcf-4f18-b396-a17be5112133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844953530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.844953530
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3797973207
Short name T372
Test name
Test status
Simulation time 1262410092 ps
CPU time 12.8 seconds
Started May 05 01:55:50 PM PDT 24
Finished May 05 01:56:03 PM PDT 24
Peak memory 253192 kb
Host smart-02bfa223-9c5c-41af-bf0f-2e957a933afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797973207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3797973207
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1616218605
Short name T334
Test name
Test status
Simulation time 3137730266 ps
CPU time 23.84 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:56:18 PM PDT 24
Peak memory 223716 kb
Host smart-41695d07-3dac-49ad-980d-4f455b58902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616218605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1616218605
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1016136787
Short name T340
Test name
Test status
Simulation time 2438725910 ps
CPU time 16.33 seconds
Started May 05 01:55:47 PM PDT 24
Finished May 05 01:56:04 PM PDT 24
Peak memory 222216 kb
Host smart-69b55017-3452-4e99-a076-e6a676702589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016136787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1016136787
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2339453458
Short name T211
Test name
Test status
Simulation time 2209126009 ps
CPU time 12.99 seconds
Started May 05 01:55:37 PM PDT 24
Finished May 05 01:55:50 PM PDT 24
Peak memory 232648 kb
Host smart-f3157f2c-049e-4f9b-8599-0bf83786f371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339453458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2339453458
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.944296326
Short name T252
Test name
Test status
Simulation time 9160335070 ps
CPU time 16.03 seconds
Started May 05 01:55:49 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 248896 kb
Host smart-f13d7283-7d4d-44f9-acaf-d6db1e82a822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944296326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.944296326
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1407331463
Short name T505
Test name
Test status
Simulation time 298394344 ps
CPU time 3.94 seconds
Started May 05 01:55:49 PM PDT 24
Finished May 05 01:55:53 PM PDT 24
Peak memory 219756 kb
Host smart-5fe6a381-c8f3-4ca9-a405-0f1d7f0b55b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1407331463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1407331463
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.758327074
Short name T645
Test name
Test status
Simulation time 3539798442 ps
CPU time 9.81 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:56:01 PM PDT 24
Peak memory 216340 kb
Host smart-bd7af42e-2069-42c2-8fb8-0466ab559fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758327074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.758327074
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1487958086
Short name T510
Test name
Test status
Simulation time 11445386740 ps
CPU time 16.47 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:56:12 PM PDT 24
Peak memory 216236 kb
Host smart-e249ff59-53dc-4465-89f7-415406c05f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487958086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1487958086
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3968445910
Short name T674
Test name
Test status
Simulation time 79118025 ps
CPU time 1.64 seconds
Started May 05 01:55:37 PM PDT 24
Finished May 05 01:55:39 PM PDT 24
Peak memory 216252 kb
Host smart-4af28b11-20b1-48d9-9c28-8eaa67a8711f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968445910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3968445910
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1232712858
Short name T528
Test name
Test status
Simulation time 72668835 ps
CPU time 0.75 seconds
Started May 05 01:55:36 PM PDT 24
Finished May 05 01:55:38 PM PDT 24
Peak memory 205760 kb
Host smart-7b1cd9e2-6840-4517-ba61-c4fdb072e2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232712858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1232712858
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3694711111
Short name T253
Test name
Test status
Simulation time 1261875556 ps
CPU time 4.93 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:55:57 PM PDT 24
Peak memory 217620 kb
Host smart-0b1a6338-089e-4ffa-8ad5-7f06fd5e80d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694711111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3694711111
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1239145759
Short name T522
Test name
Test status
Simulation time 36902547 ps
CPU time 0.72 seconds
Started May 05 01:55:57 PM PDT 24
Finished May 05 01:55:59 PM PDT 24
Peak memory 205396 kb
Host smart-42fffda7-b578-4ec3-9902-5dcd81b60bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239145759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
239145759
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1309966790
Short name T656
Test name
Test status
Simulation time 61987509 ps
CPU time 0.77 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 205956 kb
Host smart-68f68ce7-9bc1-4c91-a8de-5c80875c8a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309966790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1309966790
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.742462828
Short name T373
Test name
Test status
Simulation time 13882534096 ps
CPU time 83.37 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:57:16 PM PDT 24
Peak memory 250100 kb
Host smart-b5b6e1e8-2b10-41bd-90d7-18045ff7ac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742462828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.742462828
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2872627658
Short name T281
Test name
Test status
Simulation time 3616986570 ps
CPU time 5.68 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:55:58 PM PDT 24
Peak memory 220252 kb
Host smart-a67ce515-9d92-4a37-af16-3641736057d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872627658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2872627658
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3315321302
Short name T611
Test name
Test status
Simulation time 3793716479 ps
CPU time 8.56 seconds
Started May 05 01:55:58 PM PDT 24
Finished May 05 01:56:08 PM PDT 24
Peak memory 218936 kb
Host smart-5129da35-185b-4ecd-ba5e-7c2c7dc0b638
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315321302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3315321302
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1896285857
Short name T47
Test name
Test status
Simulation time 309378892 ps
CPU time 1.19 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:55:55 PM PDT 24
Peak memory 235100 kb
Host smart-8e0ba4a2-f371-4293-8d58-7900391a44e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896285857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1896285857
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.539082568
Short name T638
Test name
Test status
Simulation time 11296484313 ps
CPU time 32.93 seconds
Started May 05 01:55:48 PM PDT 24
Finished May 05 01:56:22 PM PDT 24
Peak memory 216316 kb
Host smart-3fccb4e2-58ea-4af4-bac0-4b07a351d901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539082568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.539082568
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.604232373
Short name T16
Test name
Test status
Simulation time 38169369 ps
CPU time 1.01 seconds
Started May 05 01:55:42 PM PDT 24
Finished May 05 01:55:43 PM PDT 24
Peak memory 206716 kb
Host smart-693587c2-511a-4d3e-b56a-f3b3e041d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604232373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.604232373
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.349114669
Short name T549
Test name
Test status
Simulation time 249292702 ps
CPU time 0.91 seconds
Started May 05 01:55:50 PM PDT 24
Finished May 05 01:55:51 PM PDT 24
Peak memory 206820 kb
Host smart-c9d424d0-a3a8-4342-92da-e0479507c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349114669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.349114669
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.581270904
Short name T192
Test name
Test status
Simulation time 1370652262 ps
CPU time 5.67 seconds
Started May 05 01:55:44 PM PDT 24
Finished May 05 01:55:50 PM PDT 24
Peak memory 216424 kb
Host smart-8ab14c20-8364-4e0b-9768-1783c56f637f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581270904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.581270904
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2656044149
Short name T541
Test name
Test status
Simulation time 35347868 ps
CPU time 0.74 seconds
Started May 05 01:56:12 PM PDT 24
Finished May 05 01:56:13 PM PDT 24
Peak memory 204840 kb
Host smart-49c3f420-91f1-4f25-9b58-ea5640185e47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656044149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2656044149
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4152824950
Short name T637
Test name
Test status
Simulation time 46250155 ps
CPU time 0.74 seconds
Started May 05 01:56:17 PM PDT 24
Finished May 05 01:56:19 PM PDT 24
Peak memory 205600 kb
Host smart-137666cb-4f6f-489d-b009-346da1ce0c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152824950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4152824950
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.357201757
Short name T350
Test name
Test status
Simulation time 1691833928 ps
CPU time 3.97 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:03 PM PDT 24
Peak memory 217356 kb
Host smart-cb5b174f-dd71-4ef9-8afa-24c9932b7ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357201757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.357201757
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2901129402
Short name T610
Test name
Test status
Simulation time 370481410 ps
CPU time 5.68 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:21 PM PDT 24
Peak memory 220364 kb
Host smart-88f7684f-4c6d-492b-874c-d74c093221c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2901129402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2901129402
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3064915115
Short name T668
Test name
Test status
Simulation time 11055063071 ps
CPU time 9.57 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:13 PM PDT 24
Peak memory 216332 kb
Host smart-13e61650-c3fb-49d2-8263-4eeb720a29ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064915115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3064915115
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1250598057
Short name T64
Test name
Test status
Simulation time 19098934 ps
CPU time 1.21 seconds
Started May 05 01:56:15 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 216260 kb
Host smart-f383eb2b-1de5-4980-948b-0c6315fb678a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250598057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1250598057
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2755303631
Short name T512
Test name
Test status
Simulation time 31548127 ps
CPU time 0.86 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:15 PM PDT 24
Peak memory 205752 kb
Host smart-ba7d67c1-405b-4fa4-8f08-0e3edf5940ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755303631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2755303631
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.836499888
Short name T223
Test name
Test status
Simulation time 15554949869 ps
CPU time 24.35 seconds
Started May 05 01:56:15 PM PDT 24
Finished May 05 01:56:41 PM PDT 24
Peak memory 221468 kb
Host smart-0c21f4dc-4ed1-4be9-8047-f56386cf82cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836499888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.836499888
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3527570006
Short name T122
Test name
Test status
Simulation time 16158964 ps
CPU time 0.81 seconds
Started May 05 01:56:15 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 207000 kb
Host smart-f48d20cd-b807-4896-b3aa-58d16e506325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527570006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3527570006
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4440542
Short name T173
Test name
Test status
Simulation time 8585520313 ps
CPU time 11.46 seconds
Started May 05 01:56:01 PM PDT 24
Finished May 05 01:56:13 PM PDT 24
Peak memory 218880 kb
Host smart-f806b500-253c-4f14-aa3a-98bd8b18964e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4440542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4440542
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2944136803
Short name T256
Test name
Test status
Simulation time 77978144 ps
CPU time 2.6 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:07 PM PDT 24
Peak memory 223236 kb
Host smart-5f07784c-8e34-4af0-b3ea-56252b5158ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944136803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2944136803
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.314857979
Short name T435
Test name
Test status
Simulation time 1923261107 ps
CPU time 10.02 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:12 PM PDT 24
Peak memory 220400 kb
Host smart-9a1be8c2-960e-4a0a-9090-c4cb4ea9dc2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=314857979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.314857979
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.709211428
Short name T546
Test name
Test status
Simulation time 25534338994 ps
CPU time 43.49 seconds
Started May 05 01:56:04 PM PDT 24
Finished May 05 01:56:48 PM PDT 24
Peak memory 216392 kb
Host smart-14fe288a-a64e-4c92-8873-134889ee9faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709211428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.709211428
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.634278030
Short name T608
Test name
Test status
Simulation time 5684636917 ps
CPU time 8.09 seconds
Started May 05 01:56:13 PM PDT 24
Finished May 05 01:56:22 PM PDT 24
Peak memory 216340 kb
Host smart-782bb1d3-b131-47e1-9758-7cc6c87aaa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634278030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.634278030
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.160269457
Short name T460
Test name
Test status
Simulation time 600392238 ps
CPU time 9.6 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:13 PM PDT 24
Peak memory 216336 kb
Host smart-539e6cb2-463c-4d17-8b2c-f46797f14f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160269457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.160269457
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3455551349
Short name T507
Test name
Test status
Simulation time 143632910 ps
CPU time 0.88 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:15 PM PDT 24
Peak memory 206844 kb
Host smart-11d1d19f-e581-477e-82f1-6cec824d89a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455551349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3455551349
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2495829900
Short name T174
Test name
Test status
Simulation time 13457080 ps
CPU time 0.68 seconds
Started May 05 01:56:07 PM PDT 24
Finished May 05 01:56:08 PM PDT 24
Peak memory 205328 kb
Host smart-d461a7b4-5bbe-48c2-8271-e07fcb432488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495829900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2495829900
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2547921619
Short name T516
Test name
Test status
Simulation time 13480003 ps
CPU time 0.75 seconds
Started May 05 01:56:05 PM PDT 24
Finished May 05 01:56:07 PM PDT 24
Peak memory 206216 kb
Host smart-186f99d0-faba-4e60-8e19-98ce30e12c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547921619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2547921619
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2283168983
Short name T300
Test name
Test status
Simulation time 4003590719 ps
CPU time 61.24 seconds
Started May 05 01:56:07 PM PDT 24
Finished May 05 01:57:09 PM PDT 24
Peak memory 240848 kb
Host smart-36138404-133f-4d4a-9535-52fb9874939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283168983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2283168983
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1312045635
Short name T319
Test name
Test status
Simulation time 891457110 ps
CPU time 5.02 seconds
Started May 05 01:56:12 PM PDT 24
Finished May 05 01:56:18 PM PDT 24
Peak memory 218512 kb
Host smart-b43f9789-a6a1-4a50-9dc8-2206b49a165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312045635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1312045635
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4137250482
Short name T320
Test name
Test status
Simulation time 4472564512 ps
CPU time 12.58 seconds
Started May 05 01:56:15 PM PDT 24
Finished May 05 01:56:28 PM PDT 24
Peak memory 222244 kb
Host smart-38565515-ceda-47b4-9f55-afa7ca81fc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137250482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4137250482
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2515253355
Short name T530
Test name
Test status
Simulation time 2321048236 ps
CPU time 10.71 seconds
Started May 05 01:56:34 PM PDT 24
Finished May 05 01:56:45 PM PDT 24
Peak memory 220852 kb
Host smart-849d3b2e-bad9-44e1-abb8-937f600bfbf4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2515253355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2515253355
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2131988947
Short name T635
Test name
Test status
Simulation time 3731945696 ps
CPU time 17.28 seconds
Started May 05 01:56:13 PM PDT 24
Finished May 05 01:56:31 PM PDT 24
Peak memory 216316 kb
Host smart-7c414930-f1e4-4a3e-8488-e056507f78e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131988947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2131988947
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2225291726
Short name T60
Test name
Test status
Simulation time 380433853 ps
CPU time 1.75 seconds
Started May 05 01:56:19 PM PDT 24
Finished May 05 01:56:21 PM PDT 24
Peak memory 216236 kb
Host smart-898d9a83-e599-453f-9d7f-558c234efe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225291726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2225291726
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3513822842
Short name T427
Test name
Test status
Simulation time 97385936 ps
CPU time 0.89 seconds
Started May 05 01:56:13 PM PDT 24
Finished May 05 01:56:15 PM PDT 24
Peak memory 206820 kb
Host smart-e6f0ddbb-87f1-4be9-9b5a-d48636e033bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513822842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3513822842
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2737323245
Short name T619
Test name
Test status
Simulation time 40312043 ps
CPU time 0.71 seconds
Started May 05 01:56:29 PM PDT 24
Finished May 05 01:56:30 PM PDT 24
Peak memory 205696 kb
Host smart-4aa40e79-a683-4361-b1ea-5ce20ba962c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737323245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2737323245
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.390109706
Short name T24
Test name
Test status
Simulation time 6389990754 ps
CPU time 13.83 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:30 PM PDT 24
Peak memory 218468 kb
Host smart-245585af-533c-418d-ba67-c63db5a244cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390109706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.390109706
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1130898675
Short name T488
Test name
Test status
Simulation time 29081436 ps
CPU time 0.78 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 206676 kb
Host smart-6fc9fcd6-1009-4ebd-a4e4-d7deef095fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130898675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1130898675
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1845901683
Short name T11
Test name
Test status
Simulation time 20006288897 ps
CPU time 141.54 seconds
Started May 05 01:56:17 PM PDT 24
Finished May 05 01:58:39 PM PDT 24
Peak memory 253556 kb
Host smart-ccb8f267-24ba-4056-b10f-3f21ba713273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845901683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1845901683
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1495388905
Short name T68
Test name
Test status
Simulation time 960289202 ps
CPU time 8.18 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:25 PM PDT 24
Peak memory 232660 kb
Host smart-8539ddb6-5b90-42be-be55-a220915a4a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495388905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1495388905
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3252702040
Short name T498
Test name
Test status
Simulation time 1115116481 ps
CPU time 12.17 seconds
Started May 05 01:56:18 PM PDT 24
Finished May 05 01:56:31 PM PDT 24
Peak memory 221860 kb
Host smart-3488dd6f-0d99-48e8-9741-92f1c8426f1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3252702040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3252702040
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3439134933
Short name T381
Test name
Test status
Simulation time 8915354948 ps
CPU time 22.96 seconds
Started May 05 01:56:05 PM PDT 24
Finished May 05 01:56:29 PM PDT 24
Peak memory 216320 kb
Host smart-fcd80d80-4ebe-426e-a39c-887cee30e13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439134933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3439134933
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2600002304
Short name T470
Test name
Test status
Simulation time 260934222 ps
CPU time 2.56 seconds
Started May 05 01:56:20 PM PDT 24
Finished May 05 01:56:22 PM PDT 24
Peak memory 216324 kb
Host smart-b6fd4b34-b8f7-40d4-8a57-37c97385e075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600002304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2600002304
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4250787748
Short name T469
Test name
Test status
Simulation time 51942872 ps
CPU time 1.37 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 208076 kb
Host smart-70a14dbd-9f3e-419b-ac1b-0d8d59a7ba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250787748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4250787748
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3428614243
Short name T599
Test name
Test status
Simulation time 19322683 ps
CPU time 0.7 seconds
Started May 05 01:56:20 PM PDT 24
Finished May 05 01:56:21 PM PDT 24
Peak memory 205780 kb
Host smart-31aa29ef-c578-4094-98f5-c81eefebf24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428614243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3428614243
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3865367931
Short name T615
Test name
Test status
Simulation time 16310451 ps
CPU time 0.71 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 204876 kb
Host smart-b27b3dbf-bd2f-47d8-9285-73f658389a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865367931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3865367931
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.561547941
Short name T438
Test name
Test status
Simulation time 67049047 ps
CPU time 0.74 seconds
Started May 05 01:56:18 PM PDT 24
Finished May 05 01:56:19 PM PDT 24
Peak memory 206988 kb
Host smart-73355afe-6f24-4495-a104-2917506b28ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561547941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.561547941
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.538166310
Short name T162
Test name
Test status
Simulation time 6290614320 ps
CPU time 34.74 seconds
Started May 05 01:56:12 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 249084 kb
Host smart-8b37b1e0-1255-4bf1-be77-4b0020c4ac62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538166310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.538166310
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.639541160
Short name T631
Test name
Test status
Simulation time 83080149 ps
CPU time 3.47 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:19 PM PDT 24
Peak memory 218532 kb
Host smart-ee84c7cd-4ede-45ae-a271-35cd6a609ccf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=639541160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.639541160
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1189932971
Short name T547
Test name
Test status
Simulation time 6341913275 ps
CPU time 30.54 seconds
Started May 05 01:56:11 PM PDT 24
Finished May 05 01:56:42 PM PDT 24
Peak memory 216412 kb
Host smart-8117264d-4eab-4db6-99f4-9d419c29ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189932971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1189932971
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.491226308
Short name T670
Test name
Test status
Simulation time 5593880373 ps
CPU time 10.46 seconds
Started May 05 01:56:15 PM PDT 24
Finished May 05 01:56:26 PM PDT 24
Peak memory 216368 kb
Host smart-fa1589c6-4500-44fa-9130-8dd454dfd72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491226308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.491226308
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2202630571
Short name T657
Test name
Test status
Simulation time 102528987 ps
CPU time 1.15 seconds
Started May 05 01:56:18 PM PDT 24
Finished May 05 01:56:20 PM PDT 24
Peak memory 216200 kb
Host smart-e703d987-7844-4f61-9e4b-48936c612718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202630571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2202630571
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1271255958
Short name T456
Test name
Test status
Simulation time 62875868 ps
CPU time 0.78 seconds
Started May 05 01:56:10 PM PDT 24
Finished May 05 01:56:11 PM PDT 24
Peak memory 205812 kb
Host smart-2cd6aec8-1df6-4085-8f4a-c0f96ca40dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271255958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1271255958
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.738486497
Short name T671
Test name
Test status
Simulation time 14285908 ps
CPU time 0.69 seconds
Started May 05 01:56:22 PM PDT 24
Finished May 05 01:56:23 PM PDT 24
Peak memory 205396 kb
Host smart-5a6b23c7-c3c0-4b07-a662-b8590e5ac4b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738486497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.738486497
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.3179663702
Short name T313
Test name
Test status
Simulation time 1584520583 ps
CPU time 16.15 seconds
Started May 05 01:56:18 PM PDT 24
Finished May 05 01:56:35 PM PDT 24
Peak memory 218488 kb
Host smart-ac6d4226-4607-45a0-88f6-cca76edf526d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179663702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.3179663702
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2446737891
Short name T402
Test name
Test status
Simulation time 147270108 ps
CPU time 0.75 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:18 PM PDT 24
Peak memory 205672 kb
Host smart-d7dde11c-f09c-4641-896e-98f933551ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446737891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2446737891
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.4274869204
Short name T371
Test name
Test status
Simulation time 16948675517 ps
CPU time 79.77 seconds
Started May 05 01:56:22 PM PDT 24
Finished May 05 01:57:43 PM PDT 24
Peak memory 263276 kb
Host smart-d76cdea2-be85-4f37-988e-f95aa9ae8716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274869204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.4274869204
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1329817080
Short name T324
Test name
Test status
Simulation time 21248852817 ps
CPU time 82.23 seconds
Started May 05 01:56:19 PM PDT 24
Finished May 05 01:57:41 PM PDT 24
Peak memory 219892 kb
Host smart-df5fabd4-f97c-4e50-97ae-91c1183dc2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329817080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1329817080
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1193138800
Short name T176
Test name
Test status
Simulation time 1233315033 ps
CPU time 4.46 seconds
Started May 05 01:56:23 PM PDT 24
Finished May 05 01:56:27 PM PDT 24
Peak memory 221836 kb
Host smart-94304602-9313-44a2-b614-871e64102ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193138800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1193138800
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2494957149
Short name T459
Test name
Test status
Simulation time 229562809 ps
CPU time 5.14 seconds
Started May 05 01:56:34 PM PDT 24
Finished May 05 01:56:40 PM PDT 24
Peak memory 223000 kb
Host smart-6b271605-9b76-45dd-a68b-e9e2eb228df6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2494957149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2494957149
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3290170081
Short name T659
Test name
Test status
Simulation time 191269504 ps
CPU time 1.11 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 207444 kb
Host smart-b356c5ce-5b30-4c16-aac1-5e5257b30c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290170081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3290170081
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1778128646
Short name T662
Test name
Test status
Simulation time 2977444208 ps
CPU time 10.52 seconds
Started May 05 01:56:22 PM PDT 24
Finished May 05 01:56:33 PM PDT 24
Peak memory 216336 kb
Host smart-6828b906-087a-453a-88d4-5456905c3109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778128646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1778128646
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3619686291
Short name T472
Test name
Test status
Simulation time 88827252337 ps
CPU time 19.07 seconds
Started May 05 01:56:22 PM PDT 24
Finished May 05 01:56:41 PM PDT 24
Peak memory 216368 kb
Host smart-dc5b4415-c5d6-4d52-a9d9-1c74ddfba172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619686291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3619686291
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.817781634
Short name T63
Test name
Test status
Simulation time 88415934 ps
CPU time 3.59 seconds
Started May 05 01:56:20 PM PDT 24
Finished May 05 01:56:24 PM PDT 24
Peak memory 216292 kb
Host smart-3b471334-edb0-4c6a-ae0d-df6ad3d6a182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817781634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.817781634
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.697557627
Short name T640
Test name
Test status
Simulation time 72935932 ps
CPU time 0.9 seconds
Started May 05 01:56:22 PM PDT 24
Finished May 05 01:56:23 PM PDT 24
Peak memory 205760 kb
Host smart-7179755b-b8dd-440b-9b08-f1bcbea58ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697557627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.697557627
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1832313600
Short name T598
Test name
Test status
Simulation time 3827770506 ps
CPU time 8.05 seconds
Started May 05 01:56:20 PM PDT 24
Finished May 05 01:56:29 PM PDT 24
Peak memory 216352 kb
Host smart-1b0c2eaa-5ba6-4b1d-9bd0-852e85ae8276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832313600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1832313600
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1441786745
Short name T482
Test name
Test status
Simulation time 16431642 ps
CPU time 0.71 seconds
Started May 05 01:56:32 PM PDT 24
Finished May 05 01:56:33 PM PDT 24
Peak memory 204860 kb
Host smart-91ef4805-d776-44e0-bdbf-23f97c7b25f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441786745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1441786745
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2852808523
Short name T696
Test name
Test status
Simulation time 33658588 ps
CPU time 0.79 seconds
Started May 05 01:56:31 PM PDT 24
Finished May 05 01:56:32 PM PDT 24
Peak memory 207208 kb
Host smart-342e18a6-ac2d-4a93-ba8c-10ef640b560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852808523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2852808523
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.781078576
Short name T365
Test name
Test status
Simulation time 32627366121 ps
CPU time 35.58 seconds
Started May 05 01:56:34 PM PDT 24
Finished May 05 01:57:10 PM PDT 24
Peak memory 249160 kb
Host smart-db29ec58-de9c-4b2e-898a-804a588cf4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781078576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.781078576
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.761172864
Short name T87
Test name
Test status
Simulation time 708819405 ps
CPU time 4.43 seconds
Started May 05 01:56:29 PM PDT 24
Finished May 05 01:56:34 PM PDT 24
Peak memory 219212 kb
Host smart-f6f8c919-5fbe-4a4a-a138-e6cba3bd7c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761172864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.761172864
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2059572287
Short name T713
Test name
Test status
Simulation time 402821566 ps
CPU time 3.17 seconds
Started May 05 01:56:33 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 218584 kb
Host smart-74f35126-f6bb-4607-b4b9-7e1c1807daf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059572287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2059572287
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3031783185
Short name T698
Test name
Test status
Simulation time 136561414 ps
CPU time 4.09 seconds
Started May 05 01:56:41 PM PDT 24
Finished May 05 01:56:45 PM PDT 24
Peak memory 223044 kb
Host smart-2327dd7a-6d53-48c5-a85c-4628a509a6ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3031783185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3031783185
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1147787780
Short name T538
Test name
Test status
Simulation time 6053108969 ps
CPU time 5.22 seconds
Started May 05 01:56:27 PM PDT 24
Finished May 05 01:56:33 PM PDT 24
Peak memory 216388 kb
Host smart-f0e2fbdc-9777-4a9e-af6b-ddf1ee05a79f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147787780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1147787780
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2658939950
Short name T607
Test name
Test status
Simulation time 356569124 ps
CPU time 1.94 seconds
Started May 05 01:56:37 PM PDT 24
Finished May 05 01:56:39 PM PDT 24
Peak memory 216380 kb
Host smart-2f12e240-dafc-4eaa-8624-2435994f4988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658939950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2658939950
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.413216600
Short name T445
Test name
Test status
Simulation time 132325126 ps
CPU time 1 seconds
Started May 05 01:56:42 PM PDT 24
Finished May 05 01:56:43 PM PDT 24
Peak memory 205776 kb
Host smart-e47068f1-b9ec-4af9-a156-655ef7cc7b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413216600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.413216600
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2192764293
Short name T56
Test name
Test status
Simulation time 466432797 ps
CPU time 5.44 seconds
Started May 05 01:56:31 PM PDT 24
Finished May 05 01:56:37 PM PDT 24
Peak memory 234556 kb
Host smart-1ab80b41-994b-433c-a65f-908dac3f6185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192764293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2192764293
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1849649343
Short name T643
Test name
Test status
Simulation time 14230536 ps
CPU time 0.74 seconds
Started May 05 01:56:41 PM PDT 24
Finished May 05 01:56:42 PM PDT 24
Peak memory 205344 kb
Host smart-d70d2d18-6c9c-4cc5-a590-28ff54b2378a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849649343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1849649343
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2277864714
Short name T515
Test name
Test status
Simulation time 16731528 ps
CPU time 0.72 seconds
Started May 05 01:56:38 PM PDT 24
Finished May 05 01:56:39 PM PDT 24
Peak memory 205588 kb
Host smart-b3375138-225d-4f34-8265-65143976efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277864714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2277864714
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.96045417
Short name T295
Test name
Test status
Simulation time 17957533585 ps
CPU time 139.21 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:58:54 PM PDT 24
Peak memory 249176 kb
Host smart-ef1ecd57-068a-409c-8392-d9f8b476707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96045417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.96045417
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2830990320
Short name T71
Test name
Test status
Simulation time 3523086336 ps
CPU time 14.67 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 237624 kb
Host smart-b1b09839-ced7-41a2-b500-bbe2e389faed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830990320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2830990320
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.359375412
Short name T110
Test name
Test status
Simulation time 387038622 ps
CPU time 4.4 seconds
Started May 05 01:56:29 PM PDT 24
Finished May 05 01:56:34 PM PDT 24
Peak memory 219148 kb
Host smart-06ac3b7d-f1db-4122-b9f9-934ed34cb1dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=359375412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.359375412
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.967426165
Short name T463
Test name
Test status
Simulation time 1169621993 ps
CPU time 1.62 seconds
Started May 05 01:56:37 PM PDT 24
Finished May 05 01:56:39 PM PDT 24
Peak memory 207856 kb
Host smart-c5075bf4-decf-4fc7-afeb-bd3201a7b9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967426165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.967426165
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3582755434
Short name T55
Test name
Test status
Simulation time 221626017 ps
CPU time 6.42 seconds
Started May 05 01:56:29 PM PDT 24
Finished May 05 01:56:35 PM PDT 24
Peak memory 216336 kb
Host smart-132dec29-0af2-4ce9-a45b-26babf1eb0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582755434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3582755434
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.332615673
Short name T175
Test name
Test status
Simulation time 84874952 ps
CPU time 0.94 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 205820 kb
Host smart-b06a035b-4ebe-4003-ba7c-4d58fdfb0c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332615673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.332615673
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4111468109
Short name T654
Test name
Test status
Simulation time 12310693 ps
CPU time 0.7 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:49 PM PDT 24
Peak memory 204804 kb
Host smart-9d6d0398-e59a-4b4a-96a3-87bf3a618893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111468109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4111468109
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1181647857
Short name T616
Test name
Test status
Simulation time 35169986 ps
CPU time 0.74 seconds
Started May 05 01:56:31 PM PDT 24
Finished May 05 01:56:32 PM PDT 24
Peak memory 206640 kb
Host smart-15aef1ae-83c7-4646-a969-408e8a1abb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181647857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1181647857
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1540226108
Short name T367
Test name
Test status
Simulation time 550779082 ps
CPU time 8.41 seconds
Started May 05 01:56:33 PM PDT 24
Finished May 05 01:56:42 PM PDT 24
Peak memory 232688 kb
Host smart-76bbbf45-707a-4607-95c3-59b2af8b8e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540226108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1540226108
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1830552694
Short name T224
Test name
Test status
Simulation time 1773290197 ps
CPU time 10.16 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:56:46 PM PDT 24
Peak memory 218652 kb
Host smart-1a067261-0c76-43b4-99b7-edbcba083997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830552694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1830552694
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2645848580
Short name T484
Test name
Test status
Simulation time 6356580085 ps
CPU time 13.63 seconds
Started May 05 01:56:33 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 220588 kb
Host smart-fca8ce66-ed82-4c93-8b89-9512826eae8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2645848580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2645848580
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3259944685
Short name T449
Test name
Test status
Simulation time 289936832 ps
CPU time 4.06 seconds
Started May 05 01:56:44 PM PDT 24
Finished May 05 01:56:48 PM PDT 24
Peak memory 217792 kb
Host smart-c7ed9465-9889-451b-b2b3-1826e631e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259944685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3259944685
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3303006823
Short name T422
Test name
Test status
Simulation time 20485400714 ps
CPU time 16.54 seconds
Started May 05 01:56:34 PM PDT 24
Finished May 05 01:56:51 PM PDT 24
Peak memory 216372 kb
Host smart-9d16ddc0-9aaf-4670-b39f-2babe2b4c58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303006823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3303006823
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3264471917
Short name T588
Test name
Test status
Simulation time 102826758 ps
CPU time 3.45 seconds
Started May 05 01:56:41 PM PDT 24
Finished May 05 01:56:45 PM PDT 24
Peak memory 216316 kb
Host smart-f17f32bd-15f6-4c1f-8e61-e3c5577087b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264471917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3264471917
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4108791474
Short name T478
Test name
Test status
Simulation time 536484520 ps
CPU time 0.88 seconds
Started May 05 01:56:40 PM PDT 24
Finished May 05 01:56:41 PM PDT 24
Peak memory 206004 kb
Host smart-e02ba4a8-0084-4c12-a68a-072c9ab18f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108791474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4108791474
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3248319197
Short name T270
Test name
Test status
Simulation time 1708627525 ps
CPU time 3.94 seconds
Started May 05 01:56:33 PM PDT 24
Finished May 05 01:56:37 PM PDT 24
Peak memory 224316 kb
Host smart-8cfe8621-87c9-4776-9023-d66c3c490d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248319197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3248319197
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3793871759
Short name T548
Test name
Test status
Simulation time 43233248 ps
CPU time 0.75 seconds
Started May 05 01:56:34 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 205440 kb
Host smart-de2bd2cc-26dc-4e4e-9569-70e58443bd73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793871759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3793871759
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3850536839
Short name T555
Test name
Test status
Simulation time 41093722 ps
CPU time 0.82 seconds
Started May 05 01:56:37 PM PDT 24
Finished May 05 01:56:39 PM PDT 24
Peak memory 206660 kb
Host smart-97b54d12-e71f-44ba-b32a-ffce42e64001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850536839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3850536839
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.557949694
Short name T629
Test name
Test status
Simulation time 7643375279 ps
CPU time 98.12 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:58:26 PM PDT 24
Peak memory 249188 kb
Host smart-65a194cd-c467-492a-bf31-4c3ddde592f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557949694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.557949694
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3824022039
Short name T356
Test name
Test status
Simulation time 7518162561 ps
CPU time 10.05 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:56:45 PM PDT 24
Peak memory 216944 kb
Host smart-66442600-5146-40c4-bede-3df2a4b8bd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824022039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3824022039
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1176520847
Short name T450
Test name
Test status
Simulation time 578667649 ps
CPU time 5.1 seconds
Started May 05 01:56:39 PM PDT 24
Finished May 05 01:56:44 PM PDT 24
Peak memory 223100 kb
Host smart-6fefa6f3-802d-41bc-8b12-a9d382ac76f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1176520847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1176520847
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1193978310
Short name T384
Test name
Test status
Simulation time 36374200122 ps
CPU time 45.85 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:57:34 PM PDT 24
Peak memory 216304 kb
Host smart-a9ce276b-05b1-40db-853e-49160337ff5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193978310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1193978310
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1279584153
Short name T518
Test name
Test status
Simulation time 12101948494 ps
CPU time 17.74 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:57:07 PM PDT 24
Peak memory 216296 kb
Host smart-7ac62eeb-c22d-41eb-9110-9e6d6c09ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279584153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1279584153
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1762958840
Short name T508
Test name
Test status
Simulation time 196097897 ps
CPU time 5.28 seconds
Started May 05 01:56:44 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 216300 kb
Host smart-2029dc37-497b-4857-97ca-8cbe7cb51897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762958840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1762958840
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2546489676
Short name T506
Test name
Test status
Simulation time 373852078 ps
CPU time 0.79 seconds
Started May 05 01:56:35 PM PDT 24
Finished May 05 01:56:36 PM PDT 24
Peak memory 205776 kb
Host smart-adab0226-5bb0-48db-994b-14be27c64362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546489676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2546489676
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.439544931
Short name T567
Test name
Test status
Simulation time 11219294 ps
CPU time 0.7 seconds
Started May 05 01:56:00 PM PDT 24
Finished May 05 01:56:01 PM PDT 24
Peak memory 205384 kb
Host smart-e6c7ebe7-24f6-4ce7-baf3-074e1bb74b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439544931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.439544931
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3251546695
Short name T96
Test name
Test status
Simulation time 2737820977 ps
CPU time 13.76 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 218788 kb
Host smart-c794dd1e-6e85-44dd-a875-87acb12c390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251546695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3251546695
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2679187555
Short name T419
Test name
Test status
Simulation time 85660500 ps
CPU time 0.78 seconds
Started May 05 01:55:57 PM PDT 24
Finished May 05 01:55:58 PM PDT 24
Peak memory 205660 kb
Host smart-0bf2883e-aa8d-4fa4-9be0-021b77dc8101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679187555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2679187555
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1400397869
Short name T705
Test name
Test status
Simulation time 18708134257 ps
CPU time 143.53 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:58:15 PM PDT 24
Peak memory 238412 kb
Host smart-555c5eea-05c2-4749-824b-57f922e5551f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400397869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1400397869
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1553077469
Short name T684
Test name
Test status
Simulation time 3459871582 ps
CPU time 14.41 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:56:07 PM PDT 24
Peak memory 218860 kb
Host smart-7aac624d-aab0-4fb5-bdae-91cf36ee1e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553077469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1553077469
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.590347727
Short name T124
Test name
Test status
Simulation time 20379727117 ps
CPU time 55.29 seconds
Started May 05 01:55:49 PM PDT 24
Finished May 05 01:56:45 PM PDT 24
Peak memory 221172 kb
Host smart-36abc16f-4be9-4e23-8728-7c7056d0ab14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590347727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.590347727
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2202631502
Short name T13
Test name
Test status
Simulation time 355094127 ps
CPU time 5.63 seconds
Started May 05 01:55:49 PM PDT 24
Finished May 05 01:55:55 PM PDT 24
Peak memory 220124 kb
Host smart-0ac7b1e2-eac6-4178-b31a-df429083545e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2202631502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2202631502
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2289797450
Short name T49
Test name
Test status
Simulation time 346758852 ps
CPU time 1.14 seconds
Started May 05 01:55:46 PM PDT 24
Finished May 05 01:55:53 PM PDT 24
Peak memory 235124 kb
Host smart-0132d0c6-9e78-4f45-854d-8d4bf40913ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289797450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2289797450
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2870882686
Short name T360
Test name
Test status
Simulation time 87875928 ps
CPU time 1.14 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:01 PM PDT 24
Peak memory 207156 kb
Host smart-cd0fdc3b-1acf-440e-9e70-003376884ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870882686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2870882686
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2484329389
Short name T387
Test name
Test status
Simulation time 4088310098 ps
CPU time 6.42 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:55:58 PM PDT 24
Peak memory 216312 kb
Host smart-fd3a053f-8d42-4e2d-8997-3ee22c316e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484329389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2484329389
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.349814816
Short name T602
Test name
Test status
Simulation time 2186497714 ps
CPU time 3.96 seconds
Started May 05 01:55:50 PM PDT 24
Finished May 05 01:55:55 PM PDT 24
Peak memory 216256 kb
Host smart-89238305-7ee9-4bf9-add1-30efabede686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349814816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.349814816
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2751219992
Short name T406
Test name
Test status
Simulation time 17749685 ps
CPU time 0.81 seconds
Started May 05 01:55:46 PM PDT 24
Finished May 05 01:55:48 PM PDT 24
Peak memory 205804 kb
Host smart-bbe38d43-6ba1-49df-94cd-6c243b2a7848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751219992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2751219992
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4171375846
Short name T109
Test name
Test status
Simulation time 39325887 ps
CPU time 0.89 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 205788 kb
Host smart-e8839ebd-419d-48b7-8031-0f00667b4505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171375846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4171375846
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1823622256
Short name T468
Test name
Test status
Simulation time 43918850 ps
CPU time 0.7 seconds
Started May 05 01:56:43 PM PDT 24
Finished May 05 01:56:44 PM PDT 24
Peak memory 205648 kb
Host smart-03165d35-bbbf-47c8-abe2-1254e9ad3242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823622256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1823622256
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3270922309
Short name T580
Test name
Test status
Simulation time 26332397 ps
CPU time 0.78 seconds
Started May 05 01:56:38 PM PDT 24
Finished May 05 01:56:39 PM PDT 24
Peak memory 206708 kb
Host smart-e233fd86-f728-4afa-bc80-8a6342678d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270922309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3270922309
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1892270554
Short name T590
Test name
Test status
Simulation time 4093583208 ps
CPU time 25.98 seconds
Started May 05 01:56:50 PM PDT 24
Finished May 05 01:57:17 PM PDT 24
Peak memory 233924 kb
Host smart-4d882d70-3e21-4181-953b-1c40e78b9102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892270554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1892270554
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1232556997
Short name T54
Test name
Test status
Simulation time 490079057 ps
CPU time 3.11 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:52 PM PDT 24
Peak memory 222380 kb
Host smart-b5cc4ad1-0425-4813-9ab5-7e7e1ee93689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232556997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1232556997
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1291752726
Short name T720
Test name
Test status
Simulation time 507542134 ps
CPU time 3.33 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:51 PM PDT 24
Peak memory 219060 kb
Host smart-8b7e5fa5-26ea-479a-b0b6-d9e79a416387
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1291752726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1291752726
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1720313344
Short name T104
Test name
Test status
Simulation time 12369027531 ps
CPU time 28.35 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:57:14 PM PDT 24
Peak memory 216308 kb
Host smart-bc8ac1d9-5008-4484-90f9-4e97410c42e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720313344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1720313344
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3057044161
Short name T414
Test name
Test status
Simulation time 768847415 ps
CPU time 2.21 seconds
Started May 05 01:56:41 PM PDT 24
Finished May 05 01:56:43 PM PDT 24
Peak memory 216216 kb
Host smart-546f518c-824c-480a-9b1d-f5768cf8b6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057044161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3057044161
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.554636206
Short name T647
Test name
Test status
Simulation time 243136772 ps
CPU time 5.37 seconds
Started May 05 01:56:44 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 216292 kb
Host smart-878b8870-04df-4ae4-b981-95e719fb0990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554636206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.554636206
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.54904237
Short name T514
Test name
Test status
Simulation time 74851064 ps
CPU time 0.78 seconds
Started May 05 01:56:42 PM PDT 24
Finished May 05 01:56:44 PM PDT 24
Peak memory 205808 kb
Host smart-c33144b6-dec7-45b5-91d6-6c7fbf2229ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54904237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.54904237
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3690412637
Short name T675
Test name
Test status
Simulation time 9330165595 ps
CPU time 31.27 seconds
Started May 05 01:56:50 PM PDT 24
Finished May 05 01:57:22 PM PDT 24
Peak memory 238568 kb
Host smart-dfa1ab8c-f781-43c4-8f2d-f35516733f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690412637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3690412637
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.298789658
Short name T655
Test name
Test status
Simulation time 13269807 ps
CPU time 0.74 seconds
Started May 05 01:56:52 PM PDT 24
Finished May 05 01:56:53 PM PDT 24
Peak memory 205404 kb
Host smart-4b8fdc3f-df43-4687-95d8-b8bdd3a49cf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298789658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.298789658
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.979022836
Short name T597
Test name
Test status
Simulation time 37003274 ps
CPU time 0.78 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:56:48 PM PDT 24
Peak memory 206672 kb
Host smart-f4540d8d-2ec1-49dc-8def-5f6196507855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979022836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.979022836
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2045660724
Short name T504
Test name
Test status
Simulation time 941548868 ps
CPU time 21.42 seconds
Started May 05 01:56:50 PM PDT 24
Finished May 05 01:57:12 PM PDT 24
Peak memory 240788 kb
Host smart-5ba8c274-e318-4c6b-af6d-745ae19eaae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045660724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2045660724
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.346099879
Short name T180
Test name
Test status
Simulation time 547189462 ps
CPU time 7.61 seconds
Started May 05 01:56:42 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 219164 kb
Host smart-1b2f1462-66df-4ff5-b7d8-c79b5a5de4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346099879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.346099879
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2982202164
Short name T620
Test name
Test status
Simulation time 4347652727 ps
CPU time 22.66 seconds
Started May 05 01:56:36 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 228192 kb
Host smart-7367ff37-c973-4b9e-ba0b-03ebd3cf97b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982202164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2982202164
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1411597194
Short name T493
Test name
Test status
Simulation time 670761691 ps
CPU time 3.72 seconds
Started May 05 01:56:50 PM PDT 24
Finished May 05 01:56:54 PM PDT 24
Peak memory 220596 kb
Host smart-8bfa3707-270e-4fc7-9f92-c9232ccf508b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1411597194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1411597194
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.562742842
Short name T390
Test name
Test status
Simulation time 5593181762 ps
CPU time 32.88 seconds
Started May 05 01:56:43 PM PDT 24
Finished May 05 01:57:17 PM PDT 24
Peak memory 216320 kb
Host smart-971738b1-d88d-4659-9cd5-fbf545740e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562742842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.562742842
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1811403016
Short name T628
Test name
Test status
Simulation time 40112357305 ps
CPU time 19.06 seconds
Started May 05 01:56:36 PM PDT 24
Finished May 05 01:56:56 PM PDT 24
Peak memory 216328 kb
Host smart-fc832b64-544a-432a-b05a-f5f795a0599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811403016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1811403016
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1388850889
Short name T476
Test name
Test status
Simulation time 276175465 ps
CPU time 2.52 seconds
Started May 05 01:56:49 PM PDT 24
Finished May 05 01:56:52 PM PDT 24
Peak memory 216256 kb
Host smart-7f802866-ca3f-422a-93a1-c2f91425d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388850889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1388850889
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.927050854
Short name T439
Test name
Test status
Simulation time 97224258 ps
CPU time 0.8 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 205764 kb
Host smart-19db5a36-382c-456c-88ce-7dcabf0a6ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927050854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.927050854
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.921778077
Short name T451
Test name
Test status
Simulation time 11154246 ps
CPU time 0.73 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 205708 kb
Host smart-fb4f87f5-63fc-4f2c-a529-1a24da3a4b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921778077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.921778077
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3896583010
Short name T540
Test name
Test status
Simulation time 43116162 ps
CPU time 0.77 seconds
Started May 05 01:56:41 PM PDT 24
Finished May 05 01:56:43 PM PDT 24
Peak memory 205968 kb
Host smart-cd64caea-ba2b-4226-821f-8a082846e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896583010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3896583010
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3924435678
Short name T466
Test name
Test status
Simulation time 118162951681 ps
CPU time 117.52 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:58:46 PM PDT 24
Peak memory 249096 kb
Host smart-bc7c913f-fb52-45c8-8ecd-cde8dfef4f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924435678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3924435678
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3229867800
Short name T9
Test name
Test status
Simulation time 1314075276 ps
CPU time 9.41 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 234844 kb
Host smart-5c6701fd-e6d6-43d5-8cd8-de85982a617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229867800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3229867800
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2451512072
Short name T453
Test name
Test status
Simulation time 597499794 ps
CPU time 8.44 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:57 PM PDT 24
Peak memory 222508 kb
Host smart-038b1f86-5b9c-4573-9a0f-d43145fee195
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2451512072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2451512072
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1048223593
Short name T396
Test name
Test status
Simulation time 6734902627 ps
CPU time 13.1 seconds
Started May 05 01:56:38 PM PDT 24
Finished May 05 01:56:51 PM PDT 24
Peak memory 216076 kb
Host smart-68d45aa4-c055-43a7-9191-99c33c12d8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048223593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1048223593
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.377753660
Short name T689
Test name
Test status
Simulation time 3980891994 ps
CPU time 6.05 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 216288 kb
Host smart-70a80c0e-bdbf-448c-b1df-9f4473e595d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377753660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.377753660
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3799854464
Short name T605
Test name
Test status
Simulation time 1572610761 ps
CPU time 11.01 seconds
Started May 05 01:56:40 PM PDT 24
Finished May 05 01:56:51 PM PDT 24
Peak memory 216268 kb
Host smart-45a8ff5a-2dce-4300-a894-c78e61eed446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799854464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3799854464
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2779299733
Short name T108
Test name
Test status
Simulation time 75919974 ps
CPU time 0.83 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:56:46 PM PDT 24
Peak memory 205780 kb
Host smart-b679dc50-97b4-4ac2-80b5-f46789b544fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779299733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2779299733
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2093788780
Short name T642
Test name
Test status
Simulation time 31174696 ps
CPU time 0.69 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:48 PM PDT 24
Peak memory 205404 kb
Host smart-c3aeef22-6c2b-4f9c-b2d1-c35c681ad046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093788780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2093788780
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.479830131
Short name T318
Test name
Test status
Simulation time 5887644935 ps
CPU time 13.7 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:57:02 PM PDT 24
Peak memory 224200 kb
Host smart-9c7e98e1-87b3-4aea-aeb5-560a869ae0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479830131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.479830131
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1888183892
Short name T59
Test name
Test status
Simulation time 26768732 ps
CPU time 0.8 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 206680 kb
Host smart-1ec62989-828c-4da2-b18b-ae28f7c4866a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888183892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1888183892
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3487003142
Short name T310
Test name
Test status
Simulation time 1809413959 ps
CPU time 30.13 seconds
Started May 05 01:56:51 PM PDT 24
Finished May 05 01:57:21 PM PDT 24
Peak memory 232716 kb
Host smart-c157d76a-a65a-4891-9087-bd636c66c384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487003142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3487003142
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2497605344
Short name T437
Test name
Test status
Simulation time 3164459498 ps
CPU time 30.32 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:57:16 PM PDT 24
Peak memory 232688 kb
Host smart-813cf6e1-4a30-4331-ab6a-b63b10c1fa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497605344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2497605344
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.637058817
Short name T501
Test name
Test status
Simulation time 4678972867 ps
CPU time 8.07 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:56 PM PDT 24
Peak memory 222528 kb
Host smart-d685c041-69f0-4570-aaa4-8f059dc90c0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=637058817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.637058817
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1498842900
Short name T626
Test name
Test status
Simulation time 16094347673 ps
CPU time 37.53 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 216328 kb
Host smart-f99e27eb-2a5e-4f83-af31-0dc5330ca1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498842900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1498842900
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2802157115
Short name T447
Test name
Test status
Simulation time 6784957537 ps
CPU time 20.37 seconds
Started May 05 01:56:42 PM PDT 24
Finished May 05 01:57:03 PM PDT 24
Peak memory 216316 kb
Host smart-688c59bf-694a-4159-9205-6a3f41390eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802157115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2802157115
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3517550402
Short name T614
Test name
Test status
Simulation time 20362147 ps
CPU time 0.94 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:49 PM PDT 24
Peak memory 206872 kb
Host smart-87d63913-9f41-4e41-b7ef-c1d9a91d1b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517550402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3517550402
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3453725647
Short name T475
Test name
Test status
Simulation time 190735938 ps
CPU time 0.88 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:56:48 PM PDT 24
Peak memory 206820 kb
Host smart-cfa9532e-e202-431d-b028-389dee370019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453725647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3453725647
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1012555382
Short name T574
Test name
Test status
Simulation time 177695891 ps
CPU time 0.69 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 204816 kb
Host smart-8ba0c283-4106-4413-b0b1-b1f0be193e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012555382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1012555382
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.62532251
Short name T177
Test name
Test status
Simulation time 22085770 ps
CPU time 0.77 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 206620 kb
Host smart-4f0d0676-f1b4-4550-a48c-2a2dd7350ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62532251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.62532251
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3259536619
Short name T44
Test name
Test status
Simulation time 2956830255 ps
CPU time 6.41 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:54 PM PDT 24
Peak memory 218900 kb
Host smart-8e818452-49ae-43f6-8106-3c846ced33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259536619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3259536619
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3282057606
Short name T359
Test name
Test status
Simulation time 627552745 ps
CPU time 7.07 seconds
Started May 05 01:56:44 PM PDT 24
Finished May 05 01:56:52 PM PDT 24
Peak memory 218700 kb
Host smart-8d65053c-6396-4b65-b5b8-0e7228fc8170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282057606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3282057606
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4266365894
Short name T91
Test name
Test status
Simulation time 188422028 ps
CPU time 4.45 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:56:52 PM PDT 24
Peak memory 222420 kb
Host smart-e54c9fa8-524d-46c6-a62d-0786073de992
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4266365894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4266365894
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1829147655
Short name T100
Test name
Test status
Simulation time 8436292282 ps
CPU time 49.01 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:57:37 PM PDT 24
Peak memory 216316 kb
Host smart-870b12f6-831f-4e8c-b4a2-a68584e497e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829147655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1829147655
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2265986399
Short name T692
Test name
Test status
Simulation time 2789624342 ps
CPU time 6.32 seconds
Started May 05 01:56:50 PM PDT 24
Finished May 05 01:56:57 PM PDT 24
Peak memory 215420 kb
Host smart-b1d5eba2-7053-4f25-a65d-bcab340674d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265986399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2265986399
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2626038198
Short name T649
Test name
Test status
Simulation time 154568320 ps
CPU time 1.19 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 207032 kb
Host smart-e777aa77-2bbf-4768-a827-7875d7cf9d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626038198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2626038198
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2432188707
Short name T678
Test name
Test status
Simulation time 98469226 ps
CPU time 0.78 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 205776 kb
Host smart-303a07a0-3e3c-44dc-a2b3-291d7b92500b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432188707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2432188707
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3854443862
Short name T679
Test name
Test status
Simulation time 75449022 ps
CPU time 0.71 seconds
Started May 05 01:56:53 PM PDT 24
Finished May 05 01:56:54 PM PDT 24
Peak memory 205500 kb
Host smart-df093eb7-d2dd-4372-bf97-9e558ccdf9d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854443862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3854443862
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2795064265
Short name T582
Test name
Test status
Simulation time 1182588906 ps
CPU time 16.71 seconds
Started May 05 01:56:55 PM PDT 24
Finished May 05 01:57:12 PM PDT 24
Peak memory 218712 kb
Host smart-2a8385e3-3f52-4db9-a3c2-9fa52944405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795064265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2795064265
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1575658334
Short name T524
Test name
Test status
Simulation time 109027967 ps
CPU time 0.75 seconds
Started May 05 01:56:45 PM PDT 24
Finished May 05 01:56:47 PM PDT 24
Peak memory 206756 kb
Host smart-fd482ac4-2a85-4bc8-acfc-dae09161e3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575658334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1575658334
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1748462463
Short name T343
Test name
Test status
Simulation time 4267314584 ps
CPU time 16.15 seconds
Started May 05 01:56:59 PM PDT 24
Finished May 05 01:57:15 PM PDT 24
Peak memory 240276 kb
Host smart-762f50ff-93f0-44ac-85fe-b2a0c6beb323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748462463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1748462463
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2078027046
Short name T206
Test name
Test status
Simulation time 67092030877 ps
CPU time 35.49 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:57:22 PM PDT 24
Peak memory 226816 kb
Host smart-b3d1839e-4742-47f7-a307-6c929e2d3f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078027046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2078027046
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3773181762
Short name T625
Test name
Test status
Simulation time 3046132272 ps
CPU time 9.28 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:07 PM PDT 24
Peak memory 222384 kb
Host smart-c167d2cf-fd0b-4882-b132-decb168c7594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3773181762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3773181762
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1325794826
Short name T591
Test name
Test status
Simulation time 2349619497 ps
CPU time 12.78 seconds
Started May 05 01:56:46 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 216304 kb
Host smart-05e6c33f-0305-40f8-a521-27cfb85b18f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325794826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1325794826
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.757372759
Short name T594
Test name
Test status
Simulation time 42613115398 ps
CPU time 34.56 seconds
Started May 05 01:56:47 PM PDT 24
Finished May 05 01:57:22 PM PDT 24
Peak memory 217564 kb
Host smart-69908b81-6910-4e48-bed8-9d410d99ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757372759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.757372759
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3496498866
Short name T561
Test name
Test status
Simulation time 289403981 ps
CPU time 9.68 seconds
Started May 05 01:56:48 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 216408 kb
Host smart-bb15e991-c7cd-40be-94d2-29487e049ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496498866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3496498866
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.582104244
Short name T499
Test name
Test status
Simulation time 70131394 ps
CPU time 0.92 seconds
Started May 05 01:56:49 PM PDT 24
Finished May 05 01:56:50 PM PDT 24
Peak memory 206516 kb
Host smart-dc2a96ca-5d7d-4b35-9588-52db2e170dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582104244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.582104244
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3266878012
Short name T25
Test name
Test status
Simulation time 48945910 ps
CPU time 2.32 seconds
Started May 05 01:56:51 PM PDT 24
Finished May 05 01:56:54 PM PDT 24
Peak memory 221888 kb
Host smart-806775a7-0c14-422f-b021-000035e91027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266878012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3266878012
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1438697932
Short name T690
Test name
Test status
Simulation time 14558561 ps
CPU time 0.79 seconds
Started May 05 01:57:00 PM PDT 24
Finished May 05 01:57:01 PM PDT 24
Peak memory 204780 kb
Host smart-9fd7d818-5a49-4375-b01e-fc02991b145f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438697932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1438697932
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1104408441
Short name T651
Test name
Test status
Simulation time 27016183 ps
CPU time 0.81 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 206644 kb
Host smart-292955b2-6515-4cb6-bbea-2d1a36f45a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104408441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1104408441
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1342647853
Short name T366
Test name
Test status
Simulation time 8415281041 ps
CPU time 59.91 seconds
Started May 05 01:56:52 PM PDT 24
Finished May 05 01:57:52 PM PDT 24
Peak memory 249064 kb
Host smart-20135c4d-6481-414b-ac84-1c1f02a7d7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342647853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1342647853
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.906195123
Short name T293
Test name
Test status
Simulation time 22514288824 ps
CPU time 7.54 seconds
Started May 05 01:56:54 PM PDT 24
Finished May 05 01:57:02 PM PDT 24
Peak memory 218888 kb
Host smart-652c9368-13b7-4ebd-8a61-1c7bd21baceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906195123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.906195123
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4121585571
Short name T205
Test name
Test status
Simulation time 2374637933 ps
CPU time 9.67 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:08 PM PDT 24
Peak memory 222820 kb
Host smart-aa398779-89da-4ebc-b9f5-af97f696e68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121585571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4121585571
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.863376496
Short name T90
Test name
Test status
Simulation time 471676938 ps
CPU time 5.17 seconds
Started May 05 01:56:56 PM PDT 24
Finished May 05 01:57:01 PM PDT 24
Peak memory 220396 kb
Host smart-9b31311b-3513-4caa-8ecd-86725dd9100f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=863376496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.863376496
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4080531236
Short name T609
Test name
Test status
Simulation time 8901257924 ps
CPU time 32.74 seconds
Started May 05 01:56:59 PM PDT 24
Finished May 05 01:57:32 PM PDT 24
Peak memory 221452 kb
Host smart-b2f26913-a88d-4d0a-898d-1107451a5ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080531236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4080531236
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3520586930
Short name T683
Test name
Test status
Simulation time 34017135205 ps
CPU time 26.07 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:24 PM PDT 24
Peak memory 216380 kb
Host smart-ecbb1b0e-e3ee-4d0d-a136-cc421fa0d9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520586930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3520586930
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1336024528
Short name T532
Test name
Test status
Simulation time 112759430 ps
CPU time 1.58 seconds
Started May 05 01:56:54 PM PDT 24
Finished May 05 01:56:56 PM PDT 24
Peak memory 216096 kb
Host smart-97c8a2bb-28c0-489a-be06-49fbec2349e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336024528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1336024528
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2548350418
Short name T502
Test name
Test status
Simulation time 323786369 ps
CPU time 1 seconds
Started May 05 01:56:55 PM PDT 24
Finished May 05 01:56:57 PM PDT 24
Peak memory 205812 kb
Host smart-15c26876-17df-4422-8e27-c46fdc1960fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548350418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2548350418
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2912315604
Short name T486
Test name
Test status
Simulation time 16076870 ps
CPU time 0.71 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 204828 kb
Host smart-df44f131-87e7-4ece-b83c-6086909f4527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912315604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2912315604
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3477004255
Short name T552
Test name
Test status
Simulation time 94594430 ps
CPU time 3.21 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:01 PM PDT 24
Peak memory 223988 kb
Host smart-9b305819-6507-47df-9e0c-3b6c31872d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477004255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3477004255
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3258184769
Short name T519
Test name
Test status
Simulation time 55960875 ps
CPU time 0.8 seconds
Started May 05 01:56:58 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 206656 kb
Host smart-8721f7c5-9038-4668-a782-001cbb283635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258184769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3258184769
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1761587127
Short name T344
Test name
Test status
Simulation time 3691778932 ps
CPU time 33.15 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:31 PM PDT 24
Peak memory 235008 kb
Host smart-526d0ec2-283e-417b-897b-ccf11a5e6821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761587127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1761587127
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3138105337
Short name T341
Test name
Test status
Simulation time 5494238579 ps
CPU time 10.64 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:08 PM PDT 24
Peak memory 239292 kb
Host smart-c28a017e-bdee-4317-9016-21c4de96b02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138105337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3138105337
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2031377790
Short name T554
Test name
Test status
Simulation time 631683249 ps
CPU time 9.01 seconds
Started May 05 01:57:00 PM PDT 24
Finished May 05 01:57:09 PM PDT 24
Peak memory 221172 kb
Host smart-6ed0b7a0-db11-435e-a0d3-6cf5d7953cdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2031377790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2031377790
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1095612903
Short name T622
Test name
Test status
Simulation time 89046908 ps
CPU time 0.94 seconds
Started May 05 01:56:58 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 206932 kb
Host smart-db7057af-7ab9-45ca-b90d-3478e99fa8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095612903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1095612903
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2508035629
Short name T480
Test name
Test status
Simulation time 3570203491 ps
CPU time 7.29 seconds
Started May 05 01:56:56 PM PDT 24
Finished May 05 01:57:03 PM PDT 24
Peak memory 216400 kb
Host smart-b80c9961-9d72-4fa7-ac86-80cb02617931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508035629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2508035629
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3198128079
Short name T410
Test name
Test status
Simulation time 732118060 ps
CPU time 3.44 seconds
Started May 05 01:56:54 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 215900 kb
Host smart-53cd30cb-5dfa-4d6b-a41a-4d7a1fe0ca78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198128079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3198128079
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3250292201
Short name T636
Test name
Test status
Simulation time 474167155 ps
CPU time 12.08 seconds
Started May 05 01:56:58 PM PDT 24
Finished May 05 01:57:11 PM PDT 24
Peak memory 216296 kb
Host smart-9227f09e-1ed2-42aa-9849-25605b9b6561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250292201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3250292201
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3565414532
Short name T604
Test name
Test status
Simulation time 23582610 ps
CPU time 0.74 seconds
Started May 05 01:56:56 PM PDT 24
Finished May 05 01:56:57 PM PDT 24
Peak memory 205776 kb
Host smart-0e060f0f-6fb9-43d5-bb44-8ae5974a1657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565414532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3565414532
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.336073481
Short name T430
Test name
Test status
Simulation time 42706619 ps
CPU time 0.71 seconds
Started May 05 01:57:00 PM PDT 24
Finished May 05 01:57:01 PM PDT 24
Peak memory 205728 kb
Host smart-58d2a879-d85c-426b-a580-9a78921d0488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336073481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.336073481
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3655636416
Short name T263
Test name
Test status
Simulation time 3601311756 ps
CPU time 25.39 seconds
Started May 05 01:57:09 PM PDT 24
Finished May 05 01:57:35 PM PDT 24
Peak memory 233020 kb
Host smart-111f1efa-f12a-4326-98c7-8061f32240e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655636416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3655636416
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2428905932
Short name T527
Test name
Test status
Simulation time 16839736 ps
CPU time 0.75 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 205684 kb
Host smart-482d0fb0-3b3a-4611-b88c-67e9b47aa144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428905932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2428905932
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2781432149
Short name T429
Test name
Test status
Simulation time 1224444911 ps
CPU time 14.55 seconds
Started May 05 01:57:02 PM PDT 24
Finished May 05 01:57:17 PM PDT 24
Peak memory 240864 kb
Host smart-e32129c3-5980-43b6-8f2f-95f75b001b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781432149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2781432149
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1522494549
Short name T593
Test name
Test status
Simulation time 316646465 ps
CPU time 4.2 seconds
Started May 05 01:57:03 PM PDT 24
Finished May 05 01:57:07 PM PDT 24
Peak memory 223048 kb
Host smart-4230516b-de93-4a53-9737-f0e2c28222ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1522494549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1522494549
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2373216627
Short name T388
Test name
Test status
Simulation time 6699596713 ps
CPU time 37.48 seconds
Started May 05 01:56:57 PM PDT 24
Finished May 05 01:57:35 PM PDT 24
Peak memory 216412 kb
Host smart-3101c104-5b0c-461b-974e-3279ea901cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373216627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2373216627
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3627256492
Short name T487
Test name
Test status
Simulation time 6308980449 ps
CPU time 9.05 seconds
Started May 05 01:56:55 PM PDT 24
Finished May 05 01:57:05 PM PDT 24
Peak memory 216308 kb
Host smart-24e2f9f7-15f8-4c34-bd7d-c4302f5c8d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627256492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3627256492
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3531135685
Short name T575
Test name
Test status
Simulation time 223724786 ps
CPU time 1.85 seconds
Started May 05 01:56:58 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 216308 kb
Host smart-c8603307-c42d-438a-b576-a97eedc91bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531135685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3531135685
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3912971922
Short name T719
Test name
Test status
Simulation time 133232678 ps
CPU time 0.86 seconds
Started May 05 01:56:59 PM PDT 24
Finished May 05 01:57:00 PM PDT 24
Peak memory 205772 kb
Host smart-9b011068-ab6a-42ec-abf8-6194a649d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912971922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3912971922
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.4191064705
Short name T664
Test name
Test status
Simulation time 39867290 ps
CPU time 0.71 seconds
Started May 05 01:57:08 PM PDT 24
Finished May 05 01:57:09 PM PDT 24
Peak memory 204848 kb
Host smart-15c3d0c0-b17b-416f-85c3-54def8a28eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191064705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
4191064705
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.568172249
Short name T464
Test name
Test status
Simulation time 16561906 ps
CPU time 0.8 seconds
Started May 05 01:57:01 PM PDT 24
Finished May 05 01:57:02 PM PDT 24
Peak memory 205612 kb
Host smart-1bfe9e00-1657-4e32-b782-a5f9ae9a9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568172249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.568172249
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.4166236734
Short name T302
Test name
Test status
Simulation time 946664735 ps
CPU time 19.29 seconds
Started May 05 01:57:10 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 250728 kb
Host smart-adc88157-fc3b-4b10-af42-dce518ee8d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166236734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.4166236734
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.694541096
Short name T184
Test name
Test status
Simulation time 2533145746 ps
CPU time 24.29 seconds
Started May 05 01:57:09 PM PDT 24
Finished May 05 01:57:34 PM PDT 24
Peak memory 219092 kb
Host smart-96237ce6-c9f2-47c2-aaec-adc289f63ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694541096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.694541096
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.962830241
Short name T448
Test name
Test status
Simulation time 237716483 ps
CPU time 3.81 seconds
Started May 05 01:57:10 PM PDT 24
Finished May 05 01:57:14 PM PDT 24
Peak memory 218752 kb
Host smart-3d3f1d43-a5be-415a-82a8-924dd7203754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962830241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.962830241
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.815669992
Short name T564
Test name
Test status
Simulation time 3735487958 ps
CPU time 9.27 seconds
Started May 05 01:57:07 PM PDT 24
Finished May 05 01:57:17 PM PDT 24
Peak memory 222552 kb
Host smart-5a9f3a8f-8b2b-4c17-8da7-1ebe1af6d8a1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=815669992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.815669992
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2055367237
Short name T394
Test name
Test status
Simulation time 10439515972 ps
CPU time 16.33 seconds
Started May 05 01:57:10 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 216312 kb
Host smart-f72a39f6-c69b-4b04-a7ab-dfe12c92dee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055367237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2055367237
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3972586136
Short name T61
Test name
Test status
Simulation time 7803935305 ps
CPU time 11.16 seconds
Started May 05 01:57:11 PM PDT 24
Finished May 05 01:57:22 PM PDT 24
Peak memory 216232 kb
Host smart-e28dcd3d-f2e5-43c5-9b23-f0e3fd02897e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972586136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3972586136
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2729289604
Short name T517
Test name
Test status
Simulation time 32765289 ps
CPU time 1.02 seconds
Started May 05 01:57:08 PM PDT 24
Finished May 05 01:57:09 PM PDT 24
Peak memory 207888 kb
Host smart-4ce9ea73-f578-48fc-99f6-8810b976af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729289604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2729289604
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3688444195
Short name T570
Test name
Test status
Simulation time 70562707 ps
CPU time 0.94 seconds
Started May 05 01:57:07 PM PDT 24
Finished May 05 01:57:09 PM PDT 24
Peak memory 206760 kb
Host smart-020aac3f-77f7-4495-b48f-f7c397ffc88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688444195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3688444195
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.891909457
Short name T586
Test name
Test status
Simulation time 19516068 ps
CPU time 0.72 seconds
Started May 05 01:55:49 PM PDT 24
Finished May 05 01:55:50 PM PDT 24
Peak memory 204796 kb
Host smart-84547ef2-9c5a-4053-8a7a-1bf5ed742c29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891909457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.891909457
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2861137984
Short name T557
Test name
Test status
Simulation time 32098539 ps
CPU time 0.77 seconds
Started May 05 01:55:45 PM PDT 24
Finished May 05 01:55:46 PM PDT 24
Peak memory 206684 kb
Host smart-80ce6102-a6fd-45b1-a1f9-1b2a02f59258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861137984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2861137984
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2923339770
Short name T189
Test name
Test status
Simulation time 236786232 ps
CPU time 4.14 seconds
Started May 05 01:56:08 PM PDT 24
Finished May 05 01:56:13 PM PDT 24
Peak memory 218456 kb
Host smart-7879aebb-7bab-4e09-a7f1-25d4bb0fa837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923339770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2923339770
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.831505407
Short name T190
Test name
Test status
Simulation time 11128722237 ps
CPU time 6.89 seconds
Started May 05 01:55:55 PM PDT 24
Finished May 05 01:56:03 PM PDT 24
Peak memory 224488 kb
Host smart-c702e008-a32f-4194-86a8-93c4a6e6c117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831505407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
831505407
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3708027019
Short name T251
Test name
Test status
Simulation time 4632971284 ps
CPU time 7.98 seconds
Started May 05 01:55:56 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 222592 kb
Host smart-4e8c9448-8620-4736-bc4c-b730eeb9eab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708027019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3708027019
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1592190101
Short name T697
Test name
Test status
Simulation time 4355815926 ps
CPU time 13.73 seconds
Started May 05 01:55:55 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 220384 kb
Host smart-2e0c0a91-d89b-49c7-9aa1-140702905f7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1592190101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1592190101
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3202066731
Short name T48
Test name
Test status
Simulation time 340904653 ps
CPU time 1.15 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:55:53 PM PDT 24
Peak memory 235092 kb
Host smart-ed586e3c-9b42-4b4f-a414-affb7bc35e52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202066731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3202066731
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2257994897
Short name T682
Test name
Test status
Simulation time 17863850324 ps
CPU time 31.14 seconds
Started May 05 01:55:48 PM PDT 24
Finished May 05 01:56:19 PM PDT 24
Peak memory 216344 kb
Host smart-c391fa1e-9894-47df-b6d3-df0331e9e3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257994897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2257994897
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3284286407
Short name T529
Test name
Test status
Simulation time 12788450633 ps
CPU time 18.52 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:56:11 PM PDT 24
Peak memory 216440 kb
Host smart-9647e325-f435-4161-92ec-0e095a6bc07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284286407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3284286407
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2817035737
Short name T3
Test name
Test status
Simulation time 200025312 ps
CPU time 1.11 seconds
Started May 05 01:55:57 PM PDT 24
Finished May 05 01:55:59 PM PDT 24
Peak memory 207156 kb
Host smart-90ea9a60-8703-45c5-a62a-c26abd3b937d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817035737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2817035737
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.517702192
Short name T585
Test name
Test status
Simulation time 154874675 ps
CPU time 0.98 seconds
Started May 05 01:55:57 PM PDT 24
Finished May 05 01:55:59 PM PDT 24
Peak memory 205784 kb
Host smart-cc9e42ef-0df3-4e0f-8ba5-f8e7bfcf2adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517702192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.517702192
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2912034541
Short name T474
Test name
Test status
Simulation time 53026283 ps
CPU time 0.72 seconds
Started May 05 01:57:12 PM PDT 24
Finished May 05 01:57:14 PM PDT 24
Peak memory 204800 kb
Host smart-99fc638b-7d8e-469d-900b-6bb6dbc99ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912034541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2912034541
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3113376098
Short name T20
Test name
Test status
Simulation time 156515686 ps
CPU time 0.75 seconds
Started May 05 01:57:08 PM PDT 24
Finished May 05 01:57:09 PM PDT 24
Peak memory 206652 kb
Host smart-975c1723-3635-458f-998c-5421974861bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113376098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3113376098
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.188699449
Short name T709
Test name
Test status
Simulation time 7740192303 ps
CPU time 30.06 seconds
Started May 05 01:57:10 PM PDT 24
Finished May 05 01:57:40 PM PDT 24
Peak memory 249136 kb
Host smart-bc7343ef-2815-496d-bb75-7519ca94dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188699449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.188699449
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3896656457
Short name T254
Test name
Test status
Simulation time 1651598412 ps
CPU time 8.02 seconds
Started May 05 01:57:10 PM PDT 24
Finished May 05 01:57:19 PM PDT 24
Peak memory 217272 kb
Host smart-bc6b06c8-46a9-4bd7-bd3b-9c44c9ff9611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896656457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3896656457
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1915795526
Short name T724
Test name
Test status
Simulation time 16775675067 ps
CPU time 13.02 seconds
Started May 05 01:57:12 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 219192 kb
Host smart-350d852d-8b2b-4108-8e31-9b5911adc557
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1915795526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1915795526
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2579840174
Short name T667
Test name
Test status
Simulation time 4065696750 ps
CPU time 14.15 seconds
Started May 05 01:57:15 PM PDT 24
Finished May 05 01:57:29 PM PDT 24
Peak memory 216280 kb
Host smart-a5df5715-22fc-4f1e-adb0-5c895e5b8d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579840174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2579840174
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.559669182
Short name T418
Test name
Test status
Simulation time 19003836358 ps
CPU time 13.1 seconds
Started May 05 01:57:11 PM PDT 24
Finished May 05 01:57:25 PM PDT 24
Peak memory 217460 kb
Host smart-c9ad8257-9383-408e-aa32-e4972ffd9712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559669182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.559669182
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.558768235
Short name T401
Test name
Test status
Simulation time 1368290368 ps
CPU time 3.73 seconds
Started May 05 01:57:13 PM PDT 24
Finished May 05 01:57:17 PM PDT 24
Peak memory 216324 kb
Host smart-e08677d3-0552-420c-a5c4-ddb2c9246961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558768235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.558768235
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2768046507
Short name T558
Test name
Test status
Simulation time 21204828 ps
CPU time 0.78 seconds
Started May 05 01:57:13 PM PDT 24
Finished May 05 01:57:14 PM PDT 24
Peak memory 205812 kb
Host smart-75cddd75-0805-4b39-ae39-f720416ebfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768046507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2768046507
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1429736563
Short name T202
Test name
Test status
Simulation time 7885158035 ps
CPU time 26.59 seconds
Started May 05 01:57:14 PM PDT 24
Finished May 05 01:57:41 PM PDT 24
Peak memory 227292 kb
Host smart-75e95af6-2e8c-4035-bf41-699bde388eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429736563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1429736563
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3614335393
Short name T178
Test name
Test status
Simulation time 19446279 ps
CPU time 0.67 seconds
Started May 05 01:57:18 PM PDT 24
Finished May 05 01:57:20 PM PDT 24
Peak memory 204796 kb
Host smart-f0b2fce3-dcd9-4fc2-9909-50246602d781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614335393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3614335393
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1731869356
Short name T462
Test name
Test status
Simulation time 14011638 ps
CPU time 0.76 seconds
Started May 05 01:57:13 PM PDT 24
Finished May 05 01:57:14 PM PDT 24
Peak memory 205952 kb
Host smart-bb37cb0c-a7b7-44f8-b3d1-4ebcf409ad6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731869356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1731869356
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2744113019
Short name T82
Test name
Test status
Simulation time 4423166230 ps
CPU time 24.64 seconds
Started May 05 01:57:20 PM PDT 24
Finished May 05 01:57:45 PM PDT 24
Peak memory 252508 kb
Host smart-cb70e8f0-7858-427c-810e-cfac951566cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744113019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2744113019
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1951816655
Short name T246
Test name
Test status
Simulation time 492723482 ps
CPU time 7.42 seconds
Started May 05 01:57:12 PM PDT 24
Finished May 05 01:57:21 PM PDT 24
Peak memory 218836 kb
Host smart-04aa0fc9-02d0-4e74-9e4f-97b331a0641b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951816655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1951816655
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1691424320
Short name T553
Test name
Test status
Simulation time 206867385 ps
CPU time 5.33 seconds
Started May 05 01:57:21 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 222876 kb
Host smart-55603e22-0710-4593-bcd1-bf45121d6184
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1691424320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1691424320
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3364915404
Short name T21
Test name
Test status
Simulation time 156215984 ps
CPU time 1.44 seconds
Started May 05 01:57:15 PM PDT 24
Finished May 05 01:57:16 PM PDT 24
Peak memory 207772 kb
Host smart-4f95e1e6-59f1-4080-9a55-8520ccceb111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364915404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3364915404
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1682650103
Short name T433
Test name
Test status
Simulation time 251799427 ps
CPU time 1.66 seconds
Started May 05 01:57:12 PM PDT 24
Finished May 05 01:57:14 PM PDT 24
Peak memory 216264 kb
Host smart-590ddcf8-92a6-47df-8655-d496dce9175b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682650103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1682650103
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1108664469
Short name T106
Test name
Test status
Simulation time 38281614 ps
CPU time 0.9 seconds
Started May 05 01:57:14 PM PDT 24
Finished May 05 01:57:15 PM PDT 24
Peak memory 205776 kb
Host smart-59d959b5-5ad4-4222-9669-e2a2e98b9db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108664469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1108664469
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3864035224
Short name T644
Test name
Test status
Simulation time 45651062 ps
CPU time 0.73 seconds
Started May 05 01:57:18 PM PDT 24
Finished May 05 01:57:19 PM PDT 24
Peak memory 204812 kb
Host smart-a968ed8a-17c8-4a96-be4a-02b0a7e0d3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864035224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3864035224
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.584844467
Short name T613
Test name
Test status
Simulation time 13666068 ps
CPU time 0.78 seconds
Started May 05 01:57:19 PM PDT 24
Finished May 05 01:57:20 PM PDT 24
Peak memory 206740 kb
Host smart-91108c16-8139-4dd1-8dc8-09900fa3e557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584844467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.584844467
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1569438940
Short name T311
Test name
Test status
Simulation time 630598662 ps
CPU time 9.61 seconds
Started May 05 01:57:20 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 223948 kb
Host smart-6c5b5c0c-585e-42a9-b314-f4419c9c5b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569438940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1569438940
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2290752831
Short name T197
Test name
Test status
Simulation time 21143583480 ps
CPU time 22.04 seconds
Started May 05 01:57:18 PM PDT 24
Finished May 05 01:57:41 PM PDT 24
Peak memory 233848 kb
Host smart-7d07fb37-52ed-40a0-a620-103a3ffa3fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290752831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2290752831
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.134353964
Short name T436
Test name
Test status
Simulation time 623086307 ps
CPU time 4.65 seconds
Started May 05 01:57:23 PM PDT 24
Finished May 05 01:57:28 PM PDT 24
Peak memory 222140 kb
Host smart-a54f7943-3233-48fd-9ed0-10c7f537921b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=134353964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.134353964
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3812442233
Short name T673
Test name
Test status
Simulation time 19853335527 ps
CPU time 33.15 seconds
Started May 05 01:57:23 PM PDT 24
Finished May 05 01:57:56 PM PDT 24
Peak memory 216348 kb
Host smart-277fe5a9-8d88-4ce2-af34-59fae9eb77c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812442233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3812442233
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1382862235
Short name T691
Test name
Test status
Simulation time 462662418 ps
CPU time 2.2 seconds
Started May 05 01:57:17 PM PDT 24
Finished May 05 01:57:20 PM PDT 24
Peak memory 216284 kb
Host smart-ec30ae44-3c54-4840-a456-1b06bbf86479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382862235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1382862235
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1303071349
Short name T509
Test name
Test status
Simulation time 456655147 ps
CPU time 7.63 seconds
Started May 05 01:57:20 PM PDT 24
Finished May 05 01:57:28 PM PDT 24
Peak memory 216508 kb
Host smart-48cc8f14-bfea-46a9-8305-f8c381e89271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303071349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1303071349
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2982874298
Short name T711
Test name
Test status
Simulation time 114741688 ps
CPU time 1.2 seconds
Started May 05 01:57:19 PM PDT 24
Finished May 05 01:57:21 PM PDT 24
Peak memory 206804 kb
Host smart-71d381ce-826c-427a-9a81-d1eb6c8e1751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982874298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2982874298
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.490966566
Short name T494
Test name
Test status
Simulation time 32306636 ps
CPU time 0.71 seconds
Started May 05 01:57:27 PM PDT 24
Finished May 05 01:57:28 PM PDT 24
Peak memory 204840 kb
Host smart-783d84ca-4071-4d10-ad79-2e928fedbf07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490966566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.490966566
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1976349802
Short name T443
Test name
Test status
Simulation time 70589533 ps
CPU time 0.76 seconds
Started May 05 01:57:23 PM PDT 24
Finished May 05 01:57:24 PM PDT 24
Peak memory 206720 kb
Host smart-1ab4d5bc-ac37-4c98-88de-bde3dc07392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976349802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1976349802
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1693450884
Short name T143
Test name
Test status
Simulation time 21142096249 ps
CPU time 47.69 seconds
Started May 05 01:57:21 PM PDT 24
Finished May 05 01:58:09 PM PDT 24
Peak memory 232820 kb
Host smart-a4f4116f-2f91-42bb-a774-4808dabedacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693450884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1693450884
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.4288426484
Short name T455
Test name
Test status
Simulation time 10675047847 ps
CPU time 15.63 seconds
Started May 05 01:57:28 PM PDT 24
Finished May 05 01:57:44 PM PDT 24
Peak memory 230260 kb
Host smart-b7092d03-aab3-4895-a9f3-e3af62a6610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288426484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.4288426484
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3682715330
Short name T269
Test name
Test status
Simulation time 5292910791 ps
CPU time 9.92 seconds
Started May 05 01:57:24 PM PDT 24
Finished May 05 01:57:34 PM PDT 24
Peak memory 234552 kb
Host smart-3bd3c13a-e110-453a-b920-417e326d190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682715330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3682715330
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.830010090
Short name T261
Test name
Test status
Simulation time 251876620 ps
CPU time 2.32 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:32 PM PDT 24
Peak memory 218740 kb
Host smart-40951888-33ab-4576-85cd-79ab6a18591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830010090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.830010090
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.720247886
Short name T712
Test name
Test status
Simulation time 4903363739 ps
CPU time 19.25 seconds
Started May 05 01:57:22 PM PDT 24
Finished May 05 01:57:42 PM PDT 24
Peak memory 220056 kb
Host smart-497662b6-04ca-4d31-9e6e-f4539d59641e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=720247886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.720247886
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1037134608
Short name T386
Test name
Test status
Simulation time 17288077835 ps
CPU time 43.8 seconds
Started May 05 01:57:21 PM PDT 24
Finished May 05 01:58:05 PM PDT 24
Peak memory 216316 kb
Host smart-8fd90451-3033-4716-b45f-54f750ba3121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037134608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1037134608
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3736368932
Short name T495
Test name
Test status
Simulation time 1359074704 ps
CPU time 8.06 seconds
Started May 05 01:57:24 PM PDT 24
Finished May 05 01:57:32 PM PDT 24
Peak memory 216292 kb
Host smart-8ec28de0-1ab5-4e45-b955-71e7e5a182c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736368932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3736368932
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3711175781
Short name T400
Test name
Test status
Simulation time 176362911 ps
CPU time 1.74 seconds
Started May 05 01:57:24 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 216260 kb
Host smart-b060d8d3-e8dc-42e8-a0bb-38ce6ada91e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711175781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3711175781
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3609444149
Short name T412
Test name
Test status
Simulation time 47265195 ps
CPU time 0.8 seconds
Started May 05 01:57:25 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 205784 kb
Host smart-c14e3351-a22a-44f8-be33-23a028173b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609444149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3609444149
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3352901764
Short name T627
Test name
Test status
Simulation time 1448091185 ps
CPU time 4.65 seconds
Started May 05 01:57:24 PM PDT 24
Finished May 05 01:57:29 PM PDT 24
Peak memory 222524 kb
Host smart-1565d339-28a7-4c6f-a280-72d40da5f6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352901764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3352901764
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3142042506
Short name T511
Test name
Test status
Simulation time 95167839 ps
CPU time 0.71 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 205020 kb
Host smart-043315c9-7509-4bbe-ac6b-d62442188e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142042506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3142042506
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.834082457
Short name T661
Test name
Test status
Simulation time 66000718 ps
CPU time 2.22 seconds
Started May 05 01:57:22 PM PDT 24
Finished May 05 01:57:24 PM PDT 24
Peak memory 222612 kb
Host smart-b96db808-e415-4080-91ce-9eb81b2b78bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834082457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.834082457
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.592923523
Short name T403
Test name
Test status
Simulation time 22582319 ps
CPU time 0.78 seconds
Started May 05 01:57:24 PM PDT 24
Finished May 05 01:57:26 PM PDT 24
Peak memory 206684 kb
Host smart-18e27e36-d1ab-4114-8250-560de516c78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592923523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.592923523
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1289188356
Short name T4
Test name
Test status
Simulation time 1917225869 ps
CPU time 20.59 seconds
Started May 05 01:57:23 PM PDT 24
Finished May 05 01:57:44 PM PDT 24
Peak memory 249036 kb
Host smart-5ccf5d08-bd91-4584-bd77-7bd3f85923ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289188356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1289188356
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.316598770
Short name T315
Test name
Test status
Simulation time 187568543 ps
CPU time 3.1 seconds
Started May 05 01:57:27 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 222864 kb
Host smart-b2b1aa26-cad3-4d9b-8292-ea2dcb3c2d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316598770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.316598770
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.502454827
Short name T577
Test name
Test status
Simulation time 161410442783 ps
CPU time 161.45 seconds
Started May 05 01:57:25 PM PDT 24
Finished May 05 02:00:07 PM PDT 24
Peak memory 249144 kb
Host smart-40ce9d8f-0b5f-4482-8d9b-57df14c9aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502454827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.502454827
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3104469936
Short name T331
Test name
Test status
Simulation time 300876318 ps
CPU time 5.58 seconds
Started May 05 01:57:30 PM PDT 24
Finished May 05 01:57:37 PM PDT 24
Peak memory 224268 kb
Host smart-639c2351-d04c-47b8-87c9-6401c0850b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104469936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3104469936
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3267030469
Short name T544
Test name
Test status
Simulation time 171551921 ps
CPU time 4.06 seconds
Started May 05 01:57:26 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 222892 kb
Host smart-e30e07de-5e65-4e66-8d6c-66f64d58aabc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3267030469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3267030469
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2178833108
Short name T382
Test name
Test status
Simulation time 52857506802 ps
CPU time 57.8 seconds
Started May 05 01:57:23 PM PDT 24
Finished May 05 01:58:21 PM PDT 24
Peak memory 216404 kb
Host smart-0926699f-6c10-469b-885a-f1171947f18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178833108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2178833108
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1512809666
Short name T718
Test name
Test status
Simulation time 3445528387 ps
CPU time 3.09 seconds
Started May 05 01:57:23 PM PDT 24
Finished May 05 01:57:27 PM PDT 24
Peak memory 216364 kb
Host smart-8da2b08d-48c0-4f40-bd0b-2f7216943138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512809666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1512809666
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3009345984
Short name T442
Test name
Test status
Simulation time 166435627 ps
CPU time 4.48 seconds
Started May 05 01:57:26 PM PDT 24
Finished May 05 01:57:31 PM PDT 24
Peak memory 216324 kb
Host smart-15f4e66c-6b26-4260-9ad4-ca00cbcd0d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009345984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3009345984
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1448585018
Short name T551
Test name
Test status
Simulation time 284019050 ps
CPU time 0.93 seconds
Started May 05 01:57:23 PM PDT 24
Finished May 05 01:57:25 PM PDT 24
Peak memory 205768 kb
Host smart-47607206-89ad-43c1-80ad-89dc5db8688e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448585018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1448585018
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1481530429
Short name T431
Test name
Test status
Simulation time 11862960 ps
CPU time 0.71 seconds
Started May 05 01:57:32 PM PDT 24
Finished May 05 01:57:33 PM PDT 24
Peak memory 205280 kb
Host smart-56f6fa34-580f-4b89-97c2-64eeae85781b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481530429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1481530429
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4163009819
Short name T274
Test name
Test status
Simulation time 105006427 ps
CPU time 3.4 seconds
Started May 05 01:57:28 PM PDT 24
Finished May 05 01:57:32 PM PDT 24
Peak memory 223072 kb
Host smart-e0800814-cc57-419a-a8fa-a37af37a6d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163009819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4163009819
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1225826249
Short name T560
Test name
Test status
Simulation time 43154845 ps
CPU time 0.75 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 206600 kb
Host smart-55817016-d537-4432-913c-141549b07fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225826249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1225826249
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3294548387
Short name T329
Test name
Test status
Simulation time 17593087371 ps
CPU time 36.13 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:58:06 PM PDT 24
Peak memory 223380 kb
Host smart-785e1f5e-5ef2-48b0-929c-680860c09dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294548387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3294548387
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3651765629
Short name T181
Test name
Test status
Simulation time 4701765948 ps
CPU time 5.42 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:35 PM PDT 24
Peak memory 220184 kb
Host smart-f4ad7d99-d9ea-4117-9af4-0c7aa0d08587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651765629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3651765629
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2571786009
Short name T342
Test name
Test status
Simulation time 245501587 ps
CPU time 2.47 seconds
Started May 05 01:57:30 PM PDT 24
Finished May 05 01:57:33 PM PDT 24
Peak memory 218676 kb
Host smart-f14044d7-5195-4865-9609-3523c6040be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571786009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2571786009
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1438014138
Short name T672
Test name
Test status
Simulation time 369712954 ps
CPU time 4.32 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:34 PM PDT 24
Peak memory 222508 kb
Host smart-459d43f6-8989-4635-9736-01ca74af8e3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1438014138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1438014138
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1610635974
Short name T166
Test name
Test status
Simulation time 58660525 ps
CPU time 1.05 seconds
Started May 05 01:57:32 PM PDT 24
Finished May 05 01:57:34 PM PDT 24
Peak memory 207084 kb
Host smart-c36fdd28-e688-4f5b-b3f9-92da1fd64439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610635974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1610635974
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.792543513
Short name T57
Test name
Test status
Simulation time 13596914211 ps
CPU time 36.98 seconds
Started May 05 01:57:32 PM PDT 24
Finished May 05 01:58:10 PM PDT 24
Peak memory 216272 kb
Host smart-5379e319-3291-4d97-acd3-f2018e331893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792543513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.792543513
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4196079308
Short name T695
Test name
Test status
Simulation time 4852399390 ps
CPU time 5.14 seconds
Started May 05 01:57:27 PM PDT 24
Finished May 05 01:57:33 PM PDT 24
Peak memory 216308 kb
Host smart-5fde392b-e24e-4de2-8276-963a27e5c7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196079308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4196079308
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1256519137
Short name T660
Test name
Test status
Simulation time 97922728 ps
CPU time 2.04 seconds
Started May 05 01:57:31 PM PDT 24
Finished May 05 01:57:33 PM PDT 24
Peak memory 216236 kb
Host smart-d89c77cb-52a2-4bfc-9ee5-c58314b84bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256519137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1256519137
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.662978351
Short name T639
Test name
Test status
Simulation time 67598682 ps
CPU time 0.89 seconds
Started May 05 01:57:27 PM PDT 24
Finished May 05 01:57:28 PM PDT 24
Peak memory 205760 kb
Host smart-117871a7-32d2-4adc-9fac-96717f39cbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662978351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.662978351
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1953709222
Short name T404
Test name
Test status
Simulation time 17453929 ps
CPU time 0.71 seconds
Started May 05 01:57:32 PM PDT 24
Finished May 05 01:57:33 PM PDT 24
Peak memory 205412 kb
Host smart-e7743d47-2734-4241-afe9-4699ec9db81e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953709222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1953709222
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1006036703
Short name T666
Test name
Test status
Simulation time 51554904 ps
CPU time 0.77 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:30 PM PDT 24
Peak memory 206728 kb
Host smart-f684907c-6c75-4a3e-ba93-76f44c9c8047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006036703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1006036703
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1476891413
Short name T523
Test name
Test status
Simulation time 9147404293 ps
CPU time 120.08 seconds
Started May 05 01:57:34 PM PDT 24
Finished May 05 01:59:34 PM PDT 24
Peak memory 240868 kb
Host smart-523096b9-94fd-428a-bbee-25bd65521fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476891413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1476891413
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4253295941
Short name T113
Test name
Test status
Simulation time 619568355 ps
CPU time 5.9 seconds
Started May 05 01:57:31 PM PDT 24
Finished May 05 01:57:37 PM PDT 24
Peak memory 223064 kb
Host smart-6ff5a217-1099-4250-8277-4244077ce924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253295941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4253295941
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2407549571
Short name T321
Test name
Test status
Simulation time 2195861908 ps
CPU time 11.83 seconds
Started May 05 01:57:32 PM PDT 24
Finished May 05 01:57:44 PM PDT 24
Peak memory 220020 kb
Host smart-c293d5ce-5f0b-4e82-b4f5-a59d02d761f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407549571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2407549571
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.250117500
Short name T497
Test name
Test status
Simulation time 540442735 ps
CPU time 8.37 seconds
Started May 05 01:57:33 PM PDT 24
Finished May 05 01:57:42 PM PDT 24
Peak memory 223012 kb
Host smart-8c1de353-4aa0-410e-a363-9ed2853f5a96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=250117500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.250117500
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2278883022
Short name T35
Test name
Test status
Simulation time 44747611 ps
CPU time 0.93 seconds
Started May 05 01:57:34 PM PDT 24
Finished May 05 01:57:36 PM PDT 24
Peak memory 206680 kb
Host smart-79ee7947-dc9b-4709-9225-ecac5a1672b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278883022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2278883022
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1627588458
Short name T623
Test name
Test status
Simulation time 463279076 ps
CPU time 4.91 seconds
Started May 05 01:57:31 PM PDT 24
Finished May 05 01:57:36 PM PDT 24
Peak memory 216344 kb
Host smart-8926fdbe-1c77-45e4-93d2-56867e9509b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627588458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1627588458
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1067211998
Short name T409
Test name
Test status
Simulation time 2407658368 ps
CPU time 8.49 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:38 PM PDT 24
Peak memory 216320 kb
Host smart-8477c22f-d981-42ab-bd65-b30176f7ffd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067211998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1067211998
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.287363505
Short name T669
Test name
Test status
Simulation time 42402109 ps
CPU time 1.04 seconds
Started May 05 01:57:29 PM PDT 24
Finished May 05 01:57:31 PM PDT 24
Peak memory 207896 kb
Host smart-466294fc-21ef-40e1-ad0d-6bad2d1d0278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287363505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.287363505
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.432134669
Short name T559
Test name
Test status
Simulation time 24116990 ps
CPU time 0.76 seconds
Started May 05 01:57:33 PM PDT 24
Finished May 05 01:57:35 PM PDT 24
Peak memory 205760 kb
Host smart-333cf439-34e7-407f-b07c-d12f23c09c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432134669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.432134669
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.227338298
Short name T481
Test name
Test status
Simulation time 32369685 ps
CPU time 0.7 seconds
Started May 05 01:57:34 PM PDT 24
Finished May 05 01:57:36 PM PDT 24
Peak memory 205384 kb
Host smart-496d43b4-2f1e-4e8b-b86e-bda0d7da14e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227338298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.227338298
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.907916922
Short name T218
Test name
Test status
Simulation time 3157693343 ps
CPU time 25.85 seconds
Started May 05 01:57:35 PM PDT 24
Finished May 05 01:58:02 PM PDT 24
Peak memory 232728 kb
Host smart-7796da43-29e0-4f52-bf87-5e6410a39b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907916922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.907916922
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1175914037
Short name T680
Test name
Test status
Simulation time 51793378 ps
CPU time 0.79 seconds
Started May 05 01:57:33 PM PDT 24
Finished May 05 01:57:34 PM PDT 24
Peak memory 206672 kb
Host smart-73681937-55fc-413a-89ec-26e437e516f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175914037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1175914037
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3305948044
Short name T296
Test name
Test status
Simulation time 6880145998 ps
CPU time 52.17 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:58:30 PM PDT 24
Peak memory 252056 kb
Host smart-db61df95-ed68-4726-b448-31a42d4c85ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305948044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3305948044
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1942782077
Short name T525
Test name
Test status
Simulation time 186530962 ps
CPU time 3.28 seconds
Started May 05 01:57:34 PM PDT 24
Finished May 05 01:57:38 PM PDT 24
Peak memory 218808 kb
Host smart-504c09e1-7a36-4b29-baa4-c2c5d7b565db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942782077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1942782077
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2209537451
Short name T330
Test name
Test status
Simulation time 2865795559 ps
CPU time 5.07 seconds
Started May 05 01:57:35 PM PDT 24
Finished May 05 01:57:41 PM PDT 24
Peak memory 216836 kb
Host smart-787732e7-cc67-4061-b043-f73a955d4cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209537451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2209537451
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.597123082
Short name T500
Test name
Test status
Simulation time 2543830341 ps
CPU time 8.64 seconds
Started May 05 01:57:35 PM PDT 24
Finished May 05 01:57:44 PM PDT 24
Peak memory 219052 kb
Host smart-c02fca4b-0b1f-44c9-8342-17e34a439fde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=597123082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.597123082
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2699218950
Short name T65
Test name
Test status
Simulation time 1466864287 ps
CPU time 11.78 seconds
Started May 05 01:57:34 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 216192 kb
Host smart-466496e4-ec79-4d8a-8f6d-b4b9073e9e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699218950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2699218950
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2441884420
Short name T107
Test name
Test status
Simulation time 8068241666 ps
CPU time 5.77 seconds
Started May 05 01:57:34 PM PDT 24
Finished May 05 01:57:40 PM PDT 24
Peak memory 216352 kb
Host smart-8e99a3db-f6e0-41b8-ab47-027407a19655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441884420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2441884420
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1182329570
Short name T440
Test name
Test status
Simulation time 63072084 ps
CPU time 0.96 seconds
Started May 05 01:57:33 PM PDT 24
Finished May 05 01:57:35 PM PDT 24
Peak memory 206788 kb
Host smart-1741b33b-2e04-449b-b740-b45ff96c893c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182329570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1182329570
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1375393132
Short name T490
Test name
Test status
Simulation time 106885853 ps
CPU time 0.99 seconds
Started May 05 01:57:33 PM PDT 24
Finished May 05 01:57:34 PM PDT 24
Peak memory 206808 kb
Host smart-cfc4cdcd-f840-474c-8fa8-756cac597743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375393132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1375393132
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1605057355
Short name T262
Test name
Test status
Simulation time 13179536985 ps
CPU time 21.23 seconds
Started May 05 01:57:31 PM PDT 24
Finished May 05 01:57:53 PM PDT 24
Peak memory 219240 kb
Host smart-6e643d40-e411-4e94-a5c7-6a8ce322c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605057355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1605057355
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.207805042
Short name T458
Test name
Test status
Simulation time 13723233 ps
CPU time 0.69 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:57:39 PM PDT 24
Peak memory 205408 kb
Host smart-7ac52d3a-758d-4caa-bdd7-620a12cfa705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207805042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.207805042
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.742875997
Short name T408
Test name
Test status
Simulation time 61488786 ps
CPU time 0.77 seconds
Started May 05 01:57:30 PM PDT 24
Finished May 05 01:57:31 PM PDT 24
Peak memory 206676 kb
Host smart-17bc08f6-5e68-49fb-b086-0d0611e152d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742875997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.742875997
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.633004692
Short name T539
Test name
Test status
Simulation time 993476597 ps
CPU time 25.67 seconds
Started May 05 01:57:38 PM PDT 24
Finished May 05 01:58:04 PM PDT 24
Peak memory 232616 kb
Host smart-75b9b6d5-832e-46cc-ab83-50eacd687f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633004692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.633004692
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2445187826
Short name T353
Test name
Test status
Simulation time 6074683530 ps
CPU time 8.4 seconds
Started May 05 01:57:38 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 234948 kb
Host smart-4e21d364-1c2e-40f3-acb7-2aa279461b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445187826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2445187826
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.708209053
Short name T277
Test name
Test status
Simulation time 12571234856 ps
CPU time 8.75 seconds
Started May 05 01:57:38 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 218780 kb
Host smart-a9040a79-b16b-4f7c-86c3-6d7e2c88c5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708209053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.708209053
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3613130798
Short name T685
Test name
Test status
Simulation time 260748708 ps
CPU time 5.67 seconds
Started May 05 01:57:39 PM PDT 24
Finished May 05 01:57:45 PM PDT 24
Peak memory 223052 kb
Host smart-1120994a-e7c1-4d88-be38-3330f00c63ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3613130798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3613130798
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2350857433
Short name T686
Test name
Test status
Simulation time 186488761 ps
CPU time 1.01 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:57:39 PM PDT 24
Peak memory 207140 kb
Host smart-904285a9-468e-4e9d-88cd-ab1243365861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350857433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2350857433
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2392882701
Short name T383
Test name
Test status
Simulation time 12291336829 ps
CPU time 31.36 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:58:09 PM PDT 24
Peak memory 216400 kb
Host smart-9030239d-e2b6-46e7-814a-936a404fe218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392882701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2392882701
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.150181303
Short name T416
Test name
Test status
Simulation time 278121892 ps
CPU time 2.88 seconds
Started May 05 01:57:33 PM PDT 24
Finished May 05 01:57:36 PM PDT 24
Peak memory 216264 kb
Host smart-12040452-e61c-4daf-aad4-379cff3b4849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150181303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.150181303
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1651531731
Short name T714
Test name
Test status
Simulation time 165610808 ps
CPU time 2.1 seconds
Started May 05 01:57:38 PM PDT 24
Finished May 05 01:57:41 PM PDT 24
Peak memory 216172 kb
Host smart-324b9f75-cd7f-48ed-a500-7bdd4d470901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651531731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1651531731
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2024579626
Short name T568
Test name
Test status
Simulation time 161797659 ps
CPU time 0.86 seconds
Started May 05 01:57:39 PM PDT 24
Finished May 05 01:57:40 PM PDT 24
Peak memory 205844 kb
Host smart-430d0de1-b913-4470-aec1-9461d1c63548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024579626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2024579626
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3126911809
Short name T723
Test name
Test status
Simulation time 43334156 ps
CPU time 0.72 seconds
Started May 05 01:57:41 PM PDT 24
Finished May 05 01:57:42 PM PDT 24
Peak memory 204844 kb
Host smart-94d682d9-dbbd-4284-b488-03a875b63ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126911809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3126911809
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4288976298
Short name T650
Test name
Test status
Simulation time 173091978 ps
CPU time 0.75 seconds
Started May 05 01:57:42 PM PDT 24
Finished May 05 01:57:43 PM PDT 24
Peak memory 205884 kb
Host smart-f178a8f8-f2ad-4847-a812-e1e4cd597bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288976298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4288976298
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.226580441
Short name T86
Test name
Test status
Simulation time 4299860150 ps
CPU time 37.68 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:58:16 PM PDT 24
Peak memory 224496 kb
Host smart-4d993a19-b595-48f2-b03b-8c5397f8f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226580441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.226580441
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1375749623
Short name T193
Test name
Test status
Simulation time 6197602732 ps
CPU time 7.67 seconds
Started May 05 01:57:39 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 218836 kb
Host smart-98fc238c-9cee-4be8-8a70-0cf363adc7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375749623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1375749623
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4137272869
Short name T228
Test name
Test status
Simulation time 11549729281 ps
CPU time 16.71 seconds
Started May 05 01:57:42 PM PDT 24
Finished May 05 01:57:59 PM PDT 24
Peak memory 232604 kb
Host smart-651f9533-481f-423a-9f7f-bfca38ff7cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137272869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4137272869
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.469623251
Short name T534
Test name
Test status
Simulation time 857917226 ps
CPU time 5.47 seconds
Started May 05 01:57:42 PM PDT 24
Finished May 05 01:57:48 PM PDT 24
Peak memory 222888 kb
Host smart-c8742c6f-2c7d-4c92-b741-c368a4328610
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=469623251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.469623251
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4024215523
Short name T676
Test name
Test status
Simulation time 12402326025 ps
CPU time 26.25 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:58:03 PM PDT 24
Peak memory 216400 kb
Host smart-b86ff3ad-8719-4459-8a04-1e417b2dcdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024215523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4024215523
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2191345892
Short name T702
Test name
Test status
Simulation time 73463064669 ps
CPU time 20.53 seconds
Started May 05 01:57:37 PM PDT 24
Finished May 05 01:57:58 PM PDT 24
Peak memory 216264 kb
Host smart-ecf2e5a8-4dc3-4480-b967-446f7d8e9489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191345892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2191345892
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2382325810
Short name T483
Test name
Test status
Simulation time 64094232 ps
CPU time 1.56 seconds
Started May 05 01:57:36 PM PDT 24
Finished May 05 01:57:38 PM PDT 24
Peak memory 216280 kb
Host smart-da7b8e7d-1dc8-4a3f-9746-0a0370dcfec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382325810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2382325810
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3676928382
Short name T461
Test name
Test status
Simulation time 88358354 ps
CPU time 0.89 seconds
Started May 05 01:57:36 PM PDT 24
Finished May 05 01:57:38 PM PDT 24
Peak memory 205784 kb
Host smart-4ff6800a-c40b-4056-99bb-5cd130aeb4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676928382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3676928382
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.112704669
Short name T213
Test name
Test status
Simulation time 4308721669 ps
CPU time 12.35 seconds
Started May 05 01:57:38 PM PDT 24
Finished May 05 01:57:51 PM PDT 24
Peak memory 238664 kb
Host smart-ddcf8b93-5e7b-41d2-84b1-aa2072d7df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112704669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.112704669
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3592810843
Short name T485
Test name
Test status
Simulation time 15691841 ps
CPU time 0.76 seconds
Started May 05 01:56:08 PM PDT 24
Finished May 05 01:56:10 PM PDT 24
Peak memory 205316 kb
Host smart-7b342a01-032e-44ef-bc75-0196aef9860d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592810843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
592810843
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2838204941
Short name T222
Test name
Test status
Simulation time 1057147145 ps
CPU time 5.56 seconds
Started May 05 01:56:11 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 218628 kb
Host smart-0924d726-bfbb-4b18-9a3d-396468d9e23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838204941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2838204941
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2422303485
Short name T423
Test name
Test status
Simulation time 53533825 ps
CPU time 0.82 seconds
Started May 05 01:55:52 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 206704 kb
Host smart-d595c4fc-be89-4610-957f-30f4f190662e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422303485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2422303485
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3734974588
Short name T309
Test name
Test status
Simulation time 1550901988 ps
CPU time 32.87 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:56:28 PM PDT 24
Peak memory 232712 kb
Host smart-7fa6b93d-398c-4aa9-935c-71b0f599303f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734974588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3734974588
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.429390708
Short name T216
Test name
Test status
Simulation time 284007296 ps
CPU time 3.91 seconds
Started May 05 01:56:05 PM PDT 24
Finished May 05 01:56:10 PM PDT 24
Peak memory 222648 kb
Host smart-e288048a-1062-484c-87f4-36abf62be36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429390708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.429390708
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1831581699
Short name T323
Test name
Test status
Simulation time 80336505 ps
CPU time 2.25 seconds
Started May 05 01:55:51 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 216228 kb
Host smart-7f34cded-c4b9-4048-866d-994eae993918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831581699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1831581699
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2541467511
Short name T587
Test name
Test status
Simulation time 799283600 ps
CPU time 4.68 seconds
Started May 05 01:56:01 PM PDT 24
Finished May 05 01:56:07 PM PDT 24
Peak memory 223032 kb
Host smart-3dc7dca8-64e5-4789-b387-b7e72f305e53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2541467511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2541467511
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1644471229
Short name T50
Test name
Test status
Simulation time 132235084 ps
CPU time 1.04 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:55:55 PM PDT 24
Peak memory 235076 kb
Host smart-6de5f8de-de16-4601-9413-affdb89ae297
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644471229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1644471229
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2048883216
Short name T699
Test name
Test status
Simulation time 921260173 ps
CPU time 9.3 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 219828 kb
Host smart-e8155fee-4831-4665-ba4b-50a33b05d267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048883216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2048883216
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2228515981
Short name T503
Test name
Test status
Simulation time 10193189745 ps
CPU time 14.52 seconds
Started May 05 01:55:55 PM PDT 24
Finished May 05 01:56:10 PM PDT 24
Peak memory 216208 kb
Host smart-f5bacb8a-15b5-447f-a80c-183662ca70cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228515981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2228515981
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2229674793
Short name T15
Test name
Test status
Simulation time 43787519 ps
CPU time 0.84 seconds
Started May 05 01:56:05 PM PDT 24
Finished May 05 01:56:07 PM PDT 24
Peak memory 206592 kb
Host smart-65585560-c8de-43b3-923b-90738a26ff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229674793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2229674793
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1522503207
Short name T584
Test name
Test status
Simulation time 34635152 ps
CPU time 0.8 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 205860 kb
Host smart-a83dd640-f36b-49e1-9079-13c35f3a1988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522503207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1522503207
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.865985621
Short name T543
Test name
Test status
Simulation time 17205805 ps
CPU time 0.71 seconds
Started May 05 01:57:46 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 205756 kb
Host smart-9d7eb8aa-ea72-4f43-9f09-37ad39e454dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865985621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.865985621
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3440761866
Short name T85
Test name
Test status
Simulation time 2022468908 ps
CPU time 4.77 seconds
Started May 05 01:57:43 PM PDT 24
Finished May 05 01:57:48 PM PDT 24
Peak memory 218308 kb
Host smart-15b78c96-6b03-4d9c-a844-dac8ae80933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440761866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3440761866
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2565752987
Short name T17
Test name
Test status
Simulation time 19206616 ps
CPU time 0.8 seconds
Started May 05 01:57:41 PM PDT 24
Finished May 05 01:57:42 PM PDT 24
Peak memory 206624 kb
Host smart-47d4d400-c076-4c8e-b07c-8cc7cab3d7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565752987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2565752987
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1888027749
Short name T663
Test name
Test status
Simulation time 1275304907 ps
CPU time 15.77 seconds
Started May 05 01:57:44 PM PDT 24
Finished May 05 01:58:00 PM PDT 24
Peak memory 223172 kb
Host smart-e611a8f2-dd26-457f-87d8-e0c9595b21f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888027749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1888027749
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3120134112
Short name T236
Test name
Test status
Simulation time 23792998088 ps
CPU time 86.57 seconds
Started May 05 01:57:41 PM PDT 24
Finished May 05 01:59:08 PM PDT 24
Peak memory 238572 kb
Host smart-0a44964e-269e-4521-9fd0-2273f72623b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120134112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3120134112
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3087700020
Short name T238
Test name
Test status
Simulation time 3003929737 ps
CPU time 13.02 seconds
Started May 05 01:57:43 PM PDT 24
Finished May 05 01:57:57 PM PDT 24
Peak memory 232348 kb
Host smart-a61c1cf0-0612-433b-b042-b4aac123e5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087700020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3087700020
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.99653597
Short name T583
Test name
Test status
Simulation time 247735407 ps
CPU time 5.32 seconds
Started May 05 01:57:47 PM PDT 24
Finished May 05 01:57:53 PM PDT 24
Peak memory 222368 kb
Host smart-db43a98f-aad4-400f-9655-77d9c7daf83e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=99653597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direc
t.99653597
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3805703280
Short name T630
Test name
Test status
Simulation time 3610576353 ps
CPU time 9.36 seconds
Started May 05 01:57:44 PM PDT 24
Finished May 05 01:57:53 PM PDT 24
Peak memory 216284 kb
Host smart-d53f58d9-12d5-4bd2-a60a-923362310482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805703280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3805703280
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.664653134
Short name T677
Test name
Test status
Simulation time 1837545960 ps
CPU time 4.63 seconds
Started May 05 01:57:42 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 216256 kb
Host smart-9c51c233-788b-4a14-a063-1388a8545904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664653134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.664653134
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3986921959
Short name T413
Test name
Test status
Simulation time 364321400 ps
CPU time 1.05 seconds
Started May 05 01:57:42 PM PDT 24
Finished May 05 01:57:44 PM PDT 24
Peak memory 206748 kb
Host smart-b56e8643-4a6d-4ebb-ba3c-02a2e4e410f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986921959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3986921959
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1788213729
Short name T454
Test name
Test status
Simulation time 42009213 ps
CPU time 0.75 seconds
Started May 05 01:57:54 PM PDT 24
Finished May 05 01:57:55 PM PDT 24
Peak memory 205448 kb
Host smart-2a533aa4-adee-44b0-9e2b-a42236beecbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788213729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1788213729
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3183551446
Short name T407
Test name
Test status
Simulation time 58352919 ps
CPU time 0.76 seconds
Started May 05 01:57:48 PM PDT 24
Finished May 05 01:57:49 PM PDT 24
Peak memory 205620 kb
Host smart-c869d308-9cdd-440e-9685-4b904a216b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183551446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3183551446
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2579363136
Short name T368
Test name
Test status
Simulation time 880740169 ps
CPU time 20.62 seconds
Started May 05 01:57:46 PM PDT 24
Finished May 05 01:58:07 PM PDT 24
Peak memory 234996 kb
Host smart-6b126a30-3446-4564-826a-d5181eed767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579363136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2579363136
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3658006253
Short name T336
Test name
Test status
Simulation time 3044746823 ps
CPU time 21.74 seconds
Started May 05 01:57:45 PM PDT 24
Finished May 05 01:58:07 PM PDT 24
Peak memory 219576 kb
Host smart-0fb34637-cb5a-4136-aa96-8df6bc715a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658006253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3658006253
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1590587174
Short name T612
Test name
Test status
Simulation time 2723529006 ps
CPU time 12.27 seconds
Started May 05 01:57:57 PM PDT 24
Finished May 05 01:58:09 PM PDT 24
Peak memory 220812 kb
Host smart-f79a9e28-2bcd-4424-adeb-4cd8078a9dd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1590587174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1590587174
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3830657984
Short name T391
Test name
Test status
Simulation time 10197514709 ps
CPU time 23.35 seconds
Started May 05 01:57:48 PM PDT 24
Finished May 05 01:58:12 PM PDT 24
Peak memory 216536 kb
Host smart-f7679275-8a29-4a7b-83b0-25ebfd9a8aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830657984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3830657984
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.835548317
Short name T536
Test name
Test status
Simulation time 165999609 ps
CPU time 1.15 seconds
Started May 05 01:57:46 PM PDT 24
Finished May 05 01:57:48 PM PDT 24
Peak memory 207584 kb
Host smart-95c1e008-2bc4-49d6-9a0d-8373ed91aa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835548317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.835548317
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.639081225
Short name T424
Test name
Test status
Simulation time 61703454 ps
CPU time 0.89 seconds
Started May 05 01:57:46 PM PDT 24
Finished May 05 01:57:47 PM PDT 24
Peak memory 206796 kb
Host smart-ce1d5ad8-7ddc-430a-809f-476853d07ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639081225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.639081225
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3864407338
Short name T492
Test name
Test status
Simulation time 28033112 ps
CPU time 0.8 seconds
Started May 05 01:57:47 PM PDT 24
Finished May 05 01:57:48 PM PDT 24
Peak memory 205760 kb
Host smart-7a0633a0-d1b5-475c-a29f-0a7ec72914cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864407338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3864407338
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2264741420
Short name T30
Test name
Test status
Simulation time 15016953 ps
CPU time 0.74 seconds
Started May 05 01:57:57 PM PDT 24
Finished May 05 01:57:58 PM PDT 24
Peak memory 205324 kb
Host smart-6194fc30-ea18-4b97-bdea-699d7d1ff8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264741420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2264741420
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.201216925
Short name T411
Test name
Test status
Simulation time 66060896 ps
CPU time 0.76 seconds
Started May 05 01:57:52 PM PDT 24
Finished May 05 01:57:53 PM PDT 24
Peak memory 205644 kb
Host smart-929229e4-44ea-40cd-b6a6-bc84363e2006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201216925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.201216925
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3021276083
Short name T306
Test name
Test status
Simulation time 21018462069 ps
CPU time 70.87 seconds
Started May 05 01:57:57 PM PDT 24
Finished May 05 01:59:08 PM PDT 24
Peak memory 249352 kb
Host smart-850c0324-3c3c-420b-9025-33fb0a1779fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021276083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3021276083
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4152515504
Short name T694
Test name
Test status
Simulation time 81593956487 ps
CPU time 77.97 seconds
Started May 05 01:57:52 PM PDT 24
Finished May 05 01:59:11 PM PDT 24
Peak memory 223604 kb
Host smart-d9a22d04-0728-4824-9db1-72e3b4d89ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152515504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4152515504
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2856013278
Short name T327
Test name
Test status
Simulation time 2006636539 ps
CPU time 5.6 seconds
Started May 05 01:57:55 PM PDT 24
Finished May 05 01:58:01 PM PDT 24
Peak memory 233620 kb
Host smart-492a5ee9-1e00-41c3-9fbd-9d9d59e185ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856013278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2856013278
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1658968703
Short name T562
Test name
Test status
Simulation time 835488223 ps
CPU time 9.36 seconds
Started May 05 01:57:50 PM PDT 24
Finished May 05 01:58:00 PM PDT 24
Peak memory 221400 kb
Host smart-7c9a377e-dc13-4181-a138-bb1263e26f27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1658968703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1658968703
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3431938907
Short name T393
Test name
Test status
Simulation time 6591984697 ps
CPU time 14.08 seconds
Started May 05 01:57:50 PM PDT 24
Finished May 05 01:58:05 PM PDT 24
Peak memory 220116 kb
Host smart-33c5880c-4824-4c26-a691-c6f1ee719b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431938907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3431938907
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2952686635
Short name T592
Test name
Test status
Simulation time 6239846049 ps
CPU time 19.42 seconds
Started May 05 01:57:52 PM PDT 24
Finished May 05 01:58:12 PM PDT 24
Peak memory 216312 kb
Host smart-b92b0181-d124-4eae-95fe-d7e71f203815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952686635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2952686635
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1907185466
Short name T434
Test name
Test status
Simulation time 372378961 ps
CPU time 2.57 seconds
Started May 05 01:57:53 PM PDT 24
Finished May 05 01:57:56 PM PDT 24
Peak memory 216224 kb
Host smart-81bbc790-f67b-40e2-875c-9979a3a7c35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907185466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1907185466
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.39196351
Short name T569
Test name
Test status
Simulation time 129141115 ps
CPU time 0.96 seconds
Started May 05 01:57:50 PM PDT 24
Finished May 05 01:57:52 PM PDT 24
Peak memory 206776 kb
Host smart-65333dfb-b120-4d65-833f-b53764068edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39196351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.39196351
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1488509649
Short name T237
Test name
Test status
Simulation time 743383448 ps
CPU time 3.48 seconds
Started May 05 01:57:57 PM PDT 24
Finished May 05 01:58:00 PM PDT 24
Peak memory 222124 kb
Host smart-9a0a5abd-3152-4f48-92ad-de6d6b69e7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488509649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1488509649
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2100045562
Short name T31
Test name
Test status
Simulation time 33649601 ps
CPU time 0.77 seconds
Started May 05 01:58:00 PM PDT 24
Finished May 05 01:58:02 PM PDT 24
Peak memory 204876 kb
Host smart-b9e123af-2ec8-4de3-aab2-3ba6c1c96c5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100045562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2100045562
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2712523962
Short name T646
Test name
Test status
Simulation time 36506662 ps
CPU time 0.79 seconds
Started May 05 01:57:55 PM PDT 24
Finished May 05 01:57:57 PM PDT 24
Peak memory 206688 kb
Host smart-a47c5b63-2470-4747-af84-0075614d48fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712523962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2712523962
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.876564263
Short name T537
Test name
Test status
Simulation time 97064548907 ps
CPU time 249.7 seconds
Started May 05 01:57:55 PM PDT 24
Finished May 05 02:02:06 PM PDT 24
Peak memory 248736 kb
Host smart-66abf937-b4fc-4e67-b0f2-301fe8e1ca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876564263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.876564263
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.514735085
Short name T232
Test name
Test status
Simulation time 240247166 ps
CPU time 5.65 seconds
Started May 05 01:57:55 PM PDT 24
Finished May 05 01:58:02 PM PDT 24
Peak memory 218872 kb
Host smart-d7b09030-dd5a-40f6-9340-7113dfad1ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514735085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.514735085
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1608223833
Short name T520
Test name
Test status
Simulation time 654197026 ps
CPU time 3.71 seconds
Started May 05 01:57:58 PM PDT 24
Finished May 05 01:58:03 PM PDT 24
Peak memory 218956 kb
Host smart-65156512-9a6d-4cea-a35c-a26aafe0bd61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1608223833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1608223833
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3884232714
Short name T99
Test name
Test status
Simulation time 58583023866 ps
CPU time 47.51 seconds
Started May 05 01:57:54 PM PDT 24
Finished May 05 01:58:43 PM PDT 24
Peak memory 216580 kb
Host smart-962447c9-8010-47ed-8337-a1065456a80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884232714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3884232714
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3953517025
Short name T531
Test name
Test status
Simulation time 6149460510 ps
CPU time 20.86 seconds
Started May 05 01:57:54 PM PDT 24
Finished May 05 01:58:16 PM PDT 24
Peak memory 216388 kb
Host smart-96e1ed3a-0651-4f5a-baa2-2f6ab03de0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953517025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3953517025
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1351275462
Short name T572
Test name
Test status
Simulation time 153357993 ps
CPU time 6.32 seconds
Started May 05 01:57:58 PM PDT 24
Finished May 05 01:58:05 PM PDT 24
Peak memory 216248 kb
Host smart-2923057f-9097-4748-b6d9-78e6affd651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351275462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1351275462
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1929215399
Short name T105
Test name
Test status
Simulation time 544531515 ps
CPU time 1.03 seconds
Started May 05 01:57:54 PM PDT 24
Finished May 05 01:57:56 PM PDT 24
Peak memory 206828 kb
Host smart-6bee0cda-a4d0-4d4c-9c99-7ba11d53cad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929215399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1929215399
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.142312813
Short name T29
Test name
Test status
Simulation time 6424737650 ps
CPU time 11.55 seconds
Started May 05 01:57:58 PM PDT 24
Finished May 05 01:58:10 PM PDT 24
Peak memory 237148 kb
Host smart-87d19f8b-e8af-422c-9bb1-871c1e5e7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142312813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.142312813
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.542801555
Short name T601
Test name
Test status
Simulation time 47987918 ps
CPU time 0.71 seconds
Started May 05 01:58:05 PM PDT 24
Finished May 05 01:58:06 PM PDT 24
Peak memory 205412 kb
Host smart-0fa6c3f4-6363-4055-b68c-3494647cb997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542801555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.542801555
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3748842685
Short name T84
Test name
Test status
Simulation time 1143559760 ps
CPU time 4.61 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:07 PM PDT 24
Peak memory 218960 kb
Host smart-74fab356-ca90-43bb-ae30-c9a8a3226695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748842685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3748842685
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3727728129
Short name T473
Test name
Test status
Simulation time 32685183 ps
CPU time 0.72 seconds
Started May 05 01:58:00 PM PDT 24
Finished May 05 01:58:01 PM PDT 24
Peak memory 205636 kb
Host smart-2c42ff25-3ab8-4bb9-8fef-d407c3a7193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727728129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3727728129
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4054351796
Short name T370
Test name
Test status
Simulation time 1412766524 ps
CPU time 14.92 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:17 PM PDT 24
Peak memory 240728 kb
Host smart-8300410c-a54e-4447-847e-5ff7587f0f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054351796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4054351796
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.377292018
Short name T233
Test name
Test status
Simulation time 10200062415 ps
CPU time 32.42 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:34 PM PDT 24
Peak memory 218580 kb
Host smart-ddd4e69d-3f22-4db6-a72c-efcf0ea4c6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377292018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.377292018
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1175729241
Short name T275
Test name
Test status
Simulation time 733522500 ps
CPU time 2.61 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:04 PM PDT 24
Peak memory 221712 kb
Host smart-cdcad6a6-3eea-4464-804e-37621487f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175729241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1175729241
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1663032644
Short name T316
Test name
Test status
Simulation time 978973976 ps
CPU time 7.73 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:10 PM PDT 24
Peak memory 223244 kb
Host smart-aaf1def6-f093-41a7-951b-885c44239070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663032644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1663032644
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1032079539
Short name T446
Test name
Test status
Simulation time 1766180291 ps
CPU time 10.1 seconds
Started May 05 01:58:00 PM PDT 24
Finished May 05 01:58:11 PM PDT 24
Peak memory 222172 kb
Host smart-3bac41b3-4a20-431d-a817-f4d49aec5d86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1032079539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1032079539
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1613594881
Short name T596
Test name
Test status
Simulation time 114427794 ps
CPU time 0.92 seconds
Started May 05 01:58:09 PM PDT 24
Finished May 05 01:58:10 PM PDT 24
Peak memory 205872 kb
Host smart-ba8f29cb-5a53-4596-9d16-80ed30b06588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613594881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1613594881
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2752261801
Short name T395
Test name
Test status
Simulation time 13039050619 ps
CPU time 34.53 seconds
Started May 05 01:58:00 PM PDT 24
Finished May 05 01:58:36 PM PDT 24
Peak memory 216604 kb
Host smart-dae9c437-9ef3-4e82-a75f-cff596c7eee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752261801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2752261801
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1354031789
Short name T715
Test name
Test status
Simulation time 3782414601 ps
CPU time 4.97 seconds
Started May 05 01:58:02 PM PDT 24
Finished May 05 01:58:08 PM PDT 24
Peak memory 216316 kb
Host smart-f3103f5b-ea50-465d-8c56-1da809ec25a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354031789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1354031789
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4209256341
Short name T489
Test name
Test status
Simulation time 132055220 ps
CPU time 1.76 seconds
Started May 05 01:58:01 PM PDT 24
Finished May 05 01:58:04 PM PDT 24
Peak memory 208092 kb
Host smart-ba67383e-6bac-4f9b-ac30-bc99c7db2a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209256341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4209256341
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1694767747
Short name T428
Test name
Test status
Simulation time 303187751 ps
CPU time 1.04 seconds
Started May 05 01:58:02 PM PDT 24
Finished May 05 01:58:04 PM PDT 24
Peak memory 206844 kb
Host smart-79f0b0a3-41d0-4b73-8ddd-7b3b3a817a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694767747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1694767747
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1572713409
Short name T491
Test name
Test status
Simulation time 41079161 ps
CPU time 0.72 seconds
Started May 05 01:58:06 PM PDT 24
Finished May 05 01:58:07 PM PDT 24
Peak memory 204732 kb
Host smart-b04d8147-e066-470c-81d9-9330f8bd3c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572713409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1572713409
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1552708211
Short name T618
Test name
Test status
Simulation time 22521882 ps
CPU time 0.79 seconds
Started May 05 01:58:04 PM PDT 24
Finished May 05 01:58:05 PM PDT 24
Peak memory 206964 kb
Host smart-6a72af87-29ac-4204-99d9-d04a1be7294c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552708211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1552708211
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1587739025
Short name T298
Test name
Test status
Simulation time 2365576965 ps
CPU time 14.08 seconds
Started May 05 01:58:06 PM PDT 24
Finished May 05 01:58:21 PM PDT 24
Peak memory 232764 kb
Host smart-3866aeaf-1691-495e-a195-0146027a19c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587739025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1587739025
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.246203821
Short name T286
Test name
Test status
Simulation time 956728326 ps
CPU time 3.9 seconds
Started May 05 01:58:08 PM PDT 24
Finished May 05 01:58:12 PM PDT 24
Peak memory 222888 kb
Host smart-1f53420a-6260-4216-9817-8b941365f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246203821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.246203821
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2161177221
Short name T111
Test name
Test status
Simulation time 227301754 ps
CPU time 4.14 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:17 PM PDT 24
Peak memory 222568 kb
Host smart-1ec73bd0-8026-4f6f-a91f-1426cde006db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2161177221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2161177221
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1462453527
Short name T563
Test name
Test status
Simulation time 5428393215 ps
CPU time 35.08 seconds
Started May 05 01:58:07 PM PDT 24
Finished May 05 01:58:43 PM PDT 24
Peak memory 216336 kb
Host smart-0f65ea89-1f8a-4752-9bec-93a57be80788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462453527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1462453527
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2629182278
Short name T633
Test name
Test status
Simulation time 388489750 ps
CPU time 2.69 seconds
Started May 05 01:58:09 PM PDT 24
Finished May 05 01:58:12 PM PDT 24
Peak memory 216276 kb
Host smart-0dd4da34-0b06-464c-bffa-f3027ad7b4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629182278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2629182278
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3459628596
Short name T425
Test name
Test status
Simulation time 200457034 ps
CPU time 1.26 seconds
Started May 05 01:58:04 PM PDT 24
Finished May 05 01:58:06 PM PDT 24
Peak memory 216236 kb
Host smart-8b417c45-3ee7-4b4c-a682-2554a1856882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459628596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3459628596
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1512735534
Short name T2
Test name
Test status
Simulation time 172137834 ps
CPU time 0.73 seconds
Started May 05 01:58:06 PM PDT 24
Finished May 05 01:58:08 PM PDT 24
Peak memory 205796 kb
Host smart-9e57f571-3866-413b-a348-42cf59058bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512735534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1512735534
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2664167717
Short name T707
Test name
Test status
Simulation time 869745918 ps
CPU time 7.84 seconds
Started May 05 01:58:08 PM PDT 24
Finished May 05 01:58:16 PM PDT 24
Peak memory 238420 kb
Host smart-3c638c13-8bb1-4655-8348-f0ad4469c481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664167717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2664167717
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1774513409
Short name T432
Test name
Test status
Simulation time 43383430 ps
CPU time 0.74 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:14 PM PDT 24
Peak memory 204860 kb
Host smart-dfe5e06b-e8b5-41fa-adf6-09f97b8cf42e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774513409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1774513409
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2674981455
Short name T23
Test name
Test status
Simulation time 1150282153 ps
CPU time 4.11 seconds
Started May 05 01:58:09 PM PDT 24
Finished May 05 01:58:14 PM PDT 24
Peak memory 218840 kb
Host smart-b66ffe9d-c587-4392-bf88-33a0f4fc084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674981455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2674981455
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3405424778
Short name T688
Test name
Test status
Simulation time 34269718 ps
CPU time 0.77 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:13 PM PDT 24
Peak memory 205696 kb
Host smart-f7c6f5cf-1b00-4797-9dae-fa5cd8cedcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405424778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3405424778
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.89196722
Short name T706
Test name
Test status
Simulation time 2848168670 ps
CPU time 18.47 seconds
Started May 05 01:58:10 PM PDT 24
Finished May 05 01:58:29 PM PDT 24
Peak memory 232884 kb
Host smart-fb4bd5f0-9041-4156-8781-e7d208223d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89196722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.89196722
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1266340330
Short name T88
Test name
Test status
Simulation time 1015557094 ps
CPU time 10.24 seconds
Started May 05 01:58:04 PM PDT 24
Finished May 05 01:58:15 PM PDT 24
Peak memory 216676 kb
Host smart-d66f333c-0565-40b6-a4f4-e2ce6ddfd708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266340330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1266340330
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.890258112
Short name T52
Test name
Test status
Simulation time 77214661673 ps
CPU time 173.95 seconds
Started May 05 01:58:07 PM PDT 24
Finished May 05 02:01:02 PM PDT 24
Peak memory 229640 kb
Host smart-595ff03f-48b8-41ba-92de-b19f4c76e7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890258112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.890258112
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3105515677
Short name T693
Test name
Test status
Simulation time 944447461 ps
CPU time 9.15 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:22 PM PDT 24
Peak memory 221608 kb
Host smart-a933dc34-838d-4f27-a38d-e13d735dc3d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3105515677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3105515677
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.162015894
Short name T550
Test name
Test status
Simulation time 1860943300 ps
CPU time 4.65 seconds
Started May 05 01:58:06 PM PDT 24
Finished May 05 01:58:11 PM PDT 24
Peak memory 216256 kb
Host smart-4a856aad-d2d7-4a84-8dda-e90f07096446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162015894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.162015894
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2222720398
Short name T606
Test name
Test status
Simulation time 401762855 ps
CPU time 1.89 seconds
Started May 05 01:58:05 PM PDT 24
Finished May 05 01:58:07 PM PDT 24
Peak memory 216336 kb
Host smart-7d2de3af-739d-45b6-9578-6b31b99f594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222720398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2222720398
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2470361914
Short name T545
Test name
Test status
Simulation time 13521997 ps
CPU time 0.69 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:13 PM PDT 24
Peak memory 205828 kb
Host smart-1b2ba725-625d-4ba3-b530-904e0cce8337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470361914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2470361914
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.622748608
Short name T280
Test name
Test status
Simulation time 8742184627 ps
CPU time 27.84 seconds
Started May 05 01:58:13 PM PDT 24
Finished May 05 01:58:41 PM PDT 24
Peak memory 236252 kb
Host smart-7ca2ff17-1cb5-4a85-ade5-5721ab99c58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622748608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.622748608
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3904105703
Short name T535
Test name
Test status
Simulation time 12925492 ps
CPU time 0.7 seconds
Started May 05 01:58:16 PM PDT 24
Finished May 05 01:58:17 PM PDT 24
Peak memory 205440 kb
Host smart-0c430095-795e-4956-8993-3deaea8a423d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904105703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3904105703
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.993795395
Short name T58
Test name
Test status
Simulation time 106217227 ps
CPU time 0.72 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:14 PM PDT 24
Peak memory 205636 kb
Host smart-408a9880-5056-4436-bb87-4b3898e15166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993795395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.993795395
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1863841108
Short name T364
Test name
Test status
Simulation time 433047628 ps
CPU time 18.48 seconds
Started May 05 01:58:09 PM PDT 24
Finished May 05 01:58:28 PM PDT 24
Peak memory 248788 kb
Host smart-19ebac83-f70e-4a34-974f-273f9bb7639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863841108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1863841108
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.312428247
Short name T337
Test name
Test status
Simulation time 222263487 ps
CPU time 6 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:19 PM PDT 24
Peak memory 232820 kb
Host smart-4d887f50-f9ab-4976-bb4a-d124062509d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312428247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.312428247
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4177800729
Short name T284
Test name
Test status
Simulation time 5074962445 ps
CPU time 16.01 seconds
Started May 05 01:58:10 PM PDT 24
Finished May 05 01:58:26 PM PDT 24
Peak memory 238156 kb
Host smart-53fdfd2d-9cfb-41f2-a75d-c09999c57f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177800729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4177800729
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1439148071
Short name T496
Test name
Test status
Simulation time 221190991 ps
CPU time 5.49 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:18 PM PDT 24
Peak memory 222188 kb
Host smart-ff86aeac-d50b-4ae6-b460-8a8513530887
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1439148071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1439148071
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.148588998
Short name T42
Test name
Test status
Simulation time 115568035 ps
CPU time 1.19 seconds
Started May 05 01:58:17 PM PDT 24
Finished May 05 01:58:19 PM PDT 24
Peak memory 207272 kb
Host smart-9b3ffb2c-5a46-4afd-94e2-8226f31e4f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148588998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.148588998
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3900116876
Short name T648
Test name
Test status
Simulation time 6347113260 ps
CPU time 24.19 seconds
Started May 05 01:58:10 PM PDT 24
Finished May 05 01:58:35 PM PDT 24
Peak memory 216388 kb
Host smart-e0ccfed3-e801-451e-a373-17f25b814f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900116876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3900116876
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2768793703
Short name T665
Test name
Test status
Simulation time 2517322056 ps
CPU time 11.54 seconds
Started May 05 01:58:11 PM PDT 24
Finished May 05 01:58:23 PM PDT 24
Peak memory 216208 kb
Host smart-ae0cce9e-9d8c-45aa-9e53-ace2e3d5d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768793703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2768793703
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3508568393
Short name T399
Test name
Test status
Simulation time 820227971 ps
CPU time 3.42 seconds
Started May 05 01:58:10 PM PDT 24
Finished May 05 01:58:14 PM PDT 24
Peak memory 216232 kb
Host smart-f45d1757-8fcf-4440-ab08-d3602c98eacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508568393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3508568393
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.190290234
Short name T687
Test name
Test status
Simulation time 40374777 ps
CPU time 0.92 seconds
Started May 05 01:58:11 PM PDT 24
Finished May 05 01:58:12 PM PDT 24
Peak memory 206784 kb
Host smart-1d7ab196-7e4c-4639-a8c8-0f7bb525dcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190290234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.190290234
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2088608777
Short name T287
Test name
Test status
Simulation time 4922638077 ps
CPU time 11.05 seconds
Started May 05 01:58:12 PM PDT 24
Finished May 05 01:58:24 PM PDT 24
Peak memory 233480 kb
Host smart-ed259505-3b36-4c80-8ffe-1a5977f6e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088608777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2088608777
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3679661432
Short name T565
Test name
Test status
Simulation time 23969985 ps
CPU time 0.69 seconds
Started May 05 01:58:15 PM PDT 24
Finished May 05 01:58:16 PM PDT 24
Peak memory 204820 kb
Host smart-a4350e04-571e-4c5c-90ba-0c3c0f33277c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679661432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3679661432
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2152739912
Short name T513
Test name
Test status
Simulation time 36230288 ps
CPU time 0.79 seconds
Started May 05 01:58:16 PM PDT 24
Finished May 05 01:58:17 PM PDT 24
Peak memory 206652 kb
Host smart-3d117a29-3947-4e30-9a69-3ab001a47eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152739912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2152739912
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3617399431
Short name T172
Test name
Test status
Simulation time 847796784 ps
CPU time 19.3 seconds
Started May 05 01:58:17 PM PDT 24
Finished May 05 01:58:36 PM PDT 24
Peak memory 232728 kb
Host smart-05638cb7-787f-45a6-839e-d19aacca4ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617399431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3617399431
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3971923506
Short name T80
Test name
Test status
Simulation time 2738493308 ps
CPU time 8.34 seconds
Started May 05 01:58:16 PM PDT 24
Finished May 05 01:58:25 PM PDT 24
Peak memory 222956 kb
Host smart-a0a8f13d-ab2b-420b-a8cc-eb0da3211ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971923506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3971923506
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1656871203
Short name T258
Test name
Test status
Simulation time 131547231208 ps
CPU time 191.84 seconds
Started May 05 01:58:16 PM PDT 24
Finished May 05 02:01:28 PM PDT 24
Peak memory 245168 kb
Host smart-395ca170-b41d-4903-8a1a-faf164b951b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656871203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1656871203
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2838005580
Short name T241
Test name
Test status
Simulation time 79775379 ps
CPU time 2.4 seconds
Started May 05 01:58:14 PM PDT 24
Finished May 05 01:58:16 PM PDT 24
Peak memory 218880 kb
Host smart-60168bd9-ccd5-432c-8b21-eda8ed2fbaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838005580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2838005580
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2621126787
Short name T479
Test name
Test status
Simulation time 1397898349 ps
CPU time 8.78 seconds
Started May 05 01:58:14 PM PDT 24
Finished May 05 01:58:24 PM PDT 24
Peak memory 222444 kb
Host smart-29375714-b46b-467f-bbfd-b5488a308eec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2621126787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2621126787
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2822147011
Short name T600
Test name
Test status
Simulation time 42470993 ps
CPU time 0.97 seconds
Started May 05 01:58:17 PM PDT 24
Finished May 05 01:58:18 PM PDT 24
Peak memory 207336 kb
Host smart-d8c509fd-73e0-4aea-ad8a-eb07d7b07714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822147011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2822147011
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2595364132
Short name T542
Test name
Test status
Simulation time 2318571062 ps
CPU time 10.72 seconds
Started May 05 01:58:16 PM PDT 24
Finished May 05 01:58:27 PM PDT 24
Peak memory 216324 kb
Host smart-e9158ef4-1a86-4e5c-9cad-eeb95f58110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595364132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2595364132
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2245277291
Short name T420
Test name
Test status
Simulation time 172239599 ps
CPU time 1.33 seconds
Started May 05 01:58:15 PM PDT 24
Finished May 05 01:58:17 PM PDT 24
Peak memory 207840 kb
Host smart-751881cc-4dd2-4d46-b187-85f3e4e72e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245277291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2245277291
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1391244728
Short name T457
Test name
Test status
Simulation time 38004724 ps
CPU time 0.73 seconds
Started May 05 01:58:14 PM PDT 24
Finished May 05 01:58:15 PM PDT 24
Peak memory 205776 kb
Host smart-75fe9a48-da15-4513-bbe6-9d241764b38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391244728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1391244728
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2798932061
Short name T191
Test name
Test status
Simulation time 1408902395 ps
CPU time 5.67 seconds
Started May 05 01:58:14 PM PDT 24
Finished May 05 01:58:20 PM PDT 24
Peak memory 216264 kb
Host smart-53cba37e-1a75-4739-92df-f1d9c72f6ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798932061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2798932061
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.536358994
Short name T717
Test name
Test status
Simulation time 24021821 ps
CPU time 0.75 seconds
Started May 05 01:58:21 PM PDT 24
Finished May 05 01:58:22 PM PDT 24
Peak memory 204796 kb
Host smart-bb466aa1-49c5-4e13-bdbd-132316de8bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536358994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.536358994
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2794117252
Short name T700
Test name
Test status
Simulation time 7739071913 ps
CPU time 32.6 seconds
Started May 05 01:58:21 PM PDT 24
Finished May 05 01:58:54 PM PDT 24
Peak memory 219096 kb
Host smart-a6c13e8e-d1a8-459b-af2e-97e3d7b43410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794117252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2794117252
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.268005933
Short name T621
Test name
Test status
Simulation time 15012735 ps
CPU time 0.76 seconds
Started May 05 01:58:17 PM PDT 24
Finished May 05 01:58:18 PM PDT 24
Peak memory 206636 kb
Host smart-217ab9c8-caf6-49db-be59-c605327f47d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268005933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.268005933
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4106083426
Short name T308
Test name
Test status
Simulation time 945346564 ps
CPU time 18.8 seconds
Started May 05 01:58:21 PM PDT 24
Finished May 05 01:58:40 PM PDT 24
Peak memory 239992 kb
Host smart-cc66cce9-abad-4fac-b2fa-80b3dc0032ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106083426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4106083426
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3761083741
Short name T358
Test name
Test status
Simulation time 3776066344 ps
CPU time 25.33 seconds
Started May 05 01:58:20 PM PDT 24
Finished May 05 01:58:46 PM PDT 24
Peak memory 232744 kb
Host smart-85d5c02f-532f-4296-b39d-a0752fc8933f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761083741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3761083741
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.914208897
Short name T221
Test name
Test status
Simulation time 635194489 ps
CPU time 6.82 seconds
Started May 05 01:58:25 PM PDT 24
Finished May 05 01:58:33 PM PDT 24
Peak memory 220308 kb
Host smart-a5fcfcfa-9f0c-43ce-8397-4388afff0f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914208897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.914208897
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4040490231
Short name T578
Test name
Test status
Simulation time 386501072 ps
CPU time 6.17 seconds
Started May 05 01:58:20 PM PDT 24
Finished May 05 01:58:26 PM PDT 24
Peak memory 222316 kb
Host smart-954638e6-6dbd-49d8-9b0e-b5d388272ee4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4040490231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4040490231
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1394505180
Short name T653
Test name
Test status
Simulation time 9114798826 ps
CPU time 58.72 seconds
Started May 05 01:58:19 PM PDT 24
Finished May 05 01:59:18 PM PDT 24
Peak memory 216284 kb
Host smart-fd4befe3-f3d8-46ec-965d-88b99eb0688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394505180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1394505180
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.64816552
Short name T421
Test name
Test status
Simulation time 4838111676 ps
CPU time 3.63 seconds
Started May 05 01:58:16 PM PDT 24
Finished May 05 01:58:20 PM PDT 24
Peak memory 216220 kb
Host smart-cdb18274-507a-4060-9995-7ec20097d59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64816552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.64816552
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4004788210
Short name T589
Test name
Test status
Simulation time 187452770 ps
CPU time 0.95 seconds
Started May 05 01:58:26 PM PDT 24
Finished May 05 01:58:28 PM PDT 24
Peak memory 206888 kb
Host smart-a3a55768-a627-4d85-9e7b-e0b3aa6f6ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004788210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4004788210
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3231527481
Short name T576
Test name
Test status
Simulation time 158069476 ps
CPU time 0.87 seconds
Started May 05 01:58:26 PM PDT 24
Finished May 05 01:58:27 PM PDT 24
Peak memory 206828 kb
Host smart-fe6b0284-cacc-4e3f-b736-11e00cd8f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231527481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3231527481
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2559936485
Short name T417
Test name
Test status
Simulation time 32373700 ps
CPU time 0.71 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:04 PM PDT 24
Peak memory 205328 kb
Host smart-72fcdbc5-ce98-41bc-8635-43670457c466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559936485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
559936485
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3052740624
Short name T97
Test name
Test status
Simulation time 190685720 ps
CPU time 5.06 seconds
Started May 05 01:55:55 PM PDT 24
Finished May 05 01:56:00 PM PDT 24
Peak memory 218976 kb
Host smart-05eb5162-7e02-445b-b7fc-eda7c0671b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052740624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3052740624
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1434248269
Short name T465
Test name
Test status
Simulation time 41438303 ps
CPU time 0.75 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:55:54 PM PDT 24
Peak memory 205676 kb
Host smart-13fbda33-4b46-4a27-8cb6-b29c05c477ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434248269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1434248269
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.204412573
Short name T369
Test name
Test status
Simulation time 20852601047 ps
CPU time 52.14 seconds
Started May 05 01:56:04 PM PDT 24
Finished May 05 01:56:57 PM PDT 24
Peak memory 249096 kb
Host smart-00252722-04b8-48f2-a071-89cc458e0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204412573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.204412573
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2892426141
Short name T198
Test name
Test status
Simulation time 8579579111 ps
CPU time 57.33 seconds
Started May 05 01:56:06 PM PDT 24
Finished May 05 01:57:04 PM PDT 24
Peak memory 238784 kb
Host smart-7c41b0a6-3fef-4b2c-8ce1-98098298e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892426141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2892426141
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.14746359
Short name T186
Test name
Test status
Simulation time 342773973 ps
CPU time 5.02 seconds
Started May 05 01:55:56 PM PDT 24
Finished May 05 01:56:01 PM PDT 24
Peak memory 223084 kb
Host smart-22b925e7-d221-4083-8b32-56990fb56a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14746359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.14746359
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.465074838
Short name T415
Test name
Test status
Simulation time 417941867 ps
CPU time 4.13 seconds
Started May 05 01:55:58 PM PDT 24
Finished May 05 01:56:04 PM PDT 24
Peak memory 219200 kb
Host smart-c1d0c991-65ce-43a5-9f2c-2bc5cdad7174
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=465074838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.465074838
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1316450917
Short name T471
Test name
Test status
Simulation time 1890929012 ps
CPU time 6.72 seconds
Started May 05 01:55:53 PM PDT 24
Finished May 05 01:56:00 PM PDT 24
Peak memory 216252 kb
Host smart-2241d629-a21a-49aa-b64e-056cb5e16591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316450917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1316450917
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1320372715
Short name T521
Test name
Test status
Simulation time 60464613 ps
CPU time 1.36 seconds
Started May 05 01:55:58 PM PDT 24
Finished May 05 01:56:01 PM PDT 24
Peak memory 216236 kb
Host smart-1b0e4322-ac1a-437a-a636-43f053ae1443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320372715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1320372715
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3361249885
Short name T571
Test name
Test status
Simulation time 62378041 ps
CPU time 0.87 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:55:56 PM PDT 24
Peak memory 205696 kb
Host smart-74c34919-85d8-4e27-a61e-5ed17d392c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361249885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3361249885
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2469104121
Short name T123
Test name
Test status
Simulation time 237994738 ps
CPU time 2.08 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:02 PM PDT 24
Peak memory 218828 kb
Host smart-d89baec0-8165-43af-90c9-62528d3aed46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469104121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2469104121
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3201534956
Short name T658
Test name
Test status
Simulation time 12196740 ps
CPU time 0.73 seconds
Started May 05 01:56:09 PM PDT 24
Finished May 05 01:56:11 PM PDT 24
Peak memory 205804 kb
Host smart-7c395230-9df7-415a-802e-e4dd25fb963c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201534956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
201534956
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3639558811
Short name T595
Test name
Test status
Simulation time 17180154 ps
CPU time 0.79 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 206660 kb
Host smart-f48a7f73-1f1e-4021-9470-c1ac0363e546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639558811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3639558811
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.693344092
Short name T533
Test name
Test status
Simulation time 3922870242 ps
CPU time 48.28 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:48 PM PDT 24
Peak memory 233820 kb
Host smart-c1501163-f499-4c7d-a0bb-14d889a57465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693344092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.693344092
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2044919415
Short name T265
Test name
Test status
Simulation time 1017325915 ps
CPU time 7.75 seconds
Started May 05 01:55:58 PM PDT 24
Finished May 05 01:56:07 PM PDT 24
Peak memory 232296 kb
Host smart-25747298-ae5f-4d9c-923f-f455ad6240a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044919415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2044919415
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3562079192
Short name T226
Test name
Test status
Simulation time 3954441491 ps
CPU time 8.11 seconds
Started May 05 01:55:56 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 222644 kb
Host smart-8efbab92-1a20-4b2a-bc9b-d7ecf405c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562079192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3562079192
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2527929529
Short name T477
Test name
Test status
Simulation time 15111725618 ps
CPU time 18.72 seconds
Started May 05 01:55:54 PM PDT 24
Finished May 05 01:56:14 PM PDT 24
Peak memory 222064 kb
Host smart-83d11900-a29e-4a43-b3d5-ab2f7c79fe59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2527929529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2527929529
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4076794287
Short name T426
Test name
Test status
Simulation time 5779157057 ps
CPU time 19.24 seconds
Started May 05 01:55:56 PM PDT 24
Finished May 05 01:56:16 PM PDT 24
Peak memory 216256 kb
Host smart-616de885-e03b-48e2-9990-9657cc71b047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076794287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4076794287
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1801558245
Short name T617
Test name
Test status
Simulation time 61137720 ps
CPU time 0.91 seconds
Started May 05 01:56:15 PM PDT 24
Finished May 05 01:56:16 PM PDT 24
Peak memory 206552 kb
Host smart-302c5bc8-4079-4b9c-bdf2-f033fde332ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801558245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1801558245
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3015080980
Short name T444
Test name
Test status
Simulation time 248567083 ps
CPU time 0.84 seconds
Started May 05 01:56:08 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 205728 kb
Host smart-f905f386-1cdb-4411-a3b2-f86a39a8876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015080980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3015080980
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2278992911
Short name T704
Test name
Test status
Simulation time 49994143 ps
CPU time 0.69 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:00 PM PDT 24
Peak memory 204768 kb
Host smart-cb185d7e-f27c-4c92-8f53-e428d334289a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278992911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
278992911
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2463580687
Short name T652
Test name
Test status
Simulation time 164216899 ps
CPU time 2.4 seconds
Started May 05 01:56:06 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 222500 kb
Host smart-24ac68ce-f6de-4e7e-af6e-69e4b2c8be19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463580687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2463580687
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1349352380
Short name T634
Test name
Test status
Simulation time 64862428 ps
CPU time 0.77 seconds
Started May 05 01:55:56 PM PDT 24
Finished May 05 01:55:58 PM PDT 24
Peak memory 206688 kb
Host smart-01a11085-97af-493a-9e5b-43025cc46c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349352380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1349352380
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.447539968
Short name T556
Test name
Test status
Simulation time 6482773089 ps
CPU time 55.84 seconds
Started May 05 01:55:58 PM PDT 24
Finished May 05 01:56:55 PM PDT 24
Peak memory 232496 kb
Host smart-7d1b2645-ba42-4556-9120-6af0f55ebb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447539968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.447539968
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3473550941
Short name T363
Test name
Test status
Simulation time 1016648554 ps
CPU time 4.02 seconds
Started May 05 01:55:59 PM PDT 24
Finished May 05 01:56:04 PM PDT 24
Peak memory 218864 kb
Host smart-2a62ee98-646e-4a76-9d50-e1e42fa6f64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473550941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3473550941
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.920734639
Short name T194
Test name
Test status
Simulation time 5617769929 ps
CPU time 59.22 seconds
Started May 05 01:55:57 PM PDT 24
Finished May 05 01:56:57 PM PDT 24
Peak memory 224112 kb
Host smart-92f57ac7-1f96-42f2-acb8-7c5243825b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920734639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.920734639
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4009162950
Short name T209
Test name
Test status
Simulation time 3443271867 ps
CPU time 8.32 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:12 PM PDT 24
Peak memory 224520 kb
Host smart-117aa651-7794-472b-bad6-4d15ffbba195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009162950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4009162950
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2555935869
Short name T161
Test name
Test status
Simulation time 153771622 ps
CPU time 4.05 seconds
Started May 05 01:56:06 PM PDT 24
Finished May 05 01:56:11 PM PDT 24
Peak memory 220440 kb
Host smart-9ddc12b9-5f48-4ade-984b-ed72bb5cd920
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2555935869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2555935869
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2447304620
Short name T392
Test name
Test status
Simulation time 20104473117 ps
CPU time 60.44 seconds
Started May 05 01:56:12 PM PDT 24
Finished May 05 01:57:13 PM PDT 24
Peak memory 216324 kb
Host smart-9d70bd26-f5e9-4eb8-98ce-3716ffdd8256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447304620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2447304620
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4181705050
Short name T452
Test name
Test status
Simulation time 2281665936 ps
CPU time 10.89 seconds
Started May 05 01:56:00 PM PDT 24
Finished May 05 01:56:11 PM PDT 24
Peak memory 216356 kb
Host smart-31f628ab-fb0b-4690-b84b-dac37837dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181705050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4181705050
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3008691538
Short name T708
Test name
Test status
Simulation time 62800029 ps
CPU time 2.16 seconds
Started May 05 01:56:02 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 216200 kb
Host smart-a801b17d-279d-428a-afab-bde387940def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008691538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3008691538
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1406500455
Short name T681
Test name
Test status
Simulation time 215605574 ps
CPU time 0.9 seconds
Started May 05 01:56:04 PM PDT 24
Finished May 05 01:56:06 PM PDT 24
Peak memory 206824 kb
Host smart-e4a01d24-3a7d-46b7-b861-823b80e2deba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406500455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1406500455
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.319331087
Short name T27
Test name
Test status
Simulation time 6399594039 ps
CPU time 22.02 seconds
Started May 05 01:56:08 PM PDT 24
Finished May 05 01:56:31 PM PDT 24
Peak memory 224440 kb
Host smart-cf352615-d342-444f-8d5b-7aa6fb65000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319331087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.319331087
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.550959911
Short name T624
Test name
Test status
Simulation time 14396790 ps
CPU time 0.69 seconds
Started May 05 01:55:58 PM PDT 24
Finished May 05 01:56:00 PM PDT 24
Peak memory 205332 kb
Host smart-1abfbb09-ed45-4f91-9922-217689c4cff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550959911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.550959911
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.359719680
Short name T18
Test name
Test status
Simulation time 70162404 ps
CPU time 0.82 seconds
Started May 05 01:56:00 PM PDT 24
Finished May 05 01:56:02 PM PDT 24
Peak memory 206728 kb
Host smart-91818349-6195-4406-a52a-93cc924bc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359719680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.359719680
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4165509915
Short name T239
Test name
Test status
Simulation time 808339221 ps
CPU time 3.66 seconds
Started May 05 01:56:01 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 219140 kb
Host smart-2f2a3492-b22e-41cf-94dd-951a355e86fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165509915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4165509915
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4010144561
Short name T355
Test name
Test status
Simulation time 5254363967 ps
CPU time 11.06 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:56:26 PM PDT 24
Peak memory 223836 kb
Host smart-cd843d3b-b963-4e12-a216-8e8b2ce98cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010144561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4010144561
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.4137489619
Short name T722
Test name
Test status
Simulation time 1460130121 ps
CPU time 17.88 seconds
Started May 05 01:56:07 PM PDT 24
Finished May 05 01:56:25 PM PDT 24
Peak memory 218764 kb
Host smart-93b43c14-89d6-4aa9-bc87-8b4cbb132b7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4137489619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.4137489619
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.522803926
Short name T101
Test name
Test status
Simulation time 8131834384 ps
CPU time 39.4 seconds
Started May 05 01:56:11 PM PDT 24
Finished May 05 01:56:51 PM PDT 24
Peak memory 216328 kb
Host smart-a053c1c1-7708-4e46-8160-cb551edd4697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522803926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.522803926
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3636562709
Short name T526
Test name
Test status
Simulation time 1656813006 ps
CPU time 5.63 seconds
Started May 05 01:56:07 PM PDT 24
Finished May 05 01:56:14 PM PDT 24
Peak memory 216236 kb
Host smart-cb7e0f8e-a7e7-4482-b94e-ca255bac3ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636562709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3636562709
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2357739128
Short name T701
Test name
Test status
Simulation time 51771261 ps
CPU time 1.55 seconds
Started May 05 01:56:00 PM PDT 24
Finished May 05 01:56:03 PM PDT 24
Peak memory 216320 kb
Host smart-877a3490-f4a0-4562-a0e7-73ce2472f754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357739128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2357739128
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.4030197988
Short name T467
Test name
Test status
Simulation time 63381393 ps
CPU time 0.84 seconds
Started May 05 01:56:08 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 205736 kb
Host smart-ce1116c2-424e-441d-afd1-3853f780f7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030197988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.4030197988
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3649639893
Short name T32
Test name
Test status
Simulation time 17377808 ps
CPU time 0.7 seconds
Started May 05 01:56:07 PM PDT 24
Finished May 05 01:56:09 PM PDT 24
Peak memory 204804 kb
Host smart-ffd37d9c-3e37-4ec5-a41b-9d2507045483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649639893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
649639893
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.379318375
Short name T721
Test name
Test status
Simulation time 22992361 ps
CPU time 0.82 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 206992 kb
Host smart-656ee3e0-9f7f-4ed8-bd41-135fab64cbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379318375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.379318375
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4255521664
Short name T632
Test name
Test status
Simulation time 938452745 ps
CPU time 26.44 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:43 PM PDT 24
Peak memory 265496 kb
Host smart-6a4f7257-733f-42b2-be60-6fcbe857de2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255521664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4255521664
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1244120480
Short name T183
Test name
Test status
Simulation time 10062632873 ps
CPU time 8.48 seconds
Started May 05 01:56:16 PM PDT 24
Finished May 05 01:56:25 PM PDT 24
Peak memory 232680 kb
Host smart-bfd31d2d-b80f-4703-9dfa-6855375b1b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244120480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1244120480
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3657834006
Short name T81
Test name
Test status
Simulation time 11492489945 ps
CPU time 24.01 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:28 PM PDT 24
Peak memory 240220 kb
Host smart-0cff4204-b6b0-4bf1-9abd-97dd7d17189c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657834006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3657834006
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2969043341
Short name T204
Test name
Test status
Simulation time 10388221839 ps
CPU time 8 seconds
Started May 05 01:56:03 PM PDT 24
Finished May 05 01:56:12 PM PDT 24
Peak memory 219936 kb
Host smart-cc0f72a0-a261-46b6-93a8-4a8a4949f2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969043341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2969043341
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.170940493
Short name T566
Test name
Test status
Simulation time 3218703042 ps
CPU time 16.4 seconds
Started May 05 01:56:13 PM PDT 24
Finished May 05 01:56:31 PM PDT 24
Peak memory 222980 kb
Host smart-27fba524-f4e6-4e50-85d6-005b60447a4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170940493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.170940493
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2482358361
Short name T397
Test name
Test status
Simulation time 8531949907 ps
CPU time 45.89 seconds
Started May 05 01:56:14 PM PDT 24
Finished May 05 01:57:01 PM PDT 24
Peak memory 216236 kb
Host smart-49028e7e-c021-4ae2-b02d-779ffb401105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482358361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2482358361
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1737583977
Short name T603
Test name
Test status
Simulation time 1148401602 ps
CPU time 9.4 seconds
Started May 05 01:56:12 PM PDT 24
Finished May 05 01:56:23 PM PDT 24
Peak memory 216288 kb
Host smart-98a89e34-94fd-4688-9ef0-4e3fa7f1c99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737583977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1737583977
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.377560286
Short name T441
Test name
Test status
Simulation time 224584441 ps
CPU time 3 seconds
Started May 05 01:56:13 PM PDT 24
Finished May 05 01:56:17 PM PDT 24
Peak memory 216060 kb
Host smart-8c753487-7d91-4b7f-9039-3dd23d1273b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377560286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.377560286
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4215783722
Short name T573
Test name
Test status
Simulation time 29508387 ps
CPU time 0.81 seconds
Started May 05 01:56:04 PM PDT 24
Finished May 05 01:56:06 PM PDT 24
Peak memory 205792 kb
Host smart-20309532-e360-46e3-add7-afc414695265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215783722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4215783722
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1101731924
Short name T244
Test name
Test status
Simulation time 88701284180 ps
CPU time 51.58 seconds
Started May 05 01:56:01 PM PDT 24
Finished May 05 01:56:58 PM PDT 24
Peak memory 232780 kb
Host smart-785d617b-f971-4327-8791-b89d367d1b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101731924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1101731924
Directory /workspace/9.spi_device_upload/latest
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