Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1532363	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1687027

1

T1

1318

T2

5

T3

2769

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2546662	1			T1	895		T2	1		T3	3711
values[0x0]	335510	1			T1	462		T2	7		T3	437
values[0x1]	337218	1			T1	431		T2	6		T3	460

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1166859	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2052531

1

T1

1413

T2

6

T3

3134

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11772	1			T1	7		T3	8		T5	16
valid_sources[0x01]	10892	1			T1	10		T3	15		T5	21
valid_sources[0x02]	13395	1			T1	7		T3	11		T5	41
valid_sources[0x03]	9879	1			T1	2		T3	13		T5	15
valid_sources[0x04]	11545	1			T1	5		T3	12		T5	14
valid_sources[0x05]	11583	1			T1	5		T3	20		T5	36
valid_sources[0x06]	15562	1			T1	8		T2	7		T3	13
valid_sources[0x07]	11346	1			T1	11		T3	22		T5	21
valid_sources[0x08]	11273	1			T1	4		T3	15		T5	20
valid_sources[0x09]	11685	1			T1	9		T3	10		T5	34
valid_sources[0x0a]	12178	1			T1	3		T3	15		T5	21
valid_sources[0x0b]	10582	1			T1	8		T3	36		T5	17
valid_sources[0x0c]	10358	1			T1	4		T3	14		T5	33
valid_sources[0x0d]	10636	1			T1	1		T3	44		T5	50
valid_sources[0x0e]	13102	1			T1	8		T3	15		T5	35
valid_sources[0x0f]	10012	1			T1	7		T3	13		T5	27
valid_sources[0x10]	10128	1			T1	6		T3	22		T5	35
valid_sources[0x11]	11515	1			T1	3		T3	28		T5	60
valid_sources[0x12]	10145	1			T1	4		T3	23		T5	24
valid_sources[0x13]	11308	1			T1	9		T3	26		T5	33
valid_sources[0x14]	9788	1			T1	6		T3	33		T5	41
valid_sources[0x15]	10037	1			T1	9		T3	17		T12	2
valid_sources[0x16]	11619	1			T1	4		T3	7		T5	46
valid_sources[0x17]	10419	1			T1	11		T3	14		T5	47
valid_sources[0x18]	16053	1			T1	2		T3	9		T5	21
valid_sources[0x19]	10170	1			T1	8		T3	17		T5	5
valid_sources[0x1a]	11381	1			T1	5		T3	23		T5	38
valid_sources[0x1b]	9751	1			T1	10		T3	15		T5	25
valid_sources[0x1c]	14871	1			T1	4		T3	31		T5	12
valid_sources[0x1d]	10763	1			T1	6		T3	21		T5	61
valid_sources[0x1e]	11176	1			T1	5		T3	17		T5	16
valid_sources[0x1f]	9247	1			T1	6		T3	16		T12	1
valid_sources[0x20]	9864	1			T1	7		T3	25		T5	60
valid_sources[0x21]	25319	1			T1	14		T3	15		T5	19
valid_sources[0x22]	9858	1			T1	9		T3	21		T5	41
valid_sources[0x23]	12112	1			T1	6		T3	17		T5	47
valid_sources[0x24]	10143	1			T1	15		T3	13		T5	30
valid_sources[0x25]	9493	1			T1	18		T2	4		T3	29
valid_sources[0x26]	10665	1			T1	7		T3	16		T5	43
valid_sources[0x27]	12012	1			T1	14		T3	15		T5	35
valid_sources[0x28]	10259	1			T1	10		T3	19		T5	19
valid_sources[0x29]	16837	1			T1	5		T3	21		T5	33
valid_sources[0x2a]	14226	1			T1	5		T3	14		T5	27
valid_sources[0x2b]	11891	1			T1	12		T3	9		T5	54
valid_sources[0x2c]	10440	1			T1	7		T3	27		T5	27
valid_sources[0x2d]	11941	1			T1	6		T3	22		T5	18
valid_sources[0x2e]	9946	1			T1	1		T3	12		T5	5
valid_sources[0x2f]	24943	1			T1	5		T3	16		T5	29
valid_sources[0x30]	10983	1			T1	5		T3	12		T5	9
valid_sources[0x31]	9911	1			T1	3		T3	29		T5	17
valid_sources[0x32]	10006	1			T1	6		T3	14		T5	44
valid_sources[0x33]	10090	1			T1	1		T3	24		T5	40
valid_sources[0x34]	10453	1			T1	4		T3	23		T5	12
valid_sources[0x35]	14421	1			T1	4		T3	18		T5	55
valid_sources[0x36]	9659	1			T1	8		T2	2		T3	17
valid_sources[0x37]	10830	1			T1	9		T3	12		T5	36
valid_sources[0x38]	10545	1			T1	14		T3	16		T5	28
valid_sources[0x39]	9847	1			T1	3		T3	15		T5	26
valid_sources[0x3a]	12799	1			T1	4		T3	17		T5	39
valid_sources[0x3b]	11815	1			T1	3		T3	12		T5	51
valid_sources[0x3c]	10988	1			T1	7		T3	20		T5	28
valid_sources[0x3d]	10016	1			T1	6		T3	19		T5	42
valid_sources[0x3e]	10767	1			T1	15		T3	18		T5	28
valid_sources[0x3f]	12430	1			T1	8		T3	16		T5	24
valid_sources[0x40]	11475	1			T1	6		T3	21		T12	1
valid_sources[0x41]	10466	1			T1	6		T3	13		T5	25
valid_sources[0x42]	39454	1			T1	5		T3	22		T5	33
valid_sources[0x43]	14350	1			T1	4		T3	22		T5	53
valid_sources[0x44]	10527	1			T1	7		T3	23		T5	14
valid_sources[0x45]	10391	1			T1	8		T3	16		T5	58
valid_sources[0x46]	10636	1			T1	7		T3	17		T5	42
valid_sources[0x47]	10303	1			T1	4		T3	11		T5	49
valid_sources[0x48]	10116	1			T1	3		T3	25		T5	31
valid_sources[0x49]	14235	1			T1	7		T3	11		T5	21
valid_sources[0x4a]	10432	1			T1	14		T3	15		T5	17
valid_sources[0x4b]	10549	1			T1	7		T3	17		T5	34
valid_sources[0x4c]	18878	1			T1	8		T3	23		T12	1
valid_sources[0x4d]	11023	1			T1	4		T3	17		T5	26
valid_sources[0x4e]	10707	1			T1	3		T3	13		T5	33
valid_sources[0x4f]	10134	1			T1	8		T3	23		T5	32
valid_sources[0x50]	11219	1			T1	8		T3	12		T5	34
valid_sources[0x51]	13783	1			T1	6		T3	10		T5	27
valid_sources[0x52]	11053	1			T1	12		T3	18		T4	451
valid_sources[0x53]	11263	1			T1	6		T3	22		T5	32
valid_sources[0x54]	10465	1			T1	11		T3	12		T5	24
valid_sources[0x55]	10428	1			T1	9		T3	21		T5	31
valid_sources[0x56]	9906	1			T1	6		T3	19		T5	43
valid_sources[0x57]	9684	1			T1	9		T3	14		T5	12
valid_sources[0x58]	10605	1			T1	5		T3	14		T5	14
valid_sources[0x59]	11669	1			T1	8		T3	20		T5	46
valid_sources[0x5a]	22595	1			T1	6		T3	16		T5	46
valid_sources[0x5b]	20822	1			T1	7		T3	23		T5	23
valid_sources[0x5c]	10178	1			T1	9		T3	9		T5	18
valid_sources[0x5d]	10438	1			T1	10		T3	16		T5	85
valid_sources[0x5e]	12182	1			T1	4		T3	15		T5	61
valid_sources[0x5f]	13655	1			T1	12		T3	11		T5	45
valid_sources[0x60]	12106	1			T1	9		T3	12		T5	55
valid_sources[0x61]	11056	1			T1	6		T3	15		T5	35
valid_sources[0x62]	10270	1			T1	10		T3	30		T5	23
valid_sources[0x63]	10487	1			T1	8		T3	8		T5	31
valid_sources[0x64]	10190	1			T1	5		T3	20		T5	62
valid_sources[0x65]	10473	1			T1	3		T3	11		T5	22
valid_sources[0x66]	10518	1			T1	6		T3	25		T5	19
valid_sources[0x67]	24511	1			T1	7		T3	15		T5	29
valid_sources[0x68]	10385	1			T1	5		T3	13		T5	21
valid_sources[0x69]	10841	1			T1	12		T3	20		T12	1
valid_sources[0x6a]	9969	1			T1	9		T3	23		T5	50
valid_sources[0x6b]	13774	1			T1	11		T3	20		T5	52
valid_sources[0x6c]	17532	1			T1	3		T3	24		T5	31
valid_sources[0x6d]	11763	1			T1	8		T3	10		T5	34
valid_sources[0x6e]	12282	1			T1	9		T3	17		T5	15
valid_sources[0x6f]	10561	1			T1	11		T3	12		T5	35
valid_sources[0x70]	11985	1			T1	4		T3	23		T5	21
valid_sources[0x71]	12259	1			T1	11		T3	17		T5	52
valid_sources[0x72]	12972	1			T1	10		T3	30		T12	1
valid_sources[0x73]	11545	1			T1	1		T3	21		T5	23
valid_sources[0x74]	10668	1			T1	7		T3	17		T5	46
valid_sources[0x75]	28910	1			T1	8		T3	14		T5	29
valid_sources[0x76]	10020	1			T1	4		T3	26		T5	32
valid_sources[0x77]	34187	1			T1	5		T3	10		T5	51
valid_sources[0x78]	11290	1			T1	15		T3	20		T5	32
valid_sources[0x79]	14190	1			T1	4		T3	16		T5	9
valid_sources[0x7a]	18928	1			T1	4		T3	19		T5	33
valid_sources[0x7b]	12817	1			T1	4		T3	18		T5	39
valid_sources[0x7c]	11994	1			T1	5		T3	13		T5	31
valid_sources[0x7d]	10642	1			T1	13		T3	18		T5	30
valid_sources[0x7e]	10075	1			T1	7		T3	13		T5	43
valid_sources[0x7f]	11805	1			T1	6		T3	16		T5	29
valid_sources[0x80]	10132	1			T1	6		T3	26		T5	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1077921

1

T1

437

T2

1

T3

1877

values[0x0]

all_enables

biggest_size

307350

1

T1

459

T2

3

T3

436

values[0x1]

all_enables

biggest_size

301756

1

T1

422

T2

1

T3

456