Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1551066

1

T1

470

T2

9

T3

1839

full_word

1688065

1

T1

1318

T2

5

T3

2769

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3238681	1			T1	1788		T2	14		T3	4608
auto[TlIntgErrCmd]	158	1			T34	14		T125	7		T126	11
auto[TlIntgErrData]	153	1			T34	12		T125	8		T126	10
auto[TlIntgErrBoth]	139	1			T34	4		T125	5		T126	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2549754

1

T1

895

T2

1

T3

3711

auto[1]

689377

1

T1

893

T2

13

T3

897

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1471415	1			T1	458		T3	1834		T4	9
auto[TlIntgErrNone]	partial	auto[1]	79227	1			T1	12		T2	9		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	1078151	1			T1	437		T2	1		T3	1877
auto[TlIntgErrNone]	full_word	auto[1]	609888	1			T1	881		T2	4		T3	892
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T34	7		T125	4		T126	4
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T34	5		T125	2		T126	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T164	1		T337	1		T338	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T34	2		T125	1		T126	2
auto[TlIntgErrData]	partial	auto[0]	65	1			T34	7		T125	1		T126	3
auto[TlIntgErrData]	partial	auto[1]	81	1			T34	5		T125	6		T126	6
auto[TlIntgErrData]	full_word	auto[0]	3	1			T125	1		T339	1		T340	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T126	1		T341	1		T342	2
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T34	2		T125	2		T126	3
auto[TlIntgErrBoth]	partial	auto[1]	81	1			T34	2		T125	2		T126	6
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T125	1		T343	1		T344	1