Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3296 |
0 |
0 |
T34 |
29732 |
3 |
0 |
0 |
T35 |
2227 |
10 |
0 |
0 |
T36 |
9423 |
6 |
0 |
0 |
T38 |
16640 |
3 |
0 |
0 |
T118 |
8344 |
45 |
0 |
0 |
T119 |
5667 |
301 |
0 |
0 |
T120 |
5640 |
85 |
0 |
0 |
T126 |
82658 |
5 |
0 |
0 |
T131 |
5629 |
72 |
0 |
0 |
T137 |
11990 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1899 |
0 |
0 |
T36 |
9423 |
2 |
0 |
0 |
T38 |
16640 |
18 |
0 |
0 |
T125 |
63874 |
88 |
0 |
0 |
T144 |
233707 |
358 |
0 |
0 |
T146 |
2324 |
3 |
0 |
0 |
T147 |
10209 |
2 |
0 |
0 |
T156 |
7471 |
58 |
0 |
0 |
T164 |
30167 |
4 |
0 |
0 |
T165 |
37528 |
22 |
0 |
0 |
T166 |
15365 |
58 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1909 |
0 |
0 |
T36 |
9423 |
8 |
0 |
0 |
T38 |
16640 |
25 |
0 |
0 |
T125 |
63874 |
74 |
0 |
0 |
T144 |
233707 |
518 |
0 |
0 |
T146 |
2324 |
3 |
0 |
0 |
T147 |
10209 |
6 |
0 |
0 |
T156 |
7471 |
29 |
0 |
0 |
T164 |
30167 |
37 |
0 |
0 |
T165 |
37528 |
45 |
0 |
0 |
T166 |
15365 |
25 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1976 |
0 |
0 |
T36 |
9423 |
5 |
0 |
0 |
T38 |
16640 |
42 |
0 |
0 |
T125 |
63874 |
107 |
0 |
0 |
T144 |
233707 |
403 |
0 |
0 |
T147 |
10209 |
7 |
0 |
0 |
T156 |
7471 |
12 |
0 |
0 |
T164 |
30167 |
46 |
0 |
0 |
T165 |
37528 |
80 |
0 |
0 |
T166 |
15365 |
19 |
0 |
0 |
T167 |
5329 |
13 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5612 |
0 |
0 |
T36 |
9423 |
127 |
0 |
0 |
T38 |
16640 |
267 |
0 |
0 |
T125 |
63874 |
738 |
0 |
0 |
T144 |
233707 |
398 |
0 |
0 |
T146 |
2324 |
2 |
0 |
0 |
T147 |
10209 |
17 |
0 |
0 |
T156 |
7471 |
7 |
0 |
0 |
T164 |
30167 |
397 |
0 |
0 |
T165 |
37528 |
900 |
0 |
0 |
T166 |
15365 |
69 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5022 |
0 |
0 |
T36 |
9423 |
86 |
0 |
0 |
T38 |
16640 |
271 |
0 |
0 |
T125 |
63874 |
513 |
0 |
0 |
T144 |
233707 |
405 |
0 |
0 |
T146 |
2324 |
4 |
0 |
0 |
T147 |
10209 |
244 |
0 |
0 |
T156 |
7471 |
35 |
0 |
0 |
T164 |
30167 |
196 |
0 |
0 |
T165 |
37528 |
879 |
0 |
0 |
T166 |
15365 |
63 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5226 |
0 |
0 |
T36 |
9423 |
58 |
0 |
0 |
T38 |
16640 |
257 |
0 |
0 |
T125 |
63874 |
782 |
0 |
0 |
T144 |
233707 |
493 |
0 |
0 |
T147 |
10209 |
126 |
0 |
0 |
T156 |
7471 |
24 |
0 |
0 |
T164 |
30167 |
467 |
0 |
0 |
T165 |
37528 |
684 |
0 |
0 |
T166 |
15365 |
49 |
0 |
0 |
T167 |
5329 |
16 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5327 |
0 |
0 |
T38 |
16640 |
32 |
0 |
0 |
T125 |
63874 |
760 |
0 |
0 |
T134 |
16547 |
5 |
0 |
0 |
T144 |
233707 |
415 |
0 |
0 |
T146 |
2324 |
5 |
0 |
0 |
T147 |
10209 |
126 |
0 |
0 |
T156 |
7471 |
14 |
0 |
0 |
T164 |
30167 |
396 |
0 |
0 |
T165 |
37528 |
773 |
0 |
0 |
T166 |
15365 |
68 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5110 |
0 |
0 |
T36 |
9423 |
121 |
0 |
0 |
T38 |
16640 |
188 |
0 |
0 |
T125 |
63874 |
730 |
0 |
0 |
T144 |
233707 |
440 |
0 |
0 |
T146 |
2324 |
8 |
0 |
0 |
T147 |
10209 |
113 |
0 |
0 |
T156 |
7471 |
17 |
0 |
0 |
T164 |
30167 |
143 |
0 |
0 |
T165 |
37528 |
469 |
0 |
0 |
T166 |
15365 |
32 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5787 |
0 |
0 |
T38 |
16640 |
276 |
0 |
0 |
T125 |
63874 |
1147 |
0 |
0 |
T134 |
16547 |
3 |
0 |
0 |
T144 |
233707 |
419 |
0 |
0 |
T147 |
10209 |
243 |
0 |
0 |
T156 |
7471 |
2 |
0 |
0 |
T164 |
30167 |
335 |
0 |
0 |
T165 |
37528 |
889 |
0 |
0 |
T166 |
15365 |
65 |
0 |
0 |
T167 |
5329 |
166 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5373 |
0 |
0 |
T36 |
9423 |
93 |
0 |
0 |
T38 |
16640 |
183 |
0 |
0 |
T125 |
63874 |
987 |
0 |
0 |
T144 |
233707 |
400 |
0 |
0 |
T147 |
10209 |
136 |
0 |
0 |
T156 |
7471 |
14 |
0 |
0 |
T164 |
30167 |
172 |
0 |
0 |
T165 |
37528 |
477 |
0 |
0 |
T166 |
15365 |
62 |
0 |
0 |
T167 |
5329 |
135 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
5842 |
0 |
0 |
T36 |
9423 |
94 |
0 |
0 |
T38 |
16640 |
244 |
0 |
0 |
T125 |
63874 |
1304 |
0 |
0 |
T144 |
233707 |
441 |
0 |
0 |
T147 |
10209 |
9 |
0 |
0 |
T156 |
7471 |
18 |
0 |
0 |
T164 |
30167 |
417 |
0 |
0 |
T165 |
37528 |
475 |
0 |
0 |
T166 |
15365 |
38 |
0 |
0 |
T167 |
5329 |
122 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3215 |
0 |
0 |
T36 |
9423 |
36 |
0 |
0 |
T38 |
16640 |
32 |
0 |
0 |
T125 |
63874 |
386 |
0 |
0 |
T144 |
233707 |
473 |
0 |
0 |
T147 |
10209 |
128 |
0 |
0 |
T156 |
7471 |
4 |
0 |
0 |
T164 |
30167 |
106 |
0 |
0 |
T165 |
37528 |
237 |
0 |
0 |
T166 |
15365 |
18 |
0 |
0 |
T167 |
5329 |
74 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3321 |
0 |
0 |
T36 |
9423 |
16 |
0 |
0 |
T38 |
16640 |
104 |
0 |
0 |
T125 |
63874 |
491 |
0 |
0 |
T135 |
16263 |
4 |
0 |
0 |
T144 |
233707 |
424 |
0 |
0 |
T147 |
10209 |
56 |
0 |
0 |
T164 |
30167 |
122 |
0 |
0 |
T165 |
37528 |
306 |
0 |
0 |
T166 |
15365 |
52 |
0 |
0 |
T167 |
5329 |
65 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3363 |
0 |
0 |
T36 |
9423 |
36 |
0 |
0 |
T38 |
16640 |
171 |
0 |
0 |
T125 |
63874 |
712 |
0 |
0 |
T144 |
233707 |
333 |
0 |
0 |
T147 |
10209 |
119 |
0 |
0 |
T156 |
7471 |
12 |
0 |
0 |
T164 |
30167 |
42 |
0 |
0 |
T165 |
37528 |
361 |
0 |
0 |
T166 |
15365 |
59 |
0 |
0 |
T167 |
5329 |
60 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3195 |
0 |
0 |
T36 |
9423 |
41 |
0 |
0 |
T38 |
16640 |
19 |
0 |
0 |
T125 |
63874 |
464 |
0 |
0 |
T144 |
233707 |
318 |
0 |
0 |
T147 |
10209 |
6 |
0 |
0 |
T156 |
7471 |
7 |
0 |
0 |
T164 |
30167 |
201 |
0 |
0 |
T165 |
37528 |
428 |
0 |
0 |
T166 |
15365 |
38 |
0 |
0 |
T167 |
5329 |
53 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3630 |
0 |
0 |
T36 |
9423 |
30 |
0 |
0 |
T38 |
16640 |
57 |
0 |
0 |
T125 |
63874 |
649 |
0 |
0 |
T144 |
233707 |
418 |
0 |
0 |
T147 |
10209 |
114 |
0 |
0 |
T156 |
7471 |
30 |
0 |
0 |
T164 |
30167 |
190 |
0 |
0 |
T165 |
37528 |
223 |
0 |
0 |
T166 |
15365 |
29 |
0 |
0 |
T167 |
5329 |
20 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3105 |
0 |
0 |
T36 |
9423 |
9 |
0 |
0 |
T38 |
16640 |
171 |
0 |
0 |
T125 |
63874 |
454 |
0 |
0 |
T144 |
233707 |
425 |
0 |
0 |
T147 |
10209 |
56 |
0 |
0 |
T156 |
7471 |
43 |
0 |
0 |
T164 |
30167 |
89 |
0 |
0 |
T165 |
37528 |
236 |
0 |
0 |
T166 |
15365 |
36 |
0 |
0 |
T167 |
5329 |
10 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3140 |
0 |
0 |
T36 |
9423 |
35 |
0 |
0 |
T38 |
16640 |
112 |
0 |
0 |
T125 |
63874 |
272 |
0 |
0 |
T144 |
233707 |
429 |
0 |
0 |
T146 |
2324 |
1 |
0 |
0 |
T147 |
10209 |
94 |
0 |
0 |
T156 |
7471 |
34 |
0 |
0 |
T164 |
30167 |
103 |
0 |
0 |
T165 |
37528 |
328 |
0 |
0 |
T166 |
15365 |
56 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3495 |
0 |
0 |
T36 |
9423 |
36 |
0 |
0 |
T38 |
16640 |
165 |
0 |
0 |
T125 |
63874 |
541 |
0 |
0 |
T144 |
233707 |
483 |
0 |
0 |
T146 |
2324 |
5 |
0 |
0 |
T147 |
10209 |
99 |
0 |
0 |
T156 |
7471 |
24 |
0 |
0 |
T164 |
30167 |
130 |
0 |
0 |
T165 |
37528 |
325 |
0 |
0 |
T166 |
15365 |
58 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3181 |
0 |
0 |
T36 |
9423 |
8 |
0 |
0 |
T38 |
16640 |
124 |
0 |
0 |
T125 |
63874 |
523 |
0 |
0 |
T144 |
233707 |
362 |
0 |
0 |
T147 |
10209 |
132 |
0 |
0 |
T156 |
7471 |
17 |
0 |
0 |
T164 |
30167 |
167 |
0 |
0 |
T165 |
37528 |
273 |
0 |
0 |
T166 |
15365 |
30 |
0 |
0 |
T167 |
5329 |
11 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3386 |
0 |
0 |
T36 |
9423 |
7 |
0 |
0 |
T38 |
16640 |
138 |
0 |
0 |
T125 |
63874 |
552 |
0 |
0 |
T144 |
233707 |
435 |
0 |
0 |
T146 |
2324 |
3 |
0 |
0 |
T147 |
10209 |
127 |
0 |
0 |
T164 |
30167 |
139 |
0 |
0 |
T165 |
37528 |
293 |
0 |
0 |
T166 |
15365 |
38 |
0 |
0 |
T167 |
5329 |
62 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3063 |
0 |
0 |
T36 |
9423 |
13 |
0 |
0 |
T38 |
16640 |
72 |
0 |
0 |
T125 |
63874 |
501 |
0 |
0 |
T144 |
233707 |
398 |
0 |
0 |
T147 |
10209 |
44 |
0 |
0 |
T156 |
7471 |
7 |
0 |
0 |
T164 |
30167 |
116 |
0 |
0 |
T165 |
37528 |
142 |
0 |
0 |
T166 |
15365 |
43 |
0 |
0 |
T167 |
5329 |
9 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2943 |
0 |
0 |
T36 |
9423 |
17 |
0 |
0 |
T38 |
16640 |
60 |
0 |
0 |
T125 |
63874 |
715 |
0 |
0 |
T144 |
233707 |
334 |
0 |
0 |
T146 |
2324 |
1 |
0 |
0 |
T147 |
10209 |
145 |
0 |
0 |
T156 |
7471 |
4 |
0 |
0 |
T164 |
30167 |
119 |
0 |
0 |
T165 |
37528 |
66 |
0 |
0 |
T166 |
15365 |
29 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3156 |
0 |
0 |
T36 |
9423 |
14 |
0 |
0 |
T38 |
16640 |
77 |
0 |
0 |
T125 |
63874 |
512 |
0 |
0 |
T144 |
233707 |
376 |
0 |
0 |
T146 |
2324 |
1 |
0 |
0 |
T147 |
10209 |
53 |
0 |
0 |
T156 |
7471 |
6 |
0 |
0 |
T164 |
30167 |
111 |
0 |
0 |
T165 |
37528 |
410 |
0 |
0 |
T166 |
15365 |
54 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3227 |
0 |
0 |
T36 |
9423 |
65 |
0 |
0 |
T38 |
16640 |
92 |
0 |
0 |
T125 |
63874 |
458 |
0 |
0 |
T144 |
233707 |
452 |
0 |
0 |
T147 |
10209 |
47 |
0 |
0 |
T156 |
7471 |
23 |
0 |
0 |
T164 |
30167 |
113 |
0 |
0 |
T165 |
37528 |
366 |
0 |
0 |
T166 |
15365 |
38 |
0 |
0 |
T168 |
14341 |
45 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3533 |
0 |
0 |
T36 |
9423 |
70 |
0 |
0 |
T38 |
16640 |
65 |
0 |
0 |
T125 |
63874 |
590 |
0 |
0 |
T144 |
233707 |
440 |
0 |
0 |
T147 |
10209 |
88 |
0 |
0 |
T156 |
7471 |
45 |
0 |
0 |
T164 |
30167 |
163 |
0 |
0 |
T165 |
37528 |
391 |
0 |
0 |
T166 |
15365 |
30 |
0 |
0 |
T167 |
5329 |
52 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3094 |
0 |
0 |
T36 |
9423 |
37 |
0 |
0 |
T38 |
16640 |
88 |
0 |
0 |
T125 |
63874 |
575 |
0 |
0 |
T144 |
233707 |
438 |
0 |
0 |
T147 |
10209 |
49 |
0 |
0 |
T156 |
7471 |
12 |
0 |
0 |
T164 |
30167 |
65 |
0 |
0 |
T165 |
37528 |
246 |
0 |
0 |
T166 |
15365 |
36 |
0 |
0 |
T167 |
5329 |
50 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3175 |
0 |
0 |
T36 |
9423 |
54 |
0 |
0 |
T38 |
16640 |
92 |
0 |
0 |
T125 |
63874 |
531 |
0 |
0 |
T144 |
233707 |
399 |
0 |
0 |
T147 |
10209 |
97 |
0 |
0 |
T156 |
7471 |
21 |
0 |
0 |
T164 |
30167 |
97 |
0 |
0 |
T165 |
37528 |
253 |
0 |
0 |
T166 |
15365 |
59 |
0 |
0 |
T167 |
5329 |
43 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3521 |
0 |
0 |
T36 |
9423 |
46 |
0 |
0 |
T38 |
16640 |
68 |
0 |
0 |
T125 |
63874 |
634 |
0 |
0 |
T144 |
233707 |
401 |
0 |
0 |
T146 |
2324 |
5 |
0 |
0 |
T147 |
10209 |
152 |
0 |
0 |
T156 |
7471 |
13 |
0 |
0 |
T164 |
30167 |
97 |
0 |
0 |
T165 |
37528 |
262 |
0 |
0 |
T166 |
15365 |
36 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3268 |
0 |
0 |
T36 |
9423 |
11 |
0 |
0 |
T38 |
16640 |
67 |
0 |
0 |
T125 |
63874 |
456 |
0 |
0 |
T144 |
233707 |
294 |
0 |
0 |
T147 |
10209 |
93 |
0 |
0 |
T156 |
7471 |
35 |
0 |
0 |
T164 |
30167 |
281 |
0 |
0 |
T165 |
37528 |
261 |
0 |
0 |
T166 |
15365 |
23 |
0 |
0 |
T167 |
5329 |
58 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3476 |
0 |
0 |
T36 |
9423 |
39 |
0 |
0 |
T38 |
16640 |
112 |
0 |
0 |
T125 |
63874 |
788 |
0 |
0 |
T144 |
233707 |
402 |
0 |
0 |
T146 |
2324 |
2 |
0 |
0 |
T147 |
10209 |
39 |
0 |
0 |
T156 |
7471 |
35 |
0 |
0 |
T164 |
30167 |
191 |
0 |
0 |
T165 |
37528 |
142 |
0 |
0 |
T166 |
15365 |
64 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3333 |
0 |
0 |
T36 |
9423 |
48 |
0 |
0 |
T38 |
16640 |
174 |
0 |
0 |
T118 |
8344 |
4 |
0 |
0 |
T125 |
63874 |
608 |
0 |
0 |
T144 |
233707 |
393 |
0 |
0 |
T146 |
2324 |
2 |
0 |
0 |
T147 |
10209 |
103 |
0 |
0 |
T156 |
7471 |
34 |
0 |
0 |
T164 |
30167 |
162 |
0 |
0 |
T165 |
37528 |
182 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3450 |
0 |
0 |
T36 |
9423 |
12 |
0 |
0 |
T38 |
16640 |
159 |
0 |
0 |
T125 |
63874 |
516 |
0 |
0 |
T144 |
233707 |
336 |
0 |
0 |
T146 |
2324 |
6 |
0 |
0 |
T147 |
10209 |
96 |
0 |
0 |
T156 |
7471 |
2 |
0 |
0 |
T164 |
30167 |
172 |
0 |
0 |
T165 |
37528 |
282 |
0 |
0 |
T166 |
15365 |
75 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3165 |
0 |
0 |
T36 |
9423 |
8 |
0 |
0 |
T38 |
16640 |
84 |
0 |
0 |
T125 |
63874 |
475 |
0 |
0 |
T144 |
233707 |
391 |
0 |
0 |
T146 |
2324 |
2 |
0 |
0 |
T147 |
10209 |
146 |
0 |
0 |
T156 |
7471 |
58 |
0 |
0 |
T164 |
30167 |
61 |
0 |
0 |
T165 |
37528 |
172 |
0 |
0 |
T166 |
15365 |
43 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
3195 |
0 |
0 |
T36 |
9423 |
20 |
0 |
0 |
T38 |
16640 |
150 |
0 |
0 |
T125 |
63874 |
339 |
0 |
0 |
T144 |
233707 |
368 |
0 |
0 |
T147 |
10209 |
12 |
0 |
0 |
T156 |
7471 |
20 |
0 |
0 |
T164 |
30167 |
135 |
0 |
0 |
T165 |
37528 |
331 |
0 |
0 |
T166 |
15365 |
34 |
0 |
0 |
T167 |
5329 |
70 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2091 |
0 |
0 |
T36 |
9423 |
8 |
0 |
0 |
T38 |
16640 |
28 |
0 |
0 |
T125 |
63874 |
126 |
0 |
0 |
T144 |
233707 |
415 |
0 |
0 |
T146 |
2324 |
1 |
0 |
0 |
T147 |
10209 |
15 |
0 |
0 |
T156 |
7471 |
4 |
0 |
0 |
T164 |
30167 |
28 |
0 |
0 |
T165 |
37528 |
84 |
0 |
0 |
T166 |
15365 |
47 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1858 |
0 |
0 |
T36 |
9423 |
18 |
0 |
0 |
T38 |
16640 |
30 |
0 |
0 |
T125 |
63874 |
96 |
0 |
0 |
T134 |
16547 |
4 |
0 |
0 |
T144 |
233707 |
358 |
0 |
0 |
T147 |
10209 |
10 |
0 |
0 |
T156 |
7471 |
12 |
0 |
0 |
T164 |
30167 |
30 |
0 |
0 |
T165 |
37528 |
69 |
0 |
0 |
T166 |
15365 |
33 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2013 |
0 |
0 |
T36 |
9423 |
17 |
0 |
0 |
T38 |
16640 |
34 |
0 |
0 |
T125 |
63874 |
111 |
0 |
0 |
T144 |
233707 |
354 |
0 |
0 |
T147 |
10209 |
13 |
0 |
0 |
T156 |
7471 |
20 |
0 |
0 |
T164 |
30167 |
33 |
0 |
0 |
T165 |
37528 |
59 |
0 |
0 |
T166 |
15365 |
68 |
0 |
0 |
T167 |
5329 |
11 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2008 |
0 |
0 |
T36 |
9423 |
7 |
0 |
0 |
T38 |
16640 |
23 |
0 |
0 |
T125 |
63874 |
123 |
0 |
0 |
T144 |
233707 |
481 |
0 |
0 |
T146 |
2324 |
6 |
0 |
0 |
T147 |
10209 |
16 |
0 |
0 |
T156 |
7471 |
25 |
0 |
0 |
T164 |
30167 |
10 |
0 |
0 |
T165 |
37528 |
62 |
0 |
0 |
T166 |
15365 |
48 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2204 |
0 |
0 |
T36 |
9423 |
17 |
0 |
0 |
T38 |
16640 |
36 |
0 |
0 |
T125 |
63874 |
210 |
0 |
0 |
T144 |
233707 |
373 |
0 |
0 |
T147 |
10209 |
34 |
0 |
0 |
T156 |
7471 |
3 |
0 |
0 |
T164 |
30167 |
51 |
0 |
0 |
T165 |
37528 |
66 |
0 |
0 |
T166 |
15365 |
83 |
0 |
0 |
T167 |
5329 |
9 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2871 |
0 |
0 |
T8 |
160400 |
0 |
0 |
0 |
T9 |
37875 |
0 |
0 |
0 |
T10 |
19828 |
0 |
0 |
0 |
T13 |
7428 |
103 |
0 |
0 |
T14 |
964 |
0 |
0 |
0 |
T15 |
11165 |
0 |
0 |
0 |
T18 |
1718 |
0 |
0 |
0 |
T30 |
1201 |
0 |
0 |
0 |
T31 |
922 |
0 |
0 |
0 |
T36 |
0 |
46 |
0 |
0 |
T38 |
0 |
58 |
0 |
0 |
T67 |
1217 |
0 |
0 |
0 |
T125 |
0 |
317 |
0 |
0 |
T144 |
0 |
413 |
0 |
0 |
T156 |
0 |
9 |
0 |
0 |
T164 |
0 |
47 |
0 |
0 |
T169 |
0 |
55 |
0 |
0 |
T170 |
0 |
21 |
0 |
0 |
T171 |
0 |
3 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2009 |
0 |
0 |
T36 |
9423 |
19 |
0 |
0 |
T38 |
16640 |
29 |
0 |
0 |
T125 |
63874 |
133 |
0 |
0 |
T144 |
233707 |
364 |
0 |
0 |
T146 |
2324 |
1 |
0 |
0 |
T147 |
10209 |
19 |
0 |
0 |
T156 |
7471 |
34 |
0 |
0 |
T164 |
30167 |
22 |
0 |
0 |
T165 |
37528 |
58 |
0 |
0 |
T166 |
15365 |
34 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1927 |
0 |
0 |
T36 |
9423 |
2 |
0 |
0 |
T38 |
16640 |
42 |
0 |
0 |
T125 |
63874 |
119 |
0 |
0 |
T144 |
233707 |
379 |
0 |
0 |
T146 |
2324 |
5 |
0 |
0 |
T147 |
10209 |
27 |
0 |
0 |
T156 |
7471 |
15 |
0 |
0 |
T164 |
30167 |
38 |
0 |
0 |
T165 |
37528 |
45 |
0 |
0 |
T166 |
15365 |
42 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1873 |
0 |
0 |
T36 |
9423 |
5 |
0 |
0 |
T38 |
16640 |
24 |
0 |
0 |
T125 |
63874 |
102 |
0 |
0 |
T144 |
233707 |
413 |
0 |
0 |
T146 |
2324 |
1 |
0 |
0 |
T147 |
10209 |
12 |
0 |
0 |
T156 |
7471 |
10 |
0 |
0 |
T164 |
30167 |
23 |
0 |
0 |
T165 |
37528 |
40 |
0 |
0 |
T166 |
15365 |
65 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1792 |
0 |
0 |
T38 |
16640 |
35 |
0 |
0 |
T125 |
63874 |
61 |
0 |
0 |
T144 |
233707 |
422 |
0 |
0 |
T146 |
2324 |
3 |
0 |
0 |
T147 |
10209 |
9 |
0 |
0 |
T156 |
7471 |
36 |
0 |
0 |
T164 |
30167 |
22 |
0 |
0 |
T165 |
37528 |
37 |
0 |
0 |
T166 |
15365 |
25 |
0 |
0 |
T167 |
5329 |
7 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1820 |
0 |
0 |
T36 |
9423 |
16 |
0 |
0 |
T38 |
16640 |
20 |
0 |
0 |
T125 |
63874 |
80 |
0 |
0 |
T144 |
233707 |
388 |
0 |
0 |
T146 |
2324 |
3 |
0 |
0 |
T147 |
10209 |
12 |
0 |
0 |
T156 |
7471 |
29 |
0 |
0 |
T164 |
30167 |
3 |
0 |
0 |
T165 |
37528 |
31 |
0 |
0 |
T166 |
15365 |
48 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1966 |
0 |
0 |
T36 |
9423 |
12 |
0 |
0 |
T38 |
16640 |
25 |
0 |
0 |
T125 |
63874 |
79 |
0 |
0 |
T144 |
233707 |
428 |
0 |
0 |
T146 |
2324 |
8 |
0 |
0 |
T147 |
10209 |
8 |
0 |
0 |
T156 |
7471 |
28 |
0 |
0 |
T164 |
30167 |
14 |
0 |
0 |
T165 |
37528 |
34 |
0 |
0 |
T166 |
15365 |
67 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2219 |
0 |
0 |
T36 |
9423 |
17 |
0 |
0 |
T38 |
16640 |
51 |
0 |
0 |
T125 |
63874 |
161 |
0 |
0 |
T144 |
233707 |
348 |
0 |
0 |
T147 |
10209 |
16 |
0 |
0 |
T156 |
7471 |
17 |
0 |
0 |
T164 |
30167 |
61 |
0 |
0 |
T165 |
37528 |
166 |
0 |
0 |
T166 |
15365 |
69 |
0 |
0 |
T167 |
5329 |
6 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1935 |
0 |
0 |
T36 |
9423 |
5 |
0 |
0 |
T38 |
16640 |
18 |
0 |
0 |
T125 |
63874 |
62 |
0 |
0 |
T144 |
233707 |
445 |
0 |
0 |
T147 |
10209 |
19 |
0 |
0 |
T156 |
7471 |
3 |
0 |
0 |
T164 |
30167 |
29 |
0 |
0 |
T165 |
37528 |
47 |
0 |
0 |
T166 |
15365 |
44 |
0 |
0 |
T167 |
5329 |
5 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
2405 |
0 |
0 |
T36 |
9423 |
6 |
0 |
0 |
T38 |
16640 |
68 |
0 |
0 |
T125 |
63874 |
232 |
0 |
0 |
T144 |
233707 |
444 |
0 |
0 |
T146 |
2324 |
3 |
0 |
0 |
T147 |
10209 |
30 |
0 |
0 |
T156 |
7471 |
24 |
0 |
0 |
T164 |
30167 |
38 |
0 |
0 |
T165 |
37528 |
126 |
0 |
0 |
T166 |
15365 |
72 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1810 |
0 |
0 |
T36 |
9423 |
6 |
0 |
0 |
T38 |
16640 |
28 |
0 |
0 |
T125 |
63874 |
112 |
0 |
0 |
T144 |
233707 |
356 |
0 |
0 |
T147 |
10209 |
19 |
0 |
0 |
T156 |
7471 |
11 |
0 |
0 |
T164 |
30167 |
30 |
0 |
0 |
T165 |
37528 |
59 |
0 |
0 |
T166 |
15365 |
22 |
0 |
0 |
T167 |
5329 |
3 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1882 |
0 |
0 |
T38 |
16640 |
18 |
0 |
0 |
T125 |
63874 |
72 |
0 |
0 |
T144 |
233707 |
447 |
0 |
0 |
T147 |
10209 |
13 |
0 |
0 |
T153 |
9742 |
1 |
0 |
0 |
T164 |
30167 |
34 |
0 |
0 |
T165 |
37528 |
24 |
0 |
0 |
T166 |
15365 |
16 |
0 |
0 |
T167 |
5329 |
9 |
0 |
0 |
T168 |
14341 |
23 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1802 |
0 |
0 |
T36 |
9423 |
2 |
0 |
0 |
T38 |
16640 |
26 |
0 |
0 |
T125 |
63874 |
57 |
0 |
0 |
T144 |
233707 |
335 |
0 |
0 |
T147 |
10209 |
8 |
0 |
0 |
T156 |
7471 |
17 |
0 |
0 |
T164 |
30167 |
9 |
0 |
0 |
T165 |
37528 |
28 |
0 |
0 |
T166 |
15365 |
57 |
0 |
0 |
T167 |
5329 |
6 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1866 |
0 |
0 |
T36 |
9423 |
3 |
0 |
0 |
T38 |
16640 |
28 |
0 |
0 |
T125 |
63874 |
56 |
0 |
0 |
T144 |
233707 |
425 |
0 |
0 |
T146 |
2324 |
6 |
0 |
0 |
T147 |
10209 |
10 |
0 |
0 |
T156 |
7471 |
18 |
0 |
0 |
T164 |
30167 |
32 |
0 |
0 |
T165 |
37528 |
38 |
0 |
0 |
T166 |
15365 |
7 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1701 |
0 |
0 |
T38 |
16640 |
15 |
0 |
0 |
T125 |
63874 |
69 |
0 |
0 |
T144 |
233707 |
418 |
0 |
0 |
T147 |
10209 |
5 |
0 |
0 |
T156 |
7471 |
11 |
0 |
0 |
T164 |
30167 |
21 |
0 |
0 |
T165 |
37528 |
43 |
0 |
0 |
T166 |
15365 |
12 |
0 |
0 |
T167 |
5329 |
10 |
0 |
0 |
T168 |
14341 |
50 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1929 |
0 |
0 |
T36 |
9423 |
3 |
0 |
0 |
T38 |
16640 |
28 |
0 |
0 |
T125 |
63874 |
68 |
0 |
0 |
T144 |
233707 |
390 |
0 |
0 |
T147 |
10209 |
15 |
0 |
0 |
T156 |
7471 |
36 |
0 |
0 |
T164 |
30167 |
18 |
0 |
0 |
T165 |
37528 |
45 |
0 |
0 |
T166 |
15365 |
29 |
0 |
0 |
T167 |
5329 |
11 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
116032763 |
1869 |
0 |
0 |
T36 |
9423 |
4 |
0 |
0 |
T38 |
16640 |
19 |
0 |
0 |
T118 |
8344 |
1 |
0 |
0 |
T125 |
63874 |
81 |
0 |
0 |
T144 |
233707 |
396 |
0 |
0 |
T147 |
10209 |
5 |
0 |
0 |
T164 |
30167 |
22 |
0 |
0 |
T165 |
37528 |
21 |
0 |
0 |
T166 |
15365 |
35 |
0 |
0 |
T167 |
5329 |
11 |
0 |
0 |