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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.09 97.49 92.82 98.61 80.85 95.87 90.94 88.03


Total test records in report: 830
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T122 /workspace/coverage/default/32.spi_device_mailbox.559962606 May 07 02:24:51 PM PDT 24 May 07 02:26:14 PM PDT 24 16232535771 ps
T274 /workspace/coverage/default/8.spi_device_mailbox.3791838694 May 07 02:18:51 PM PDT 24 May 07 02:19:33 PM PDT 24 81387105501 ps
T291 /workspace/coverage/default/3.spi_device_flash_mode.1885990791 May 07 02:17:39 PM PDT 24 May 07 02:19:01 PM PDT 24 5988111272 ps
T614 /workspace/coverage/default/42.spi_device_flash_mode.2075567432 May 07 02:25:42 PM PDT 24 May 07 02:26:09 PM PDT 24 917188579 ps
T615 /workspace/coverage/default/23.spi_device_tpm_sts_read.436781144 May 07 02:23:44 PM PDT 24 May 07 02:23:45 PM PDT 24 233537863 ps
T616 /workspace/coverage/default/35.spi_device_csb_read.3311854101 May 07 02:25:09 PM PDT 24 May 07 02:25:10 PM PDT 24 40002088 ps
T617 /workspace/coverage/default/1.spi_device_cfg_cmd.694089322 May 07 02:17:09 PM PDT 24 May 07 02:17:23 PM PDT 24 11475597336 ps
T364 /workspace/coverage/default/32.spi_device_pass_cmd_filtering.157432470 May 07 02:24:50 PM PDT 24 May 07 02:24:53 PM PDT 24 202776807 ps
T618 /workspace/coverage/default/31.spi_device_tpm_all.1025265069 May 07 02:24:42 PM PDT 24 May 07 02:25:17 PM PDT 24 5827175236 ps
T320 /workspace/coverage/default/34.spi_device_intercept.2140685009 May 07 02:25:01 PM PDT 24 May 07 02:25:10 PM PDT 24 3008240864 ps
T278 /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2129119129 May 07 02:24:16 PM PDT 24 May 07 02:24:28 PM PDT 24 12610836559 ps
T619 /workspace/coverage/default/21.spi_device_intercept.1946516926 May 07 02:23:10 PM PDT 24 May 07 02:23:25 PM PDT 24 1797815745 ps
T620 /workspace/coverage/default/19.spi_device_flash_mode.545594603 May 07 02:22:35 PM PDT 24 May 07 02:22:55 PM PDT 24 6538278947 ps
T621 /workspace/coverage/default/19.spi_device_tpm_rw.3618489495 May 07 02:22:22 PM PDT 24 May 07 02:22:28 PM PDT 24 1985513597 ps
T365 /workspace/coverage/default/48.spi_device_pass_cmd_filtering.594798144 May 07 02:26:23 PM PDT 24 May 07 02:26:40 PM PDT 24 15606254738 ps
T322 /workspace/coverage/default/24.spi_device_intercept.2863606167 May 07 02:23:58 PM PDT 24 May 07 02:24:26 PM PDT 24 2632590165 ps
T622 /workspace/coverage/default/11.spi_device_tpm_rw.1628658910 May 07 02:19:39 PM PDT 24 May 07 02:19:41 PM PDT 24 86199784 ps
T374 /workspace/coverage/default/46.spi_device_tpm_all.4026123038 May 07 02:26:06 PM PDT 24 May 07 02:27:09 PM PDT 24 49391718890 ps
T623 /workspace/coverage/default/47.spi_device_read_buffer_direct.365782848 May 07 02:26:21 PM PDT 24 May 07 02:26:27 PM PDT 24 1590474015 ps
T624 /workspace/coverage/default/42.spi_device_read_buffer_direct.1270183950 May 07 02:25:44 PM PDT 24 May 07 02:26:00 PM PDT 24 4479073387 ps
T124 /workspace/coverage/default/17.spi_device_intercept.4064676857 May 07 02:21:50 PM PDT 24 May 07 02:22:30 PM PDT 24 3809585785 ps
T625 /workspace/coverage/default/4.spi_device_upload.3955604200 May 07 02:17:52 PM PDT 24 May 07 02:17:55 PM PDT 24 262820488 ps
T373 /workspace/coverage/default/48.spi_device_tpm_all.3819682773 May 07 02:26:20 PM PDT 24 May 07 02:27:16 PM PDT 24 46987852686 ps
T358 /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1309424697 May 07 02:20:06 PM PDT 24 May 07 02:20:12 PM PDT 24 2748461394 ps
T626 /workspace/coverage/default/18.spi_device_csb_read.1844033503 May 07 02:21:57 PM PDT 24 May 07 02:21:58 PM PDT 24 36728906 ps
T627 /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2001059616 May 07 02:24:21 PM PDT 24 May 07 02:24:51 PM PDT 24 10526436751 ps
T628 /workspace/coverage/default/33.spi_device_tpm_all.3191855977 May 07 02:24:55 PM PDT 24 May 07 02:25:05 PM PDT 24 911731459 ps
T47 /workspace/coverage/default/4.spi_device_sec_cm.3240825431 May 07 02:17:57 PM PDT 24 May 07 02:17:58 PM PDT 24 184766419 ps
T629 /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4207302671 May 07 02:24:17 PM PDT 24 May 07 02:24:22 PM PDT 24 1814470994 ps
T218 /workspace/coverage/default/49.spi_device_upload.3721017901 May 07 02:26:29 PM PDT 24 May 07 02:26:54 PM PDT 24 32724147806 ps
T630 /workspace/coverage/default/4.spi_device_intercept.1426009067 May 07 02:17:51 PM PDT 24 May 07 02:18:03 PM PDT 24 833501479 ps
T631 /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.115646161 May 07 02:26:27 PM PDT 24 May 07 02:26:52 PM PDT 24 9708532064 ps
T316 /workspace/coverage/default/39.spi_device_upload.2207715404 May 07 02:25:27 PM PDT 24 May 07 02:25:46 PM PDT 24 8901364367 ps
T84 /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2926578697 May 07 02:21:27 PM PDT 24 May 07 02:21:32 PM PDT 24 1459316052 ps
T191 /workspace/coverage/default/11.spi_device_upload.2117463805 May 07 02:19:48 PM PDT 24 May 07 02:20:09 PM PDT 24 4892984913 ps
T632 /workspace/coverage/default/9.spi_device_read_buffer_direct.1443638990 May 07 02:19:12 PM PDT 24 May 07 02:19:24 PM PDT 24 10408338612 ps
T48 /workspace/coverage/default/2.spi_device_sec_cm.1823542848 May 07 02:17:31 PM PDT 24 May 07 02:17:32 PM PDT 24 125266336 ps
T327 /workspace/coverage/default/14.spi_device_intercept.1902523544 May 07 02:20:46 PM PDT 24 May 07 02:21:00 PM PDT 24 1076598931 ps
T633 /workspace/coverage/default/12.spi_device_read_buffer_direct.3750094378 May 07 02:20:04 PM PDT 24 May 07 02:20:11 PM PDT 24 1304252314 ps
T634 /workspace/coverage/default/0.spi_device_tpm_sts_read.617394731 May 07 02:16:46 PM PDT 24 May 07 02:16:48 PM PDT 24 64378628 ps
T306 /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3307302757 May 07 02:17:08 PM PDT 24 May 07 02:17:12 PM PDT 24 209111422 ps
T635 /workspace/coverage/default/19.spi_device_tpm_sts_read.4277255687 May 07 02:22:21 PM PDT 24 May 07 02:22:23 PM PDT 24 124894006 ps
T636 /workspace/coverage/default/36.spi_device_flash_mode.3681869026 May 07 02:25:15 PM PDT 24 May 07 02:26:30 PM PDT 24 22672053394 ps
T637 /workspace/coverage/default/46.spi_device_read_buffer_direct.4209361336 May 07 02:26:14 PM PDT 24 May 07 02:26:18 PM PDT 24 753902498 ps
T638 /workspace/coverage/default/41.spi_device_tpm_sts_read.2465793952 May 07 02:25:38 PM PDT 24 May 07 02:25:39 PM PDT 24 2339376499 ps
T639 /workspace/coverage/default/17.spi_device_read_buffer_direct.582547757 May 07 02:21:56 PM PDT 24 May 07 02:22:06 PM PDT 24 15817292113 ps
T640 /workspace/coverage/default/46.spi_device_tpm_rw.4106813097 May 07 02:26:05 PM PDT 24 May 07 02:26:12 PM PDT 24 223752434 ps
T641 /workspace/coverage/default/5.spi_device_tpm_rw.978174446 May 07 02:18:04 PM PDT 24 May 07 02:18:09 PM PDT 24 1280175499 ps
T642 /workspace/coverage/default/36.spi_device_tpm_rw.2136071872 May 07 02:25:14 PM PDT 24 May 07 02:25:17 PM PDT 24 657765380 ps
T101 /workspace/coverage/default/49.spi_device_intercept.3142336665 May 07 02:26:29 PM PDT 24 May 07 02:26:38 PM PDT 24 520933663 ps
T643 /workspace/coverage/default/24.spi_device_flash_mode.180048842 May 07 02:23:58 PM PDT 24 May 07 02:26:13 PM PDT 24 21930800052 ps
T644 /workspace/coverage/default/5.spi_device_read_buffer_direct.2385999939 May 07 02:18:07 PM PDT 24 May 07 02:18:12 PM PDT 24 157514751 ps
T645 /workspace/coverage/default/30.spi_device_read_buffer_direct.1009882252 May 07 02:24:42 PM PDT 24 May 07 02:24:51 PM PDT 24 2692820323 ps
T217 /workspace/coverage/default/27.spi_device_mailbox.2699084871 May 07 02:24:17 PM PDT 24 May 07 02:26:25 PM PDT 24 52379427995 ps
T646 /workspace/coverage/default/5.spi_device_stress_all.2017899872 May 07 02:18:16 PM PDT 24 May 07 02:18:18 PM PDT 24 203113139 ps
T326 /workspace/coverage/default/4.spi_device_cfg_cmd.2060635078 May 07 02:17:52 PM PDT 24 May 07 02:17:57 PM PDT 24 315312571 ps
T281 /workspace/coverage/default/9.spi_device_pass_cmd_filtering.561082654 May 07 02:19:07 PM PDT 24 May 07 02:19:10 PM PDT 24 37592688 ps
T647 /workspace/coverage/default/12.spi_device_tpm_all.595528212 May 07 02:19:58 PM PDT 24 May 07 02:20:34 PM PDT 24 26996561307 ps
T648 /workspace/coverage/default/37.spi_device_tpm_sts_read.4249240842 May 07 02:25:14 PM PDT 24 May 07 02:25:15 PM PDT 24 175966943 ps
T649 /workspace/coverage/default/24.spi_device_alert_test.1700417108 May 07 02:24:04 PM PDT 24 May 07 02:24:05 PM PDT 24 11986621 ps
T650 /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2257776479 May 07 02:25:22 PM PDT 24 May 07 02:25:28 PM PDT 24 2162241683 ps
T651 /workspace/coverage/default/37.spi_device_tpm_rw.1267513314 May 07 02:25:13 PM PDT 24 May 07 02:25:14 PM PDT 24 49931343 ps
T652 /workspace/coverage/default/32.spi_device_tpm_sts_read.4170500609 May 07 02:24:50 PM PDT 24 May 07 02:24:52 PM PDT 24 159845825 ps
T210 /workspace/coverage/default/0.spi_device_upload.3250977828 May 07 02:16:48 PM PDT 24 May 07 02:17:04 PM PDT 24 7728825336 ps
T653 /workspace/coverage/default/43.spi_device_alert_test.3759924183 May 07 02:25:54 PM PDT 24 May 07 02:25:55 PM PDT 24 13850200 ps
T235 /workspace/coverage/default/11.spi_device_intercept.152960845 May 07 02:19:50 PM PDT 24 May 07 02:20:04 PM PDT 24 3584724637 ps
T654 /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1559065869 May 07 02:23:17 PM PDT 24 May 07 02:23:27 PM PDT 24 4200196125 ps
T655 /workspace/coverage/default/5.spi_device_flash_mode.2445946301 May 07 02:18:08 PM PDT 24 May 07 02:21:19 PM PDT 24 48887404298 ps
T656 /workspace/coverage/default/46.spi_device_csb_read.3927843605 May 07 02:26:06 PM PDT 24 May 07 02:26:08 PM PDT 24 12558882 ps
T657 /workspace/coverage/default/4.spi_device_csb_read.3059487994 May 07 02:17:45 PM PDT 24 May 07 02:17:47 PM PDT 24 21961293 ps
T658 /workspace/coverage/default/3.spi_device_tpm_all.3304594822 May 07 02:17:26 PM PDT 24 May 07 02:17:35 PM PDT 24 916139543 ps
T659 /workspace/coverage/default/23.spi_device_read_buffer_direct.91508118 May 07 02:23:52 PM PDT 24 May 07 02:23:57 PM PDT 24 567824797 ps
T345 /workspace/coverage/default/22.spi_device_intercept.2551128364 May 07 02:23:27 PM PDT 24 May 07 02:23:48 PM PDT 24 14127038946 ps
T660 /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1396497197 May 07 02:25:14 PM PDT 24 May 07 02:25:19 PM PDT 24 7817927074 ps
T661 /workspace/coverage/default/19.spi_device_stress_all.4279820272 May 07 02:22:34 PM PDT 24 May 07 02:22:36 PM PDT 24 49750590 ps
T662 /workspace/coverage/default/44.spi_device_tpm_sts_read.3528193628 May 07 02:25:54 PM PDT 24 May 07 02:25:56 PM PDT 24 29509639 ps
T663 /workspace/coverage/default/40.spi_device_flash_mode.601412099 May 07 02:25:33 PM PDT 24 May 07 02:25:56 PM PDT 24 1078136748 ps
T664 /workspace/coverage/default/5.spi_device_tpm_all.1429870701 May 07 02:18:03 PM PDT 24 May 07 02:18:46 PM PDT 24 10444510495 ps
T665 /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3703349566 May 07 02:26:01 PM PDT 24 May 07 02:26:05 PM PDT 24 856039963 ps
T178 /workspace/coverage/default/40.spi_device_mailbox.4028177333 May 07 02:25:37 PM PDT 24 May 07 02:25:59 PM PDT 24 5314674105 ps
T666 /workspace/coverage/default/16.spi_device_stress_all.216523659 May 07 02:21:36 PM PDT 24 May 07 02:21:38 PM PDT 24 215259240 ps
T313 /workspace/coverage/default/21.spi_device_upload.3275324028 May 07 02:23:11 PM PDT 24 May 07 02:23:15 PM PDT 24 79727887 ps
T257 /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2541431109 May 07 02:26:08 PM PDT 24 May 07 02:26:13 PM PDT 24 261558850 ps
T667 /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1108590244 May 07 02:16:58 PM PDT 24 May 07 02:17:08 PM PDT 24 1752678908 ps
T668 /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.755779455 May 07 02:23:57 PM PDT 24 May 07 02:24:13 PM PDT 24 13880914774 ps
T41 /workspace/coverage/default/0.spi_device_ram_cfg.2402750242 May 07 02:16:46 PM PDT 24 May 07 02:16:47 PM PDT 24 31293850 ps
T669 /workspace/coverage/default/24.spi_device_tpm_sts_read.1385987634 May 07 02:23:58 PM PDT 24 May 07 02:24:00 PM PDT 24 66900505 ps
T670 /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3084097996 May 07 02:20:16 PM PDT 24 May 07 02:20:20 PM PDT 24 690081833 ps
T671 /workspace/coverage/default/34.spi_device_tpm_rw.961107221 May 07 02:25:02 PM PDT 24 May 07 02:25:04 PM PDT 24 71381948 ps
T324 /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2629208298 May 07 02:25:41 PM PDT 24 May 07 02:25:45 PM PDT 24 134509878 ps
T672 /workspace/coverage/default/19.spi_device_csb_read.2695739481 May 07 02:22:20 PM PDT 24 May 07 02:22:22 PM PDT 24 56114747 ps
T220 /workspace/coverage/default/42.spi_device_upload.3283636913 May 07 02:25:47 PM PDT 24 May 07 02:25:56 PM PDT 24 570487876 ps
T673 /workspace/coverage/default/23.spi_device_csb_read.1232224821 May 07 02:23:43 PM PDT 24 May 07 02:23:44 PM PDT 24 20632920 ps
T674 /workspace/coverage/default/45.spi_device_tpm_sts_read.2648629538 May 07 02:25:58 PM PDT 24 May 07 02:26:00 PM PDT 24 105145650 ps
T675 /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1513231784 May 07 02:21:00 PM PDT 24 May 07 02:21:08 PM PDT 24 7539039239 ps
T335 /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2697729055 May 07 02:20:09 PM PDT 24 May 07 02:20:17 PM PDT 24 1817930252 ps
T49 /workspace/coverage/default/1.spi_device_sec_cm.2003713405 May 07 02:17:10 PM PDT 24 May 07 02:17:12 PM PDT 24 99700419 ps
T331 /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.284793809 May 07 02:19:07 PM PDT 24 May 07 02:19:14 PM PDT 24 17592448769 ps
T300 /workspace/coverage/default/15.spi_device_flash_mode.2802165519 May 07 02:21:12 PM PDT 24 May 07 02:21:30 PM PDT 24 2856364170 ps
T283 /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3964639014 May 07 02:17:34 PM PDT 24 May 07 02:17:45 PM PDT 24 3642980941 ps
T370 /workspace/coverage/default/16.spi_device_tpm_all.514288908 May 07 02:21:27 PM PDT 24 May 07 02:22:03 PM PDT 24 10118511938 ps
T304 /workspace/coverage/default/34.spi_device_flash_mode.743890923 May 07 02:25:01 PM PDT 24 May 07 02:26:35 PM PDT 24 38780218852 ps
T676 /workspace/coverage/default/48.spi_device_read_buffer_direct.2573395582 May 07 02:26:24 PM PDT 24 May 07 02:26:41 PM PDT 24 1513777330 ps
T677 /workspace/coverage/default/17.spi_device_tpm_sts_read.1106004220 May 07 02:21:44 PM PDT 24 May 07 02:21:45 PM PDT 24 55290358 ps
T678 /workspace/coverage/default/33.spi_device_tpm_rw.70784458 May 07 02:24:56 PM PDT 24 May 07 02:25:01 PM PDT 24 430534272 ps
T679 /workspace/coverage/default/6.spi_device_tpm_all.467787081 May 07 02:18:21 PM PDT 24 May 07 02:18:37 PM PDT 24 2878425165 ps
T680 /workspace/coverage/default/17.spi_device_tpm_rw.1497431237 May 07 02:21:43 PM PDT 24 May 07 02:21:45 PM PDT 24 52855113 ps
T301 /workspace/coverage/default/37.spi_device_flash_mode.2389716766 May 07 02:25:13 PM PDT 24 May 07 02:25:33 PM PDT 24 4308416665 ps
T243 /workspace/coverage/default/33.spi_device_mailbox.3066062314 May 07 02:24:54 PM PDT 24 May 07 02:26:07 PM PDT 24 11153481415 ps
T681 /workspace/coverage/default/25.spi_device_csb_read.464134402 May 07 02:24:03 PM PDT 24 May 07 02:24:04 PM PDT 24 179609378 ps
T682 /workspace/coverage/default/3.spi_device_tpm_rw.3258032096 May 07 02:17:32 PM PDT 24 May 07 02:17:36 PM PDT 24 496871677 ps
T683 /workspace/coverage/default/47.spi_device_tpm_sts_read.766685812 May 07 02:26:15 PM PDT 24 May 07 02:26:17 PM PDT 24 78594228 ps
T684 /workspace/coverage/default/10.spi_device_tpm_rw.2876428691 May 07 02:19:22 PM PDT 24 May 07 02:19:25 PM PDT 24 723223992 ps
T685 /workspace/coverage/default/45.spi_device_tpm_rw.816459986 May 07 02:25:59 PM PDT 24 May 07 02:26:08 PM PDT 24 334619095 ps
T315 /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1650082594 May 07 02:21:44 PM PDT 24 May 07 02:22:10 PM PDT 24 18780579617 ps
T179 /workspace/coverage/default/21.spi_device_pass_cmd_filtering.922397017 May 07 02:23:05 PM PDT 24 May 07 02:23:17 PM PDT 24 5785911000 ps
T686 /workspace/coverage/default/0.spi_device_tpm_all.613598521 May 07 02:16:47 PM PDT 24 May 07 02:16:50 PM PDT 24 398450406 ps
T687 /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.483677054 May 07 02:25:44 PM PDT 24 May 07 02:25:53 PM PDT 24 3181693613 ps
T688 /workspace/coverage/default/14.spi_device_tpm_sts_read.3622746202 May 07 02:20:40 PM PDT 24 May 07 02:20:41 PM PDT 24 284308244 ps
T689 /workspace/coverage/default/27.spi_device_csb_read.4188690172 May 07 02:24:19 PM PDT 24 May 07 02:24:20 PM PDT 24 58406199 ps
T690 /workspace/coverage/default/28.spi_device_csb_read.2979548369 May 07 02:24:24 PM PDT 24 May 07 02:24:25 PM PDT 24 129184640 ps
T691 /workspace/coverage/default/45.spi_device_upload.2661950078 May 07 02:26:07 PM PDT 24 May 07 02:26:11 PM PDT 24 1083434664 ps
T692 /workspace/coverage/default/16.spi_device_tpm_rw.1617848797 May 07 02:21:26 PM PDT 24 May 07 02:21:32 PM PDT 24 354340894 ps
T693 /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3131674824 May 07 02:25:39 PM PDT 24 May 07 02:25:44 PM PDT 24 3302300243 ps
T694 /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.337973527 May 07 02:25:51 PM PDT 24 May 07 02:26:01 PM PDT 24 1814679589 ps
T695 /workspace/coverage/default/39.spi_device_csb_read.4090534178 May 07 02:25:31 PM PDT 24 May 07 02:25:33 PM PDT 24 23233964 ps
T696 /workspace/coverage/default/47.spi_device_alert_test.4016618005 May 07 02:26:21 PM PDT 24 May 07 02:26:23 PM PDT 24 27433020 ps
T697 /workspace/coverage/default/30.spi_device_csb_read.2229378036 May 07 02:24:39 PM PDT 24 May 07 02:24:40 PM PDT 24 20388386 ps
T356 /workspace/coverage/default/32.spi_device_flash_mode.839637454 May 07 02:24:50 PM PDT 24 May 07 02:25:23 PM PDT 24 1352429555 ps
T698 /workspace/coverage/default/9.spi_device_tpm_rw.2122035073 May 07 02:19:06 PM PDT 24 May 07 02:19:17 PM PDT 24 662476290 ps
T184 /workspace/coverage/default/47.spi_device_mailbox.3843760443 May 07 02:26:13 PM PDT 24 May 07 02:26:47 PM PDT 24 2915523962 ps
T699 /workspace/coverage/default/42.spi_device_cfg_cmd.3940092913 May 07 02:25:47 PM PDT 24 May 07 02:25:51 PM PDT 24 110987339 ps
T282 /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2437496607 May 07 02:25:27 PM PDT 24 May 07 02:25:44 PM PDT 24 12051412547 ps
T226 /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3396611896 May 07 02:21:27 PM PDT 24 May 07 02:21:35 PM PDT 24 2024340596 ps
T700 /workspace/coverage/default/22.spi_device_tpm_all.1468193290 May 07 02:23:17 PM PDT 24 May 07 02:24:15 PM PDT 24 22220214024 ps
T192 /workspace/coverage/default/48.spi_device_mailbox.1923082742 May 07 02:26:19 PM PDT 24 May 07 02:26:29 PM PDT 24 2903448774 ps
T701 /workspace/coverage/default/30.spi_device_tpm_rw.4292617097 May 07 02:24:37 PM PDT 24 May 07 02:24:39 PM PDT 24 23429431 ps
T267 /workspace/coverage/default/7.spi_device_intercept.2841702156 May 07 02:18:40 PM PDT 24 May 07 02:18:51 PM PDT 24 924029672 ps
T702 /workspace/coverage/default/37.spi_device_csb_read.4057942902 May 07 02:25:14 PM PDT 24 May 07 02:25:15 PM PDT 24 43997689 ps
T703 /workspace/coverage/default/11.spi_device_read_buffer_direct.1492592124 May 07 02:19:52 PM PDT 24 May 07 02:19:59 PM PDT 24 625396347 ps
T704 /workspace/coverage/default/14.spi_device_tpm_rw.2831070893 May 07 02:20:40 PM PDT 24 May 07 02:20:42 PM PDT 24 393445778 ps
T705 /workspace/coverage/default/49.spi_device_cfg_cmd.3347098333 May 07 02:26:32 PM PDT 24 May 07 02:26:37 PM PDT 24 1151754144 ps
T706 /workspace/coverage/default/32.spi_device_csb_read.4084405006 May 07 02:24:48 PM PDT 24 May 07 02:24:49 PM PDT 24 17212048 ps
T707 /workspace/coverage/default/6.spi_device_stress_all.2633096556 May 07 02:18:31 PM PDT 24 May 07 02:18:33 PM PDT 24 42600850 ps
T708 /workspace/coverage/default/28.spi_device_upload.1657444239 May 07 02:24:33 PM PDT 24 May 07 02:24:38 PM PDT 24 271398211 ps
T228 /workspace/coverage/default/18.spi_device_pass_cmd_filtering.963681315 May 07 02:22:08 PM PDT 24 May 07 02:22:20 PM PDT 24 1565563133 ps
T357 /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1216890243 May 07 02:16:48 PM PDT 24 May 07 02:16:51 PM PDT 24 130128455 ps
T709 /workspace/coverage/default/3.spi_device_read_buffer_direct.1576320782 May 07 02:17:39 PM PDT 24 May 07 02:17:59 PM PDT 24 26108026367 ps
T710 /workspace/coverage/default/29.spi_device_intercept.408343769 May 07 02:24:37 PM PDT 24 May 07 02:24:43 PM PDT 24 370139124 ps
T711 /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1276138314 May 07 02:25:38 PM PDT 24 May 07 02:25:48 PM PDT 24 5049691213 ps
T712 /workspace/coverage/default/47.spi_device_csb_read.3823830556 May 07 02:26:12 PM PDT 24 May 07 02:26:14 PM PDT 24 112512472 ps
T713 /workspace/coverage/default/1.spi_device_read_buffer_direct.2921174726 May 07 02:17:10 PM PDT 24 May 07 02:17:20 PM PDT 24 2486621402 ps
T714 /workspace/coverage/default/17.spi_device_tpm_all.1999907166 May 07 02:21:37 PM PDT 24 May 07 02:21:47 PM PDT 24 1617279627 ps
T715 /workspace/coverage/default/43.spi_device_read_buffer_direct.3619706855 May 07 02:25:53 PM PDT 24 May 07 02:26:12 PM PDT 24 1598283352 ps
T227 /workspace/coverage/default/39.spi_device_pass_cmd_filtering.586621503 May 07 02:25:30 PM PDT 24 May 07 02:25:38 PM PDT 24 1217088617 ps
T716 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.787815875 May 07 01:29:01 PM PDT 24 May 07 01:29:03 PM PDT 24 187398766 ps
T34 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1766422165 May 07 01:28:55 PM PDT 24 May 07 01:29:15 PM PDT 24 309743502 ps
T170 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2824914606 May 07 01:28:51 PM PDT 24 May 07 01:28:53 PM PDT 24 15781308 ps
T171 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4112689401 May 07 01:28:57 PM PDT 24 May 07 01:28:59 PM PDT 24 14286403 ps
T717 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3479859581 May 07 01:29:14 PM PDT 24 May 07 01:29:17 PM PDT 24 92325797 ps
T718 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3196254829 May 07 01:29:12 PM PDT 24 May 07 01:29:14 PM PDT 24 12533728 ps
T37 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1270881328 May 07 01:28:52 PM PDT 24 May 07 01:28:55 PM PDT 24 105536971 ps
T35 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3546035358 May 07 01:28:54 PM PDT 24 May 07 01:28:56 PM PDT 24 44578534 ps
T719 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3336131479 May 07 01:29:12 PM PDT 24 May 07 01:29:15 PM PDT 24 63646427 ps
T36 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1483398963 May 07 01:28:54 PM PDT 24 May 07 01:28:58 PM PDT 24 94263462 ps
T720 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2621642985 May 07 01:28:43 PM PDT 24 May 07 01:28:45 PM PDT 24 12304606 ps
T38 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3135296578 May 07 01:29:05 PM PDT 24 May 07 01:29:10 PM PDT 24 166425542 ps
T156 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1197777337 May 07 01:28:59 PM PDT 24 May 07 01:29:01 PM PDT 24 77038572 ps
T157 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1166598910 May 07 01:28:41 PM PDT 24 May 07 01:28:44 PM PDT 24 21139293 ps
T118 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3565962190 May 07 01:29:13 PM PDT 24 May 07 01:29:17 PM PDT 24 927264503 ps
T119 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3663114572 May 07 01:28:54 PM PDT 24 May 07 01:28:59 PM PDT 24 226759548 ps
T120 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2678873588 May 07 01:29:02 PM PDT 24 May 07 01:29:05 PM PDT 24 58781357 ps
T137 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4068203464 May 07 01:29:15 PM PDT 24 May 07 01:29:20 PM PDT 24 1499076939 ps
T125 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2057921292 May 07 01:28:49 PM PDT 24 May 07 01:29:05 PM PDT 24 2661506057 ps
T142 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.605270632 May 07 01:29:01 PM PDT 24 May 07 01:29:04 PM PDT 24 45680616 ps
T158 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3122778042 May 07 01:28:48 PM PDT 24 May 07 01:28:53 PM PDT 24 235175478 ps
T143 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1329429730 May 07 01:28:39 PM PDT 24 May 07 01:28:42 PM PDT 24 85705289 ps
T131 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2004525319 May 07 01:28:48 PM PDT 24 May 07 01:28:51 PM PDT 24 122390934 ps
T159 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1692816081 May 07 01:28:41 PM PDT 24 May 07 01:28:46 PM PDT 24 59709160 ps
T126 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3562806329 May 07 01:28:55 PM PDT 24 May 07 01:29:19 PM PDT 24 898522183 ps
T721 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1150510984 May 07 01:28:55 PM PDT 24 May 07 01:28:57 PM PDT 24 23410496 ps
T138 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.102621250 May 07 01:28:47 PM PDT 24 May 07 01:28:50 PM PDT 24 64571588 ps
T362 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.627705631 May 07 01:28:49 PM PDT 24 May 07 01:29:07 PM PDT 24 289360313 ps
T144 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.874150372 May 07 01:28:42 PM PDT 24 May 07 01:29:18 PM PDT 24 19475511497 ps
T722 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.385703332 May 07 01:28:49 PM PDT 24 May 07 01:29:15 PM PDT 24 1232239839 ps
T723 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1294406806 May 07 01:28:40 PM PDT 24 May 07 01:28:42 PM PDT 24 18940851 ps
T724 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1566169574 May 07 01:28:56 PM PDT 24 May 07 01:28:59 PM PDT 24 121592243 ps
T725 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3602447493 May 07 01:29:14 PM PDT 24 May 07 01:29:17 PM PDT 24 51776131 ps
T164 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2207353068 May 07 01:28:40 PM PDT 24 May 07 01:28:49 PM PDT 24 301697552 ps
T145 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1756166388 May 07 01:28:57 PM PDT 24 May 07 01:29:01 PM PDT 24 377812747 ps
T146 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.698068340 May 07 01:28:41 PM PDT 24 May 07 01:28:44 PM PDT 24 24241576 ps
T726 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1598572834 May 07 01:28:38 PM PDT 24 May 07 01:28:39 PM PDT 24 36225320 ps
T132 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.499277963 May 07 01:28:39 PM PDT 24 May 07 01:28:43 PM PDT 24 550444265 ps
T727 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4002079015 May 07 01:29:17 PM PDT 24 May 07 01:29:19 PM PDT 24 14426393 ps
T130 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2666883611 May 07 01:28:38 PM PDT 24 May 07 01:28:41 PM PDT 24 420546085 ps
T728 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4258118269 May 07 01:29:02 PM PDT 24 May 07 01:29:04 PM PDT 24 20156980 ps
T729 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1350572081 May 07 01:28:49 PM PDT 24 May 07 01:29:02 PM PDT 24 2892626027 ps
T165 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.522841781 May 07 01:28:40 PM PDT 24 May 07 01:28:50 PM PDT 24 2502001256 ps
T147 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2333380534 May 07 01:28:54 PM PDT 24 May 07 01:28:58 PM PDT 24 102115125 ps
T105 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1710832167 May 07 01:28:38 PM PDT 24 May 07 01:28:40 PM PDT 24 105352236 ps
T730 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.169925541 May 07 01:29:17 PM PDT 24 May 07 01:29:19 PM PDT 24 14614965 ps
T731 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2792938733 May 07 01:28:40 PM PDT 24 May 07 01:28:42 PM PDT 24 42083921 ps
T134 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2788368929 May 07 01:29:11 PM PDT 24 May 07 01:29:15 PM PDT 24 689522034 ps
T160 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4164664962 May 07 01:29:06 PM PDT 24 May 07 01:29:11 PM PDT 24 174017836 ps
T161 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3010026737 May 07 01:28:42 PM PDT 24 May 07 01:28:46 PM PDT 24 190150916 ps
T732 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2156396868 May 07 01:29:14 PM PDT 24 May 07 01:29:17 PM PDT 24 13404930 ps
T733 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2674754371 May 07 01:29:02 PM PDT 24 May 07 01:29:06 PM PDT 24 398360923 ps
T734 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3609856608 May 07 01:29:01 PM PDT 24 May 07 01:29:05 PM PDT 24 130690274 ps
T148 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.983081886 May 07 01:28:47 PM PDT 24 May 07 01:28:49 PM PDT 24 206920876 ps
T149 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3445008957 May 07 01:28:45 PM PDT 24 May 07 01:29:00 PM PDT 24 209296163 ps
T133 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.836844416 May 07 01:28:53 PM PDT 24 May 07 01:28:57 PM PDT 24 55770628 ps
T735 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1286140420 May 07 01:29:18 PM PDT 24 May 07 01:29:21 PM PDT 24 11143943 ps
T736 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4095881176 May 07 01:28:57 PM PDT 24 May 07 01:29:05 PM PDT 24 256553357 ps
T737 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1295675367 May 07 01:29:12 PM PDT 24 May 07 01:29:18 PM PDT 24 323307561 ps
T106 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1083940579 May 07 01:28:45 PM PDT 24 May 07 01:28:47 PM PDT 24 75417696 ps
T166 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3364411481 May 07 01:28:53 PM PDT 24 May 07 01:28:58 PM PDT 24 640320151 ps
T738 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4180377110 May 07 01:28:56 PM PDT 24 May 07 01:28:59 PM PDT 24 121161029 ps
T739 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3545984507 May 07 01:28:54 PM PDT 24 May 07 01:28:56 PM PDT 24 50069871 ps
T150 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2909731101 May 07 01:29:06 PM PDT 24 May 07 01:29:09 PM PDT 24 331743908 ps
T343 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1727171594 May 07 01:29:15 PM PDT 24 May 07 01:29:36 PM PDT 24 293678923 ps
T740 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2837000052 May 07 01:28:56 PM PDT 24 May 07 01:29:00 PM PDT 24 165695389 ps
T151 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.737385303 May 07 01:28:55 PM PDT 24 May 07 01:28:58 PM PDT 24 66552136 ps
T741 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.564085532 May 07 01:28:58 PM PDT 24 May 07 01:29:00 PM PDT 24 22900644 ps
T167 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2066475535 May 07 01:28:53 PM PDT 24 May 07 01:28:56 PM PDT 24 242307713 ps
T742 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1502156073 May 07 01:29:13 PM PDT 24 May 07 01:29:15 PM PDT 24 15150582 ps
T743 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1458469193 May 07 01:29:06 PM PDT 24 May 07 01:29:11 PM PDT 24 220420682 ps
T135 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2680530060 May 07 01:28:53 PM PDT 24 May 07 01:28:58 PM PDT 24 677694280 ps
T337 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3717292327 May 07 01:28:40 PM PDT 24 May 07 01:28:59 PM PDT 24 652375774 ps
T338 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.9090807 May 07 01:28:57 PM PDT 24 May 07 01:29:20 PM PDT 24 6256759889 ps
T152 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2043081167 May 07 01:28:40 PM PDT 24 May 07 01:28:52 PM PDT 24 190105097 ps
T155 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.835335673 May 07 01:28:44 PM PDT 24 May 07 01:28:47 PM PDT 24 240081893 ps
T168 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2572851316 May 07 01:28:41 PM PDT 24 May 07 01:28:46 PM PDT 24 149416751 ps
T153 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3050755872 May 07 01:29:03 PM PDT 24 May 07 01:29:07 PM PDT 24 97452783 ps
T744 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.66851897 May 07 01:28:56 PM PDT 24 May 07 01:28:59 PM PDT 24 195292761 ps
T745 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4005499021 May 07 01:29:12 PM PDT 24 May 07 01:29:15 PM PDT 24 12585507 ps
T746 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2473374767 May 07 01:29:11 PM PDT 24 May 07 01:29:13 PM PDT 24 13018081 ps
T136 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4214687652 May 07 01:28:41 PM PDT 24 May 07 01:28:47 PM PDT 24 167334343 ps
T747 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2351314516 May 07 01:29:11 PM PDT 24 May 07 01:29:13 PM PDT 24 16316440 ps
T748 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2295247886 May 07 01:29:02 PM PDT 24 May 07 01:29:04 PM PDT 24 20802808 ps
T749 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3580635532 May 07 01:29:01 PM PDT 24 May 07 01:29:04 PM PDT 24 153092086 ps
T750 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2922986984 May 07 01:29:18 PM PDT 24 May 07 01:29:21 PM PDT 24 23106991 ps
T139 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1357996352 May 07 01:28:49 PM PDT 24 May 07 01:28:55 PM PDT 24 710289811 ps
T751 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.908783145 May 07 01:28:55 PM PDT 24 May 07 01:28:58 PM PDT 24 60186398 ps
T752 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.33402815 May 07 01:29:12 PM PDT 24 May 07 01:29:15 PM PDT 24 16073527 ps
T753 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2136762913 May 07 01:29:01 PM PDT 24 May 07 01:29:05 PM PDT 24 54576818 ps
T754 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1663899362 May 07 01:28:49 PM PDT 24 May 07 01:28:52 PM PDT 24 57429320 ps
T755 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.505008505 May 07 01:29:02 PM PDT 24 May 07 01:29:07 PM PDT 24 127119599 ps
T756 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2550975725 May 07 01:29:12 PM PDT 24 May 07 01:29:18 PM PDT 24 128737491 ps
T757 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1249685290 May 07 01:29:17 PM PDT 24 May 07 01:29:19 PM PDT 24 32946017 ps
T344 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2898233153 May 07 01:29:04 PM PDT 24 May 07 01:29:19 PM PDT 24 432747242 ps
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