Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.09 97.49 92.82 98.61 80.85 95.87 90.94 88.03


Total test records in report: 830
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T341 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.167832362 May 07 01:28:52 PM PDT 24 May 07 01:28:59 PM PDT 24 106060241 ps
T758 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.446178248 May 07 01:29:19 PM PDT 24 May 07 01:29:21 PM PDT 24 12277763 ps
T759 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3721675685 May 07 01:29:02 PM PDT 24 May 07 01:29:06 PM PDT 24 505667651 ps
T154 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1546421165 May 07 01:28:41 PM PDT 24 May 07 01:29:16 PM PDT 24 1743035004 ps
T760 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3315596536 May 07 01:29:14 PM PDT 24 May 07 01:29:17 PM PDT 24 55122619 ps
T761 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1417299991 May 07 01:29:13 PM PDT 24 May 07 01:29:15 PM PDT 24 13532854 ps
T762 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4185467569 May 07 01:28:52 PM PDT 24 May 07 01:28:57 PM PDT 24 59137366 ps
T763 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3495787009 May 07 01:29:01 PM PDT 24 May 07 01:29:04 PM PDT 24 357459569 ps
T764 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1320376520 May 07 01:28:52 PM PDT 24 May 07 01:28:54 PM PDT 24 12309936 ps
T342 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4204598734 May 07 01:28:51 PM PDT 24 May 07 01:29:06 PM PDT 24 1083328151 ps
T765 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2528515660 May 07 01:29:04 PM PDT 24 May 07 01:29:06 PM PDT 24 18934147 ps
T766 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1197369774 May 07 01:28:53 PM PDT 24 May 07 01:29:08 PM PDT 24 2248918136 ps
T767 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1267445549 May 07 01:28:56 PM PDT 24 May 07 01:28:59 PM PDT 24 69720660 ps
T768 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.667404185 May 07 01:29:02 PM PDT 24 May 07 01:29:06 PM PDT 24 371639927 ps
T769 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2289263583 May 07 01:28:48 PM PDT 24 May 07 01:29:04 PM PDT 24 1464266071 ps
T107 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2349528442 May 07 01:28:48 PM PDT 24 May 07 01:28:51 PM PDT 24 40393701 ps
T770 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3390530032 May 07 01:28:53 PM PDT 24 May 07 01:28:59 PM PDT 24 466035903 ps
T771 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4034350505 May 07 01:28:41 PM PDT 24 May 07 01:28:46 PM PDT 24 127412658 ps
T772 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3896773059 May 07 01:29:14 PM PDT 24 May 07 01:29:17 PM PDT 24 14107235 ps
T773 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3201097482 May 07 01:29:01 PM PDT 24 May 07 01:29:03 PM PDT 24 39032771 ps
T774 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.633106109 May 07 01:28:54 PM PDT 24 May 07 01:28:55 PM PDT 24 36474770 ps
T775 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.880622278 May 07 01:28:55 PM PDT 24 May 07 01:28:59 PM PDT 24 598100761 ps
T776 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4111437584 May 07 01:29:14 PM PDT 24 May 07 01:29:19 PM PDT 24 118720543 ps
T777 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3888799807 May 07 01:28:40 PM PDT 24 May 07 01:28:57 PM PDT 24 2750191201 ps
T778 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3529887577 May 07 01:29:13 PM PDT 24 May 07 01:29:16 PM PDT 24 19535878 ps
T779 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2663973129 May 07 01:29:12 PM PDT 24 May 07 01:29:14 PM PDT 24 13766174 ps
T780 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2707081709 May 07 01:29:11 PM PDT 24 May 07 01:29:13 PM PDT 24 11600890 ps
T781 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2770139018 May 07 01:29:13 PM PDT 24 May 07 01:29:16 PM PDT 24 28964348 ps
T782 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3092080044 May 07 01:29:16 PM PDT 24 May 07 01:29:18 PM PDT 24 15217099 ps
T783 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1058812680 May 07 01:28:47 PM PDT 24 May 07 01:28:48 PM PDT 24 80440153 ps
T784 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2379427476 May 07 01:29:18 PM PDT 24 May 07 01:29:21 PM PDT 24 29880159 ps
T339 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2346864518 May 07 01:29:03 PM PDT 24 May 07 01:29:23 PM PDT 24 1218188056 ps
T785 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4004475995 May 07 01:28:54 PM PDT 24 May 07 01:28:57 PM PDT 24 221907364 ps
T786 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2229378140 May 07 01:28:49 PM PDT 24 May 07 01:28:51 PM PDT 24 211045647 ps
T787 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2568425157 May 07 01:29:03 PM PDT 24 May 07 01:29:07 PM PDT 24 90446894 ps
T788 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.965880656 May 07 01:29:11 PM PDT 24 May 07 01:29:19 PM PDT 24 109736326 ps
T789 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1500557190 May 07 01:29:02 PM PDT 24 May 07 01:29:06 PM PDT 24 149370527 ps
T790 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1365158620 May 07 01:28:52 PM PDT 24 May 07 01:28:54 PM PDT 24 14535855 ps
T791 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2764766954 May 07 01:29:12 PM PDT 24 May 07 01:29:15 PM PDT 24 52091627 ps
T792 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.212929394 May 07 01:29:14 PM PDT 24 May 07 01:29:17 PM PDT 24 50629205 ps
T793 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2850699364 May 07 01:29:01 PM PDT 24 May 07 01:29:17 PM PDT 24 1135831683 ps
T794 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3308350603 May 07 01:28:42 PM PDT 24 May 07 01:28:45 PM PDT 24 23207449 ps
T795 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.943219171 May 07 01:28:53 PM PDT 24 May 07 01:28:58 PM PDT 24 144620180 ps
T796 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4118657403 May 07 01:29:02 PM PDT 24 May 07 01:29:06 PM PDT 24 331205563 ps
T797 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4105313988 May 07 01:28:53 PM PDT 24 May 07 01:28:57 PM PDT 24 475698852 ps
T798 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2791452890 May 07 01:28:39 PM PDT 24 May 07 01:28:42 PM PDT 24 34786245 ps
T799 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.12495370 May 07 01:28:40 PM PDT 24 May 07 01:28:43 PM PDT 24 110023106 ps
T800 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.596062703 May 07 01:28:41 PM PDT 24 May 07 01:28:45 PM PDT 24 30175100 ps
T801 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2295359465 May 07 01:28:40 PM PDT 24 May 07 01:28:42 PM PDT 24 10711188 ps
T802 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1789184959 May 07 01:28:55 PM PDT 24 May 07 01:28:56 PM PDT 24 90781080 ps
T803 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.960959612 May 07 01:29:13 PM PDT 24 May 07 01:29:16 PM PDT 24 38330722 ps
T804 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.768375715 May 07 01:28:55 PM PDT 24 May 07 01:28:59 PM PDT 24 99120369 ps
T805 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1890424677 May 07 01:29:04 PM PDT 24 May 07 01:29:07 PM PDT 24 45377865 ps
T806 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1722147237 May 07 01:28:39 PM PDT 24 May 07 01:29:02 PM PDT 24 4104010542 ps
T807 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2343929155 May 07 01:28:53 PM PDT 24 May 07 01:28:56 PM PDT 24 110067290 ps
T808 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2736976187 May 07 01:29:02 PM PDT 24 May 07 01:29:22 PM PDT 24 302563853 ps
T809 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3355388943 May 07 01:28:47 PM PDT 24 May 07 01:29:03 PM PDT 24 203537415 ps
T810 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2944695854 May 07 01:29:14 PM PDT 24 May 07 01:29:20 PM PDT 24 582226103 ps
T811 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3035992351 May 07 01:29:12 PM PDT 24 May 07 01:29:16 PM PDT 24 35116979 ps
T108 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.333920415 May 07 01:28:52 PM PDT 24 May 07 01:28:55 PM PDT 24 46680643 ps
T812 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4137687668 May 07 01:28:49 PM PDT 24 May 07 01:28:53 PM PDT 24 172564532 ps
T813 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2036042068 May 07 01:29:11 PM PDT 24 May 07 01:29:12 PM PDT 24 13014908 ps
T814 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.277214152 May 07 01:28:44 PM PDT 24 May 07 01:28:45 PM PDT 24 67838141 ps
T815 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.635254838 May 07 01:29:15 PM PDT 24 May 07 01:29:19 PM PDT 24 90055528 ps
T816 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1237812256 May 07 01:29:14 PM PDT 24 May 07 01:29:36 PM PDT 24 603069492 ps
T817 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4244771151 May 07 01:29:11 PM PDT 24 May 07 01:29:13 PM PDT 24 13198049 ps
T818 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2228674754 May 07 01:28:38 PM PDT 24 May 07 01:28:40 PM PDT 24 72625963 ps
T819 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4233836431 May 07 01:28:42 PM PDT 24 May 07 01:28:46 PM PDT 24 204976357 ps
T820 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2064015804 May 07 01:29:10 PM PDT 24 May 07 01:29:15 PM PDT 24 684676034 ps
T821 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2971947205 May 07 01:29:13 PM PDT 24 May 07 01:29:15 PM PDT 24 13515671 ps
T822 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1579852296 May 07 01:29:04 PM PDT 24 May 07 01:29:06 PM PDT 24 15107331 ps
T823 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1458753344 May 07 01:29:02 PM PDT 24 May 07 01:29:06 PM PDT 24 188152706 ps
T824 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2143715983 May 07 01:28:48 PM PDT 24 May 07 01:28:50 PM PDT 24 27547464 ps
T340 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4046957881 May 07 01:29:05 PM PDT 24 May 07 01:29:23 PM PDT 24 1346852159 ps
T825 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2884672141 May 07 01:29:11 PM PDT 24 May 07 01:29:14 PM PDT 24 12817967 ps
T826 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.756899236 May 07 01:29:14 PM PDT 24 May 07 01:29:17 PM PDT 24 35621985 ps
T827 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.671694245 May 07 01:29:05 PM PDT 24 May 07 01:29:09 PM PDT 24 777044830 ps
T828 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4136052096 May 07 01:29:16 PM PDT 24 May 07 01:29:18 PM PDT 24 21953219 ps
T829 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2429759249 May 07 01:29:11 PM PDT 24 May 07 01:29:14 PM PDT 24 293362657 ps
T830 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2364251325 May 07 01:28:48 PM PDT 24 May 07 01:28:49 PM PDT 24 10825643 ps

Test location /workspace/coverage/default/11.spi_device_mailbox.730260007
Short name T3
Test name
Test status
Simulation time 927158159 ps
CPU time 9.55 seconds
Started May 07 02:19:50 PM PDT 24
Finished May 07 02:20:00 PM PDT 24
Peak memory 219072 kb
Host smart-16b1b8d6-35c8-442e-893a-964f3877ef26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730260007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.730260007
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.13005228
Short name T17
Test name
Test status
Simulation time 6160151066 ps
CPU time 27.89 seconds
Started May 07 02:23:50 PM PDT 24
Finished May 07 02:24:18 PM PDT 24
Peak memory 216404 kb
Host smart-9ad8c2ef-52e8-499d-85c4-1517662ab092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13005228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.13005228
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.859440653
Short name T42
Test name
Test status
Simulation time 2897966599 ps
CPU time 22.11 seconds
Started May 07 02:26:05 PM PDT 24
Finished May 07 02:26:28 PM PDT 24
Peak memory 240048 kb
Host smart-45d380ec-dff7-4690-bdbb-0e9276a91677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859440653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.859440653
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4105454925
Short name T4
Test name
Test status
Simulation time 37446269695 ps
CPU time 20.82 seconds
Started May 07 02:22:48 PM PDT 24
Finished May 07 02:23:10 PM PDT 24
Peak memory 236732 kb
Host smart-b9edb019-5363-4259-9831-34545af218cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105454925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4105454925
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3656550303
Short name T111
Test name
Test status
Simulation time 2295887092 ps
CPU time 34.6 seconds
Started May 07 02:23:03 PM PDT 24
Finished May 07 02:23:39 PM PDT 24
Peak memory 216532 kb
Host smart-9c92a42e-dbdd-4a5a-8a83-21d4bf4f1dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656550303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3656550303
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2057921292
Short name T125
Test name
Test status
Simulation time 2661506057 ps
CPU time 14.86 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:29:05 PM PDT 24
Peak memory 215796 kb
Host smart-16b231d9-2653-4b6b-a761-2dc339b911b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057921292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2057921292
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.541672278
Short name T13
Test name
Test status
Simulation time 74309369 ps
CPU time 1.26 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:25:17 PM PDT 24
Peak memory 208068 kb
Host smart-f37aaac2-4999-456b-9fb4-922c5d0b1af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541672278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.541672278
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_upload.3080503106
Short name T10
Test name
Test status
Simulation time 901389609 ps
CPU time 3.61 seconds
Started May 07 02:22:08 PM PDT 24
Finished May 07 02:22:12 PM PDT 24
Peak memory 219964 kb
Host smart-cca681ac-36fb-4a15-943a-6ff2b182e15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080503106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3080503106
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3593104165
Short name T63
Test name
Test status
Simulation time 48060037326 ps
CPU time 20.05 seconds
Started May 07 02:23:46 PM PDT 24
Finished May 07 02:24:06 PM PDT 24
Peak memory 216312 kb
Host smart-216a3d07-8a8b-4531-99d5-8880e75a4c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593104165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3593104165
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3413868797
Short name T25
Test name
Test status
Simulation time 147455865 ps
CPU time 3.55 seconds
Started May 07 02:23:29 PM PDT 24
Finished May 07 02:23:33 PM PDT 24
Peak memory 218812 kb
Host smart-d8e0189f-7ba5-4e0d-9e33-2a5509da43af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413868797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3413868797
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2402750242
Short name T41
Test name
Test status
Simulation time 31293850 ps
CPU time 0.76 seconds
Started May 07 02:16:46 PM PDT 24
Finished May 07 02:16:47 PM PDT 24
Peak memory 216416 kb
Host smart-a9eae0b4-833c-428e-ad90-88b8f7cc812d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402750242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2402750242
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2831080208
Short name T378
Test name
Test status
Simulation time 46969800498 ps
CPU time 59.95 seconds
Started May 07 02:25:52 PM PDT 24
Finished May 07 02:26:53 PM PDT 24
Peak memory 216388 kb
Host smart-79a2abf1-b1de-4017-adf4-d72dce10ac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831080208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2831080208
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3424770441
Short name T5
Test name
Test status
Simulation time 1467286709 ps
CPU time 30.16 seconds
Started May 07 02:23:49 PM PDT 24
Finished May 07 02:24:20 PM PDT 24
Peak memory 233952 kb
Host smart-7e94a18a-ee2d-4a29-96eb-5ff334e72c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424770441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3424770441
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2422963094
Short name T45
Test name
Test status
Simulation time 3508859356 ps
CPU time 31.22 seconds
Started May 07 02:22:54 PM PDT 24
Finished May 07 02:23:26 PM PDT 24
Peak memory 218904 kb
Host smart-e3b37d25-90da-4bf9-a237-9c5482998a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422963094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2422963094
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3532553889
Short name T187
Test name
Test status
Simulation time 8907687152 ps
CPU time 53.76 seconds
Started May 07 02:26:33 PM PDT 24
Finished May 07 02:27:27 PM PDT 24
Peak memory 218620 kb
Host smart-bee7777d-0261-454a-ba01-6442eff984f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532553889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3532553889
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.223889685
Short name T366
Test name
Test status
Simulation time 17404465212 ps
CPU time 40.59 seconds
Started May 07 02:20:16 PM PDT 24
Finished May 07 02:20:57 PM PDT 24
Peak memory 216488 kb
Host smart-3a7cd0ff-fde9-4733-b7b0-44e075c7d5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223889685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.223889685
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.638715215
Short name T30
Test name
Test status
Simulation time 12038361 ps
CPU time 0.7 seconds
Started May 07 02:19:55 PM PDT 24
Finished May 07 02:19:56 PM PDT 24
Peak memory 205328 kb
Host smart-f4361ccc-9638-442d-bb67-cdc87e36920f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638715215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.638715215
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3565962190
Short name T118
Test name
Test status
Simulation time 927264503 ps
CPU time 2.3 seconds
Started May 07 01:29:13 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 215564 kb
Host smart-e6498f8b-d2f8-4d1b-a5b1-8cce86684693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565962190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3565962190
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2282777067
Short name T199
Test name
Test status
Simulation time 58265162798 ps
CPU time 54.9 seconds
Started May 07 02:24:43 PM PDT 24
Finished May 07 02:25:39 PM PDT 24
Peak memory 230276 kb
Host smart-d67b8cc4-72a2-45a7-a2c3-5571c3cc1a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282777067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2282777067
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1417807485
Short name T68
Test name
Test status
Simulation time 430753162 ps
CPU time 8.3 seconds
Started May 07 02:18:51 PM PDT 24
Finished May 07 02:19:00 PM PDT 24
Peak memory 222540 kb
Host smart-7d04a57e-4505-469b-866b-fa679320e38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417807485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1417807485
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_upload.2051998247
Short name T29
Test name
Test status
Simulation time 22146390886 ps
CPU time 17.09 seconds
Started May 07 02:26:13 PM PDT 24
Finished May 07 02:26:31 PM PDT 24
Peak memory 235580 kb
Host smart-dbc62190-bfd6-40f5-8737-ccd4f1c30c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051998247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2051998247
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2333380534
Short name T147
Test name
Test status
Simulation time 102115125 ps
CPU time 2.51 seconds
Started May 07 01:28:54 PM PDT 24
Finished May 07 01:28:58 PM PDT 24
Peak memory 215192 kb
Host smart-a629e408-2bc4-471e-8078-3c7f19626df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333380534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2333380534
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2104589748
Short name T202
Test name
Test status
Simulation time 3850963588 ps
CPU time 15.03 seconds
Started May 07 02:24:09 PM PDT 24
Finished May 07 02:24:25 PM PDT 24
Peak memory 247748 kb
Host smart-7befc1a4-2fc3-4545-ab67-e53e9f527d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104589748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2104589748
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2129119129
Short name T278
Test name
Test status
Simulation time 12610836559 ps
CPU time 11.68 seconds
Started May 07 02:24:16 PM PDT 24
Finished May 07 02:24:28 PM PDT 24
Peak memory 218968 kb
Host smart-43832730-f3fc-48e7-9825-2607fb101a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129119129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2129119129
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2556248105
Short name T115
Test name
Test status
Simulation time 16302645808 ps
CPU time 38.52 seconds
Started May 07 02:25:18 PM PDT 24
Finished May 07 02:25:57 PM PDT 24
Peak memory 221172 kb
Host smart-e2aed86d-c93c-484d-8364-3ea336b5fa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556248105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2556248105
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2258890165
Short name T72
Test name
Test status
Simulation time 9606216811 ps
CPU time 20.03 seconds
Started May 07 02:17:51 PM PDT 24
Finished May 07 02:18:11 PM PDT 24
Peak memory 234764 kb
Host smart-61048f41-c83a-4fb4-9182-2b0b1284e805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258890165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2258890165
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.353054940
Short name T325
Test name
Test status
Simulation time 510689819 ps
CPU time 7.53 seconds
Started May 07 02:26:31 PM PDT 24
Finished May 07 02:26:39 PM PDT 24
Peak memory 220060 kb
Host smart-c2c312c2-e7ff-4442-9dbc-bc79a5904ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353054940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.353054940
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2666594077
Short name T82
Test name
Test status
Simulation time 2820346146 ps
CPU time 12.13 seconds
Started May 07 02:26:21 PM PDT 24
Finished May 07 02:26:34 PM PDT 24
Peak memory 224500 kb
Host smart-d5542322-e543-4b2d-ad2a-aceb38c5566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666594077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2666594077
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2699084871
Short name T217
Test name
Test status
Simulation time 52379427995 ps
CPU time 127.71 seconds
Started May 07 02:24:17 PM PDT 24
Finished May 07 02:26:25 PM PDT 24
Peak memory 232768 kb
Host smart-97e00328-9d92-42f9-89a1-39cdcecb2d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699084871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2699084871
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_upload.320324263
Short name T261
Test name
Test status
Simulation time 3112014611 ps
CPU time 6.6 seconds
Started May 07 02:17:10 PM PDT 24
Finished May 07 02:17:18 PM PDT 24
Peak memory 221492 kb
Host smart-262f8194-7734-4015-9ddf-4788b6d29274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320324263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.320324263
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2437496607
Short name T282
Test name
Test status
Simulation time 12051412547 ps
CPU time 15.73 seconds
Started May 07 02:25:27 PM PDT 24
Finished May 07 02:25:44 PM PDT 24
Peak memory 218780 kb
Host smart-4c0460dd-1f2a-4c0f-9a86-44decc5b2aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437496607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2437496607
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3830248930
Short name T238
Test name
Test status
Simulation time 8204165340 ps
CPU time 23.44 seconds
Started May 07 02:24:35 PM PDT 24
Finished May 07 02:24:59 PM PDT 24
Peak memory 218784 kb
Host smart-e8b5a2a9-c530-4e9e-a1f3-9734a72c2227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830248930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3830248930
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2765341532
Short name T96
Test name
Test status
Simulation time 1007386651 ps
CPU time 10 seconds
Started May 07 02:18:22 PM PDT 24
Finished May 07 02:18:33 PM PDT 24
Peak memory 240652 kb
Host smart-32995e7d-f383-4308-a3d5-f59c973b0ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765341532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2765341532
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3107794318
Short name T295
Test name
Test status
Simulation time 7039338411 ps
CPU time 64.36 seconds
Started May 07 02:18:57 PM PDT 24
Finished May 07 02:20:02 PM PDT 24
Peak memory 249128 kb
Host smart-edf7ea94-735b-4d42-b9eb-3825c9fcea59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107794318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3107794318
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.730000402
Short name T55
Test name
Test status
Simulation time 40221698657 ps
CPU time 46.31 seconds
Started May 07 02:24:42 PM PDT 24
Finished May 07 02:25:29 PM PDT 24
Peak memory 219184 kb
Host smart-068b5c6d-862c-4f7c-93ca-3aa188a80e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730000402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.730000402
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1936841293
Short name T46
Test name
Test status
Simulation time 247603329 ps
CPU time 1.08 seconds
Started May 07 02:16:58 PM PDT 24
Finished May 07 02:17:00 PM PDT 24
Peak memory 235104 kb
Host smart-d1f8987b-577f-4b0b-b148-30e065aabf12
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936841293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1936841293
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2288371955
Short name T127
Test name
Test status
Simulation time 2819981347 ps
CPU time 9.99 seconds
Started May 07 02:19:23 PM PDT 24
Finished May 07 02:19:34 PM PDT 24
Peak memory 216364 kb
Host smart-92120621-73e8-4eab-a185-424d303b734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288371955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2288371955
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.198255675
Short name T205
Test name
Test status
Simulation time 1422367230 ps
CPU time 6.72 seconds
Started May 07 02:16:47 PM PDT 24
Finished May 07 02:16:54 PM PDT 24
Peak memory 218476 kb
Host smart-44ae18e8-bf4f-4d31-937a-99c953c7cb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198255675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
198255675
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4152650697
Short name T123
Test name
Test status
Simulation time 778142955 ps
CPU time 11.64 seconds
Started May 07 02:24:51 PM PDT 24
Finished May 07 02:25:03 PM PDT 24
Peak memory 232780 kb
Host smart-87b75e38-62ae-4a7c-8818-04871e68e26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152650697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4152650697
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.9023198
Short name T348
Test name
Test status
Simulation time 14130061315 ps
CPU time 37.23 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:26:22 PM PDT 24
Peak memory 223516 kb
Host smart-af9bcfdf-0bbc-40f2-ac45-bc740b436a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9023198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.9023198
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.157432470
Short name T364
Test name
Test status
Simulation time 202776807 ps
CPU time 2.65 seconds
Started May 07 02:24:50 PM PDT 24
Finished May 07 02:24:53 PM PDT 24
Peak memory 218684 kb
Host smart-28b9cfcb-d569-4f06-9946-0d18be2fd4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157432470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.157432470
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_upload.245564073
Short name T43
Test name
Test status
Simulation time 2114699234 ps
CPU time 10.05 seconds
Started May 07 02:24:47 PM PDT 24
Finished May 07 02:24:58 PM PDT 24
Peak memory 223372 kb
Host smart-4b914010-4309-40c5-9683-bfd422b0f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245564073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.245564073
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2716847633
Short name T78
Test name
Test status
Simulation time 8210891509 ps
CPU time 27.27 seconds
Started May 07 02:25:03 PM PDT 24
Finished May 07 02:25:31 PM PDT 24
Peak memory 227444 kb
Host smart-176761c1-13b7-4dbc-bdfb-152056055681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716847633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2716847633
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3723009577
Short name T102
Test name
Test status
Simulation time 2296163599 ps
CPU time 16.85 seconds
Started May 07 02:18:21 PM PDT 24
Finished May 07 02:18:39 PM PDT 24
Peak memory 219036 kb
Host smart-05c8c00c-0257-4b5b-b6a7-822e196b65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723009577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3723009577
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intercept.221498307
Short name T198
Test name
Test status
Simulation time 6569216734 ps
CPU time 12.17 seconds
Started May 07 02:25:40 PM PDT 24
Finished May 07 02:25:53 PM PDT 24
Peak memory 223804 kb
Host smart-8fddb842-75a9-48b1-9185-f07a8bf5cf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221498307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.221498307
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1773095227
Short name T214
Test name
Test status
Simulation time 7542221501 ps
CPU time 6.35 seconds
Started May 07 02:26:05 PM PDT 24
Finished May 07 02:26:13 PM PDT 24
Peak memory 216748 kb
Host smart-90b01290-fdba-4d82-bd2a-bf8db594737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773095227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1773095227
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3040406458
Short name T303
Test name
Test status
Simulation time 1402187797 ps
CPU time 8.95 seconds
Started May 07 02:24:41 PM PDT 24
Finished May 07 02:24:51 PM PDT 24
Peak memory 233872 kb
Host smart-eca91044-ae98-4dd6-b275-c218ac551522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040406458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3040406458
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2680530060
Short name T135
Test name
Test status
Simulation time 677694280 ps
CPU time 3.68 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:58 PM PDT 24
Peak memory 215420 kb
Host smart-4267cdc8-b4db-40ca-ad0a-2cb922dbb9e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680530060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2680530060
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.4198226129
Short name T196
Test name
Test status
Simulation time 1735154717 ps
CPU time 5 seconds
Started May 07 02:19:40 PM PDT 24
Finished May 07 02:19:45 PM PDT 24
Peak memory 225248 kb
Host smart-f5842173-cc1a-497a-af25-61ef74896ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198226129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.4198226129
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.805916597
Short name T272
Test name
Test status
Simulation time 9138353332 ps
CPU time 90.23 seconds
Started May 07 02:22:57 PM PDT 24
Finished May 07 02:24:28 PM PDT 24
Peak memory 234544 kb
Host smart-5cba36c4-c463-4311-a89d-b70e01deb0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805916597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.805916597
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3242182750
Short name T248
Test name
Test status
Simulation time 179346544 ps
CPU time 2.42 seconds
Started May 07 02:17:35 PM PDT 24
Finished May 07 02:17:38 PM PDT 24
Peak memory 218436 kb
Host smart-dd6ac0da-491c-4133-a154-8bde50741be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242182750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3242182750
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3037646745
Short name T294
Test name
Test status
Simulation time 37469317141 ps
CPU time 130.63 seconds
Started May 07 02:26:22 PM PDT 24
Finished May 07 02:28:34 PM PDT 24
Peak memory 249316 kb
Host smart-aa7ff209-8cd2-4e30-9c09-80890e56b3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037646745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3037646745
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1674327516
Short name T330
Test name
Test status
Simulation time 1982778798 ps
CPU time 8.68 seconds
Started May 07 02:17:16 PM PDT 24
Finished May 07 02:17:25 PM PDT 24
Peak memory 235960 kb
Host smart-62ed086e-e1a6-47df-8e70-d8f6ac370d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674327516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1674327516
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3136210180
Short name T175
Test name
Test status
Simulation time 7372019911 ps
CPU time 12.49 seconds
Started May 07 02:17:16 PM PDT 24
Finished May 07 02:17:29 PM PDT 24
Peak memory 223428 kb
Host smart-b00a8fb7-8019-4369-89e0-d4f019799c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136210180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3136210180
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2219743683
Short name T387
Test name
Test status
Simulation time 952524514 ps
CPU time 10.76 seconds
Started May 07 02:17:16 PM PDT 24
Finished May 07 02:17:27 PM PDT 24
Peak memory 216360 kb
Host smart-4d8d0984-ced6-4ef0-ad17-03893a6408d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219743683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2219743683
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1312336541
Short name T317
Test name
Test status
Simulation time 6941847634 ps
CPU time 22.83 seconds
Started May 07 02:22:47 PM PDT 24
Finished May 07 02:23:11 PM PDT 24
Peak memory 224536 kb
Host smart-81186e4e-12ce-4aec-b7e1-8c54b9a047b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312336541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1312336541
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2746024143
Short name T225
Test name
Test status
Simulation time 313367875 ps
CPU time 2.76 seconds
Started May 07 02:25:17 PM PDT 24
Finished May 07 02:25:20 PM PDT 24
Peak memory 220512 kb
Host smart-8d1920be-8799-4842-8d7e-41172827e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746024143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2746024143
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2975040529
Short name T98
Test name
Test status
Simulation time 4603241602 ps
CPU time 5.71 seconds
Started May 07 02:25:46 PM PDT 24
Finished May 07 02:25:53 PM PDT 24
Peak memory 219076 kb
Host smart-417932f3-c966-4ea1-8ce5-5d5509e3a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975040529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2975040529
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3663873534
Short name T203
Test name
Test status
Simulation time 2260784580 ps
CPU time 12.42 seconds
Started May 07 02:18:50 PM PDT 24
Finished May 07 02:19:03 PM PDT 24
Peak memory 223052 kb
Host smart-16e57223-1b33-492e-9374-8346c50b56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663873534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3663873534
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3830325286
Short name T53
Test name
Test status
Simulation time 2171044591 ps
CPU time 6.8 seconds
Started May 07 02:18:50 PM PDT 24
Finished May 07 02:18:58 PM PDT 24
Peak memory 221580 kb
Host smart-bd030fe5-dba4-4814-bced-7091f0b9b869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830325286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3830325286
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1864985272
Short name T239
Test name
Test status
Simulation time 895196561 ps
CPU time 13.72 seconds
Started May 07 02:16:45 PM PDT 24
Finished May 07 02:16:59 PM PDT 24
Peak memory 226944 kb
Host smart-9808c0ac-2819-4c97-b7ee-c65d4127c328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864985272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1864985272
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1309424697
Short name T358
Test name
Test status
Simulation time 2748461394 ps
CPU time 5.15 seconds
Started May 07 02:20:06 PM PDT 24
Finished May 07 02:20:12 PM PDT 24
Peak memory 218848 kb
Host smart-954c0afd-f52b-43e0-85b8-504ec5c7ea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309424697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1309424697
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1902523544
Short name T327
Test name
Test status
Simulation time 1076598931 ps
CPU time 13.57 seconds
Started May 07 02:20:46 PM PDT 24
Finished May 07 02:21:00 PM PDT 24
Peak memory 219384 kb
Host smart-80dccc27-28ff-4d1f-ac09-0cfeba3871a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902523544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1902523544
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4082798224
Short name T80
Test name
Test status
Simulation time 3669413093 ps
CPU time 6.74 seconds
Started May 07 02:20:46 PM PDT 24
Finished May 07 02:20:53 PM PDT 24
Peak memory 218820 kb
Host smart-868b5a18-84f8-4da1-831b-a28c025b01d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082798224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4082798224
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.479160112
Short name T298
Test name
Test status
Simulation time 3613438037 ps
CPU time 24.62 seconds
Started May 07 02:24:04 PM PDT 24
Finished May 07 02:24:30 PM PDT 24
Peak memory 254192 kb
Host smart-8f505c15-7f5e-4aae-90d0-fe863a64d4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479160112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.479160112
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3964639014
Short name T283
Test name
Test status
Simulation time 3642980941 ps
CPU time 10.63 seconds
Started May 07 02:17:34 PM PDT 24
Finished May 07 02:17:45 PM PDT 24
Peak memory 222784 kb
Host smart-679c0918-eded-4653-9df1-7252dfce98c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964639014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3964639014
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.905021902
Short name T81
Test name
Test status
Simulation time 9602987294 ps
CPU time 15.58 seconds
Started May 07 02:24:41 PM PDT 24
Finished May 07 02:24:58 PM PDT 24
Peak memory 223112 kb
Host smart-2b995033-c793-4812-b58e-b14b9dd0fec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905021902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.905021902
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1470277495
Short name T251
Test name
Test status
Simulation time 241900887 ps
CPU time 3.48 seconds
Started May 07 02:24:55 PM PDT 24
Finished May 07 02:25:00 PM PDT 24
Peak memory 223120 kb
Host smart-f318430d-4834-49aa-b117-2d590b77a3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470277495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1470277495
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2725701012
Short name T286
Test name
Test status
Simulation time 2438655730 ps
CPU time 9.32 seconds
Started May 07 02:25:02 PM PDT 24
Finished May 07 02:25:12 PM PDT 24
Peak memory 219196 kb
Host smart-9a410f2d-c90f-43d6-a4e9-f27a92983c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725701012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2725701012
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2179453321
Short name T200
Test name
Test status
Simulation time 47396526151 ps
CPU time 16.98 seconds
Started May 07 02:25:16 PM PDT 24
Finished May 07 02:25:33 PM PDT 24
Peak memory 235296 kb
Host smart-fa2fd07b-4f61-4780-b0ad-dc0be67774c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179453321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2179453321
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2453248077
Short name T83
Test name
Test status
Simulation time 7246771557 ps
CPU time 19.63 seconds
Started May 07 02:25:21 PM PDT 24
Finished May 07 02:25:41 PM PDT 24
Peak memory 223136 kb
Host smart-c2e7c29e-87d9-47c2-a838-e590182e225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453248077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2453248077
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4263848108
Short name T346
Test name
Test status
Simulation time 7537448984 ps
CPU time 22.08 seconds
Started May 07 02:25:38 PM PDT 24
Finished May 07 02:26:01 PM PDT 24
Peak memory 232424 kb
Host smart-7708f7f4-b1cd-4b7f-91ec-38d54c00e852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263848108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4263848108
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.27691542
Short name T369
Test name
Test status
Simulation time 10957940725 ps
CPU time 34.53 seconds
Started May 07 02:25:37 PM PDT 24
Finished May 07 02:26:12 PM PDT 24
Peak memory 221084 kb
Host smart-392a6fb9-ee1f-4ef5-bd48-a108bb63e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27691542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.27691542
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3390112551
Short name T212
Test name
Test status
Simulation time 2845904205 ps
CPU time 4.3 seconds
Started May 07 02:25:53 PM PDT 24
Finished May 07 02:25:58 PM PDT 24
Peak memory 220300 kb
Host smart-a10cb029-9a15-4795-8a1e-19739a821ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390112551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3390112551
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3843760443
Short name T184
Test name
Test status
Simulation time 2915523962 ps
CPU time 32.95 seconds
Started May 07 02:26:13 PM PDT 24
Finished May 07 02:26:47 PM PDT 24
Peak memory 219748 kb
Host smart-40ee8e7e-5c58-4623-92c4-63ecc9df85e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843760443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3843760443
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1322102316
Short name T181
Test name
Test status
Simulation time 1182961095 ps
CPU time 5.37 seconds
Started May 07 02:26:17 PM PDT 24
Finished May 07 02:26:23 PM PDT 24
Peak memory 222892 kb
Host smart-6127405d-b99f-43af-a288-cc2c6592b6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322102316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1322102316
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_intercept.780325630
Short name T99
Test name
Test status
Simulation time 2779584413 ps
CPU time 21.53 seconds
Started May 07 02:24:06 PM PDT 24
Finished May 07 02:24:28 PM PDT 24
Peak memory 223660 kb
Host smart-293e5e4c-0757-49da-940a-5630b0ca12cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780325630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.780325630
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3562806329
Short name T126
Test name
Test status
Simulation time 898522183 ps
CPU time 22.78 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 215204 kb
Host smart-9952a546-cd56-43fd-a557-f7e10c7dac8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562806329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3562806329
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1216890243
Short name T357
Test name
Test status
Simulation time 130128455 ps
CPU time 2.45 seconds
Started May 07 02:16:48 PM PDT 24
Finished May 07 02:16:51 PM PDT 24
Peak memory 216776 kb
Host smart-7cb4aff1-4642-4288-b286-767c5b7ca30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216890243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1216890243
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1014345218
Short name T289
Test name
Test status
Simulation time 16769207403 ps
CPU time 65.38 seconds
Started May 07 02:17:09 PM PDT 24
Finished May 07 02:18:15 PM PDT 24
Peak memory 240456 kb
Host smart-0e3b8fb1-0915-41ab-80c4-116360eda32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014345218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1014345218
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_upload.2400775959
Short name T242
Test name
Test status
Simulation time 259806623 ps
CPU time 3.2 seconds
Started May 07 02:19:27 PM PDT 24
Finished May 07 02:19:30 PM PDT 24
Peak memory 222512 kb
Host smart-10cf4484-6548-4214-bc6b-409d854f9c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400775959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2400775959
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2090641782
Short name T230
Test name
Test status
Simulation time 900973670 ps
CPU time 6.99 seconds
Started May 07 02:19:40 PM PDT 24
Finished May 07 02:19:47 PM PDT 24
Peak memory 221200 kb
Host smart-8533874c-4ecc-4e76-b96a-cdb24ac2f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090641782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2090641782
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1949945141
Short name T73
Test name
Test status
Simulation time 4115993624 ps
CPU time 4.97 seconds
Started May 07 02:20:16 PM PDT 24
Finished May 07 02:20:22 PM PDT 24
Peak memory 218632 kb
Host smart-0b1c98d6-b37e-4c78-b36a-9a7a0766188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949945141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1949945141
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.574281470
Short name T271
Test name
Test status
Simulation time 1649521224 ps
CPU time 7.3 seconds
Started May 07 02:21:23 PM PDT 24
Finished May 07 02:21:30 PM PDT 24
Peak memory 224488 kb
Host smart-fb7994ad-2ebf-40fd-8a24-8b5d032c6611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574281470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.574281470
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2926578697
Short name T84
Test name
Test status
Simulation time 1459316052 ps
CPU time 4.11 seconds
Started May 07 02:21:27 PM PDT 24
Finished May 07 02:21:32 PM PDT 24
Peak memory 222316 kb
Host smart-d94b5f9f-bee5-48fc-a73b-348fd9d242bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926578697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2926578697
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.963681315
Short name T228
Test name
Test status
Simulation time 1565563133 ps
CPU time 11.63 seconds
Started May 07 02:22:08 PM PDT 24
Finished May 07 02:22:20 PM PDT 24
Peak memory 240600 kb
Host smart-8cbd49ac-10be-4398-bf78-95079baae0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963681315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.963681315
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.157714591
Short name T8
Test name
Test status
Simulation time 1688394899 ps
CPU time 10.52 seconds
Started May 07 02:22:21 PM PDT 24
Finished May 07 02:22:32 PM PDT 24
Peak memory 223068 kb
Host smart-09e56d41-8ac5-44ec-a9bd-1e461a033c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157714591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.157714591
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.922397017
Short name T179
Test name
Test status
Simulation time 5785911000 ps
CPU time 12.06 seconds
Started May 07 02:23:05 PM PDT 24
Finished May 07 02:23:17 PM PDT 24
Peak memory 223780 kb
Host smart-df674d90-a017-49fb-91d9-3577b92b30c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922397017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.922397017
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_upload.3275324028
Short name T313
Test name
Test status
Simulation time 79727887 ps
CPU time 2.86 seconds
Started May 07 02:23:11 PM PDT 24
Finished May 07 02:23:15 PM PDT 24
Peak memory 223252 kb
Host smart-fcd60f35-3017-42ca-aaef-0f087277ce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275324028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3275324028
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1647450009
Short name T194
Test name
Test status
Simulation time 1202820596 ps
CPU time 6.47 seconds
Started May 07 02:23:25 PM PDT 24
Finished May 07 02:23:32 PM PDT 24
Peak memory 222008 kb
Host smart-88aa43b1-109c-4f40-a0e9-23aa54df1144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647450009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1647450009
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2030636297
Short name T265
Test name
Test status
Simulation time 13992156368 ps
CPU time 38.91 seconds
Started May 07 02:25:39 PM PDT 24
Finished May 07 02:26:19 PM PDT 24
Peak memory 232796 kb
Host smart-d3191f9a-b949-4bce-ab25-30b9e1b2ac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030636297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2030636297
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4240029165
Short name T354
Test name
Test status
Simulation time 5348491648 ps
CPU time 31.11 seconds
Started May 07 02:25:51 PM PDT 24
Finished May 07 02:26:23 PM PDT 24
Peak memory 218652 kb
Host smart-195639ac-cd82-4151-b7e7-e76616734354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240029165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4240029165
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2541431109
Short name T257
Test name
Test status
Simulation time 261558850 ps
CPU time 3.93 seconds
Started May 07 02:26:08 PM PDT 24
Finished May 07 02:26:13 PM PDT 24
Peak memory 222956 kb
Host smart-00951548-765e-4602-ac3e-17e7e7aa051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541431109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2541431109
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1923082742
Short name T192
Test name
Test status
Simulation time 2903448774 ps
CPU time 9.38 seconds
Started May 07 02:26:19 PM PDT 24
Finished May 07 02:26:29 PM PDT 24
Peak memory 219152 kb
Host smart-9ee9d456-86e7-4366-b216-2d41bd9a84e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923082742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1923082742
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1394573450
Short name T79
Test name
Test status
Simulation time 793948940 ps
CPU time 7.25 seconds
Started May 07 02:26:28 PM PDT 24
Finished May 07 02:26:36 PM PDT 24
Peak memory 221252 kb
Host smart-2d173706-04ff-40b7-9dde-d2a64d6e7c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394573450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1394573450
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2841702156
Short name T267
Test name
Test status
Simulation time 924029672 ps
CPU time 10.89 seconds
Started May 07 02:18:40 PM PDT 24
Finished May 07 02:18:51 PM PDT 24
Peak memory 216872 kb
Host smart-88824239-1ddc-4275-89fe-bdc4b37907af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841702156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2841702156
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3663114572
Short name T119
Test name
Test status
Simulation time 226759548 ps
CPU time 3.43 seconds
Started May 07 01:28:54 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215384 kb
Host smart-f424c3da-9c04-46b7-a2df-7bd5476ecd90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663114572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
663114572
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.178948256
Short name T128
Test name
Test status
Simulation time 6853416914 ps
CPU time 19.26 seconds
Started May 07 02:25:24 PM PDT 24
Finished May 07 02:25:44 PM PDT 24
Peak memory 237244 kb
Host smart-fa0593fe-0dd3-4b8f-a8b0-15102ea18edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178948256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.178948256
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3717292327
Short name T337
Test name
Test status
Simulation time 652375774 ps
CPU time 17.01 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215672 kb
Host smart-c516297a-2ce9-420f-bd72-63bdc7b0202d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717292327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3717292327
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2983029825
Short name T312
Test name
Test status
Simulation time 857147844 ps
CPU time 4.73 seconds
Started May 07 02:16:55 PM PDT 24
Finished May 07 02:17:00 PM PDT 24
Peak memory 223804 kb
Host smart-2e6e8326-86bc-4a6b-ba43-aeb70baee8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983029825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2983029825
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3385478848
Short name T209
Test name
Test status
Simulation time 1078946433 ps
CPU time 6.08 seconds
Started May 07 02:16:47 PM PDT 24
Finished May 07 02:16:53 PM PDT 24
Peak memory 218596 kb
Host smart-8b9ad64f-4ea9-4ae4-8c81-2a63605afbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385478848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3385478848
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.157845213
Short name T329
Test name
Test status
Simulation time 22609682893 ps
CPU time 9.79 seconds
Started May 07 02:17:20 PM PDT 24
Finished May 07 02:17:31 PM PDT 24
Peak memory 221532 kb
Host smart-5913d680-a778-43f7-bab1-598b24574cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157845213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
157845213
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3307302757
Short name T306
Test name
Test status
Simulation time 209111422 ps
CPU time 3.91 seconds
Started May 07 02:17:08 PM PDT 24
Finished May 07 02:17:12 PM PDT 24
Peak memory 222760 kb
Host smart-55aa6936-052d-4d6d-84ff-c83ebf6a4382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307302757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3307302757
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3225523657
Short name T206
Test name
Test status
Simulation time 31922367932 ps
CPU time 69.18 seconds
Started May 07 02:19:30 PM PDT 24
Finished May 07 02:20:39 PM PDT 24
Peak memory 235276 kb
Host smart-4de02742-1a9a-4eb3-866f-b19542cc3702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225523657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3225523657
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3384557306
Short name T593
Test name
Test status
Simulation time 5907928324 ps
CPU time 35.64 seconds
Started May 07 02:19:22 PM PDT 24
Finished May 07 02:19:58 PM PDT 24
Peak memory 216660 kb
Host smart-910dbedd-efcb-4866-a1a5-f409132518e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384557306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3384557306
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3576106277
Short name T285
Test name
Test status
Simulation time 4018686720 ps
CPU time 10.03 seconds
Started May 07 02:19:51 PM PDT 24
Finished May 07 02:20:02 PM PDT 24
Peak memory 218692 kb
Host smart-00a5ff76-8d82-44d8-9414-2990462050ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576106277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3576106277
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_intercept.152960845
Short name T235
Test name
Test status
Simulation time 3584724637 ps
CPU time 13.12 seconds
Started May 07 02:19:50 PM PDT 24
Finished May 07 02:20:04 PM PDT 24
Peak memory 223244 kb
Host smart-93614a37-d006-427a-a506-47829b9ca003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152960845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.152960845
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2697729055
Short name T335
Test name
Test status
Simulation time 1817930252 ps
CPU time 7.52 seconds
Started May 07 02:20:09 PM PDT 24
Finished May 07 02:20:17 PM PDT 24
Peak memory 222752 kb
Host smart-c2b96a7c-087c-42ca-a72b-18eb352dd289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697729055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2697729055
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.990910805
Short name T69
Test name
Test status
Simulation time 7585957802 ps
CPU time 100.42 seconds
Started May 07 02:20:44 PM PDT 24
Finished May 07 02:22:25 PM PDT 24
Peak memory 240100 kb
Host smart-9cbe03fb-cbaf-4a2c-bdec-be62189556d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990910805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.990910805
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.568338609
Short name T186
Test name
Test status
Simulation time 608684725 ps
CPU time 5.72 seconds
Started May 07 02:21:07 PM PDT 24
Finished May 07 02:21:13 PM PDT 24
Peak memory 218412 kb
Host smart-11572ed0-c016-4119-831e-1df2479039ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568338609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.568338609
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1203892243
Short name T245
Test name
Test status
Simulation time 522614440 ps
CPU time 6.64 seconds
Started May 07 02:21:22 PM PDT 24
Finished May 07 02:21:29 PM PDT 24
Peak memory 222964 kb
Host smart-f6403ac1-f3c9-417e-ba89-5b01e223b2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203892243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1203892243
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_upload.588971591
Short name T91
Test name
Test status
Simulation time 93926361 ps
CPU time 2.21 seconds
Started May 07 02:21:31 PM PDT 24
Finished May 07 02:21:34 PM PDT 24
Peak memory 216276 kb
Host smart-c7a0cb10-91b0-4c06-94d3-2774067dfe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588971591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.588971591
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1861758315
Short name T234
Test name
Test status
Simulation time 4010735855 ps
CPU time 7.19 seconds
Started May 07 02:22:12 PM PDT 24
Finished May 07 02:22:20 PM PDT 24
Peak memory 216804 kb
Host smart-008afac7-2b63-4152-8f5d-c0cfea69d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861758315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1861758315
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2629420463
Short name T276
Test name
Test status
Simulation time 86639423376 ps
CPU time 185.34 seconds
Started May 07 02:22:29 PM PDT 24
Finished May 07 02:25:35 PM PDT 24
Peak memory 240856 kb
Host smart-9aca1548-126f-4105-a14f-faca3a1033b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629420463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2629420463
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3940788465
Short name T318
Test name
Test status
Simulation time 514619072 ps
CPU time 3.62 seconds
Started May 07 02:22:22 PM PDT 24
Finished May 07 02:22:27 PM PDT 24
Peak memory 219012 kb
Host smart-a3f9d4ed-7817-4682-a5e7-d58243fe10aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940788465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3940788465
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2595124064
Short name T299
Test name
Test status
Simulation time 1347609673 ps
CPU time 14.16 seconds
Started May 07 02:23:30 PM PDT 24
Finished May 07 02:23:45 PM PDT 24
Peak memory 249556 kb
Host smart-8d256b59-fb44-419c-94e6-b456364dfbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595124064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2595124064
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3853452087
Short name T332
Test name
Test status
Simulation time 30527458347 ps
CPU time 18.19 seconds
Started May 07 02:23:45 PM PDT 24
Finished May 07 02:24:04 PM PDT 24
Peak memory 235304 kb
Host smart-32d0a8c7-4b0f-4ab3-a41d-54a7cb8aeae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853452087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3853452087
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.743342715
Short name T182
Test name
Test status
Simulation time 11140629078 ps
CPU time 9.79 seconds
Started May 07 02:24:04 PM PDT 24
Finished May 07 02:24:15 PM PDT 24
Peak memory 221520 kb
Host smart-f29b6d80-dd73-4679-bb93-29c7184e78a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743342715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.743342715
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2782312605
Short name T288
Test name
Test status
Simulation time 1390059563 ps
CPU time 7.72 seconds
Started May 07 02:24:23 PM PDT 24
Finished May 07 02:24:31 PM PDT 24
Peak memory 216760 kb
Host smart-e8811c02-5880-4baa-9ef8-b397994efcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782312605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2782312605
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1358898210
Short name T260
Test name
Test status
Simulation time 3548622609 ps
CPU time 14.24 seconds
Started May 07 02:24:36 PM PDT 24
Finished May 07 02:24:51 PM PDT 24
Peak memory 236576 kb
Host smart-349f1e59-8846-46f8-90dd-430b5c2a9df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358898210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1358898210
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_upload.3051436628
Short name T90
Test name
Test status
Simulation time 178687798 ps
CPU time 2.64 seconds
Started May 07 02:24:36 PM PDT 24
Finished May 07 02:24:40 PM PDT 24
Peak memory 222696 kb
Host smart-52025b2b-b5f5-4b74-abf5-4921e0310cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051436628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3051436628
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_intercept.4243697957
Short name T103
Test name
Test status
Simulation time 3632581438 ps
CPU time 16.98 seconds
Started May 07 02:17:35 PM PDT 24
Finished May 07 02:17:52 PM PDT 24
Peak memory 221120 kb
Host smart-e9db1b46-471c-46a7-802b-83b430522fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243697957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.4243697957
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1635465111
Short name T221
Test name
Test status
Simulation time 1406330193 ps
CPU time 4.16 seconds
Started May 07 02:24:55 PM PDT 24
Finished May 07 02:25:00 PM PDT 24
Peak memory 224340 kb
Host smart-0b3eb70e-04e7-4d9f-a741-4f8bd4a8f6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635465111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1635465111
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3197636961
Short name T273
Test name
Test status
Simulation time 18108105960 ps
CPU time 25.19 seconds
Started May 07 02:24:55 PM PDT 24
Finished May 07 02:25:21 PM PDT 24
Peak memory 232692 kb
Host smart-16d20ff9-dc0b-4384-84db-b013b53b39d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197636961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3197636961
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_upload.2992820974
Short name T266
Test name
Test status
Simulation time 565871158 ps
CPU time 3.26 seconds
Started May 07 02:25:03 PM PDT 24
Finished May 07 02:25:07 PM PDT 24
Peak memory 221420 kb
Host smart-6769f229-5b4a-4046-83ae-2b394eb65a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992820974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2992820974
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.604983698
Short name T336
Test name
Test status
Simulation time 39749443431 ps
CPU time 29.27 seconds
Started May 07 02:25:17 PM PDT 24
Finished May 07 02:25:47 PM PDT 24
Peak memory 233792 kb
Host smart-4b7c0378-f318-47d4-a24c-9c4b43c68cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604983698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.604983698
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1965405980
Short name T185
Test name
Test status
Simulation time 2069607640 ps
CPU time 3.75 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:25:19 PM PDT 24
Peak memory 221660 kb
Host smart-656a0220-2cee-442e-aaf7-c29a86828a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965405980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1965405980
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2389716766
Short name T301
Test name
Test status
Simulation time 4308416665 ps
CPU time 19.34 seconds
Started May 07 02:25:13 PM PDT 24
Finished May 07 02:25:33 PM PDT 24
Peak memory 234876 kb
Host smart-c951a9b7-d3bb-44d5-b4db-f2dab029ffe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389716766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2389716766
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_upload.2207715404
Short name T316
Test name
Test status
Simulation time 8901364367 ps
CPU time 17.29 seconds
Started May 07 02:25:27 PM PDT 24
Finished May 07 02:25:46 PM PDT 24
Peak memory 233028 kb
Host smart-7b6452e2-f5c2-4558-a97b-da99c63ed1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207715404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2207715404
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1643661627
Short name T244
Test name
Test status
Simulation time 1458456715 ps
CPU time 10.8 seconds
Started May 07 02:25:35 PM PDT 24
Finished May 07 02:25:47 PM PDT 24
Peak memory 222128 kb
Host smart-547961b9-a24b-49a8-8652-01d88c871338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643661627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1643661627
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_upload.2881410898
Short name T233
Test name
Test status
Simulation time 359514580 ps
CPU time 2.66 seconds
Started May 07 02:25:37 PM PDT 24
Finished May 07 02:25:40 PM PDT 24
Peak memory 222388 kb
Host smart-9ad70393-52c9-48cb-bd5d-c2807b135339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881410898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2881410898
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2337078747
Short name T319
Test name
Test status
Simulation time 5737759798 ps
CPU time 19.69 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:26:04 PM PDT 24
Peak memory 222844 kb
Host smart-10d7fcba-9cdc-42e7-89f5-bde17a8fdd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337078747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2337078747
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_upload.3283636913
Short name T220
Test name
Test status
Simulation time 570487876 ps
CPU time 8.47 seconds
Started May 07 02:25:47 PM PDT 24
Finished May 07 02:25:56 PM PDT 24
Peak memory 216372 kb
Host smart-d4c93b50-0769-4e45-8155-f7691dfa70da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283636913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3283636913
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1431084926
Short name T254
Test name
Test status
Simulation time 281473152 ps
CPU time 3.45 seconds
Started May 07 02:25:47 PM PDT 24
Finished May 07 02:25:51 PM PDT 24
Peak memory 218736 kb
Host smart-edb83a9a-52dc-4613-a119-9cbb7ff74e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431084926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1431084926
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2884390453
Short name T224
Test name
Test status
Simulation time 664582377 ps
CPU time 3.64 seconds
Started May 07 02:25:53 PM PDT 24
Finished May 07 02:25:57 PM PDT 24
Peak memory 222888 kb
Host smart-6eafee5d-7ce8-4d6e-837a-7b4dbc4e7711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884390453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2884390453
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.667594430
Short name T252
Test name
Test status
Simulation time 625263689 ps
CPU time 7.55 seconds
Started May 07 02:26:03 PM PDT 24
Finished May 07 02:26:11 PM PDT 24
Peak memory 223712 kb
Host smart-9292c6a1-0c30-459d-aa75-127b996cfb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667594430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.667594430
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.118054229
Short name T174
Test name
Test status
Simulation time 15581809191 ps
CPU time 109.17 seconds
Started May 07 02:26:14 PM PDT 24
Finished May 07 02:28:04 PM PDT 24
Peak memory 224500 kb
Host smart-f7b1d0a6-5f96-46fc-9cce-88d770721ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118054229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.118054229
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3697266120
Short name T231
Test name
Test status
Simulation time 2208064164 ps
CPU time 9.81 seconds
Started May 07 02:26:05 PM PDT 24
Finished May 07 02:26:15 PM PDT 24
Peak memory 233532 kb
Host smart-71b251db-d6e0-4bf3-b793-4dae3ae001c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697266120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3697266120
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_upload.3721017901
Short name T218
Test name
Test status
Simulation time 32724147806 ps
CPU time 23.65 seconds
Started May 07 02:26:29 PM PDT 24
Finished May 07 02:26:54 PM PDT 24
Peak memory 236800 kb
Host smart-914a53a4-5c17-42f1-aec7-9faf2daabde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721017901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3721017901
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3629350110
Short name T207
Test name
Test status
Simulation time 7689141101 ps
CPU time 22.46 seconds
Started May 07 02:18:03 PM PDT 24
Finished May 07 02:18:27 PM PDT 24
Peak memory 219232 kb
Host smart-576b8984-6e1e-4381-9ae5-2c549cd8335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629350110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3629350110
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4189476952
Short name T236
Test name
Test status
Simulation time 1246245079 ps
CPU time 3.12 seconds
Started May 07 02:18:39 PM PDT 24
Finished May 07 02:18:43 PM PDT 24
Peak memory 222752 kb
Host smart-00ffed5a-4834-494a-a20b-9b50362a7ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189476952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4189476952
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1895989590
Short name T240
Test name
Test status
Simulation time 297908761 ps
CPU time 2.99 seconds
Started May 07 02:18:37 PM PDT 24
Finished May 07 02:18:41 PM PDT 24
Peak memory 218996 kb
Host smart-da9a28db-f64c-4064-9c8d-0729206c097c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895989590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1895989590
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4049636313
Short name T86
Test name
Test status
Simulation time 1762829158 ps
CPU time 12.88 seconds
Started May 07 02:20:04 PM PDT 24
Finished May 07 02:20:17 PM PDT 24
Peak memory 232800 kb
Host smart-5f8486d4-4706-4aa4-a5b5-d7b124c29bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049636313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4049636313
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3546035358
Short name T35
Test name
Test status
Simulation time 44578534 ps
CPU time 1.44 seconds
Started May 07 01:28:54 PM PDT 24
Finished May 07 01:28:56 PM PDT 24
Peak memory 207184 kb
Host smart-2534d3fa-6f41-47ca-8ddc-7e9157581285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546035358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3546035358
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.333920415
Short name T108
Test name
Test status
Simulation time 46680643 ps
CPU time 1.36 seconds
Started May 07 01:28:52 PM PDT 24
Finished May 07 01:28:55 PM PDT 24
Peak memory 207064 kb
Host smart-9763ae00-6ab8-4372-872b-d82ca69327db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333920415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.333920415
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.694089322
Short name T617
Test name
Test status
Simulation time 11475597336 ps
CPU time 13.93 seconds
Started May 07 02:17:09 PM PDT 24
Finished May 07 02:17:23 PM PDT 24
Peak memory 224480 kb
Host smart-1261c790-22e4-4807-ba2b-1828db6de038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694089322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.694089322
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2563055360
Short name T405
Test name
Test status
Simulation time 4462795282 ps
CPU time 5.4 seconds
Started May 07 02:21:12 PM PDT 24
Finished May 07 02:21:18 PM PDT 24
Peak memory 222576 kb
Host smart-1f14461a-3303-4601-b011-09ebb3451993
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2563055360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2563055360
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1722147237
Short name T806
Test name
Test status
Simulation time 4104010542 ps
CPU time 21.41 seconds
Started May 07 01:28:39 PM PDT 24
Finished May 07 01:29:02 PM PDT 24
Peak memory 207144 kb
Host smart-86d4c72b-ae48-4bc0-870f-1503edc4ba70
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722147237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1722147237
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2043081167
Short name T152
Test name
Test status
Simulation time 190105097 ps
CPU time 11.13 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:52 PM PDT 24
Peak memory 207100 kb
Host smart-609f6ad3-cb03-425c-a3f7-59e2a2f76660
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043081167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2043081167
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.698068340
Short name T146
Test name
Test status
Simulation time 24241576 ps
CPU time 0.95 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:28:44 PM PDT 24
Peak memory 206768 kb
Host smart-5657e422-b32b-4318-89d3-513c9ddcd2a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698068340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.698068340
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.12495370
Short name T799
Test name
Test status
Simulation time 110023106 ps
CPU time 1.73 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:43 PM PDT 24
Peak memory 215476 kb
Host smart-525336f8-6b90-4882-bb4a-c74b701b1c81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12495370 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.12495370
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1166598910
Short name T157
Test name
Test status
Simulation time 21139293 ps
CPU time 1.23 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:28:44 PM PDT 24
Peak memory 215224 kb
Host smart-7b2e46f6-59e6-4369-adde-22b624f5ec62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166598910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
166598910
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.277214152
Short name T814
Test name
Test status
Simulation time 67838141 ps
CPU time 0.7 seconds
Started May 07 01:28:44 PM PDT 24
Finished May 07 01:28:45 PM PDT 24
Peak memory 203700 kb
Host smart-4c4de53f-6363-4d65-a80f-0f9a8d0c81cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277214152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.277214152
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.835335673
Short name T155
Test name
Test status
Simulation time 240081893 ps
CPU time 1.32 seconds
Started May 07 01:28:44 PM PDT 24
Finished May 07 01:28:47 PM PDT 24
Peak memory 215296 kb
Host smart-3e39d3fb-15ee-4e9c-9ab4-52bd0a100b7d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835335673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.835335673
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1598572834
Short name T726
Test name
Test status
Simulation time 36225320 ps
CPU time 0.64 seconds
Started May 07 01:28:38 PM PDT 24
Finished May 07 01:28:39 PM PDT 24
Peak memory 203888 kb
Host smart-ca1697db-d1b7-4b1b-8dc6-f87a48b7eece
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598572834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1598572834
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1692816081
Short name T159
Test name
Test status
Simulation time 59709160 ps
CPU time 3.64 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:28:46 PM PDT 24
Peak memory 215252 kb
Host smart-b536de2e-e19a-4835-a9ad-5a6bb19c448b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692816081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1692816081
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2666883611
Short name T130
Test name
Test status
Simulation time 420546085 ps
CPU time 1.83 seconds
Started May 07 01:28:38 PM PDT 24
Finished May 07 01:28:41 PM PDT 24
Peak memory 215368 kb
Host smart-44bd01b5-0d11-411b-8e89-8a1f8cb01e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666883611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
666883611
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3888799807
Short name T777
Test name
Test status
Simulation time 2750191201 ps
CPU time 14.69 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:57 PM PDT 24
Peak memory 207096 kb
Host smart-733fb309-10d5-4a27-8047-809e57d5498d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888799807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3888799807
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1546421165
Short name T154
Test name
Test status
Simulation time 1743035004 ps
CPU time 33.56 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:29:16 PM PDT 24
Peak memory 206996 kb
Host smart-77dfbcbd-8894-464d-9314-41c2457957e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546421165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1546421165
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1083940579
Short name T106
Test name
Test status
Simulation time 75417696 ps
CPU time 0.94 seconds
Started May 07 01:28:45 PM PDT 24
Finished May 07 01:28:47 PM PDT 24
Peak memory 206880 kb
Host smart-d49c43fa-5b4e-4af9-b6d3-c6d2ad3da2b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083940579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1083940579
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4233836431
Short name T819
Test name
Test status
Simulation time 204976357 ps
CPU time 2.68 seconds
Started May 07 01:28:42 PM PDT 24
Finished May 07 01:28:46 PM PDT 24
Peak memory 216396 kb
Host smart-e5577dcf-2ff9-41e7-81ae-2ce13fbf757c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233836431 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4233836431
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3010026737
Short name T161
Test name
Test status
Simulation time 190150916 ps
CPU time 2.92 seconds
Started May 07 01:28:42 PM PDT 24
Finished May 07 01:28:46 PM PDT 24
Peak memory 215212 kb
Host smart-e1396174-97a3-4ca8-8aa5-3e3aea337aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010026737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
010026737
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2792938733
Short name T731
Test name
Test status
Simulation time 42083921 ps
CPU time 0.68 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:42 PM PDT 24
Peak memory 203988 kb
Host smart-716ce502-ddf8-47f5-8f60-0561bd215294
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792938733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
792938733
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1329429730
Short name T143
Test name
Test status
Simulation time 85705289 ps
CPU time 1.98 seconds
Started May 07 01:28:39 PM PDT 24
Finished May 07 01:28:42 PM PDT 24
Peak memory 215356 kb
Host smart-108f8516-233d-44d3-a7a2-def499d6eece
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329429730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1329429730
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2295359465
Short name T801
Test name
Test status
Simulation time 10711188 ps
CPU time 0.66 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:42 PM PDT 24
Peak memory 203552 kb
Host smart-6a6f7cfe-a230-4c9a-8d31-8f8cd4a07c04
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295359465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2295359465
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2572851316
Short name T168
Test name
Test status
Simulation time 149416751 ps
CPU time 3.2 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:28:46 PM PDT 24
Peak memory 215200 kb
Host smart-a0d3b4c1-2c0e-495a-b508-cec22b19e3c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572851316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2572851316
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.499277963
Short name T132
Test name
Test status
Simulation time 550444265 ps
CPU time 3.36 seconds
Started May 07 01:28:39 PM PDT 24
Finished May 07 01:28:43 PM PDT 24
Peak memory 215416 kb
Host smart-29552944-7fc1-48bb-a87c-3f6f00ad4f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499277963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.499277963
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2207353068
Short name T164
Test name
Test status
Simulation time 301697552 ps
CPU time 7.1 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:49 PM PDT 24
Peak memory 215296 kb
Host smart-f74e9e29-1ead-438d-9176-c2c4ab7dfb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207353068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2207353068
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3495787009
Short name T763
Test name
Test status
Simulation time 357459569 ps
CPU time 2.63 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:04 PM PDT 24
Peak memory 216524 kb
Host smart-3cf8c211-6471-46f9-9928-00efdafb6bbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495787009 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3495787009
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4112689401
Short name T171
Test name
Test status
Simulation time 14286403 ps
CPU time 0.72 seconds
Started May 07 01:28:57 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 203700 kb
Host smart-bc86d638-dd17-4657-a032-b4f667c84e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112689401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4112689401
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.880622278
Short name T775
Test name
Test status
Simulation time 598100761 ps
CPU time 3.57 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215172 kb
Host smart-ae9e9fc5-9dc0-4a9c-8ab2-ccddf9fe9798
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880622278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.880622278
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1766422165
Short name T34
Test name
Test status
Simulation time 309743502 ps
CPU time 19 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 215200 kb
Host smart-f5233f49-797d-4416-a6fd-edb162afd6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766422165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1766422165
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.564085532
Short name T741
Test name
Test status
Simulation time 22900644 ps
CPU time 1.61 seconds
Started May 07 01:28:58 PM PDT 24
Finished May 07 01:29:00 PM PDT 24
Peak memory 215292 kb
Host smart-24c9106c-fc29-4429-a107-93ff97370e48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564085532 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.564085532
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4180377110
Short name T738
Test name
Test status
Simulation time 121161029 ps
CPU time 1.96 seconds
Started May 07 01:28:56 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215204 kb
Host smart-5589b8af-c684-4548-beaf-128e01363195
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180377110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4180377110
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1150510984
Short name T721
Test name
Test status
Simulation time 23410496 ps
CPU time 0.73 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:28:57 PM PDT 24
Peak memory 203688 kb
Host smart-5cf9df09-661c-47fc-8395-ecfdace71aa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150510984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1150510984
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4004475995
Short name T785
Test name
Test status
Simulation time 221907364 ps
CPU time 1.62 seconds
Started May 07 01:28:54 PM PDT 24
Finished May 07 01:28:57 PM PDT 24
Peak memory 215232 kb
Host smart-3ec07179-9e2b-4b6e-bc66-a107a0112941
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004475995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4004475995
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2850699364
Short name T793
Test name
Test status
Simulation time 1135831683 ps
CPU time 15.06 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 215640 kb
Host smart-20a251e8-ad53-4dee-bced-b47f1738b4f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850699364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2850699364
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2568425157
Short name T787
Test name
Test status
Simulation time 90446894 ps
CPU time 2.86 seconds
Started May 07 01:29:03 PM PDT 24
Finished May 07 01:29:07 PM PDT 24
Peak memory 216784 kb
Host smart-74884d86-0b8f-4592-870b-cfa62b8236a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568425157 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2568425157
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1890424677
Short name T805
Test name
Test status
Simulation time 45377865 ps
CPU time 1.56 seconds
Started May 07 01:29:04 PM PDT 24
Finished May 07 01:29:07 PM PDT 24
Peak memory 207028 kb
Host smart-1d245f02-2901-4408-be4c-171b981c704b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890424677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1890424677
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4258118269
Short name T728
Test name
Test status
Simulation time 20156980 ps
CPU time 0.77 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:04 PM PDT 24
Peak memory 203688 kb
Host smart-cf850a7d-7931-4350-8278-7477ac82c6c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258118269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4258118269
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1458469193
Short name T743
Test name
Test status
Simulation time 220420682 ps
CPU time 3.92 seconds
Started May 07 01:29:06 PM PDT 24
Finished May 07 01:29:11 PM PDT 24
Peak memory 215296 kb
Host smart-5416e045-2aa3-4ff6-8991-8e378677197b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458469193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1458469193
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.943219171
Short name T795
Test name
Test status
Simulation time 144620180 ps
CPU time 3.66 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:58 PM PDT 24
Peak memory 215348 kb
Host smart-f9d18aaf-3726-42c3-b1ef-7f228e120cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943219171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.943219171
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4095881176
Short name T736
Test name
Test status
Simulation time 256553357 ps
CPU time 7.29 seconds
Started May 07 01:28:57 PM PDT 24
Finished May 07 01:29:05 PM PDT 24
Peak memory 215608 kb
Host smart-e1df0f52-13b7-4e2a-8b9e-8d9d816068ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095881176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4095881176
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2136762913
Short name T753
Test name
Test status
Simulation time 54576818 ps
CPU time 3.51 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:05 PM PDT 24
Peak memory 217968 kb
Host smart-2ba9fd86-895a-4337-bdbf-35feba143309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136762913 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2136762913
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.605270632
Short name T142
Test name
Test status
Simulation time 45680616 ps
CPU time 1.78 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:04 PM PDT 24
Peak memory 206992 kb
Host smart-4a5205ab-35b4-419e-a923-df5a7c978c8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605270632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.605270632
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.787815875
Short name T716
Test name
Test status
Simulation time 187398766 ps
CPU time 0.75 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:03 PM PDT 24
Peak memory 204020 kb
Host smart-d0f06413-9048-4c63-9c27-1198b2f4c133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787815875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.787815875
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1197777337
Short name T156
Test name
Test status
Simulation time 77038572 ps
CPU time 1.79 seconds
Started May 07 01:28:59 PM PDT 24
Finished May 07 01:29:01 PM PDT 24
Peak memory 206980 kb
Host smart-d8a4fa59-cb02-4818-ae29-856421973db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197777337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1197777337
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1458753344
Short name T823
Test name
Test status
Simulation time 188152706 ps
CPU time 3.12 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 215668 kb
Host smart-7c17bf0d-5035-413b-bec6-037f835eb1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458753344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1458753344
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4046957881
Short name T340
Test name
Test status
Simulation time 1346852159 ps
CPU time 16.32 seconds
Started May 07 01:29:05 PM PDT 24
Finished May 07 01:29:23 PM PDT 24
Peak memory 215156 kb
Host smart-f3738cf3-d5ae-4896-badd-698f258fc316
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046957881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4046957881
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3135296578
Short name T38
Test name
Test status
Simulation time 166425542 ps
CPU time 4.18 seconds
Started May 07 01:29:05 PM PDT 24
Finished May 07 01:29:10 PM PDT 24
Peak memory 217072 kb
Host smart-a4b1e577-868c-46a0-be81-dc70697ea94f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135296578 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3135296578
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3050755872
Short name T153
Test name
Test status
Simulation time 97452783 ps
CPU time 2.5 seconds
Started May 07 01:29:03 PM PDT 24
Finished May 07 01:29:07 PM PDT 24
Peak memory 215224 kb
Host smart-cce718f1-eeec-4eb0-bda7-0db98cfabfec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050755872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3050755872
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2528515660
Short name T765
Test name
Test status
Simulation time 18934147 ps
CPU time 0.73 seconds
Started May 07 01:29:04 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 203708 kb
Host smart-7e82519b-1328-4f3e-80a1-1be8890baece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528515660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2528515660
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2674754371
Short name T733
Test name
Test status
Simulation time 398360923 ps
CPU time 2.97 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 215232 kb
Host smart-96865b96-ee14-44c9-ab7b-aca184381dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674754371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2674754371
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.505008505
Short name T755
Test name
Test status
Simulation time 127119599 ps
CPU time 4.25 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:07 PM PDT 24
Peak memory 215396 kb
Host smart-051b6a44-a866-499a-8b01-0c490cedd96a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505008505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.505008505
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2736976187
Short name T808
Test name
Test status
Simulation time 302563853 ps
CPU time 18.4 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:22 PM PDT 24
Peak memory 215192 kb
Host smart-fb03e70b-9d2a-46a4-854e-ab31bd520675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736976187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2736976187
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1500557190
Short name T789
Test name
Test status
Simulation time 149370527 ps
CPU time 2.69 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 216812 kb
Host smart-822a995f-4cca-4810-a9c4-1856d5ab8b0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500557190 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1500557190
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4118657403
Short name T796
Test name
Test status
Simulation time 331205563 ps
CPU time 2.61 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 215220 kb
Host smart-132914ef-ab29-49cd-8291-28896044e86e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118657403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4118657403
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1579852296
Short name T822
Test name
Test status
Simulation time 15107331 ps
CPU time 0.77 seconds
Started May 07 01:29:04 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 204024 kb
Host smart-dd8d64a9-3d77-487e-9b7a-292880d4cfa5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579852296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1579852296
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4164664962
Short name T160
Test name
Test status
Simulation time 174017836 ps
CPU time 3.96 seconds
Started May 07 01:29:06 PM PDT 24
Finished May 07 01:29:11 PM PDT 24
Peak memory 215284 kb
Host smart-913044dd-443f-45af-9172-d67b5a6ce851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164664962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4164664962
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.671694245
Short name T827
Test name
Test status
Simulation time 777044830 ps
CPU time 2.83 seconds
Started May 07 01:29:05 PM PDT 24
Finished May 07 01:29:09 PM PDT 24
Peak memory 215464 kb
Host smart-133ffe50-783b-42d2-b7c8-df13340afd7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671694245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.671694245
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2346864518
Short name T339
Test name
Test status
Simulation time 1218188056 ps
CPU time 18.36 seconds
Started May 07 01:29:03 PM PDT 24
Finished May 07 01:29:23 PM PDT 24
Peak memory 215248 kb
Host smart-a4903992-6d5a-44ba-94e8-e20608241451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346864518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2346864518
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3721675685
Short name T759
Test name
Test status
Simulation time 505667651 ps
CPU time 3.49 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 218092 kb
Host smart-348bee76-5c09-4469-bf96-af0c562c6a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721675685 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3721675685
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2909731101
Short name T150
Test name
Test status
Simulation time 331743908 ps
CPU time 1.72 seconds
Started May 07 01:29:06 PM PDT 24
Finished May 07 01:29:09 PM PDT 24
Peak memory 215244 kb
Host smart-ca2e7d6c-d178-4324-8942-dc725baec1d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909731101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2909731101
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2295247886
Short name T748
Test name
Test status
Simulation time 20802808 ps
CPU time 0.7 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:04 PM PDT 24
Peak memory 203712 kb
Host smart-3bc42a7b-649f-4cbe-971f-69bef8753619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295247886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2295247886
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.667404185
Short name T768
Test name
Test status
Simulation time 371639927 ps
CPU time 2.83 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 215164 kb
Host smart-9b565276-cefd-46a6-88d3-acca1ed28d05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667404185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.667404185
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2678873588
Short name T120
Test name
Test status
Simulation time 58781357 ps
CPU time 1.91 seconds
Started May 07 01:29:02 PM PDT 24
Finished May 07 01:29:05 PM PDT 24
Peak memory 215400 kb
Host smart-1c06e51b-f523-4135-9489-49a27f49c224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678873588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2678873588
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2898233153
Short name T344
Test name
Test status
Simulation time 432747242 ps
CPU time 13 seconds
Started May 07 01:29:04 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 215228 kb
Host smart-14cb9baf-f5ef-4392-962c-ede6d49be395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898233153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2898233153
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2944695854
Short name T810
Test name
Test status
Simulation time 582226103 ps
CPU time 3.85 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:20 PM PDT 24
Peak memory 217320 kb
Host smart-8edcaf83-46e4-4fc4-8cc3-2dc397150571
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944695854 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2944695854
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2770139018
Short name T781
Test name
Test status
Simulation time 28964348 ps
CPU time 1.31 seconds
Started May 07 01:29:13 PM PDT 24
Finished May 07 01:29:16 PM PDT 24
Peak memory 207072 kb
Host smart-4b28b1aa-8375-4677-a5fe-535f5b10550c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770139018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2770139018
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2663973129
Short name T779
Test name
Test status
Simulation time 13766174 ps
CPU time 0.76 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:14 PM PDT 24
Peak memory 203984 kb
Host smart-1dd05012-b0a6-4199-8b23-4f47bc655089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663973129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2663973129
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2429759249
Short name T829
Test name
Test status
Simulation time 293362657 ps
CPU time 1.86 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:14 PM PDT 24
Peak memory 215212 kb
Host smart-cabadaa7-1c66-465a-8a27-79308889fed3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429759249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2429759249
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4111437584
Short name T776
Test name
Test status
Simulation time 118720543 ps
CPU time 3.32 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 215396 kb
Host smart-e660d5fc-946d-4666-b96a-679d2943ea15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111437584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4111437584
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1237812256
Short name T816
Test name
Test status
Simulation time 603069492 ps
CPU time 19.97 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:36 PM PDT 24
Peak memory 215348 kb
Host smart-649086b1-01ce-4845-873f-e26145381169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237812256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1237812256
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2550975725
Short name T756
Test name
Test status
Simulation time 128737491 ps
CPU time 3.79 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:18 PM PDT 24
Peak memory 217220 kb
Host smart-7b263b9f-e148-441a-804a-d8501c4e1ff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550975725 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2550975725
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3035992351
Short name T811
Test name
Test status
Simulation time 35116979 ps
CPU time 2.2 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:16 PM PDT 24
Peak memory 215212 kb
Host smart-061a4c98-5ce6-4c28-b081-f5b54ad221a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035992351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3035992351
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3196254829
Short name T718
Test name
Test status
Simulation time 12533728 ps
CPU time 0.69 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:14 PM PDT 24
Peak memory 204016 kb
Host smart-59ad4059-6abf-46fa-94d1-27e4c8176af7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196254829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3196254829
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2064015804
Short name T820
Test name
Test status
Simulation time 684676034 ps
CPU time 4.08 seconds
Started May 07 01:29:10 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 215228 kb
Host smart-f28ff5a8-3a61-4294-9afd-17de97471f72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064015804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2064015804
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.965880656
Short name T788
Test name
Test status
Simulation time 109736326 ps
CPU time 6.43 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 215272 kb
Host smart-16020167-e482-4db2-b31a-399aab32f5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965880656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.965880656
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4068203464
Short name T137
Test name
Test status
Simulation time 1499076939 ps
CPU time 3.36 seconds
Started May 07 01:29:15 PM PDT 24
Finished May 07 01:29:20 PM PDT 24
Peak memory 215636 kb
Host smart-28bd3b6b-8bc4-4bc2-9188-b5f6bc70a3d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068203464 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4068203464
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.635254838
Short name T815
Test name
Test status
Simulation time 90055528 ps
CPU time 2.14 seconds
Started May 07 01:29:15 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 215244 kb
Host smart-ce280dce-d5f9-4d81-83cf-61a328609b99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635254838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.635254838
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2473374767
Short name T746
Test name
Test status
Simulation time 13018081 ps
CPU time 0.75 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:13 PM PDT 24
Peak memory 203720 kb
Host smart-6950f3ee-3399-4cc6-a7ae-bb4e120dd007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473374767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2473374767
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1295675367
Short name T737
Test name
Test status
Simulation time 323307561 ps
CPU time 3.96 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:18 PM PDT 24
Peak memory 215248 kb
Host smart-b147f90b-1391-4a2e-b7bf-01ed6ade3417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295675367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1295675367
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2788368929
Short name T134
Test name
Test status
Simulation time 689522034 ps
CPU time 4.07 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 216488 kb
Host smart-f05e306b-bf03-464e-8815-5f3f53963503
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788368929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2788368929
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1727171594
Short name T343
Test name
Test status
Simulation time 293678923 ps
CPU time 18.46 seconds
Started May 07 01:29:15 PM PDT 24
Finished May 07 01:29:36 PM PDT 24
Peak memory 215224 kb
Host smart-45088442-0879-4e1f-bdc9-968415607402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727171594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1727171594
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3445008957
Short name T149
Test name
Test status
Simulation time 209296163 ps
CPU time 14.63 seconds
Started May 07 01:28:45 PM PDT 24
Finished May 07 01:29:00 PM PDT 24
Peak memory 207076 kb
Host smart-7b77495f-9bb9-43c9-b580-760c9fc42ce9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445008957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3445008957
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.874150372
Short name T144
Test name
Test status
Simulation time 19475511497 ps
CPU time 34.91 seconds
Started May 07 01:28:42 PM PDT 24
Finished May 07 01:29:18 PM PDT 24
Peak memory 207128 kb
Host smart-dc731706-d0ba-4d6b-a1d7-d210a2bb6538
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874150372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.874150372
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1710832167
Short name T105
Test name
Test status
Simulation time 105352236 ps
CPU time 1.01 seconds
Started May 07 01:28:38 PM PDT 24
Finished May 07 01:28:40 PM PDT 24
Peak memory 206844 kb
Host smart-bc77c501-70f3-4966-a525-a1c06ef11741
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710832167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1710832167
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4034350505
Short name T771
Test name
Test status
Simulation time 127412658 ps
CPU time 3.48 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:28:46 PM PDT 24
Peak memory 216992 kb
Host smart-de3b71f0-fe42-41f1-8db4-53e55306666b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034350505 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4034350505
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2791452890
Short name T798
Test name
Test status
Simulation time 34786245 ps
CPU time 2.17 seconds
Started May 07 01:28:39 PM PDT 24
Finished May 07 01:28:42 PM PDT 24
Peak memory 207012 kb
Host smart-7ff2babb-5faa-4e8f-867d-c0d8b35e634c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791452890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
791452890
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1294406806
Short name T723
Test name
Test status
Simulation time 18940851 ps
CPU time 0.71 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:42 PM PDT 24
Peak memory 204020 kb
Host smart-39581009-3978-4ca9-a81e-e5b24437c712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294406806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
294406806
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2228674754
Short name T818
Test name
Test status
Simulation time 72625963 ps
CPU time 1.35 seconds
Started May 07 01:28:38 PM PDT 24
Finished May 07 01:28:40 PM PDT 24
Peak memory 215340 kb
Host smart-2ab64127-702a-485e-a807-91314e6f8f67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228674754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2228674754
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2621642985
Short name T720
Test name
Test status
Simulation time 12304606 ps
CPU time 0.68 seconds
Started May 07 01:28:43 PM PDT 24
Finished May 07 01:28:45 PM PDT 24
Peak memory 203904 kb
Host smart-d3cbd45c-54f2-4a65-a633-5e4619a4af56
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621642985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2621642985
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.596062703
Short name T800
Test name
Test status
Simulation time 30175100 ps
CPU time 1.89 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:28:45 PM PDT 24
Peak memory 215212 kb
Host smart-82a6a82f-09e5-4249-9875-d60c929df712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596062703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.596062703
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4214687652
Short name T136
Test name
Test status
Simulation time 167334343 ps
CPU time 3.85 seconds
Started May 07 01:28:41 PM PDT 24
Finished May 07 01:28:47 PM PDT 24
Peak memory 215424 kb
Host smart-774d19d9-e973-47ca-b3cc-b590412c3f1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214687652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
214687652
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.522841781
Short name T165
Test name
Test status
Simulation time 2502001256 ps
CPU time 8.5 seconds
Started May 07 01:28:40 PM PDT 24
Finished May 07 01:28:50 PM PDT 24
Peak memory 215320 kb
Host smart-d1d7ec02-4e5a-4d9d-bf1c-5da8ba1308d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522841781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.522841781
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4244771151
Short name T817
Test name
Test status
Simulation time 13198049 ps
CPU time 0.66 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:13 PM PDT 24
Peak memory 203708 kb
Host smart-1cc28c34-de9e-45e4-8c9e-256d2578a4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244771151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4244771151
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1286140420
Short name T735
Test name
Test status
Simulation time 11143943 ps
CPU time 0.71 seconds
Started May 07 01:29:18 PM PDT 24
Finished May 07 01:29:21 PM PDT 24
Peak memory 204004 kb
Host smart-83c15d37-1d9c-41e7-8085-e6a883ebbea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286140420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1286140420
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3092080044
Short name T782
Test name
Test status
Simulation time 15217099 ps
CPU time 0.75 seconds
Started May 07 01:29:16 PM PDT 24
Finished May 07 01:29:18 PM PDT 24
Peak memory 203672 kb
Host smart-ef5dbb91-faa2-434b-87c9-084a31963a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092080044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3092080044
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1417299991
Short name T761
Test name
Test status
Simulation time 13532854 ps
CPU time 0.69 seconds
Started May 07 01:29:13 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 203992 kb
Host smart-48194244-f6d2-4930-9227-eaaf89847672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417299991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1417299991
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.169925541
Short name T730
Test name
Test status
Simulation time 14614965 ps
CPU time 0.78 seconds
Started May 07 01:29:17 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 203984 kb
Host smart-53bfc73a-1cb5-4f86-b667-2210a7569642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169925541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.169925541
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3602447493
Short name T725
Test name
Test status
Simulation time 51776131 ps
CPU time 0.72 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 204008 kb
Host smart-3b6b795b-e7cb-40fe-9150-8caa07de0eed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602447493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3602447493
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2884672141
Short name T825
Test name
Test status
Simulation time 12817967 ps
CPU time 0.72 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:14 PM PDT 24
Peak memory 203680 kb
Host smart-789cdd95-b00a-44fd-a217-cf91c5f85c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884672141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2884672141
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4005499021
Short name T745
Test name
Test status
Simulation time 12585507 ps
CPU time 0.68 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 203696 kb
Host smart-cb38098a-6968-4b12-8e97-fca82c316789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005499021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4005499021
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2922986984
Short name T750
Test name
Test status
Simulation time 23106991 ps
CPU time 0.75 seconds
Started May 07 01:29:18 PM PDT 24
Finished May 07 01:29:21 PM PDT 24
Peak memory 203696 kb
Host smart-54439d5b-e1e1-4d56-9f44-197182dd0a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922986984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2922986984
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2764766954
Short name T791
Test name
Test status
Simulation time 52091627 ps
CPU time 0.7 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 203708 kb
Host smart-c08439d1-67a8-472b-b3a0-f9680bd27a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764766954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2764766954
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3355388943
Short name T809
Test name
Test status
Simulation time 203537415 ps
CPU time 14.2 seconds
Started May 07 01:28:47 PM PDT 24
Finished May 07 01:29:03 PM PDT 24
Peak memory 215252 kb
Host smart-cd510d4f-d050-40e8-bb0b-9ce908822fb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355388943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3355388943
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1350572081
Short name T729
Test name
Test status
Simulation time 2892626027 ps
CPU time 12.1 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:29:02 PM PDT 24
Peak memory 207176 kb
Host smart-a1bb1a47-ebd7-429d-a694-41e6320d41e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350572081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1350572081
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.4185467569
Short name T762
Test name
Test status
Simulation time 59137366 ps
CPU time 4.11 seconds
Started May 07 01:28:52 PM PDT 24
Finished May 07 01:28:57 PM PDT 24
Peak memory 217408 kb
Host smart-a2ac8c8c-7d9b-4ca1-be9d-9c794746a466
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185467569 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.4185467569
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4137687668
Short name T812
Test name
Test status
Simulation time 172564532 ps
CPU time 2.83 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:28:53 PM PDT 24
Peak memory 215268 kb
Host smart-5c8c3396-8192-4e7a-9d10-f8b85e6deaa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137687668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
137687668
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2824914606
Short name T170
Test name
Test status
Simulation time 15781308 ps
CPU time 0.79 seconds
Started May 07 01:28:51 PM PDT 24
Finished May 07 01:28:53 PM PDT 24
Peak memory 204012 kb
Host smart-7248d1ea-f142-4bb6-89de-ae4e68eba4ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824914606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
824914606
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2229378140
Short name T786
Test name
Test status
Simulation time 211045647 ps
CPU time 1.75 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:28:51 PM PDT 24
Peak memory 215460 kb
Host smart-9b9bd2bd-a4b7-4db3-8668-9ca3cd3b4257
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229378140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2229378140
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1058812680
Short name T783
Test name
Test status
Simulation time 80440153 ps
CPU time 0.66 seconds
Started May 07 01:28:47 PM PDT 24
Finished May 07 01:28:48 PM PDT 24
Peak memory 203612 kb
Host smart-25fa436b-0fa6-44a1-a146-9bae2cdabe95
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058812680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1058812680
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3122778042
Short name T158
Test name
Test status
Simulation time 235175478 ps
CPU time 3.96 seconds
Started May 07 01:28:48 PM PDT 24
Finished May 07 01:28:53 PM PDT 24
Peak memory 215156 kb
Host smart-fd1590e7-d34c-4885-b534-3b7b56ec6597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122778042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3122778042
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3308350603
Short name T794
Test name
Test status
Simulation time 23207449 ps
CPU time 1.39 seconds
Started May 07 01:28:42 PM PDT 24
Finished May 07 01:28:45 PM PDT 24
Peak memory 207160 kb
Host smart-bc91f5ca-6080-4712-9a31-a49288ea957e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308350603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
308350603
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3336131479
Short name T719
Test name
Test status
Simulation time 63646427 ps
CPU time 0.75 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 203984 kb
Host smart-ab48085a-ae35-47a3-a5ed-116c0ee56dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336131479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3336131479
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.212929394
Short name T792
Test name
Test status
Simulation time 50629205 ps
CPU time 0.72 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 203688 kb
Host smart-0622dfbd-c03a-4e4a-bc66-d8adc32d9a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212929394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.212929394
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.960959612
Short name T803
Test name
Test status
Simulation time 38330722 ps
CPU time 0.77 seconds
Started May 07 01:29:13 PM PDT 24
Finished May 07 01:29:16 PM PDT 24
Peak memory 203704 kb
Host smart-d90cfd23-4ac9-4a2e-806f-53970f9f6d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960959612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.960959612
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1502156073
Short name T742
Test name
Test status
Simulation time 15150582 ps
CPU time 0.67 seconds
Started May 07 01:29:13 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 203692 kb
Host smart-653806ce-fc0a-4bd6-9019-613c41c85e1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502156073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1502156073
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3479859581
Short name T717
Test name
Test status
Simulation time 92325797 ps
CPU time 0.68 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 203596 kb
Host smart-dc5a880a-421c-4835-bc28-71d91add806e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479859581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3479859581
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2707081709
Short name T780
Test name
Test status
Simulation time 11600890 ps
CPU time 0.69 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:13 PM PDT 24
Peak memory 203680 kb
Host smart-d13ea295-41a6-4f8e-8bd3-7b39fdb119d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707081709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2707081709
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4136052096
Short name T828
Test name
Test status
Simulation time 21953219 ps
CPU time 0.72 seconds
Started May 07 01:29:16 PM PDT 24
Finished May 07 01:29:18 PM PDT 24
Peak memory 203672 kb
Host smart-cba5560b-9d9c-4070-a12d-e24c906253e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136052096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4136052096
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.756899236
Short name T826
Test name
Test status
Simulation time 35621985 ps
CPU time 0.71 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 203700 kb
Host smart-fa83e266-60b3-4877-b916-53e39b1572c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756899236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.756899236
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.446178248
Short name T758
Test name
Test status
Simulation time 12277763 ps
CPU time 0.69 seconds
Started May 07 01:29:19 PM PDT 24
Finished May 07 01:29:21 PM PDT 24
Peak memory 204048 kb
Host smart-e84f505f-212d-4ede-b55d-f6350348657b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446178248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.446178248
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2351314516
Short name T747
Test name
Test status
Simulation time 16316440 ps
CPU time 0.76 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:13 PM PDT 24
Peak memory 203720 kb
Host smart-b3c4f4a6-5853-462a-9df4-cf5e8f14115b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351314516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2351314516
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2289263583
Short name T769
Test name
Test status
Simulation time 1464266071 ps
CPU time 15.25 seconds
Started May 07 01:28:48 PM PDT 24
Finished May 07 01:29:04 PM PDT 24
Peak memory 215188 kb
Host smart-8c2ca022-aad6-47e3-a2aa-2694720009e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289263583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2289263583
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.385703332
Short name T722
Test name
Test status
Simulation time 1232239839 ps
CPU time 25.33 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 207000 kb
Host smart-c2c51b05-6e81-4b30-8fa5-8f0f54ad904a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385703332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.385703332
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2349528442
Short name T107
Test name
Test status
Simulation time 40393701 ps
CPU time 1.3 seconds
Started May 07 01:28:48 PM PDT 24
Finished May 07 01:28:51 PM PDT 24
Peak memory 206956 kb
Host smart-6af977ad-ffb5-49b8-a2ff-c81dc830a1d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349528442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2349528442
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.102621250
Short name T138
Test name
Test status
Simulation time 64571588 ps
CPU time 1.45 seconds
Started May 07 01:28:47 PM PDT 24
Finished May 07 01:28:50 PM PDT 24
Peak memory 215256 kb
Host smart-9917e076-3356-4c7c-98be-88e26d9daf6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102621250 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.102621250
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.983081886
Short name T148
Test name
Test status
Simulation time 206920876 ps
CPU time 1.28 seconds
Started May 07 01:28:47 PM PDT 24
Finished May 07 01:28:49 PM PDT 24
Peak memory 207040 kb
Host smart-03f114c6-ab57-4be6-b78f-76d2a5c1a6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983081886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.983081886
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2143715983
Short name T824
Test name
Test status
Simulation time 27547464 ps
CPU time 0.74 seconds
Started May 07 01:28:48 PM PDT 24
Finished May 07 01:28:50 PM PDT 24
Peak memory 204000 kb
Host smart-1790f5f6-d600-488b-8448-648d83546b97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143715983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
143715983
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1663899362
Short name T754
Test name
Test status
Simulation time 57429320 ps
CPU time 2.13 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:28:52 PM PDT 24
Peak memory 215392 kb
Host smart-0f207f28-d685-4e59-a843-b7f145e883d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663899362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1663899362
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2364251325
Short name T830
Test name
Test status
Simulation time 10825643 ps
CPU time 0.64 seconds
Started May 07 01:28:48 PM PDT 24
Finished May 07 01:28:49 PM PDT 24
Peak memory 203896 kb
Host smart-027db9ba-61f5-4fca-b2f5-7aed02551d25
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364251325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2364251325
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1270881328
Short name T37
Test name
Test status
Simulation time 105536971 ps
CPU time 1.78 seconds
Started May 07 01:28:52 PM PDT 24
Finished May 07 01:28:55 PM PDT 24
Peak memory 215192 kb
Host smart-73e0135e-f5cf-483f-b62b-1160fb1f458d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270881328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1270881328
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2004525319
Short name T131
Test name
Test status
Simulation time 122390934 ps
CPU time 1.72 seconds
Started May 07 01:28:48 PM PDT 24
Finished May 07 01:28:51 PM PDT 24
Peak memory 215408 kb
Host smart-82741e8a-391b-4e24-9ecc-4f69be8c08e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004525319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
004525319
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.627705631
Short name T362
Test name
Test status
Simulation time 289360313 ps
CPU time 16.52 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:29:07 PM PDT 24
Peak memory 215192 kb
Host smart-7842a39d-abb0-4c84-aaeb-bbcba6fca507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627705631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.627705631
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2379427476
Short name T784
Test name
Test status
Simulation time 29880159 ps
CPU time 0.69 seconds
Started May 07 01:29:18 PM PDT 24
Finished May 07 01:29:21 PM PDT 24
Peak memory 204004 kb
Host smart-ff8281cd-8514-4ee1-b04e-2cf9bee97824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379427476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2379427476
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4002079015
Short name T727
Test name
Test status
Simulation time 14426393 ps
CPU time 0.69 seconds
Started May 07 01:29:17 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 203688 kb
Host smart-f040f6b8-5bd3-44ed-aba4-f9366275b8ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002079015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4002079015
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3896773059
Short name T772
Test name
Test status
Simulation time 14107235 ps
CPU time 0.73 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 203700 kb
Host smart-9de6f798-4b96-4fcb-bee4-38b147b0dc1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896773059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3896773059
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2036042068
Short name T813
Test name
Test status
Simulation time 13014908 ps
CPU time 0.73 seconds
Started May 07 01:29:11 PM PDT 24
Finished May 07 01:29:12 PM PDT 24
Peak memory 203720 kb
Host smart-7b769709-b5d6-48f1-972c-7530b4b3ed9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036042068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2036042068
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3529887577
Short name T778
Test name
Test status
Simulation time 19535878 ps
CPU time 0.67 seconds
Started May 07 01:29:13 PM PDT 24
Finished May 07 01:29:16 PM PDT 24
Peak memory 203712 kb
Host smart-904e7005-6217-4486-bfe4-1f2e0c54e855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529887577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3529887577
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3315596536
Short name T760
Test name
Test status
Simulation time 55122619 ps
CPU time 0.67 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 203700 kb
Host smart-479f25ce-cfab-44c6-a7f0-7eaa3862b9cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315596536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3315596536
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.33402815
Short name T752
Test name
Test status
Simulation time 16073527 ps
CPU time 0.73 seconds
Started May 07 01:29:12 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 203692 kb
Host smart-c9175539-d654-4bfc-acf4-7de16a58a6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33402815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.33402815
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2971947205
Short name T821
Test name
Test status
Simulation time 13515671 ps
CPU time 0.74 seconds
Started May 07 01:29:13 PM PDT 24
Finished May 07 01:29:15 PM PDT 24
Peak memory 203704 kb
Host smart-1f1eeb85-ebe3-47ce-92ea-c98d42863909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971947205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2971947205
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2156396868
Short name T732
Test name
Test status
Simulation time 13404930 ps
CPU time 0.72 seconds
Started May 07 01:29:14 PM PDT 24
Finished May 07 01:29:17 PM PDT 24
Peak memory 203692 kb
Host smart-77283938-252f-40fb-afce-d7f26557195b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156396868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2156396868
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1249685290
Short name T757
Test name
Test status
Simulation time 32946017 ps
CPU time 0.81 seconds
Started May 07 01:29:17 PM PDT 24
Finished May 07 01:29:19 PM PDT 24
Peak memory 203684 kb
Host smart-aa49eda0-510b-42ba-9861-d5b5d96b55dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249685290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1249685290
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.66851897
Short name T744
Test name
Test status
Simulation time 195292761 ps
CPU time 1.65 seconds
Started May 07 01:28:56 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215264 kb
Host smart-0924a895-affb-47a1-bd3b-a5b6e881a6e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66851897 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.66851897
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1267445549
Short name T767
Test name
Test status
Simulation time 69720660 ps
CPU time 2.03 seconds
Started May 07 01:28:56 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 218356 kb
Host smart-faa0d758-a939-4e2d-aa94-311c117279ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267445549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
267445549
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1320376520
Short name T764
Test name
Test status
Simulation time 12309936 ps
CPU time 0.74 seconds
Started May 07 01:28:52 PM PDT 24
Finished May 07 01:28:54 PM PDT 24
Peak memory 203708 kb
Host smart-0f1ff64e-209d-4e15-b520-64d0722d534c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320376520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
320376520
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3364411481
Short name T166
Test name
Test status
Simulation time 640320151 ps
CPU time 3.31 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:58 PM PDT 24
Peak memory 215180 kb
Host smart-f28a06d2-e135-469b-ac61-73831bad5426
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364411481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3364411481
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1357996352
Short name T139
Test name
Test status
Simulation time 710289811 ps
CPU time 4.46 seconds
Started May 07 01:28:49 PM PDT 24
Finished May 07 01:28:55 PM PDT 24
Peak memory 215368 kb
Host smart-d75bf711-ce89-4e1f-a59e-ca063b1cc9b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357996352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
357996352
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4204598734
Short name T342
Test name
Test status
Simulation time 1083328151 ps
CPU time 14.25 seconds
Started May 07 01:28:51 PM PDT 24
Finished May 07 01:29:06 PM PDT 24
Peak memory 216500 kb
Host smart-3eb211dc-328a-4959-a0fd-ba2cce819eef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204598734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4204598734
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1483398963
Short name T36
Test name
Test status
Simulation time 94263462 ps
CPU time 2.57 seconds
Started May 07 01:28:54 PM PDT 24
Finished May 07 01:28:58 PM PDT 24
Peak memory 216516 kb
Host smart-ae10835a-d388-43c8-a6bf-015fdaa289cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483398963 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1483398963
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1756166388
Short name T145
Test name
Test status
Simulation time 377812747 ps
CPU time 2.64 seconds
Started May 07 01:28:57 PM PDT 24
Finished May 07 01:29:01 PM PDT 24
Peak memory 215276 kb
Host smart-1a0280b7-07f4-4f5b-b2b6-55b2ff7ce786
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756166388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
756166388
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1789184959
Short name T802
Test name
Test status
Simulation time 90781080 ps
CPU time 0.68 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:28:56 PM PDT 24
Peak memory 204024 kb
Host smart-1cc7cf34-6e1e-4189-b9a9-1654f9c83d36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789184959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
789184959
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3609856608
Short name T734
Test name
Test status
Simulation time 130690274 ps
CPU time 3.05 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:05 PM PDT 24
Peak memory 215176 kb
Host smart-a665ceb1-9b41-4e48-bf25-580696158dc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609856608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3609856608
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1197369774
Short name T766
Test name
Test status
Simulation time 2248918136 ps
CPU time 14.32 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:29:08 PM PDT 24
Peak memory 215304 kb
Host smart-ddcca452-3651-4fa9-a79c-554a0240471b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197369774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1197369774
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2066475535
Short name T167
Test name
Test status
Simulation time 242307713 ps
CPU time 1.77 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:56 PM PDT 24
Peak memory 215356 kb
Host smart-0b3be7d1-3630-40f6-b689-69525317bff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066475535 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2066475535
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3201097482
Short name T773
Test name
Test status
Simulation time 39032771 ps
CPU time 1.31 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:03 PM PDT 24
Peak memory 207024 kb
Host smart-bdd05024-4e75-4ac1-9be4-50466c778a53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201097482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
201097482
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1365158620
Short name T790
Test name
Test status
Simulation time 14535855 ps
CPU time 0.72 seconds
Started May 07 01:28:52 PM PDT 24
Finished May 07 01:28:54 PM PDT 24
Peak memory 203712 kb
Host smart-1f7ed2ed-1ed3-4da7-aa54-af27ae1d05f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365158620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
365158620
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3390530032
Short name T770
Test name
Test status
Simulation time 466035903 ps
CPU time 4.14 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215192 kb
Host smart-13c3ab00-e66a-48a9-819a-8ef59637f071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390530032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3390530032
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1566169574
Short name T724
Test name
Test status
Simulation time 121592243 ps
CPU time 2.13 seconds
Started May 07 01:28:56 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215332 kb
Host smart-7a84bc59-21d1-477d-8f62-9e6e0f8e44f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566169574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
566169574
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2343929155
Short name T807
Test name
Test status
Simulation time 110067290 ps
CPU time 1.63 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:56 PM PDT 24
Peak memory 215288 kb
Host smart-57b9268d-84a2-4976-b6a1-d8d15400f558
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343929155 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2343929155
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.768375715
Short name T804
Test name
Test status
Simulation time 99120369 ps
CPU time 2.58 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215224 kb
Host smart-14e225bc-8253-4dc7-ae85-4b342bc3103d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768375715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.768375715
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3545984507
Short name T739
Test name
Test status
Simulation time 50069871 ps
CPU time 0.71 seconds
Started May 07 01:28:54 PM PDT 24
Finished May 07 01:28:56 PM PDT 24
Peak memory 204016 kb
Host smart-290ca039-9e43-432f-978d-2109eb7c7387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545984507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
545984507
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4105313988
Short name T797
Test name
Test status
Simulation time 475698852 ps
CPU time 2.5 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:57 PM PDT 24
Peak memory 215188 kb
Host smart-7c9b0c44-0a35-4c2e-b84c-ea60dff1be0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105313988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4105313988
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.836844416
Short name T133
Test name
Test status
Simulation time 55770628 ps
CPU time 3.15 seconds
Started May 07 01:28:53 PM PDT 24
Finished May 07 01:28:57 PM PDT 24
Peak memory 215388 kb
Host smart-67b85f8d-0bfd-44fc-8907-31a825fdd3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836844416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.836844416
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.9090807
Short name T338
Test name
Test status
Simulation time 6256759889 ps
CPU time 21.67 seconds
Started May 07 01:28:57 PM PDT 24
Finished May 07 01:29:20 PM PDT 24
Peak memory 215348 kb
Host smart-2916da77-7a00-4abb-b6a8-2830d2611efe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9090807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl
_intg_err.9090807
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.908783145
Short name T751
Test name
Test status
Simulation time 60186398 ps
CPU time 1.63 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:28:58 PM PDT 24
Peak memory 215252 kb
Host smart-602cb1c5-6495-450f-a6aa-92fc2ebaea7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908783145 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.908783145
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.737385303
Short name T151
Test name
Test status
Simulation time 66552136 ps
CPU time 1.2 seconds
Started May 07 01:28:55 PM PDT 24
Finished May 07 01:28:58 PM PDT 24
Peak memory 215268 kb
Host smart-41f9eece-71cf-41bf-9e73-16a40f4b61ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737385303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.737385303
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.633106109
Short name T774
Test name
Test status
Simulation time 36474770 ps
CPU time 0.68 seconds
Started May 07 01:28:54 PM PDT 24
Finished May 07 01:28:55 PM PDT 24
Peak memory 203692 kb
Host smart-c48b9453-9260-45d1-9041-00da01d64ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633106109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.633106109
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2837000052
Short name T740
Test name
Test status
Simulation time 165695389 ps
CPU time 2.73 seconds
Started May 07 01:28:56 PM PDT 24
Finished May 07 01:29:00 PM PDT 24
Peak memory 215148 kb
Host smart-58d2ac4d-33a3-4fa2-bec9-e573f2791862
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837000052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2837000052
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3580635532
Short name T749
Test name
Test status
Simulation time 153092086 ps
CPU time 1.55 seconds
Started May 07 01:29:01 PM PDT 24
Finished May 07 01:29:04 PM PDT 24
Peak memory 215380 kb
Host smart-d92c1170-992e-4484-ad1d-f0dab8c81b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580635532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
580635532
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.167832362
Short name T341
Test name
Test status
Simulation time 106060241 ps
CPU time 6.09 seconds
Started May 07 01:28:52 PM PDT 24
Finished May 07 01:28:59 PM PDT 24
Peak memory 215184 kb
Host smart-2db85ff0-086f-449f-8950-f92ea21d7dfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167832362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.167832362
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4026580979
Short name T421
Test name
Test status
Simulation time 53895920 ps
CPU time 0.79 seconds
Started May 07 02:17:03 PM PDT 24
Finished May 07 02:17:04 PM PDT 24
Peak memory 204700 kb
Host smart-aa0538f4-4e6c-44b6-ae09-a5e651725de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026580979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
026580979
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1862580263
Short name T585
Test name
Test status
Simulation time 51021212 ps
CPU time 0.8 seconds
Started May 07 02:16:40 PM PDT 24
Finished May 07 02:16:42 PM PDT 24
Peak memory 206760 kb
Host smart-5abfa135-eabd-4df8-b9d0-2e5ecfecfe9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862580263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1862580263
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.138935636
Short name T287
Test name
Test status
Simulation time 9142108456 ps
CPU time 80.13 seconds
Started May 07 02:16:53 PM PDT 24
Finished May 07 02:18:13 PM PDT 24
Peak memory 240696 kb
Host smart-4f96197d-19d8-4bad-a649-6d3e92f7f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138935636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.138935636
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2347780074
Short name T472
Test name
Test status
Simulation time 195769985 ps
CPU time 3.29 seconds
Started May 07 02:16:53 PM PDT 24
Finished May 07 02:16:57 PM PDT 24
Peak memory 219012 kb
Host smart-4b28afda-efc5-485f-b7ef-0c18bac57705
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2347780074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2347780074
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1545750766
Short name T39
Test name
Test status
Simulation time 908201614 ps
CPU time 1.04 seconds
Started May 07 02:16:56 PM PDT 24
Finished May 07 02:16:58 PM PDT 24
Peak memory 207184 kb
Host smart-f90b7ab6-af21-4b1d-83d9-3957d15a87d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545750766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1545750766
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.613598521
Short name T686
Test name
Test status
Simulation time 398450406 ps
CPU time 2.85 seconds
Started May 07 02:16:47 PM PDT 24
Finished May 07 02:16:50 PM PDT 24
Peak memory 216128 kb
Host smart-95ee2623-e718-4882-af20-366bc7fb5260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613598521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.613598521
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2243385663
Short name T398
Test name
Test status
Simulation time 908806946 ps
CPU time 1.5 seconds
Started May 07 02:16:46 PM PDT 24
Finished May 07 02:16:48 PM PDT 24
Peak memory 207780 kb
Host smart-a9057709-ef26-4fca-a0a9-841f866c67ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243385663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2243385663
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3857928040
Short name T66
Test name
Test status
Simulation time 62593835 ps
CPU time 1.18 seconds
Started May 07 02:16:47 PM PDT 24
Finished May 07 02:16:49 PM PDT 24
Peak memory 216304 kb
Host smart-cd6ffc61-98cc-4619-bd40-d2ed2e2e2a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857928040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3857928040
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.617394731
Short name T634
Test name
Test status
Simulation time 64378628 ps
CPU time 0.72 seconds
Started May 07 02:16:46 PM PDT 24
Finished May 07 02:16:48 PM PDT 24
Peak memory 205844 kb
Host smart-5247794d-d3ba-4d8e-905e-d025134a22de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617394731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.617394731
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3250977828
Short name T210
Test name
Test status
Simulation time 7728825336 ps
CPU time 16.05 seconds
Started May 07 02:16:48 PM PDT 24
Finished May 07 02:17:04 PM PDT 24
Peak memory 240604 kb
Host smart-ad183694-faf4-4bf1-b439-1dcf2fbbd3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250977828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3250977828
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4043252812
Short name T435
Test name
Test status
Simulation time 13373515 ps
CPU time 0.71 seconds
Started May 07 02:17:21 PM PDT 24
Finished May 07 02:17:22 PM PDT 24
Peak memory 205264 kb
Host smart-a3739563-3ccc-42a5-bf28-ff97e77dc032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043252812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
043252812
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1199623484
Short name T453
Test name
Test status
Simulation time 59466011 ps
CPU time 0.88 seconds
Started May 07 02:17:03 PM PDT 24
Finished May 07 02:17:04 PM PDT 24
Peak memory 206884 kb
Host smart-ee595bb4-d120-45ad-ab60-aa26c39a1020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199623484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1199623484
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3424545049
Short name T426
Test name
Test status
Simulation time 451819110 ps
CPU time 3.17 seconds
Started May 07 02:17:16 PM PDT 24
Finished May 07 02:17:20 PM PDT 24
Peak memory 218760 kb
Host smart-a52fceb7-ec82-43d3-aca4-196fdec91d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424545049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3424545049
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.4093603216
Short name T176
Test name
Test status
Simulation time 4523413858 ps
CPU time 13.93 seconds
Started May 07 02:17:08 PM PDT 24
Finished May 07 02:17:23 PM PDT 24
Peak memory 221996 kb
Host smart-f9f4a685-33fc-4766-ae06-c8d6d5f8d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093603216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4093603216
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2921174726
Short name T713
Test name
Test status
Simulation time 2486621402 ps
CPU time 9.83 seconds
Started May 07 02:17:10 PM PDT 24
Finished May 07 02:17:20 PM PDT 24
Peak memory 222024 kb
Host smart-1d052a0f-d3e9-4154-81c9-6cc068b6f7ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2921174726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2921174726
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2003713405
Short name T49
Test name
Test status
Simulation time 99700419 ps
CPU time 0.96 seconds
Started May 07 02:17:10 PM PDT 24
Finished May 07 02:17:12 PM PDT 24
Peak memory 235144 kb
Host smart-1e5e9a3e-eaac-477c-ac4b-0c2ad887c967
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003713405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2003713405
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2873902532
Short name T60
Test name
Test status
Simulation time 839681849 ps
CPU time 6.16 seconds
Started May 07 02:16:57 PM PDT 24
Finished May 07 02:17:04 PM PDT 24
Peak memory 216244 kb
Host smart-be70ce3e-e44c-4724-b091-1f90f6408a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873902532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2873902532
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1108590244
Short name T667
Test name
Test status
Simulation time 1752678908 ps
CPU time 9.32 seconds
Started May 07 02:16:58 PM PDT 24
Finished May 07 02:17:08 PM PDT 24
Peak memory 216308 kb
Host smart-d41c377c-0f6f-4d70-bf25-eb3bc31b2aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108590244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1108590244
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4236952058
Short name T62
Test name
Test status
Simulation time 30652826 ps
CPU time 1.66 seconds
Started May 07 02:17:03 PM PDT 24
Finished May 07 02:17:06 PM PDT 24
Peak memory 216300 kb
Host smart-98d8a781-479e-45af-be4f-a181ac8e47ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236952058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4236952058
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3328438842
Short name T418
Test name
Test status
Simulation time 62671274 ps
CPU time 0.86 seconds
Started May 07 02:16:58 PM PDT 24
Finished May 07 02:16:59 PM PDT 24
Peak memory 206840 kb
Host smart-f6857b58-d4b3-4f97-b530-615cd323a60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328438842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3328438842
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3057642429
Short name T568
Test name
Test status
Simulation time 173767220 ps
CPU time 0.71 seconds
Started May 07 02:19:37 PM PDT 24
Finished May 07 02:19:38 PM PDT 24
Peak memory 204776 kb
Host smart-af4d9e39-843d-44ad-ac6a-f4e7a4d9c390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057642429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3057642429
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.678697500
Short name T612
Test name
Test status
Simulation time 18192571 ps
CPU time 0.75 seconds
Started May 07 02:19:18 PM PDT 24
Finished May 07 02:19:19 PM PDT 24
Peak memory 205708 kb
Host smart-628b4b18-9d7c-4f85-b816-a66cfcce6dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678697500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.678697500
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4192910325
Short name T355
Test name
Test status
Simulation time 9871956097 ps
CPU time 41.64 seconds
Started May 07 02:19:30 PM PDT 24
Finished May 07 02:20:12 PM PDT 24
Peak memory 240976 kb
Host smart-f7454f71-24cc-4055-8f65-111b4356971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192910325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4192910325
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2800696964
Short name T100
Test name
Test status
Simulation time 2287302813 ps
CPU time 7.21 seconds
Started May 07 02:19:29 PM PDT 24
Finished May 07 02:19:37 PM PDT 24
Peak memory 219116 kb
Host smart-e39cbad7-1cd2-477b-b7a5-f46dec9b5ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800696964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2800696964
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3872520338
Short name T216
Test name
Test status
Simulation time 237052142 ps
CPU time 2.34 seconds
Started May 07 02:19:24 PM PDT 24
Finished May 07 02:19:27 PM PDT 24
Peak memory 221584 kb
Host smart-ad3ebd40-013b-4816-a1dd-78c9e46c8fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872520338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3872520338
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2921970726
Short name T249
Test name
Test status
Simulation time 11591671650 ps
CPU time 10.91 seconds
Started May 07 02:19:25 PM PDT 24
Finished May 07 02:19:36 PM PDT 24
Peak memory 223228 kb
Host smart-8211ed55-fdc8-4452-9aff-de5d63027782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921970726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2921970726
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1494871110
Short name T552
Test name
Test status
Simulation time 305822487 ps
CPU time 5.43 seconds
Started May 07 02:19:32 PM PDT 24
Finished May 07 02:19:38 PM PDT 24
Peak memory 219224 kb
Host smart-e77ef44a-0a2b-4b45-bd49-a131d3c77976
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1494871110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1494871110
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2876428691
Short name T684
Test name
Test status
Simulation time 723223992 ps
CPU time 1.84 seconds
Started May 07 02:19:22 PM PDT 24
Finished May 07 02:19:25 PM PDT 24
Peak memory 216352 kb
Host smart-17e2f5fa-5cfa-4f08-bf58-ce7b29bfcfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876428691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2876428691
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.153782332
Short name T465
Test name
Test status
Simulation time 116588661 ps
CPU time 0.99 seconds
Started May 07 02:19:24 PM PDT 24
Finished May 07 02:19:26 PM PDT 24
Peak memory 206912 kb
Host smart-413df7fd-a152-4791-abf2-deabcebb2a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153782332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.153782332
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1151198971
Short name T443
Test name
Test status
Simulation time 29814227 ps
CPU time 0.75 seconds
Started May 07 02:19:35 PM PDT 24
Finished May 07 02:19:37 PM PDT 24
Peak memory 206720 kb
Host smart-b2f370ab-329a-487b-8c3e-bd814c2f9323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151198971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1151198971
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2577571991
Short name T352
Test name
Test status
Simulation time 2603053405 ps
CPU time 49.86 seconds
Started May 07 02:19:52 PM PDT 24
Finished May 07 02:20:43 PM PDT 24
Peak memory 249180 kb
Host smart-d6ec167a-0aa1-4748-9fe3-5f23a5721aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577571991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2577571991
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1492592124
Short name T703
Test name
Test status
Simulation time 625396347 ps
CPU time 5.88 seconds
Started May 07 02:19:52 PM PDT 24
Finished May 07 02:19:59 PM PDT 24
Peak memory 220528 kb
Host smart-57022599-a73f-4303-8b4c-0b27634d35b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1492592124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1492592124
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1491182272
Short name T611
Test name
Test status
Simulation time 2890113095 ps
CPU time 38.41 seconds
Started May 07 02:19:41 PM PDT 24
Finished May 07 02:20:20 PM PDT 24
Peak memory 216328 kb
Host smart-3d46f668-5e31-4d69-923a-97dfc37a2d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491182272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1491182272
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2528601869
Short name T422
Test name
Test status
Simulation time 8483299155 ps
CPU time 29.15 seconds
Started May 07 02:19:36 PM PDT 24
Finished May 07 02:20:06 PM PDT 24
Peak memory 216256 kb
Host smart-e77fec29-45b5-4309-9e43-be982065806b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528601869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2528601869
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1628658910
Short name T622
Test name
Test status
Simulation time 86199784 ps
CPU time 2.01 seconds
Started May 07 02:19:39 PM PDT 24
Finished May 07 02:19:41 PM PDT 24
Peak memory 208156 kb
Host smart-9dbe69d1-891e-4d19-b9dc-23b92aacf149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628658910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1628658910
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1722539250
Short name T495
Test name
Test status
Simulation time 528185195 ps
CPU time 1.14 seconds
Started May 07 02:19:40 PM PDT 24
Finished May 07 02:19:42 PM PDT 24
Peak memory 206868 kb
Host smart-2a6613cc-6d49-4dfb-93a4-b94b5c5512dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722539250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1722539250
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2117463805
Short name T191
Test name
Test status
Simulation time 4892984913 ps
CPU time 19.78 seconds
Started May 07 02:19:48 PM PDT 24
Finished May 07 02:20:09 PM PDT 24
Peak memory 235176 kb
Host smart-80695b90-e369-4fa1-b4d4-58eff95fd26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117463805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2117463805
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.243542061
Short name T392
Test name
Test status
Simulation time 48002919 ps
CPU time 0.68 seconds
Started May 07 02:20:12 PM PDT 24
Finished May 07 02:20:13 PM PDT 24
Peak memory 205792 kb
Host smart-8afe16ec-b889-4423-8e24-97f8379aeadb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243542061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.243542061
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1584191983
Short name T519
Test name
Test status
Simulation time 18254358107 ps
CPU time 40.94 seconds
Started May 07 02:20:05 PM PDT 24
Finished May 07 02:20:47 PM PDT 24
Peak memory 218792 kb
Host smart-d0afaf9b-0047-4172-94f2-2ad52c771631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584191983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1584191983
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1444580546
Short name T544
Test name
Test status
Simulation time 49587845 ps
CPU time 0.8 seconds
Started May 07 02:19:52 PM PDT 24
Finished May 07 02:19:53 PM PDT 24
Peak memory 206380 kb
Host smart-5f1d55db-6913-4fb0-9a39-ce9bb5f22436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444580546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1444580546
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.150009384
Short name T77
Test name
Test status
Simulation time 45695148474 ps
CPU time 116.66 seconds
Started May 07 02:20:04 PM PDT 24
Finished May 07 02:22:02 PM PDT 24
Peak memory 250932 kb
Host smart-6ace0400-410a-49c2-b6ed-b66ce5f6f497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150009384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.150009384
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3750094378
Short name T633
Test name
Test status
Simulation time 1304252314 ps
CPU time 6.23 seconds
Started May 07 02:20:04 PM PDT 24
Finished May 07 02:20:11 PM PDT 24
Peak memory 218984 kb
Host smart-39b1e7c1-7bc7-46d4-8ba0-e14e67793730
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3750094378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3750094378
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.595528212
Short name T647
Test name
Test status
Simulation time 26996561307 ps
CPU time 35.51 seconds
Started May 07 02:19:58 PM PDT 24
Finished May 07 02:20:34 PM PDT 24
Peak memory 216368 kb
Host smart-c298960e-65c5-469e-a5dd-73502280dde0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595528212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.595528212
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3650161952
Short name T574
Test name
Test status
Simulation time 332793200 ps
CPU time 2.57 seconds
Started May 07 02:19:59 PM PDT 24
Finished May 07 02:20:03 PM PDT 24
Peak memory 216336 kb
Host smart-8c8ca066-ddbe-4fbc-9417-668aca798e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650161952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3650161952
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.384532340
Short name T499
Test name
Test status
Simulation time 61567460 ps
CPU time 1.7 seconds
Started May 07 02:19:57 PM PDT 24
Finished May 07 02:19:59 PM PDT 24
Peak memory 216276 kb
Host smart-2d74dc3c-8698-4ca4-97f2-7dc731d07706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384532340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.384532340
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.300010256
Short name T511
Test name
Test status
Simulation time 308194403 ps
CPU time 0.85 seconds
Started May 07 02:20:03 PM PDT 24
Finished May 07 02:20:04 PM PDT 24
Peak memory 206836 kb
Host smart-1a6c7782-d73f-4f35-ae56-e3fa48256dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300010256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.300010256
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.526864259
Short name T2
Test name
Test status
Simulation time 14413839 ps
CPU time 0.73 seconds
Started May 07 02:20:33 PM PDT 24
Finished May 07 02:20:35 PM PDT 24
Peak memory 205456 kb
Host smart-e4b738df-bd13-4d7d-9db0-3e8ca8abd886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526864259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.526864259
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1724924732
Short name T314
Test name
Test status
Simulation time 4842575563 ps
CPU time 10.18 seconds
Started May 07 02:20:27 PM PDT 24
Finished May 07 02:20:38 PM PDT 24
Peak memory 219020 kb
Host smart-a210081c-d7c8-4e6a-bdc2-ce4e6ca4eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724924732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1724924732
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1294743493
Short name T411
Test name
Test status
Simulation time 31240280 ps
CPU time 0.81 seconds
Started May 07 02:20:15 PM PDT 24
Finished May 07 02:20:16 PM PDT 24
Peak memory 205628 kb
Host smart-594c1916-ab4c-459d-8920-a3d960cfdea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294743493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1294743493
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1192194573
Short name T349
Test name
Test status
Simulation time 451848998 ps
CPU time 13.61 seconds
Started May 07 02:20:34 PM PDT 24
Finished May 07 02:20:48 PM PDT 24
Peak memory 249700 kb
Host smart-7a26cb58-8bb4-4629-874e-ff42ad6d0d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192194573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1192194573
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2567464090
Short name T477
Test name
Test status
Simulation time 111338666 ps
CPU time 2.42 seconds
Started May 07 02:20:23 PM PDT 24
Finished May 07 02:20:26 PM PDT 24
Peak memory 216620 kb
Host smart-1b3fb38b-6852-4a8d-82f0-ca7db1bda179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567464090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2567464090
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3464413855
Short name T410
Test name
Test status
Simulation time 823340216 ps
CPU time 16.08 seconds
Started May 07 02:20:23 PM PDT 24
Finished May 07 02:20:40 PM PDT 24
Peak memory 240544 kb
Host smart-65d5c4fa-d6a6-42e9-8f3f-2003521b026c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464413855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3464413855
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3084097996
Short name T670
Test name
Test status
Simulation time 690081833 ps
CPU time 3.65 seconds
Started May 07 02:20:16 PM PDT 24
Finished May 07 02:20:20 PM PDT 24
Peak memory 218588 kb
Host smart-4c5db5be-69fd-4b4d-b044-47463e09935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084097996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3084097996
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.654097683
Short name T508
Test name
Test status
Simulation time 683416553 ps
CPU time 3.45 seconds
Started May 07 02:20:32 PM PDT 24
Finished May 07 02:20:36 PM PDT 24
Peak memory 220264 kb
Host smart-3a560ffe-61ed-4081-a763-a1659ef5e043
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=654097683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.654097683
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1727043970
Short name T492
Test name
Test status
Simulation time 23713589613 ps
CPU time 35.04 seconds
Started May 07 02:20:13 PM PDT 24
Finished May 07 02:20:49 PM PDT 24
Peak memory 216256 kb
Host smart-cb468b48-d5ce-4dee-ba22-f643424f8a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727043970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1727043970
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2086031707
Short name T463
Test name
Test status
Simulation time 198651175 ps
CPU time 1.36 seconds
Started May 07 02:20:19 PM PDT 24
Finished May 07 02:20:21 PM PDT 24
Peak memory 208060 kb
Host smart-523e03b5-7715-4928-b28b-dd4851acf406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086031707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2086031707
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2047071220
Short name T580
Test name
Test status
Simulation time 72765747 ps
CPU time 0.93 seconds
Started May 07 02:20:17 PM PDT 24
Finished May 07 02:20:18 PM PDT 24
Peak memory 206848 kb
Host smart-07af8b00-247a-406f-b197-56db60e225b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047071220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2047071220
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3349360929
Short name T415
Test name
Test status
Simulation time 12862315 ps
CPU time 0.71 seconds
Started May 07 02:20:52 PM PDT 24
Finished May 07 02:20:53 PM PDT 24
Peak memory 205392 kb
Host smart-7bac980e-4030-493c-878d-309ef10ef739
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349360929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3349360929
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.332146118
Short name T26
Test name
Test status
Simulation time 140483582 ps
CPU time 2.21 seconds
Started May 07 02:20:48 PM PDT 24
Finished May 07 02:20:50 PM PDT 24
Peak memory 218876 kb
Host smart-e999c713-3999-44e3-860f-763f71b93916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332146118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.332146118
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3422431468
Short name T20
Test name
Test status
Simulation time 57882729 ps
CPU time 0.78 seconds
Started May 07 02:20:40 PM PDT 24
Finished May 07 02:20:42 PM PDT 24
Peak memory 206652 kb
Host smart-d5a23995-807f-4128-b0a6-d493c3ce62f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422431468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3422431468
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.186373573
Short name T76
Test name
Test status
Simulation time 95474359 ps
CPU time 2.53 seconds
Started May 07 02:20:48 PM PDT 24
Finished May 07 02:20:51 PM PDT 24
Peak memory 222296 kb
Host smart-2754cd98-af01-460d-8335-570b42029ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186373573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.186373573
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.608247569
Short name T513
Test name
Test status
Simulation time 441061006 ps
CPU time 3.6 seconds
Started May 07 02:20:40 PM PDT 24
Finished May 07 02:20:44 PM PDT 24
Peak memory 218972 kb
Host smart-c279fedd-9a27-42ee-bc7f-c5f86fd7eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608247569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.608247569
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.899874696
Short name T599
Test name
Test status
Simulation time 4594200641 ps
CPU time 9.7 seconds
Started May 07 02:20:46 PM PDT 24
Finished May 07 02:20:57 PM PDT 24
Peak memory 220064 kb
Host smart-6fb1e9b3-4c7d-4617-a020-627ffe4dcbf6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899874696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.899874696
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.591182166
Short name T543
Test name
Test status
Simulation time 1639505743 ps
CPU time 8.77 seconds
Started May 07 02:20:40 PM PDT 24
Finished May 07 02:20:49 PM PDT 24
Peak memory 216280 kb
Host smart-e50b1fab-7fba-4456-a54e-6a57c1c37796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591182166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.591182166
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2229324998
Short name T507
Test name
Test status
Simulation time 3106868064 ps
CPU time 9.69 seconds
Started May 07 02:20:40 PM PDT 24
Finished May 07 02:20:51 PM PDT 24
Peak memory 216404 kb
Host smart-7239c687-eb9e-4cf4-88bc-898dadaed15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229324998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2229324998
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2831070893
Short name T704
Test name
Test status
Simulation time 393445778 ps
CPU time 1.92 seconds
Started May 07 02:20:40 PM PDT 24
Finished May 07 02:20:42 PM PDT 24
Peak memory 216464 kb
Host smart-7ddd6a2e-983d-4f1c-8765-54550b3c6da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831070893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2831070893
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3622746202
Short name T688
Test name
Test status
Simulation time 284308244 ps
CPU time 0.91 seconds
Started May 07 02:20:40 PM PDT 24
Finished May 07 02:20:41 PM PDT 24
Peak memory 206868 kb
Host smart-8cd2a5b9-7040-4a54-acef-a53d47d6df0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622746202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3622746202
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2163001002
Short name T475
Test name
Test status
Simulation time 39693476 ps
CPU time 0.71 seconds
Started May 07 02:21:20 PM PDT 24
Finished May 07 02:21:21 PM PDT 24
Peak memory 204860 kb
Host smart-9fa02c22-115c-4d08-916c-eb8a0bb383a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163001002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2163001002
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1708281809
Short name T406
Test name
Test status
Simulation time 53286817 ps
CPU time 0.79 seconds
Started May 07 02:20:58 PM PDT 24
Finished May 07 02:21:00 PM PDT 24
Peak memory 206708 kb
Host smart-dbc2e0fe-6152-4be1-ae64-9716312472c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708281809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1708281809
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2802165519
Short name T300
Test name
Test status
Simulation time 2856364170 ps
CPU time 17.84 seconds
Started May 07 02:21:12 PM PDT 24
Finished May 07 02:21:30 PM PDT 24
Peak memory 252616 kb
Host smart-21a5c6b3-0a43-4e92-b32d-4f108780d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802165519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2802165519
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.925275799
Short name T44
Test name
Test status
Simulation time 7373543981 ps
CPU time 15.7 seconds
Started May 07 02:21:12 PM PDT 24
Finished May 07 02:21:28 PM PDT 24
Peak memory 218828 kb
Host smart-8a9bd77f-d256-47cd-aa0c-7fd208d91c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925275799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.925275799
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.436968674
Short name T229
Test name
Test status
Simulation time 16042349910 ps
CPU time 34.11 seconds
Started May 07 02:21:12 PM PDT 24
Finished May 07 02:21:47 PM PDT 24
Peak memory 224684 kb
Host smart-eaed5db5-b846-4960-9fba-caad8b805037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436968674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.436968674
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1513231784
Short name T675
Test name
Test status
Simulation time 7539039239 ps
CPU time 7.77 seconds
Started May 07 02:21:00 PM PDT 24
Finished May 07 02:21:08 PM PDT 24
Peak memory 223868 kb
Host smart-895bf3d6-dcfc-440d-9fff-5f30847d5128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513231784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1513231784
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2492256820
Short name T367
Test name
Test status
Simulation time 27756805042 ps
CPU time 41.79 seconds
Started May 07 02:20:58 PM PDT 24
Finished May 07 02:21:41 PM PDT 24
Peak memory 216328 kb
Host smart-9a5f4c01-2384-49b2-b8ee-a149f05102af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492256820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2492256820
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1173271500
Short name T521
Test name
Test status
Simulation time 9288475142 ps
CPU time 15.11 seconds
Started May 07 02:20:58 PM PDT 24
Finished May 07 02:21:13 PM PDT 24
Peak memory 216400 kb
Host smart-ea19d5f7-f0ed-4543-94ad-aee539914a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173271500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1173271500
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.170661187
Short name T613
Test name
Test status
Simulation time 110264600 ps
CPU time 3.2 seconds
Started May 07 02:20:58 PM PDT 24
Finished May 07 02:21:02 PM PDT 24
Peak memory 216372 kb
Host smart-cacc2b85-0175-4c7e-8088-7244e4f674de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170661187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.170661187
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3775088649
Short name T22
Test name
Test status
Simulation time 92873710 ps
CPU time 1.03 seconds
Started May 07 02:20:58 PM PDT 24
Finished May 07 02:21:00 PM PDT 24
Peak memory 206864 kb
Host smart-a9afe607-9536-4b95-80c5-60fe93ad3fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775088649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3775088649
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3516987875
Short name T541
Test name
Test status
Simulation time 14905529 ps
CPU time 0.7 seconds
Started May 07 02:21:37 PM PDT 24
Finished May 07 02:21:38 PM PDT 24
Peak memory 205428 kb
Host smart-39c7ec89-61ce-463d-9b07-79d9d72585f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516987875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3516987875
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3712565185
Short name T603
Test name
Test status
Simulation time 41799742 ps
CPU time 0.76 seconds
Started May 07 02:21:19 PM PDT 24
Finished May 07 02:21:20 PM PDT 24
Peak memory 206708 kb
Host smart-4cec974f-676e-4b3d-bf36-73a819536629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712565185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3712565185
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4176645667
Short name T87
Test name
Test status
Simulation time 389109836 ps
CPU time 15 seconds
Started May 07 02:21:30 PM PDT 24
Finished May 07 02:21:46 PM PDT 24
Peak memory 240828 kb
Host smart-49c08ad2-2130-48c8-b080-64ab5abe479e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176645667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4176645667
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3396611896
Short name T226
Test name
Test status
Simulation time 2024340596 ps
CPU time 6.84 seconds
Started May 07 02:21:27 PM PDT 24
Finished May 07 02:21:35 PM PDT 24
Peak memory 224336 kb
Host smart-655e0eff-8cc8-4a18-b99a-476d81907155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396611896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3396611896
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2270259947
Short name T419
Test name
Test status
Simulation time 2259451241 ps
CPU time 4.82 seconds
Started May 07 02:21:30 PM PDT 24
Finished May 07 02:21:35 PM PDT 24
Peak memory 222892 kb
Host smart-7976cfd0-4e7b-4a07-acc9-39958e82118e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2270259947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2270259947
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.216523659
Short name T666
Test name
Test status
Simulation time 215259240 ps
CPU time 1.1 seconds
Started May 07 02:21:36 PM PDT 24
Finished May 07 02:21:38 PM PDT 24
Peak memory 207464 kb
Host smart-c19572a1-a3db-40f7-908f-029275ef82fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216523659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.216523659
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.514288908
Short name T370
Test name
Test status
Simulation time 10118511938 ps
CPU time 35.08 seconds
Started May 07 02:21:27 PM PDT 24
Finished May 07 02:22:03 PM PDT 24
Peak memory 216264 kb
Host smart-b33a1c77-e064-4488-b577-491b1f2c7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514288908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.514288908
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.807755309
Short name T559
Test name
Test status
Simulation time 1986920270 ps
CPU time 7.39 seconds
Started May 07 02:21:25 PM PDT 24
Finished May 07 02:21:33 PM PDT 24
Peak memory 216252 kb
Host smart-05391fa8-220e-424e-ab09-1a1845d971ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807755309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.807755309
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1617848797
Short name T692
Test name
Test status
Simulation time 354340894 ps
CPU time 5.22 seconds
Started May 07 02:21:26 PM PDT 24
Finished May 07 02:21:32 PM PDT 24
Peak memory 216204 kb
Host smart-6142ccc6-c977-4a74-8423-599a9e1e2dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617848797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1617848797
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1316070975
Short name T532
Test name
Test status
Simulation time 113060214 ps
CPU time 0.88 seconds
Started May 07 02:21:22 PM PDT 24
Finished May 07 02:21:23 PM PDT 24
Peak memory 205844 kb
Host smart-65993484-11ec-4c5c-ae7d-fabb5e515f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316070975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1316070975
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2489890841
Short name T572
Test name
Test status
Simulation time 18361817 ps
CPU time 0.71 seconds
Started May 07 02:21:57 PM PDT 24
Finished May 07 02:21:58 PM PDT 24
Peak memory 205828 kb
Host smart-14b6aab0-8b3b-44e8-83ce-4272fb037fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489890841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2489890841
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2807946943
Short name T432
Test name
Test status
Simulation time 19845051 ps
CPU time 0.78 seconds
Started May 07 02:21:38 PM PDT 24
Finished May 07 02:21:40 PM PDT 24
Peak memory 206688 kb
Host smart-1bc1c8cd-186d-4a3f-8391-8c1fc626f091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807946943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2807946943
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2427660673
Short name T88
Test name
Test status
Simulation time 12400256282 ps
CPU time 43.9 seconds
Started May 07 02:21:57 PM PDT 24
Finished May 07 02:22:42 PM PDT 24
Peak memory 241432 kb
Host smart-2c57f376-fbe4-49dc-8097-276ac5f10c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427660673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2427660673
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4064676857
Short name T124
Test name
Test status
Simulation time 3809585785 ps
CPU time 39.17 seconds
Started May 07 02:21:50 PM PDT 24
Finished May 07 02:22:30 PM PDT 24
Peak memory 232744 kb
Host smart-2dcbfcfe-986e-4a78-9a00-6b8b1848a009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064676857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4064676857
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3916304060
Short name T328
Test name
Test status
Simulation time 17847613994 ps
CPU time 9.99 seconds
Started May 07 02:21:48 PM PDT 24
Finished May 07 02:21:59 PM PDT 24
Peak memory 232364 kb
Host smart-8db25232-f61c-4f99-8c94-4e841e20945d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916304060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3916304060
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1650082594
Short name T315
Test name
Test status
Simulation time 18780579617 ps
CPU time 25.82 seconds
Started May 07 02:21:44 PM PDT 24
Finished May 07 02:22:10 PM PDT 24
Peak memory 232824 kb
Host smart-5c8bef88-c064-4ec8-93dc-14914dc9bc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650082594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1650082594
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.582547757
Short name T639
Test name
Test status
Simulation time 15817292113 ps
CPU time 9.34 seconds
Started May 07 02:21:56 PM PDT 24
Finished May 07 02:22:06 PM PDT 24
Peak memory 220652 kb
Host smart-25dd04d0-c4c9-4819-84a7-f522e58e2fa0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=582547757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.582547757
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1999907166
Short name T714
Test name
Test status
Simulation time 1617279627 ps
CPU time 9.7 seconds
Started May 07 02:21:37 PM PDT 24
Finished May 07 02:21:47 PM PDT 24
Peak memory 216276 kb
Host smart-97003788-f264-4dc2-ae37-ce5dcc5b8c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999907166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1999907166
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.878716348
Short name T539
Test name
Test status
Simulation time 34596545136 ps
CPU time 22.65 seconds
Started May 07 02:21:36 PM PDT 24
Finished May 07 02:22:00 PM PDT 24
Peak memory 216412 kb
Host smart-16061862-d48e-4bd3-b7f4-05281d8f851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878716348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.878716348
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1497431237
Short name T680
Test name
Test status
Simulation time 52855113 ps
CPU time 1.25 seconds
Started May 07 02:21:43 PM PDT 24
Finished May 07 02:21:45 PM PDT 24
Peak memory 216360 kb
Host smart-df6f4e53-b15a-4414-83d8-e25bacfaa677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497431237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1497431237
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1106004220
Short name T677
Test name
Test status
Simulation time 55290358 ps
CPU time 0.76 seconds
Started May 07 02:21:44 PM PDT 24
Finished May 07 02:21:45 PM PDT 24
Peak memory 205804 kb
Host smart-d531fb37-35ab-4cdd-a623-889d3163e5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106004220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1106004220
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1816869810
Short name T183
Test name
Test status
Simulation time 17161837799 ps
CPU time 18.2 seconds
Started May 07 02:21:50 PM PDT 24
Finished May 07 02:22:09 PM PDT 24
Peak memory 233332 kb
Host smart-f197f47a-20ff-4f0d-9a00-a031d79ebd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816869810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1816869810
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.342890590
Short name T427
Test name
Test status
Simulation time 21966147 ps
CPU time 0.69 seconds
Started May 07 02:22:15 PM PDT 24
Finished May 07 02:22:17 PM PDT 24
Peak memory 204832 kb
Host smart-1a129934-b1c2-4d5e-82cd-6d9950c66380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342890590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.342890590
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1844033503
Short name T626
Test name
Test status
Simulation time 36728906 ps
CPU time 0.8 seconds
Started May 07 02:21:57 PM PDT 24
Finished May 07 02:21:58 PM PDT 24
Peak memory 206744 kb
Host smart-b44aa214-d980-4032-b5ed-137f187cc63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844033503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1844033503
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3165922422
Short name T565
Test name
Test status
Simulation time 1429586783 ps
CPU time 17.27 seconds
Started May 07 02:22:09 PM PDT 24
Finished May 07 02:22:27 PM PDT 24
Peak memory 249112 kb
Host smart-e49b9012-3bd6-43fc-b3ee-5c41e04f458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165922422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3165922422
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2911231778
Short name T204
Test name
Test status
Simulation time 3639540465 ps
CPU time 33.66 seconds
Started May 07 02:22:10 PM PDT 24
Finished May 07 02:22:44 PM PDT 24
Peak memory 235652 kb
Host smart-3c1024b6-2725-44bb-86b6-ea1e9727cf43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911231778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2911231778
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2065695545
Short name T412
Test name
Test status
Simulation time 112353704 ps
CPU time 3.88 seconds
Started May 07 02:22:16 PM PDT 24
Finished May 07 02:22:20 PM PDT 24
Peak memory 223112 kb
Host smart-eb71e7ec-e401-44bf-ac95-ab4f05a6558b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2065695545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2065695545
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2953289089
Short name T380
Test name
Test status
Simulation time 8143665128 ps
CPU time 33.93 seconds
Started May 07 02:22:03 PM PDT 24
Finished May 07 02:22:37 PM PDT 24
Peak memory 216420 kb
Host smart-c264550f-9d10-41f1-a507-cc00055ba811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953289089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2953289089
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3941324285
Short name T486
Test name
Test status
Simulation time 1025402922 ps
CPU time 6.48 seconds
Started May 07 02:22:07 PM PDT 24
Finished May 07 02:22:14 PM PDT 24
Peak memory 216312 kb
Host smart-0924f689-f43f-4aac-8842-43f17cf7d200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941324285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3941324285
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.543699868
Short name T489
Test name
Test status
Simulation time 137117354 ps
CPU time 2 seconds
Started May 07 02:22:08 PM PDT 24
Finished May 07 02:22:11 PM PDT 24
Peak memory 216340 kb
Host smart-9b3d41e2-6b85-49a6-b628-f4a6484b5037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543699868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.543699868
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.959004978
Short name T461
Test name
Test status
Simulation time 292753877 ps
CPU time 0.92 seconds
Started May 07 02:22:04 PM PDT 24
Finished May 07 02:22:05 PM PDT 24
Peak memory 205740 kb
Host smart-2a680384-d0f3-40f1-adcd-5aea4abbed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959004978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.959004978
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1813757108
Short name T456
Test name
Test status
Simulation time 62814997 ps
CPU time 0.7 seconds
Started May 07 02:22:41 PM PDT 24
Finished May 07 02:22:42 PM PDT 24
Peak memory 205420 kb
Host smart-bc5113a0-2ceb-4181-9670-99717d6edcbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813757108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1813757108
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2695739481
Short name T672
Test name
Test status
Simulation time 56114747 ps
CPU time 0.76 seconds
Started May 07 02:22:20 PM PDT 24
Finished May 07 02:22:22 PM PDT 24
Peak memory 205684 kb
Host smart-ea96d300-3b73-49ed-8c13-20a3e02f483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695739481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2695739481
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.545594603
Short name T620
Test name
Test status
Simulation time 6538278947 ps
CPU time 18.2 seconds
Started May 07 02:22:35 PM PDT 24
Finished May 07 02:22:55 PM PDT 24
Peak memory 249216 kb
Host smart-65bb6e9e-b99d-4b70-a5e6-5005fa752edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545594603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.545594603
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4188558654
Short name T482
Test name
Test status
Simulation time 3690714229 ps
CPU time 11.11 seconds
Started May 07 02:22:33 PM PDT 24
Finished May 07 02:22:46 PM PDT 24
Peak memory 220400 kb
Host smart-912c6fec-f066-4a34-9b8b-16b67fafef52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4188558654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4188558654
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4279820272
Short name T661
Test name
Test status
Simulation time 49750590 ps
CPU time 1.07 seconds
Started May 07 02:22:34 PM PDT 24
Finished May 07 02:22:36 PM PDT 24
Peak memory 207400 kb
Host smart-e91b8f6f-be63-4a7f-9c87-26953901dbea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279820272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4279820272
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.744018929
Short name T596
Test name
Test status
Simulation time 7438389950 ps
CPU time 41.8 seconds
Started May 07 02:22:21 PM PDT 24
Finished May 07 02:23:04 PM PDT 24
Peak memory 221316 kb
Host smart-d045280d-ecb1-4663-83ed-3b39ec982fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744018929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.744018929
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1739872814
Short name T523
Test name
Test status
Simulation time 38469966340 ps
CPU time 12.68 seconds
Started May 07 02:22:23 PM PDT 24
Finished May 07 02:22:36 PM PDT 24
Peak memory 216396 kb
Host smart-9572384e-e034-4166-8310-4487cd051e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739872814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1739872814
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3618489495
Short name T621
Test name
Test status
Simulation time 1985513597 ps
CPU time 4.66 seconds
Started May 07 02:22:22 PM PDT 24
Finished May 07 02:22:28 PM PDT 24
Peak memory 216252 kb
Host smart-e91fa20f-538a-4796-919a-93499fa6099b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618489495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3618489495
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4277255687
Short name T635
Test name
Test status
Simulation time 124894006 ps
CPU time 0.78 seconds
Started May 07 02:22:21 PM PDT 24
Finished May 07 02:22:23 PM PDT 24
Peak memory 205820 kb
Host smart-5755f9c3-cda0-470c-96a7-9f204be0a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277255687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4277255687
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.388535188
Short name T454
Test name
Test status
Simulation time 21717901 ps
CPU time 0.72 seconds
Started May 07 02:17:27 PM PDT 24
Finished May 07 02:17:28 PM PDT 24
Peak memory 205440 kb
Host smart-d4aacfad-59d0-49d6-a8d4-58f48ee19f7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388535188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.388535188
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3933297717
Short name T110
Test name
Test status
Simulation time 25583032499 ps
CPU time 25.44 seconds
Started May 07 02:17:20 PM PDT 24
Finished May 07 02:17:46 PM PDT 24
Peak memory 219084 kb
Host smart-8082c1d1-454d-4ef1-822d-3b147089a4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933297717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3933297717
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2753480444
Short name T542
Test name
Test status
Simulation time 13923054 ps
CPU time 0.83 seconds
Started May 07 02:17:13 PM PDT 24
Finished May 07 02:17:14 PM PDT 24
Peak memory 207056 kb
Host smart-8604f0cb-bfa2-47d0-b872-4a886928b5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753480444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2753480444
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1459037289
Short name T522
Test name
Test status
Simulation time 10026543344 ps
CPU time 77.48 seconds
Started May 07 02:17:24 PM PDT 24
Finished May 07 02:18:42 PM PDT 24
Peak memory 249196 kb
Host smart-e2139a2c-21df-4d64-a40d-2cbfdc60adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459037289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1459037289
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.202833276
Short name T253
Test name
Test status
Simulation time 35685975095 ps
CPU time 33.96 seconds
Started May 07 02:17:14 PM PDT 24
Finished May 07 02:17:48 PM PDT 24
Peak memory 232728 kb
Host smart-3f5c82af-eaac-4324-a936-da31489190ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202833276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.202833276
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1829046283
Short name T269
Test name
Test status
Simulation time 2637131874 ps
CPU time 8.79 seconds
Started May 07 02:17:16 PM PDT 24
Finished May 07 02:17:26 PM PDT 24
Peak memory 219008 kb
Host smart-2496f0b1-af0b-43e5-89cb-a30896da0d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829046283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1829046283
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1961776425
Short name T408
Test name
Test status
Simulation time 7738069425 ps
CPU time 6.6 seconds
Started May 07 02:17:22 PM PDT 24
Finished May 07 02:17:29 PM PDT 24
Peak memory 220092 kb
Host smart-91760b10-3f0a-48cf-92c9-092fed7a32d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1961776425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1961776425
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1823542848
Short name T48
Test name
Test status
Simulation time 125266336 ps
CPU time 0.93 seconds
Started May 07 02:17:31 PM PDT 24
Finished May 07 02:17:32 PM PDT 24
Peak memory 235012 kb
Host smart-c1bcd0ea-4a53-43d6-8c4c-ce5f9aac9727
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823542848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1823542848
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2317978297
Short name T536
Test name
Test status
Simulation time 1541484640 ps
CPU time 9.3 seconds
Started May 07 02:17:16 PM PDT 24
Finished May 07 02:17:26 PM PDT 24
Peak memory 216284 kb
Host smart-538d9d09-802b-4aa8-ac5f-b1468cbb62a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317978297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2317978297
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1625137385
Short name T570
Test name
Test status
Simulation time 63918981 ps
CPU time 0.78 seconds
Started May 07 02:17:16 PM PDT 24
Finished May 07 02:17:17 PM PDT 24
Peak memory 205832 kb
Host smart-5edb41bc-cbec-4d44-a03a-bfc6f83ead3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625137385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1625137385
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.540865021
Short name T441
Test name
Test status
Simulation time 238444482 ps
CPU time 0.99 seconds
Started May 07 02:17:15 PM PDT 24
Finished May 07 02:17:17 PM PDT 24
Peak memory 206824 kb
Host smart-fcec28d5-1ffa-4495-a1be-5ef654af2f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540865021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.540865021
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2998458239
Short name T529
Test name
Test status
Simulation time 13971905 ps
CPU time 0.68 seconds
Started May 07 02:22:58 PM PDT 24
Finished May 07 02:22:59 PM PDT 24
Peak memory 205340 kb
Host smart-88fa7732-8c60-4302-9d47-ae93c507dee4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998458239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2998458239
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4277035129
Short name T582
Test name
Test status
Simulation time 17325228 ps
CPU time 0.77 seconds
Started May 07 02:22:40 PM PDT 24
Finished May 07 02:22:41 PM PDT 24
Peak memory 207036 kb
Host smart-e5572e65-305b-48d7-88b0-8265a405177b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277035129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4277035129
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1871321934
Short name T550
Test name
Test status
Simulation time 920708909 ps
CPU time 19.96 seconds
Started May 07 02:22:58 PM PDT 24
Finished May 07 02:23:19 PM PDT 24
Peak memory 249052 kb
Host smart-3ee4f7a4-ccca-483c-bdc2-739282d60d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871321934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1871321934
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2461410723
Short name T557
Test name
Test status
Simulation time 358242094 ps
CPU time 5.63 seconds
Started May 07 02:22:59 PM PDT 24
Finished May 07 02:23:05 PM PDT 24
Peak memory 220672 kb
Host smart-c52a698f-6001-4870-948d-cb05117f2d33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2461410723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2461410723
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.969684660
Short name T595
Test name
Test status
Simulation time 8477539471 ps
CPU time 26.62 seconds
Started May 07 02:22:39 PM PDT 24
Finished May 07 02:23:07 PM PDT 24
Peak memory 216416 kb
Host smart-3472aefa-1997-4b9e-8474-58da8bb7d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969684660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.969684660
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1018556574
Short name T535
Test name
Test status
Simulation time 25255497839 ps
CPU time 14.53 seconds
Started May 07 02:22:41 PM PDT 24
Finished May 07 02:22:56 PM PDT 24
Peak memory 216304 kb
Host smart-5f8b58ef-08ef-49d5-8133-147eb33da4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018556574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1018556574
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2550783238
Short name T451
Test name
Test status
Simulation time 209261913 ps
CPU time 1.52 seconds
Started May 07 02:22:48 PM PDT 24
Finished May 07 02:22:51 PM PDT 24
Peak memory 216204 kb
Host smart-074cb02d-60ee-4fe9-9e25-f985d4232ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550783238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2550783238
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.207676725
Short name T469
Test name
Test status
Simulation time 231261664 ps
CPU time 0.82 seconds
Started May 07 02:22:47 PM PDT 24
Finished May 07 02:22:48 PM PDT 24
Peak memory 205816 kb
Host smart-9b51ab50-bf40-4fa4-99b6-dfe58856493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207676725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.207676725
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.914065806
Short name T11
Test name
Test status
Simulation time 115521946881 ps
CPU time 19.87 seconds
Started May 07 02:22:54 PM PDT 24
Finished May 07 02:23:15 PM PDT 24
Peak memory 218416 kb
Host smart-f8dfef6d-8812-46be-a66f-5c90e5614651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914065806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.914065806
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1965931840
Short name T395
Test name
Test status
Simulation time 11818751 ps
CPU time 0.72 seconds
Started May 07 02:23:19 PM PDT 24
Finished May 07 02:23:21 PM PDT 24
Peak memory 205440 kb
Host smart-cb227a80-0609-4d1a-8fd0-d3831258758e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965931840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1965931840
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4253062083
Short name T256
Test name
Test status
Simulation time 2623649304 ps
CPU time 19.72 seconds
Started May 07 02:23:10 PM PDT 24
Finished May 07 02:23:31 PM PDT 24
Peak memory 224628 kb
Host smart-4f29eded-9a2d-4375-8c6c-953c2d253f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253062083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4253062083
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3644014143
Short name T438
Test name
Test status
Simulation time 14844554 ps
CPU time 0.85 seconds
Started May 07 02:23:05 PM PDT 24
Finished May 07 02:23:07 PM PDT 24
Peak memory 206692 kb
Host smart-f1fed0f1-36b3-4431-8338-dab071d53f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644014143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3644014143
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1946516926
Short name T619
Test name
Test status
Simulation time 1797815745 ps
CPU time 13.59 seconds
Started May 07 02:23:10 PM PDT 24
Finished May 07 02:23:25 PM PDT 24
Peak memory 222916 kb
Host smart-737df5bd-92bc-4f15-b8e8-24c407864ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946516926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1946516926
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1316973924
Short name T56
Test name
Test status
Simulation time 14050996999 ps
CPU time 16.92 seconds
Started May 07 02:23:10 PM PDT 24
Finished May 07 02:23:28 PM PDT 24
Peak memory 232804 kb
Host smart-b3d749a8-3fcd-4f3a-b604-0a2d049c28ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316973924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1316973924
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3785193548
Short name T333
Test name
Test status
Simulation time 372960400 ps
CPU time 3.37 seconds
Started May 07 02:23:11 PM PDT 24
Finished May 07 02:23:15 PM PDT 24
Peak memory 218688 kb
Host smart-2c8d9af3-b247-4ec0-b91d-e48cae1c2497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785193548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3785193548
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.170494356
Short name T6
Test name
Test status
Simulation time 2610161458 ps
CPU time 5.36 seconds
Started May 07 02:23:11 PM PDT 24
Finished May 07 02:23:18 PM PDT 24
Peak memory 223084 kb
Host smart-a1a089f4-95dd-42e2-995c-268082736e71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=170494356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.170494356
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3086473686
Short name T417
Test name
Test status
Simulation time 913404070 ps
CPU time 3.08 seconds
Started May 07 02:23:03 PM PDT 24
Finished May 07 02:23:07 PM PDT 24
Peak memory 216308 kb
Host smart-59ce4ae5-b04f-41dc-af06-b9f32251adfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086473686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3086473686
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.995584347
Short name T64
Test name
Test status
Simulation time 179052550 ps
CPU time 1.47 seconds
Started May 07 02:23:05 PM PDT 24
Finished May 07 02:23:07 PM PDT 24
Peak memory 216192 kb
Host smart-014dde27-4413-4676-a40a-78a4efa2863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995584347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.995584347
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3589309124
Short name T58
Test name
Test status
Simulation time 199463653 ps
CPU time 1.19 seconds
Started May 07 02:23:03 PM PDT 24
Finished May 07 02:23:05 PM PDT 24
Peak memory 206836 kb
Host smart-636e6d83-c114-4654-8861-5e60c64f483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589309124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3589309124
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3755254402
Short name T31
Test name
Test status
Simulation time 36958903 ps
CPU time 0.71 seconds
Started May 07 02:23:45 PM PDT 24
Finished May 07 02:23:46 PM PDT 24
Peak memory 204876 kb
Host smart-d1643ea2-0ca3-4cf0-969d-e9b1d35a565b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755254402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3755254402
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1254426413
Short name T590
Test name
Test status
Simulation time 62128009 ps
CPU time 0.81 seconds
Started May 07 02:23:19 PM PDT 24
Finished May 07 02:23:21 PM PDT 24
Peak memory 206760 kb
Host smart-a07c4bbc-0ab5-4cfa-b376-3dfd4d86feac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254426413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1254426413
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2551128364
Short name T345
Test name
Test status
Simulation time 14127038946 ps
CPU time 20.62 seconds
Started May 07 02:23:27 PM PDT 24
Finished May 07 02:23:48 PM PDT 24
Peak memory 223848 kb
Host smart-a02b53cc-d212-4555-a6bc-d6272211deea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551128364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2551128364
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2244436756
Short name T71
Test name
Test status
Simulation time 1707551604 ps
CPU time 7.25 seconds
Started May 07 02:23:25 PM PDT 24
Finished May 07 02:23:33 PM PDT 24
Peak memory 222560 kb
Host smart-e7090cf5-db0f-4369-943d-aa0b236a2af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244436756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2244436756
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1314342708
Short name T424
Test name
Test status
Simulation time 3729598804 ps
CPU time 6.11 seconds
Started May 07 02:23:36 PM PDT 24
Finished May 07 02:23:42 PM PDT 24
Peak memory 223128 kb
Host smart-1da86d64-f9f1-4249-82d7-3e4ec0d01f7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1314342708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1314342708
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2714217735
Short name T360
Test name
Test status
Simulation time 145883184 ps
CPU time 0.95 seconds
Started May 07 02:23:43 PM PDT 24
Finished May 07 02:23:45 PM PDT 24
Peak memory 206768 kb
Host smart-c7da9795-44c5-41e3-9d33-bbab6cd81bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714217735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2714217735
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1468193290
Short name T700
Test name
Test status
Simulation time 22220214024 ps
CPU time 56.27 seconds
Started May 07 02:23:17 PM PDT 24
Finished May 07 02:24:15 PM PDT 24
Peak memory 216320 kb
Host smart-65f127f4-cda9-4ed8-aa88-fcbb68c66329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468193290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1468193290
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1559065869
Short name T654
Test name
Test status
Simulation time 4200196125 ps
CPU time 8.67 seconds
Started May 07 02:23:17 PM PDT 24
Finished May 07 02:23:27 PM PDT 24
Peak memory 216372 kb
Host smart-fa0785a1-136a-484b-bdd2-f02feba59a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559065869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1559065869
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.872054887
Short name T527
Test name
Test status
Simulation time 455596602 ps
CPU time 1.24 seconds
Started May 07 02:23:24 PM PDT 24
Finished May 07 02:23:26 PM PDT 24
Peak memory 207836 kb
Host smart-3b52cff8-b8bf-4524-9c04-682c956c4866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872054887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.872054887
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.66609200
Short name T430
Test name
Test status
Simulation time 76353070 ps
CPU time 0.91 seconds
Started May 07 02:23:24 PM PDT 24
Finished May 07 02:23:26 PM PDT 24
Peak memory 205788 kb
Host smart-e44d62a0-9f29-4c04-879a-9ff5f0afa338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66609200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.66609200
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.158787514
Short name T404
Test name
Test status
Simulation time 13282317 ps
CPU time 0.72 seconds
Started May 07 02:23:49 PM PDT 24
Finished May 07 02:23:50 PM PDT 24
Peak memory 205404 kb
Host smart-12d9d7c4-017c-446d-9265-8d00094b79fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158787514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.158787514
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1232224821
Short name T673
Test name
Test status
Simulation time 20632920 ps
CPU time 0.75 seconds
Started May 07 02:23:43 PM PDT 24
Finished May 07 02:23:44 PM PDT 24
Peak memory 206052 kb
Host smart-138bdf81-1c06-4023-bf06-432ee6afa85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232224821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1232224821
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_intercept.65289674
Short name T275
Test name
Test status
Simulation time 862765043 ps
CPU time 6.28 seconds
Started May 07 02:23:44 PM PDT 24
Finished May 07 02:23:51 PM PDT 24
Peak memory 221216 kb
Host smart-a070f6b7-f586-4635-8a6b-f4215f7732a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65289674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.65289674
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.278221370
Short name T219
Test name
Test status
Simulation time 1887216853 ps
CPU time 2.39 seconds
Started May 07 02:23:41 PM PDT 24
Finished May 07 02:23:44 PM PDT 24
Peak memory 216824 kb
Host smart-9159618f-fcb5-4d6c-9296-9308cc5dff51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278221370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.278221370
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.91508118
Short name T659
Test name
Test status
Simulation time 567824797 ps
CPU time 3.91 seconds
Started May 07 02:23:52 PM PDT 24
Finished May 07 02:23:57 PM PDT 24
Peak memory 218872 kb
Host smart-bfc09f77-f332-49f2-a07b-f7e030b67d37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=91508118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.91508118
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.660027745
Short name T558
Test name
Test status
Simulation time 52594358 ps
CPU time 1.22 seconds
Started May 07 02:23:46 PM PDT 24
Finished May 07 02:23:48 PM PDT 24
Peak memory 206964 kb
Host smart-b0eaf295-0828-4945-a7fb-6b23a902c450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660027745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.660027745
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.450591842
Short name T528
Test name
Test status
Simulation time 14563852 ps
CPU time 0.85 seconds
Started May 07 02:23:44 PM PDT 24
Finished May 07 02:23:45 PM PDT 24
Peak memory 206828 kb
Host smart-29049697-2b3f-4aee-8a09-3475d69f2501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450591842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.450591842
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.436781144
Short name T615
Test name
Test status
Simulation time 233537863 ps
CPU time 0.95 seconds
Started May 07 02:23:44 PM PDT 24
Finished May 07 02:23:45 PM PDT 24
Peak memory 206772 kb
Host smart-5586ea22-66e0-4445-af3a-f38c07f7041e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436781144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.436781144
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3832466357
Short name T193
Test name
Test status
Simulation time 17731244182 ps
CPU time 30.47 seconds
Started May 07 02:23:46 PM PDT 24
Finished May 07 02:24:17 PM PDT 24
Peak memory 218988 kb
Host smart-d0dc4bc0-f364-468d-9412-dfb13cf7613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832466357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3832466357
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1700417108
Short name T649
Test name
Test status
Simulation time 11986621 ps
CPU time 0.73 seconds
Started May 07 02:24:04 PM PDT 24
Finished May 07 02:24:05 PM PDT 24
Peak memory 205584 kb
Host smart-d210e359-ff25-4d7b-b797-d99828ab16ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700417108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1700417108
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.109658689
Short name T423
Test name
Test status
Simulation time 82153634 ps
CPU time 0.73 seconds
Started May 07 02:23:50 PM PDT 24
Finished May 07 02:23:51 PM PDT 24
Peak memory 205672 kb
Host smart-762dd40e-6481-4723-831c-763191694949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109658689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.109658689
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.180048842
Short name T643
Test name
Test status
Simulation time 21930800052 ps
CPU time 133.51 seconds
Started May 07 02:23:58 PM PDT 24
Finished May 07 02:26:13 PM PDT 24
Peak memory 249084 kb
Host smart-759d90bb-b123-47f4-8a2a-6c804c951d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180048842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.180048842
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2863606167
Short name T322
Test name
Test status
Simulation time 2632590165 ps
CPU time 27.2 seconds
Started May 07 02:23:58 PM PDT 24
Finished May 07 02:24:26 PM PDT 24
Peak memory 223388 kb
Host smart-69152141-7967-41c5-ab7e-13f74cc83018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863606167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2863606167
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1956922697
Short name T279
Test name
Test status
Simulation time 9772090419 ps
CPU time 68.29 seconds
Started May 07 02:23:59 PM PDT 24
Finished May 07 02:25:08 PM PDT 24
Peak memory 236600 kb
Host smart-26671bad-2dfc-41c7-945c-efb6bb84fa06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956922697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1956922697
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3470488528
Short name T280
Test name
Test status
Simulation time 2417110843 ps
CPU time 8.1 seconds
Started May 07 02:23:57 PM PDT 24
Finished May 07 02:24:05 PM PDT 24
Peak memory 218524 kb
Host smart-89c27b41-18fb-4ae7-85b6-a7655cebafe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470488528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3470488528
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.411063594
Short name T9
Test name
Test status
Simulation time 1023690562 ps
CPU time 6.89 seconds
Started May 07 02:23:58 PM PDT 24
Finished May 07 02:24:05 PM PDT 24
Peak memory 230844 kb
Host smart-ed621b6d-7f67-4276-95e9-ed8261be9f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411063594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.411063594
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2460910057
Short name T610
Test name
Test status
Simulation time 1782708480 ps
CPU time 21.29 seconds
Started May 07 02:23:56 PM PDT 24
Finished May 07 02:24:18 PM PDT 24
Peak memory 222940 kb
Host smart-b989aa0c-1487-40cb-95c9-1e36c689f0dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2460910057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2460910057
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.755779455
Short name T668
Test name
Test status
Simulation time 13880914774 ps
CPU time 15.89 seconds
Started May 07 02:23:57 PM PDT 24
Finished May 07 02:24:13 PM PDT 24
Peak memory 216400 kb
Host smart-83863891-9188-4183-b77c-7cd2cbcac5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755779455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.755779455
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3086543229
Short name T51
Test name
Test status
Simulation time 101170189 ps
CPU time 1.51 seconds
Started May 07 02:23:58 PM PDT 24
Finished May 07 02:24:00 PM PDT 24
Peak memory 216260 kb
Host smart-2f0e6d7c-6f18-4a83-995d-594c71e0eb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086543229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3086543229
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1385987634
Short name T669
Test name
Test status
Simulation time 66900505 ps
CPU time 0.96 seconds
Started May 07 02:23:58 PM PDT 24
Finished May 07 02:24:00 PM PDT 24
Peak memory 206852 kb
Host smart-48639a1a-6d63-48b4-bf71-2bb013e89bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385987634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1385987634
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3365322363
Short name T524
Test name
Test status
Simulation time 70718407 ps
CPU time 0.72 seconds
Started May 07 02:24:10 PM PDT 24
Finished May 07 02:24:11 PM PDT 24
Peak memory 204844 kb
Host smart-cb6714ca-235c-4ef6-9341-de45ceca3915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365322363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3365322363
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.464134402
Short name T681
Test name
Test status
Simulation time 179609378 ps
CPU time 0.79 seconds
Started May 07 02:24:03 PM PDT 24
Finished May 07 02:24:04 PM PDT 24
Peak memory 206768 kb
Host smart-fffbadc8-fe5e-4481-af98-a0b09167f81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464134402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.464134402
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2662859189
Short name T311
Test name
Test status
Simulation time 37214580773 ps
CPU time 93.15 seconds
Started May 07 02:24:05 PM PDT 24
Finished May 07 02:25:39 PM PDT 24
Peak memory 232464 kb
Host smart-d319c34e-695b-4dde-9dc4-68c5df771031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662859189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2662859189
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.802677554
Short name T255
Test name
Test status
Simulation time 1923757667 ps
CPU time 5.88 seconds
Started May 07 02:24:05 PM PDT 24
Finished May 07 02:24:11 PM PDT 24
Peak memory 219156 kb
Host smart-290d02ac-14ac-4126-9e89-33a24131ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802677554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.802677554
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1771576839
Short name T163
Test name
Test status
Simulation time 166655214 ps
CPU time 3.87 seconds
Started May 07 02:24:04 PM PDT 24
Finished May 07 02:24:08 PM PDT 24
Peak memory 222968 kb
Host smart-2043ba15-df00-4fe1-a2ac-2b9096ba46ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1771576839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1771576839
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1855132375
Short name T504
Test name
Test status
Simulation time 46487075441 ps
CPU time 59.19 seconds
Started May 07 02:24:05 PM PDT 24
Finished May 07 02:25:05 PM PDT 24
Peak memory 216392 kb
Host smart-b27fdee3-cb11-4e32-b036-66a92b40a70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855132375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1855132375
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1330274639
Short name T420
Test name
Test status
Simulation time 4354705907 ps
CPU time 8.68 seconds
Started May 07 02:24:05 PM PDT 24
Finished May 07 02:24:15 PM PDT 24
Peak memory 216304 kb
Host smart-74464733-2f23-4253-8dac-6c91dddb7d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330274639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1330274639
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.717964552
Short name T457
Test name
Test status
Simulation time 78545883 ps
CPU time 1.26 seconds
Started May 07 02:24:06 PM PDT 24
Finished May 07 02:24:08 PM PDT 24
Peak memory 216316 kb
Host smart-1240304c-18f6-4080-aba8-df968191df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717964552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.717964552
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4203018073
Short name T431
Test name
Test status
Simulation time 64737850 ps
CPU time 0.88 seconds
Started May 07 02:24:03 PM PDT 24
Finished May 07 02:24:05 PM PDT 24
Peak memory 206856 kb
Host smart-6018107c-d4d5-4745-8155-8311ae23ca0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203018073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4203018073
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.75938713
Short name T195
Test name
Test status
Simulation time 23262777525 ps
CPU time 11.25 seconds
Started May 07 02:24:04 PM PDT 24
Finished May 07 02:24:16 PM PDT 24
Peak memory 234944 kb
Host smart-5d5f5f29-b7d6-423a-9281-23d989039d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75938713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.75938713
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3535961158
Short name T437
Test name
Test status
Simulation time 34313006 ps
CPU time 0.7 seconds
Started May 07 02:24:19 PM PDT 24
Finished May 07 02:24:20 PM PDT 24
Peak memory 205780 kb
Host smart-79b0711f-85e8-4a10-a720-43ad36840cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535961158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3535961158
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3763143912
Short name T321
Test name
Test status
Simulation time 4418248258 ps
CPU time 18.03 seconds
Started May 07 02:24:20 PM PDT 24
Finished May 07 02:24:38 PM PDT 24
Peak memory 232768 kb
Host smart-529d4a8c-caf9-462e-8aac-11454aefd190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763143912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3763143912
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1088004425
Short name T502
Test name
Test status
Simulation time 101482250 ps
CPU time 0.81 seconds
Started May 07 02:24:09 PM PDT 24
Finished May 07 02:24:10 PM PDT 24
Peak memory 207020 kb
Host smart-473e52cf-4056-44df-a7a8-490f1ecef337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088004425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1088004425
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.962708111
Short name T607
Test name
Test status
Simulation time 4702255472 ps
CPU time 17.83 seconds
Started May 07 02:24:18 PM PDT 24
Finished May 07 02:24:36 PM PDT 24
Peak memory 232820 kb
Host smart-ef6f24d5-9d9d-44df-a434-bca06e1992b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962708111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.962708111
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1660757831
Short name T262
Test name
Test status
Simulation time 1087232602 ps
CPU time 16.55 seconds
Started May 07 02:24:08 PM PDT 24
Finished May 07 02:24:25 PM PDT 24
Peak memory 234744 kb
Host smart-408461d0-9c61-4b4f-8e7f-0ad80d49326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660757831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1660757831
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1869100640
Short name T310
Test name
Test status
Simulation time 285833189 ps
CPU time 4.71 seconds
Started May 07 02:24:08 PM PDT 24
Finished May 07 02:24:13 PM PDT 24
Peak memory 222856 kb
Host smart-8f18429d-7f18-452c-a778-8876b1f4711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869100640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1869100640
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3742681676
Short name T526
Test name
Test status
Simulation time 3196641073 ps
CPU time 20.48 seconds
Started May 07 02:24:18 PM PDT 24
Finished May 07 02:24:39 PM PDT 24
Peak memory 220612 kb
Host smart-cb073e4a-6b0a-438d-89c7-aa6f6a15c3cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742681676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3742681676
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.104620694
Short name T384
Test name
Test status
Simulation time 356233395 ps
CPU time 2.47 seconds
Started May 07 02:24:07 PM PDT 24
Finished May 07 02:24:11 PM PDT 24
Peak memory 216656 kb
Host smart-4e8d2131-c506-4688-90ab-83877b0c6ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104620694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.104620694
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.995128596
Short name T586
Test name
Test status
Simulation time 9075246798 ps
CPU time 25.11 seconds
Started May 07 02:24:09 PM PDT 24
Finished May 07 02:24:35 PM PDT 24
Peak memory 216448 kb
Host smart-81a0debb-844c-4c9e-a8bd-50b88985918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995128596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.995128596
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3724825183
Short name T464
Test name
Test status
Simulation time 47830640 ps
CPU time 0.79 seconds
Started May 07 02:24:09 PM PDT 24
Finished May 07 02:24:10 PM PDT 24
Peak memory 206484 kb
Host smart-db0930fe-dd2d-4df8-85d1-76d8d0bb9ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724825183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3724825183
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1113512643
Short name T591
Test name
Test status
Simulation time 165971407 ps
CPU time 0.85 seconds
Started May 07 02:24:08 PM PDT 24
Finished May 07 02:24:10 PM PDT 24
Peak memory 205824 kb
Host smart-5d8559c6-be12-4a89-bda0-a0db558631ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113512643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1113512643
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1110740692
Short name T476
Test name
Test status
Simulation time 19272157 ps
CPU time 0.7 seconds
Started May 07 02:24:23 PM PDT 24
Finished May 07 02:24:24 PM PDT 24
Peak memory 205356 kb
Host smart-e2888459-49cc-4c56-8138-94bd73427c50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110740692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1110740692
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4188690172
Short name T689
Test name
Test status
Simulation time 58406199 ps
CPU time 0.78 seconds
Started May 07 02:24:19 PM PDT 24
Finished May 07 02:24:20 PM PDT 24
Peak memory 206740 kb
Host smart-af9901f9-529c-4c41-bcd2-8e715f2ce5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188690172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4188690172
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3938073020
Short name T290
Test name
Test status
Simulation time 30802331314 ps
CPU time 49.93 seconds
Started May 07 02:24:25 PM PDT 24
Finished May 07 02:25:16 PM PDT 24
Peak memory 235324 kb
Host smart-62d0e2e6-c7e0-428f-8822-8543f0cc16bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938073020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3938073020
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3628693920
Short name T232
Test name
Test status
Simulation time 11201692522 ps
CPU time 27.2 seconds
Started May 07 02:24:18 PM PDT 24
Finished May 07 02:24:46 PM PDT 24
Peak memory 224608 kb
Host smart-876b537a-e630-44f5-b9a2-c76e695c9d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628693920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3628693920
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4207302671
Short name T629
Test name
Test status
Simulation time 1814470994 ps
CPU time 3.97 seconds
Started May 07 02:24:17 PM PDT 24
Finished May 07 02:24:22 PM PDT 24
Peak memory 222920 kb
Host smart-25c4657e-fd73-44ca-8330-aeb614fb91ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207302671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4207302671
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3943673967
Short name T512
Test name
Test status
Simulation time 1624060382 ps
CPU time 13.28 seconds
Started May 07 02:24:24 PM PDT 24
Finished May 07 02:24:38 PM PDT 24
Peak memory 221508 kb
Host smart-5f08e7ca-d1f0-40d1-840b-a61969250196
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3943673967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3943673967
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.907852255
Short name T375
Test name
Test status
Simulation time 3517372929 ps
CPU time 21.86 seconds
Started May 07 02:24:18 PM PDT 24
Finished May 07 02:24:41 PM PDT 24
Peak memory 216368 kb
Host smart-1323fdb5-0134-4d9d-b562-969bcc272e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907852255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.907852255
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2001059616
Short name T627
Test name
Test status
Simulation time 10526436751 ps
CPU time 29.67 seconds
Started May 07 02:24:21 PM PDT 24
Finished May 07 02:24:51 PM PDT 24
Peak memory 216416 kb
Host smart-5ff0cf71-769c-438a-ab7f-57399ddbf207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001059616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2001059616
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.470189360
Short name T479
Test name
Test status
Simulation time 178860998 ps
CPU time 1.95 seconds
Started May 07 02:24:19 PM PDT 24
Finished May 07 02:24:22 PM PDT 24
Peak memory 216324 kb
Host smart-e92ee767-7120-4af5-8f47-0d6246b2a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470189360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.470189360
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1782559158
Short name T59
Test name
Test status
Simulation time 81204654 ps
CPU time 0.98 seconds
Started May 07 02:24:18 PM PDT 24
Finished May 07 02:24:20 PM PDT 24
Peak memory 206836 kb
Host smart-31395457-8e8a-4f13-9743-5ecd471fde33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782559158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1782559158
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3410633490
Short name T497
Test name
Test status
Simulation time 14432674 ps
CPU time 0.7 seconds
Started May 07 02:24:29 PM PDT 24
Finished May 07 02:24:31 PM PDT 24
Peak memory 205436 kb
Host smart-c21e8ef5-699a-4275-b0ed-d3289788859e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410633490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3410633490
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2979548369
Short name T690
Test name
Test status
Simulation time 129184640 ps
CPU time 0.75 seconds
Started May 07 02:24:24 PM PDT 24
Finished May 07 02:24:25 PM PDT 24
Peak memory 205668 kb
Host smart-56e263fd-37ed-415b-bf13-8a12a9983957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979548369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2979548369
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.635738195
Short name T89
Test name
Test status
Simulation time 2324682922 ps
CPU time 43.23 seconds
Started May 07 02:24:32 PM PDT 24
Finished May 07 02:25:16 PM PDT 24
Peak memory 234900 kb
Host smart-026ea18e-f331-479f-9980-82323c4261e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635738195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.635738195
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2331735099
Short name T470
Test name
Test status
Simulation time 10580694866 ps
CPU time 9.98 seconds
Started May 07 02:24:25 PM PDT 24
Finished May 07 02:24:36 PM PDT 24
Peak memory 223332 kb
Host smart-713e7038-981e-4ca3-a325-56e3e43386e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331735099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2331735099
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2180839436
Short name T334
Test name
Test status
Simulation time 6888259881 ps
CPU time 13.79 seconds
Started May 07 02:24:22 PM PDT 24
Finished May 07 02:24:37 PM PDT 24
Peak memory 224404 kb
Host smart-db447aca-5d81-48b0-beba-4b05745fc9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180839436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2180839436
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3292481267
Short name T449
Test name
Test status
Simulation time 1899705643 ps
CPU time 18.44 seconds
Started May 07 02:24:30 PM PDT 24
Finished May 07 02:24:50 PM PDT 24
Peak memory 222336 kb
Host smart-8dd44603-0e09-40af-81aa-1bbfc53c723b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3292481267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3292481267
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2780133059
Short name T368
Test name
Test status
Simulation time 2744143700 ps
CPU time 18.79 seconds
Started May 07 02:24:23 PM PDT 24
Finished May 07 02:24:43 PM PDT 24
Peak memory 216332 kb
Host smart-07221145-93ca-442b-b59c-09fbb5ca13e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780133059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2780133059
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1300454850
Short name T576
Test name
Test status
Simulation time 8508348554 ps
CPU time 22.79 seconds
Started May 07 02:24:22 PM PDT 24
Finished May 07 02:24:46 PM PDT 24
Peak memory 216420 kb
Host smart-d9fb1163-fdef-4a14-a531-4f217a3c8764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300454850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1300454850
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.981447135
Short name T386
Test name
Test status
Simulation time 92946597 ps
CPU time 0.72 seconds
Started May 07 02:24:23 PM PDT 24
Finished May 07 02:24:25 PM PDT 24
Peak memory 205856 kb
Host smart-7da9a093-e685-4021-b3d2-0234c574afcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981447135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.981447135
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1611760422
Short name T517
Test name
Test status
Simulation time 708274439 ps
CPU time 0.89 seconds
Started May 07 02:24:23 PM PDT 24
Finished May 07 02:24:25 PM PDT 24
Peak memory 205800 kb
Host smart-2452585f-bde2-4344-9359-c96a7acc5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611760422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1611760422
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1657444239
Short name T708
Test name
Test status
Simulation time 271398211 ps
CPU time 5.07 seconds
Started May 07 02:24:33 PM PDT 24
Finished May 07 02:24:38 PM PDT 24
Peak memory 232712 kb
Host smart-150accf4-80c7-49d0-9af6-c0fe07f0e28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657444239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1657444239
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2119169484
Short name T592
Test name
Test status
Simulation time 35587726 ps
CPU time 0.73 seconds
Started May 07 02:24:35 PM PDT 24
Finished May 07 02:24:36 PM PDT 24
Peak memory 205788 kb
Host smart-5fc87165-a885-4ed2-8293-146e27df0816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119169484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2119169484
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1757100860
Short name T587
Test name
Test status
Simulation time 30325318 ps
CPU time 0.76 seconds
Started May 07 02:24:28 PM PDT 24
Finished May 07 02:24:30 PM PDT 24
Peak memory 207024 kb
Host smart-96f0ec1b-2561-4f6e-9005-ba6118e1ac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757100860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1757100860
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.108972806
Short name T302
Test name
Test status
Simulation time 10504907294 ps
CPU time 48.58 seconds
Started May 07 02:24:37 PM PDT 24
Finished May 07 02:25:26 PM PDT 24
Peak memory 240952 kb
Host smart-25c4540f-621a-4e90-aafb-2d82d53c1bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108972806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.108972806
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.408343769
Short name T710
Test name
Test status
Simulation time 370139124 ps
CPU time 5.73 seconds
Started May 07 02:24:37 PM PDT 24
Finished May 07 02:24:43 PM PDT 24
Peak memory 220632 kb
Host smart-a719c0ca-755b-454a-bc6f-c90b9ad86277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408343769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.408343769
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3835453540
Short name T347
Test name
Test status
Simulation time 6775238865 ps
CPU time 42.46 seconds
Started May 07 02:24:35 PM PDT 24
Finished May 07 02:25:18 PM PDT 24
Peak memory 224136 kb
Host smart-d33af676-247c-492e-879e-6048f7978228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835453540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3835453540
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2095465139
Short name T247
Test name
Test status
Simulation time 126062094 ps
CPU time 3.32 seconds
Started May 07 02:24:36 PM PDT 24
Finished May 07 02:24:40 PM PDT 24
Peak memory 216824 kb
Host smart-ca8f5229-9968-4cbb-920e-2a9fe22d7e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095465139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2095465139
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3705402777
Short name T460
Test name
Test status
Simulation time 6405307799 ps
CPU time 19.3 seconds
Started May 07 02:24:36 PM PDT 24
Finished May 07 02:24:56 PM PDT 24
Peak memory 219052 kb
Host smart-a2c42404-29ef-4463-be77-4aaf8676c0bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705402777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3705402777
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.558975078
Short name T381
Test name
Test status
Simulation time 24187228486 ps
CPU time 37.47 seconds
Started May 07 02:24:30 PM PDT 24
Finished May 07 02:25:08 PM PDT 24
Peak memory 216384 kb
Host smart-f1f37acc-5b66-4c27-b7e6-673b1c2ae0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558975078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.558975078
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2417018891
Short name T57
Test name
Test status
Simulation time 14781464096 ps
CPU time 6.94 seconds
Started May 07 02:24:31 PM PDT 24
Finished May 07 02:24:39 PM PDT 24
Peak memory 216392 kb
Host smart-092e93be-9b4a-4439-8a1d-0b948d843d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417018891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2417018891
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1764028486
Short name T15
Test name
Test status
Simulation time 111684390 ps
CPU time 1.65 seconds
Started May 07 02:24:29 PM PDT 24
Finished May 07 02:24:31 PM PDT 24
Peak memory 216344 kb
Host smart-e35f97a5-a19e-4d2f-b58e-89bc9e70d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764028486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1764028486
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.843738862
Short name T440
Test name
Test status
Simulation time 20126976 ps
CPU time 0.78 seconds
Started May 07 02:24:31 PM PDT 24
Finished May 07 02:24:33 PM PDT 24
Peak memory 205816 kb
Host smart-200417d6-f960-40b7-b63b-42a43b2729e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843738862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.843738862
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3336113045
Short name T490
Test name
Test status
Simulation time 90230318 ps
CPU time 0.72 seconds
Started May 07 02:17:48 PM PDT 24
Finished May 07 02:17:50 PM PDT 24
Peak memory 205940 kb
Host smart-2756beb2-63e8-41f7-9ce0-1c2036494953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336113045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
336113045
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2680763682
Short name T474
Test name
Test status
Simulation time 26449002 ps
CPU time 0.76 seconds
Started May 07 02:17:26 PM PDT 24
Finished May 07 02:17:28 PM PDT 24
Peak memory 206736 kb
Host smart-45aa83bc-0bde-4cd8-8c6e-17535c863aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680763682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2680763682
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1885990791
Short name T291
Test name
Test status
Simulation time 5988111272 ps
CPU time 81.42 seconds
Started May 07 02:17:39 PM PDT 24
Finished May 07 02:19:01 PM PDT 24
Peak memory 239832 kb
Host smart-a2631c4a-714d-400b-8c4e-10a777aa320f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885990791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1885990791
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.531159515
Short name T117
Test name
Test status
Simulation time 9159556307 ps
CPU time 31.84 seconds
Started May 07 02:17:41 PM PDT 24
Finished May 07 02:18:14 PM PDT 24
Peak memory 239416 kb
Host smart-2d0fd0a3-678c-404c-90dd-c763b307f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531159515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.531159515
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1576320782
Short name T709
Test name
Test status
Simulation time 26108026367 ps
CPU time 19.02 seconds
Started May 07 02:17:39 PM PDT 24
Finished May 07 02:17:59 PM PDT 24
Peak memory 218652 kb
Host smart-5406cc92-0f2f-43ea-8008-614b49d81f72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1576320782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1576320782
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3705410350
Short name T33
Test name
Test status
Simulation time 36834063 ps
CPU time 0.94 seconds
Started May 07 02:17:40 PM PDT 24
Finished May 07 02:17:41 PM PDT 24
Peak memory 235180 kb
Host smart-5a22c3c2-4389-4258-8f91-e43b7b9a2e4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705410350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3705410350
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3304594822
Short name T658
Test name
Test status
Simulation time 916139543 ps
CPU time 7.89 seconds
Started May 07 02:17:26 PM PDT 24
Finished May 07 02:17:35 PM PDT 24
Peak memory 219016 kb
Host smart-bae51abe-02e3-405c-bd66-0fa183d41281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304594822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3304594822
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2852052109
Short name T478
Test name
Test status
Simulation time 8215381443 ps
CPU time 13.89 seconds
Started May 07 02:17:26 PM PDT 24
Finished May 07 02:17:41 PM PDT 24
Peak memory 216428 kb
Host smart-e138e6db-7447-497e-8b5b-5ae59c82f8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852052109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2852052109
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3258032096
Short name T682
Test name
Test status
Simulation time 496871677 ps
CPU time 3.22 seconds
Started May 07 02:17:32 PM PDT 24
Finished May 07 02:17:36 PM PDT 24
Peak memory 216308 kb
Host smart-295ff165-6bba-4f61-b061-7f714bb0b710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258032096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3258032096
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1191596051
Short name T547
Test name
Test status
Simulation time 69819402 ps
CPU time 0.84 seconds
Started May 07 02:17:35 PM PDT 24
Finished May 07 02:17:37 PM PDT 24
Peak memory 205740 kb
Host smart-51723ffa-e8f6-4007-b47f-8281f6d6d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191596051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1191596051
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2548182917
Short name T569
Test name
Test status
Simulation time 22727017 ps
CPU time 0.71 seconds
Started May 07 02:24:47 PM PDT 24
Finished May 07 02:24:48 PM PDT 24
Peak memory 205424 kb
Host smart-dfb9ed38-20f2-4a2b-8130-05a9e8b88448
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548182917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2548182917
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3627107838
Short name T555
Test name
Test status
Simulation time 262007326 ps
CPU time 4.37 seconds
Started May 07 02:24:42 PM PDT 24
Finished May 07 02:24:48 PM PDT 24
Peak memory 222660 kb
Host smart-6890fcf9-e367-4668-afcf-92a900599973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627107838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3627107838
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2229378036
Short name T697
Test name
Test status
Simulation time 20388386 ps
CPU time 0.77 seconds
Started May 07 02:24:39 PM PDT 24
Finished May 07 02:24:40 PM PDT 24
Peak memory 206756 kb
Host smart-70c3f91a-1ed2-4145-983f-5bc2fab6e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229378036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2229378036
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2910883300
Short name T74
Test name
Test status
Simulation time 499329679 ps
CPU time 7.11 seconds
Started May 07 02:24:35 PM PDT 24
Finished May 07 02:24:43 PM PDT 24
Peak memory 219856 kb
Host smart-965ad5e6-783f-4c8b-bbbf-ddb377991837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910883300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2910883300
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1009882252
Short name T645
Test name
Test status
Simulation time 2692820323 ps
CPU time 8.52 seconds
Started May 07 02:24:42 PM PDT 24
Finished May 07 02:24:51 PM PDT 24
Peak memory 223188 kb
Host smart-13d1b9a6-6729-4233-9460-7375ca4913be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009882252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1009882252
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1201980204
Short name T388
Test name
Test status
Simulation time 5400185742 ps
CPU time 29.57 seconds
Started May 07 02:24:37 PM PDT 24
Finished May 07 02:25:07 PM PDT 24
Peak memory 216376 kb
Host smart-037041af-826d-44af-b9c8-edb841d978f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201980204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1201980204
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2341998633
Short name T501
Test name
Test status
Simulation time 3144681751 ps
CPU time 5.04 seconds
Started May 07 02:24:37 PM PDT 24
Finished May 07 02:24:43 PM PDT 24
Peak memory 216344 kb
Host smart-379f724f-1340-48fb-93ee-5098e1f0e492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341998633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2341998633
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4292617097
Short name T701
Test name
Test status
Simulation time 23429431 ps
CPU time 1.39 seconds
Started May 07 02:24:37 PM PDT 24
Finished May 07 02:24:39 PM PDT 24
Peak memory 216344 kb
Host smart-37860580-3eaa-4389-8234-f643134fd160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292617097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4292617097
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3613752381
Short name T428
Test name
Test status
Simulation time 175625243 ps
CPU time 0.84 seconds
Started May 07 02:24:36 PM PDT 24
Finished May 07 02:24:38 PM PDT 24
Peak memory 205748 kb
Host smart-c844f5c4-798b-4554-8377-cd51a5448b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613752381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3613752381
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2813229584
Short name T263
Test name
Test status
Simulation time 15813246090 ps
CPU time 23.45 seconds
Started May 07 02:24:44 PM PDT 24
Finished May 07 02:25:08 PM PDT 24
Peak memory 224416 kb
Host smart-8d063b4d-7189-484b-a68f-6fbe6c3457b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813229584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2813229584
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1620634516
Short name T414
Test name
Test status
Simulation time 15528805 ps
CPU time 0.72 seconds
Started May 07 02:24:50 PM PDT 24
Finished May 07 02:24:52 PM PDT 24
Peak memory 205432 kb
Host smart-bead85e5-0aa6-4234-ba10-4f0a4b3ee3e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620634516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1620634516
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.775747163
Short name T400
Test name
Test status
Simulation time 33416571 ps
CPU time 0.78 seconds
Started May 07 02:24:42 PM PDT 24
Finished May 07 02:24:44 PM PDT 24
Peak memory 207076 kb
Host smart-b33e5cf9-ea7e-47d7-a252-e8528c1d8b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775747163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.775747163
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1774851463
Short name T296
Test name
Test status
Simulation time 1583513456 ps
CPU time 12.51 seconds
Started May 07 02:24:48 PM PDT 24
Finished May 07 02:25:01 PM PDT 24
Peak memory 241212 kb
Host smart-06bca284-5a13-4863-98bb-eb4c0c700a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774851463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1774851463
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1096456159
Short name T393
Test name
Test status
Simulation time 262906915 ps
CPU time 2.86 seconds
Started May 07 02:24:41 PM PDT 24
Finished May 07 02:24:45 PM PDT 24
Peak memory 223240 kb
Host smart-fe46cb98-d365-4e59-85c1-56e6729041fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096456159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1096456159
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2342776792
Short name T241
Test name
Test status
Simulation time 12136820423 ps
CPU time 30.61 seconds
Started May 07 02:24:42 PM PDT 24
Finished May 07 02:25:14 PM PDT 24
Peak memory 232768 kb
Host smart-993fd1fa-4759-495a-92de-972ac3b5e980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342776792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2342776792
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.792279893
Short name T104
Test name
Test status
Simulation time 1762591256 ps
CPU time 12.36 seconds
Started May 07 02:24:50 PM PDT 24
Finished May 07 02:25:03 PM PDT 24
Peak memory 221436 kb
Host smart-37edf3b5-0b0d-4a80-aa03-3bb5593de366
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=792279893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.792279893
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1025265069
Short name T618
Test name
Test status
Simulation time 5827175236 ps
CPU time 33.53 seconds
Started May 07 02:24:42 PM PDT 24
Finished May 07 02:25:17 PM PDT 24
Peak memory 216432 kb
Host smart-e2b61f2d-4f2d-4ec2-a82c-36fd82abe7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025265069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1025265069
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1820707714
Short name T442
Test name
Test status
Simulation time 1296064103 ps
CPU time 5.01 seconds
Started May 07 02:24:42 PM PDT 24
Finished May 07 02:24:48 PM PDT 24
Peak memory 216356 kb
Host smart-9b318680-2245-4fca-a133-d75281b0dab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820707714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1820707714
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3970501337
Short name T518
Test name
Test status
Simulation time 122352404 ps
CPU time 2.85 seconds
Started May 07 02:24:46 PM PDT 24
Finished May 07 02:24:50 PM PDT 24
Peak memory 216268 kb
Host smart-6b49fc56-09d3-4bee-a4df-86a661e35467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970501337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3970501337
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2346179907
Short name T575
Test name
Test status
Simulation time 17654598 ps
CPU time 0.73 seconds
Started May 07 02:24:41 PM PDT 24
Finished May 07 02:24:43 PM PDT 24
Peak memory 205828 kb
Host smart-14ddbe95-52f3-4d59-a2cf-c544e2dba555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346179907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2346179907
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3506212072
Short name T506
Test name
Test status
Simulation time 35888476 ps
CPU time 0.67 seconds
Started May 07 02:24:57 PM PDT 24
Finished May 07 02:24:58 PM PDT 24
Peak memory 204852 kb
Host smart-b6aec26d-201a-41e5-ab56-207ae493b81f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506212072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3506212072
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4084405006
Short name T706
Test name
Test status
Simulation time 17212048 ps
CPU time 0.76 seconds
Started May 07 02:24:48 PM PDT 24
Finished May 07 02:24:49 PM PDT 24
Peak memory 205992 kb
Host smart-b1272b1c-8d02-486c-a48a-958cff88ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084405006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4084405006
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.839637454
Short name T356
Test name
Test status
Simulation time 1352429555 ps
CPU time 31.51 seconds
Started May 07 02:24:50 PM PDT 24
Finished May 07 02:25:23 PM PDT 24
Peak memory 240860 kb
Host smart-25634bc4-3e70-440b-a712-e3122f86f405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839637454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.839637454
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.559962606
Short name T122
Test name
Test status
Simulation time 16232535771 ps
CPU time 82.45 seconds
Started May 07 02:24:51 PM PDT 24
Finished May 07 02:26:14 PM PDT 24
Peak memory 217124 kb
Host smart-e8912003-a09e-4528-9d58-fd9f75f69c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559962606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.559962606
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3042341085
Short name T211
Test name
Test status
Simulation time 309624798 ps
CPU time 2.36 seconds
Started May 07 02:24:48 PM PDT 24
Finished May 07 02:24:51 PM PDT 24
Peak memory 222996 kb
Host smart-530b0cd7-ed99-4972-946c-1c832d4fdbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042341085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3042341085
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1872511135
Short name T459
Test name
Test status
Simulation time 305053987 ps
CPU time 3.23 seconds
Started May 07 02:24:50 PM PDT 24
Finished May 07 02:24:54 PM PDT 24
Peak memory 219908 kb
Host smart-a503ce3b-d282-48c8-96a7-7f9537d636ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1872511135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1872511135
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.605467838
Short name T377
Test name
Test status
Simulation time 18600046193 ps
CPU time 18.55 seconds
Started May 07 02:24:49 PM PDT 24
Finished May 07 02:25:09 PM PDT 24
Peak memory 216388 kb
Host smart-7ce7f687-7f3b-4288-8e16-4ab6c15cd806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605467838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.605467838
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2759251707
Short name T21
Test name
Test status
Simulation time 860018951 ps
CPU time 3.56 seconds
Started May 07 02:24:48 PM PDT 24
Finished May 07 02:24:52 PM PDT 24
Peak memory 216352 kb
Host smart-018f8900-23cc-4c8f-8f4a-ed031c2d0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759251707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2759251707
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.970294766
Short name T554
Test name
Test status
Simulation time 86021727 ps
CPU time 4.84 seconds
Started May 07 02:24:46 PM PDT 24
Finished May 07 02:24:52 PM PDT 24
Peak memory 216364 kb
Host smart-a6f81fa4-de10-477f-9e52-8876d95e3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970294766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.970294766
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.4170500609
Short name T652
Test name
Test status
Simulation time 159845825 ps
CPU time 1.08 seconds
Started May 07 02:24:50 PM PDT 24
Finished May 07 02:24:52 PM PDT 24
Peak memory 206876 kb
Host smart-4512a69b-2435-410e-8dec-f68fdb450bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170500609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.4170500609
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.886953388
Short name T608
Test name
Test status
Simulation time 12033825 ps
CPU time 0.77 seconds
Started May 07 02:25:01 PM PDT 24
Finished May 07 02:25:03 PM PDT 24
Peak memory 205460 kb
Host smart-36037c04-7527-4a49-a66a-2d24bfd2e649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886953388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.886953388
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2383219989
Short name T473
Test name
Test status
Simulation time 32599657 ps
CPU time 0.78 seconds
Started May 07 02:24:56 PM PDT 24
Finished May 07 02:24:57 PM PDT 24
Peak memory 206728 kb
Host smart-4886a22b-2ec4-4f0c-aa76-80c4cb96eba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383219989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2383219989
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3066062314
Short name T243
Test name
Test status
Simulation time 11153481415 ps
CPU time 72.19 seconds
Started May 07 02:24:54 PM PDT 24
Finished May 07 02:26:07 PM PDT 24
Peak memory 232816 kb
Host smart-6696d364-577f-40e1-86bf-035d05c80dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066062314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3066062314
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1139831547
Short name T496
Test name
Test status
Simulation time 296769486 ps
CPU time 3.71 seconds
Started May 07 02:24:54 PM PDT 24
Finished May 07 02:24:58 PM PDT 24
Peak memory 222612 kb
Host smart-ac066477-9d6c-422d-a9c3-fa817d63bfdc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1139831547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1139831547
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.655057387
Short name T564
Test name
Test status
Simulation time 56964735 ps
CPU time 1.21 seconds
Started May 07 02:25:02 PM PDT 24
Finished May 07 02:25:05 PM PDT 24
Peak memory 207168 kb
Host smart-785e04d3-c5a3-47a7-bb9b-c70122c6d785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655057387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.655057387
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3191855977
Short name T628
Test name
Test status
Simulation time 911731459 ps
CPU time 9.03 seconds
Started May 07 02:24:55 PM PDT 24
Finished May 07 02:25:05 PM PDT 24
Peak memory 216272 kb
Host smart-6b3c4551-e426-4b8b-aff0-8da6cb280b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191855977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3191855977
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3096622344
Short name T520
Test name
Test status
Simulation time 23373176920 ps
CPU time 32.9 seconds
Started May 07 02:24:54 PM PDT 24
Finished May 07 02:25:27 PM PDT 24
Peak memory 216308 kb
Host smart-1cde50ad-61fc-48d7-a56d-81194c07b3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096622344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3096622344
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.70784458
Short name T678
Test name
Test status
Simulation time 430534272 ps
CPU time 3.94 seconds
Started May 07 02:24:56 PM PDT 24
Finished May 07 02:25:01 PM PDT 24
Peak memory 216196 kb
Host smart-1458a5c5-1949-49e4-b462-3f4ad6caeea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70784458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.70784458
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3476692441
Short name T407
Test name
Test status
Simulation time 231271435 ps
CPU time 0.85 seconds
Started May 07 02:24:56 PM PDT 24
Finished May 07 02:24:57 PM PDT 24
Peak memory 205812 kb
Host smart-f4476503-0bfc-4a33-a0e1-fa5e9a166249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476692441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3476692441
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.497324318
Short name T277
Test name
Test status
Simulation time 625878079 ps
CPU time 6.73 seconds
Started May 07 02:24:55 PM PDT 24
Finished May 07 02:25:02 PM PDT 24
Peak memory 239876 kb
Host smart-a12b3f5c-9a43-4ab5-9dc7-f257ccf74916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497324318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.497324318
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1098673835
Short name T491
Test name
Test status
Simulation time 16057202 ps
CPU time 0.74 seconds
Started May 07 02:25:08 PM PDT 24
Finished May 07 02:25:09 PM PDT 24
Peak memory 205828 kb
Host smart-9c15f872-d0e2-4d33-b523-7740a3f2607a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098673835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1098673835
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2741552331
Short name T394
Test name
Test status
Simulation time 288553526 ps
CPU time 0.81 seconds
Started May 07 02:25:02 PM PDT 24
Finished May 07 02:25:04 PM PDT 24
Peak memory 207072 kb
Host smart-d53ad9fc-e4bd-43f4-92ab-d1b77e8afa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741552331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2741552331
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.743890923
Short name T304
Test name
Test status
Simulation time 38780218852 ps
CPU time 92.63 seconds
Started May 07 02:25:01 PM PDT 24
Finished May 07 02:26:35 PM PDT 24
Peak memory 249092 kb
Host smart-ac34fb74-a8c1-4b87-8c25-47dec32b2355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743890923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.743890923
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2140685009
Short name T320
Test name
Test status
Simulation time 3008240864 ps
CPU time 9.04 seconds
Started May 07 02:25:01 PM PDT 24
Finished May 07 02:25:10 PM PDT 24
Peak memory 222976 kb
Host smart-185d3302-827f-4949-bd6e-51e16a54ceb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140685009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2140685009
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.465453649
Short name T172
Test name
Test status
Simulation time 5283555538 ps
CPU time 14.13 seconds
Started May 07 02:25:02 PM PDT 24
Finished May 07 02:25:17 PM PDT 24
Peak memory 223012 kb
Host smart-f91632e5-a863-4c41-8cda-ef7abc5f0d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465453649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.465453649
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1113226726
Short name T467
Test name
Test status
Simulation time 566176761 ps
CPU time 3.06 seconds
Started May 07 02:25:01 PM PDT 24
Finished May 07 02:25:05 PM PDT 24
Peak memory 219556 kb
Host smart-57e1d60a-bf02-4fcf-85df-0401fd1f79bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1113226726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1113226726
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2960287991
Short name T169
Test name
Test status
Simulation time 122758746 ps
CPU time 1.1 seconds
Started May 07 02:25:10 PM PDT 24
Finished May 07 02:25:12 PM PDT 24
Peak memory 207308 kb
Host smart-870c0c1f-a113-4d4d-bc1a-a8240fc5c254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960287991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2960287991
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2129289193
Short name T65
Test name
Test status
Simulation time 2751487251 ps
CPU time 21.95 seconds
Started May 07 02:25:00 PM PDT 24
Finished May 07 02:25:23 PM PDT 24
Peak memory 216396 kb
Host smart-3d6fe210-adf3-4d05-b5aa-70d291d688d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129289193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2129289193
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1751433470
Short name T509
Test name
Test status
Simulation time 821200363 ps
CPU time 2.19 seconds
Started May 07 02:25:02 PM PDT 24
Finished May 07 02:25:06 PM PDT 24
Peak memory 207076 kb
Host smart-5a1f8650-940e-4a49-b24c-78ed6a630f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751433470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1751433470
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.961107221
Short name T671
Test name
Test status
Simulation time 71381948 ps
CPU time 0.94 seconds
Started May 07 02:25:02 PM PDT 24
Finished May 07 02:25:04 PM PDT 24
Peak memory 207260 kb
Host smart-83d6202b-9620-4994-8faa-8d68ef3b85be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961107221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.961107221
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.84920923
Short name T556
Test name
Test status
Simulation time 138340680 ps
CPU time 0.9 seconds
Started May 07 02:25:01 PM PDT 24
Finished May 07 02:25:02 PM PDT 24
Peak memory 205844 kb
Host smart-19e5bf34-bb91-439a-857c-c398b4311f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84920923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.84920923
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3211921513
Short name T409
Test name
Test status
Simulation time 16892761 ps
CPU time 0.75 seconds
Started May 07 02:25:20 PM PDT 24
Finished May 07 02:25:22 PM PDT 24
Peak memory 205464 kb
Host smart-106bff75-f971-4253-8931-5a1018ec0658
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211921513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3211921513
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3311854101
Short name T616
Test name
Test status
Simulation time 40002088 ps
CPU time 0.76 seconds
Started May 07 02:25:09 PM PDT 24
Finished May 07 02:25:10 PM PDT 24
Peak memory 206736 kb
Host smart-f59725d7-5373-4a22-9ea1-dade1cfea4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311854101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3311854101
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1282645302
Short name T94
Test name
Test status
Simulation time 324582341 ps
CPU time 8.06 seconds
Started May 07 02:25:08 PM PDT 24
Finished May 07 02:25:17 PM PDT 24
Peak memory 218824 kb
Host smart-fbe509c6-40b9-471b-ab79-d9f83096f08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282645302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1282645302
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.702016859
Short name T222
Test name
Test status
Simulation time 10859644322 ps
CPU time 18.33 seconds
Started May 07 02:25:09 PM PDT 24
Finished May 07 02:25:29 PM PDT 24
Peak memory 219060 kb
Host smart-c50cd962-2397-49a6-ba15-f8595b6e4d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702016859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.702016859
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.668351417
Short name T268
Test name
Test status
Simulation time 1003961459 ps
CPU time 3.21 seconds
Started May 07 02:25:09 PM PDT 24
Finished May 07 02:25:13 PM PDT 24
Peak memory 222844 kb
Host smart-5b7320d6-33e5-4792-9a80-01de05711a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668351417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.668351417
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3334969989
Short name T97
Test name
Test status
Simulation time 9649000431 ps
CPU time 33.23 seconds
Started May 07 02:25:08 PM PDT 24
Finished May 07 02:25:42 PM PDT 24
Peak memory 234040 kb
Host smart-e9f0f448-f026-4d50-bdb0-495eb334efdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334969989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3334969989
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3997641847
Short name T436
Test name
Test status
Simulation time 1477527500 ps
CPU time 7.02 seconds
Started May 07 02:25:13 PM PDT 24
Finished May 07 02:25:21 PM PDT 24
Peak memory 219308 kb
Host smart-12b3389e-11be-45ba-b07f-3ff86c59cb2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3997641847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3997641847
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3219806178
Short name T371
Test name
Test status
Simulation time 334871455 ps
CPU time 1.92 seconds
Started May 07 02:25:08 PM PDT 24
Finished May 07 02:25:11 PM PDT 24
Peak memory 216504 kb
Host smart-f999a3c0-7e26-417c-9432-87d123b16421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219806178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3219806178
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3221473044
Short name T413
Test name
Test status
Simulation time 1988414284 ps
CPU time 6.48 seconds
Started May 07 02:25:08 PM PDT 24
Finished May 07 02:25:16 PM PDT 24
Peak memory 216224 kb
Host smart-9be9fbbd-a6ac-4af0-807c-ba07000adb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221473044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3221473044
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1726101466
Short name T563
Test name
Test status
Simulation time 748202311 ps
CPU time 2.08 seconds
Started May 07 02:25:07 PM PDT 24
Finished May 07 02:25:10 PM PDT 24
Peak memory 216264 kb
Host smart-81802101-b204-4df5-bd05-6e70c0a0636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726101466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1726101466
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.716475389
Short name T455
Test name
Test status
Simulation time 34735298 ps
CPU time 0.86 seconds
Started May 07 02:25:07 PM PDT 24
Finished May 07 02:25:08 PM PDT 24
Peak memory 206812 kb
Host smart-a567952d-acfe-4587-9057-f78cbf757009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716475389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.716475389
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3073669779
Short name T466
Test name
Test status
Simulation time 13787711 ps
CPU time 0.7 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:25:17 PM PDT 24
Peak memory 204832 kb
Host smart-a4ec503d-2af8-494e-a2b0-4b3a48ab6b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073669779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3073669779
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1064885425
Short name T270
Test name
Test status
Simulation time 1620159203 ps
CPU time 15.9 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:25:32 PM PDT 24
Peak memory 223700 kb
Host smart-c913eca4-73c3-4d43-b149-dd6b44cec1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064885425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1064885425
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3468819191
Short name T397
Test name
Test status
Simulation time 101810955 ps
CPU time 0.75 seconds
Started May 07 02:25:14 PM PDT 24
Finished May 07 02:25:16 PM PDT 24
Peak memory 205976 kb
Host smart-f1193714-82db-4e46-8566-490005a535c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468819191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3468819191
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3681869026
Short name T636
Test name
Test status
Simulation time 22672053394 ps
CPU time 74.35 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:26:30 PM PDT 24
Peak memory 239708 kb
Host smart-26b04395-f6ce-41ad-a5f3-4b6722b15eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681869026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3681869026
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3767834434
Short name T223
Test name
Test status
Simulation time 593761928 ps
CPU time 4.57 seconds
Started May 07 02:25:14 PM PDT 24
Finished May 07 02:25:20 PM PDT 24
Peak memory 224112 kb
Host smart-ac49a5b2-f74e-44a7-b45a-c39eeaf4a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767834434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3767834434
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3382474546
Short name T1
Test name
Test status
Simulation time 2413683860 ps
CPU time 5.5 seconds
Started May 07 02:25:16 PM PDT 24
Finished May 07 02:25:22 PM PDT 24
Peak memory 222980 kb
Host smart-70180d98-bc7b-430f-a402-88f1d00726cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3382474546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3382474546
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1603777094
Short name T458
Test name
Test status
Simulation time 420205683 ps
CPU time 1.99 seconds
Started May 07 02:25:20 PM PDT 24
Finished May 07 02:25:23 PM PDT 24
Peak memory 207704 kb
Host smart-d9c7b89e-1e3d-436b-a015-9f113a338e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603777094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1603777094
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2136071872
Short name T642
Test name
Test status
Simulation time 657765380 ps
CPU time 2.06 seconds
Started May 07 02:25:14 PM PDT 24
Finished May 07 02:25:17 PM PDT 24
Peak memory 216340 kb
Host smart-56d00006-7af3-4af7-b112-71131bf6f564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136071872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2136071872
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1004516277
Short name T452
Test name
Test status
Simulation time 212590294 ps
CPU time 0.86 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:25:17 PM PDT 24
Peak memory 205812 kb
Host smart-65249429-82c3-466d-8582-476d8e977832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004516277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1004516277
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2209181019
Short name T538
Test name
Test status
Simulation time 24341630 ps
CPU time 0.72 seconds
Started May 07 02:25:26 PM PDT 24
Finished May 07 02:25:27 PM PDT 24
Peak memory 204892 kb
Host smart-53f77885-6b5a-4427-80a3-f50727041210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209181019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2209181019
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4057942902
Short name T702
Test name
Test status
Simulation time 43997689 ps
CPU time 0.71 seconds
Started May 07 02:25:14 PM PDT 24
Finished May 07 02:25:15 PM PDT 24
Peak memory 205672 kb
Host smart-a38b757e-5aac-4f96-9962-f3eefe903736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057942902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4057942902
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3486587706
Short name T121
Test name
Test status
Simulation time 2782658281 ps
CPU time 19.76 seconds
Started May 07 02:25:20 PM PDT 24
Finished May 07 02:25:41 PM PDT 24
Peak memory 221500 kb
Host smart-c620f1d6-34c5-42b2-a80a-52d0fb749b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486587706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3486587706
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3285871405
Short name T213
Test name
Test status
Simulation time 14434135129 ps
CPU time 125.63 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:27:21 PM PDT 24
Peak memory 234344 kb
Host smart-67b4aa28-9027-4910-8716-3269ff5d3d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285871405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3285871405
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1285635599
Short name T448
Test name
Test status
Simulation time 2857074370 ps
CPU time 7.7 seconds
Started May 07 02:25:17 PM PDT 24
Finished May 07 02:25:25 PM PDT 24
Peak memory 220564 kb
Host smart-b1fa3951-4f15-453d-962d-383c817a148f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1285635599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1285635599
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.551866700
Short name T40
Test name
Test status
Simulation time 165861199 ps
CPU time 1.03 seconds
Started May 07 02:25:21 PM PDT 24
Finished May 07 02:25:23 PM PDT 24
Peak memory 208020 kb
Host smart-e9373748-f7e0-4715-866b-2139c27994ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551866700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.551866700
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2287797935
Short name T598
Test name
Test status
Simulation time 2542906719 ps
CPU time 4.22 seconds
Started May 07 02:25:15 PM PDT 24
Finished May 07 02:25:20 PM PDT 24
Peak memory 216392 kb
Host smart-2cc3f076-5ace-4e5a-a8ef-8ac623d7918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287797935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2287797935
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1396497197
Short name T660
Test name
Test status
Simulation time 7817927074 ps
CPU time 4.7 seconds
Started May 07 02:25:14 PM PDT 24
Finished May 07 02:25:19 PM PDT 24
Peak memory 216332 kb
Host smart-8465a9db-7371-48a3-b881-12a47c3ffd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396497197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1396497197
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1267513314
Short name T651
Test name
Test status
Simulation time 49931343 ps
CPU time 1.23 seconds
Started May 07 02:25:13 PM PDT 24
Finished May 07 02:25:14 PM PDT 24
Peak memory 207948 kb
Host smart-08e4e01f-5236-4a3a-ac89-a43b6a8c613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267513314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1267513314
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4249240842
Short name T648
Test name
Test status
Simulation time 175966943 ps
CPU time 0.74 seconds
Started May 07 02:25:14 PM PDT 24
Finished May 07 02:25:15 PM PDT 24
Peak memory 205816 kb
Host smart-d12e1809-5464-4766-98fd-ce65f0a2f1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249240842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4249240842
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3442232557
Short name T391
Test name
Test status
Simulation time 14387404 ps
CPU time 0.73 seconds
Started May 07 02:25:28 PM PDT 24
Finished May 07 02:25:30 PM PDT 24
Peak memory 205408 kb
Host smart-76441228-3abb-4094-a636-003538ee00de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442232557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3442232557
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3154977725
Short name T93
Test name
Test status
Simulation time 1995326747 ps
CPU time 5.09 seconds
Started May 07 02:25:21 PM PDT 24
Finished May 07 02:25:27 PM PDT 24
Peak memory 223520 kb
Host smart-9206ef27-27ae-4f40-864a-0e8820d17542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154977725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3154977725
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.700743991
Short name T445
Test name
Test status
Simulation time 69922567 ps
CPU time 0.82 seconds
Started May 07 02:25:21 PM PDT 24
Finished May 07 02:25:23 PM PDT 24
Peak memory 206688 kb
Host smart-dcbcbdbe-fd0f-4219-b43b-c3efa1599a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700743991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.700743991
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1262132938
Short name T208
Test name
Test status
Simulation time 297427560 ps
CPU time 5.39 seconds
Started May 07 02:25:23 PM PDT 24
Finished May 07 02:25:29 PM PDT 24
Peak memory 218476 kb
Host smart-7d106986-a8e5-476d-876a-9d931f33ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262132938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1262132938
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.872495146
Short name T309
Test name
Test status
Simulation time 6560750488 ps
CPU time 10.68 seconds
Started May 07 02:25:23 PM PDT 24
Finished May 07 02:25:34 PM PDT 24
Peak memory 222880 kb
Host smart-c9b71f21-b560-4380-b943-229cf8d094c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872495146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.872495146
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1447072506
Short name T7
Test name
Test status
Simulation time 122899746 ps
CPU time 4.63 seconds
Started May 07 02:25:21 PM PDT 24
Finished May 07 02:25:26 PM PDT 24
Peak memory 223068 kb
Host smart-78f72ea9-ebc3-440c-803b-293e5c11d79a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1447072506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1447072506
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2532468824
Short name T361
Test name
Test status
Simulation time 94733130 ps
CPU time 1.13 seconds
Started May 07 02:25:27 PM PDT 24
Finished May 07 02:25:29 PM PDT 24
Peak memory 207348 kb
Host smart-e37c0f64-c828-434a-9276-5fe476ea71c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532468824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2532468824
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3677305934
Short name T372
Test name
Test status
Simulation time 1950637764 ps
CPU time 13.18 seconds
Started May 07 02:25:23 PM PDT 24
Finished May 07 02:25:37 PM PDT 24
Peak memory 216308 kb
Host smart-319e1e37-938c-4348-aa4d-f341824e66e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677305934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3677305934
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2257776479
Short name T650
Test name
Test status
Simulation time 2162241683 ps
CPU time 5.31 seconds
Started May 07 02:25:22 PM PDT 24
Finished May 07 02:25:28 PM PDT 24
Peak memory 216364 kb
Host smart-97561129-e982-4859-87ee-a97a9355c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257776479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2257776479
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1917667040
Short name T494
Test name
Test status
Simulation time 1212585094 ps
CPU time 8.05 seconds
Started May 07 02:25:22 PM PDT 24
Finished May 07 02:25:31 PM PDT 24
Peak memory 216288 kb
Host smart-629d597d-49c5-4678-a7f7-3978cbf90456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917667040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1917667040
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2459094917
Short name T12
Test name
Test status
Simulation time 82102621 ps
CPU time 0.9 seconds
Started May 07 02:25:21 PM PDT 24
Finished May 07 02:25:23 PM PDT 24
Peak memory 205760 kb
Host smart-62866672-5aaa-4e79-b9fe-6061ccecc9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459094917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2459094917
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3653387193
Short name T307
Test name
Test status
Simulation time 3890414136 ps
CPU time 10.66 seconds
Started May 07 02:25:23 PM PDT 24
Finished May 07 02:25:34 PM PDT 24
Peak memory 236464 kb
Host smart-257127eb-884c-4f2d-b99d-f5f18361110a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653387193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3653387193
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.385641631
Short name T425
Test name
Test status
Simulation time 19182188 ps
CPU time 0.72 seconds
Started May 07 02:25:30 PM PDT 24
Finished May 07 02:25:32 PM PDT 24
Peak memory 204876 kb
Host smart-f347fe37-adc3-48a0-8dbd-40d1f43bce71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385641631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.385641631
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3870579575
Short name T24
Test name
Test status
Simulation time 3172774559 ps
CPU time 23.78 seconds
Started May 07 02:25:33 PM PDT 24
Finished May 07 02:25:58 PM PDT 24
Peak memory 219016 kb
Host smart-e83a4561-5923-4bcc-96c1-3b09caf46c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870579575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3870579575
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4090534178
Short name T695
Test name
Test status
Simulation time 23233964 ps
CPU time 0.81 seconds
Started May 07 02:25:31 PM PDT 24
Finished May 07 02:25:33 PM PDT 24
Peak memory 206752 kb
Host smart-d11b1976-7c21-4195-81e1-cd76d02f4ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090534178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4090534178
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1700840689
Short name T293
Test name
Test status
Simulation time 36890647555 ps
CPU time 57.4 seconds
Started May 07 02:25:27 PM PDT 24
Finished May 07 02:26:25 PM PDT 24
Peak memory 249660 kb
Host smart-c4a51ec8-22fe-44f8-b6e5-8aca4e3f8f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700840689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1700840689
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2813623405
Short name T85
Test name
Test status
Simulation time 14408393987 ps
CPU time 135.98 seconds
Started May 07 02:25:28 PM PDT 24
Finished May 07 02:27:45 PM PDT 24
Peak memory 230696 kb
Host smart-1cb257c6-d9fb-4ff1-b310-47845259a31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813623405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2813623405
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.586621503
Short name T227
Test name
Test status
Simulation time 1217088617 ps
CPU time 6.85 seconds
Started May 07 02:25:30 PM PDT 24
Finished May 07 02:25:38 PM PDT 24
Peak memory 223652 kb
Host smart-1c3226e7-bf46-4a4d-a473-0f73da9d9243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586621503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.586621503
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3985067761
Short name T162
Test name
Test status
Simulation time 1892583242 ps
CPU time 21.26 seconds
Started May 07 02:25:31 PM PDT 24
Finished May 07 02:25:53 PM PDT 24
Peak memory 222016 kb
Host smart-1ec0681a-6203-4cbc-bcf7-0bc5779b787a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3985067761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3985067761
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3157962434
Short name T602
Test name
Test status
Simulation time 2914399132 ps
CPU time 13.31 seconds
Started May 07 02:25:28 PM PDT 24
Finished May 07 02:25:43 PM PDT 24
Peak memory 216512 kb
Host smart-6e7aa136-098f-4d05-b9f3-ccb974965221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157962434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3157962434
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1405580325
Short name T549
Test name
Test status
Simulation time 892323230 ps
CPU time 5.69 seconds
Started May 07 02:25:27 PM PDT 24
Finished May 07 02:25:34 PM PDT 24
Peak memory 216348 kb
Host smart-3cf42ec5-e2b3-4dda-a7b8-8892e5b17351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405580325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1405580325
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.97855167
Short name T61
Test name
Test status
Simulation time 617561178 ps
CPU time 6.19 seconds
Started May 07 02:25:28 PM PDT 24
Finished May 07 02:25:35 PM PDT 24
Peak memory 216304 kb
Host smart-ada52800-20f1-459b-bc4a-d99b9ec46aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97855167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.97855167
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2630855428
Short name T605
Test name
Test status
Simulation time 136261961 ps
CPU time 0.96 seconds
Started May 07 02:25:31 PM PDT 24
Finished May 07 02:25:33 PM PDT 24
Peak memory 206808 kb
Host smart-a1e2133f-2185-4fcc-a904-c885e59991c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630855428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2630855428
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1758100468
Short name T50
Test name
Test status
Simulation time 19340551 ps
CPU time 0.71 seconds
Started May 07 02:17:59 PM PDT 24
Finished May 07 02:18:00 PM PDT 24
Peak memory 205456 kb
Host smart-746936e0-43fa-4a94-b424-39d0bca2af8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758100468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
758100468
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2060635078
Short name T326
Test name
Test status
Simulation time 315312571 ps
CPU time 4.02 seconds
Started May 07 02:17:52 PM PDT 24
Finished May 07 02:17:57 PM PDT 24
Peak memory 223708 kb
Host smart-abad072c-b7e0-4ac7-99ad-038a83c463a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060635078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2060635078
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3059487994
Short name T657
Test name
Test status
Simulation time 21961293 ps
CPU time 0.81 seconds
Started May 07 02:17:45 PM PDT 24
Finished May 07 02:17:47 PM PDT 24
Peak memory 207044 kb
Host smart-b04cf27b-aa93-4b6e-b74a-00fcb61510aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059487994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3059487994
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.947134689
Short name T54
Test name
Test status
Simulation time 1492631169 ps
CPU time 14.46 seconds
Started May 07 02:17:55 PM PDT 24
Finished May 07 02:18:11 PM PDT 24
Peak memory 240832 kb
Host smart-2988b0a6-7e81-4d06-97e1-5e20ce84f310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947134689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.947134689
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1426009067
Short name T630
Test name
Test status
Simulation time 833501479 ps
CPU time 11.79 seconds
Started May 07 02:17:51 PM PDT 24
Finished May 07 02:18:03 PM PDT 24
Peak memory 217376 kb
Host smart-5924b788-378d-4f9a-8d06-39a27eb1dc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426009067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1426009067
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3072885336
Short name T215
Test name
Test status
Simulation time 74699603162 ps
CPU time 23.64 seconds
Started May 07 02:17:50 PM PDT 24
Finished May 07 02:18:14 PM PDT 24
Peak memory 223948 kb
Host smart-ec6597ec-a33a-4074-b3f4-a484d58bc273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072885336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3072885336
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2394602036
Short name T485
Test name
Test status
Simulation time 1246394729 ps
CPU time 8.79 seconds
Started May 07 02:17:55 PM PDT 24
Finished May 07 02:18:05 PM PDT 24
Peak memory 221864 kb
Host smart-ae1610fa-bf46-4c3a-8456-330b14ea5277
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2394602036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2394602036
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3240825431
Short name T47
Test name
Test status
Simulation time 184766419 ps
CPU time 1.14 seconds
Started May 07 02:17:57 PM PDT 24
Finished May 07 02:17:58 PM PDT 24
Peak memory 235128 kb
Host smart-f0442caa-516d-4ed8-a6b7-26645fce53af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240825431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3240825431
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1560140151
Short name T540
Test name
Test status
Simulation time 6616384089 ps
CPU time 15.04 seconds
Started May 07 02:17:45 PM PDT 24
Finished May 07 02:18:01 PM PDT 24
Peak memory 216344 kb
Host smart-742e5b90-b135-420c-8d02-628d25bb7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560140151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1560140151
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2168995357
Short name T403
Test name
Test status
Simulation time 7882668892 ps
CPU time 19.33 seconds
Started May 07 02:17:44 PM PDT 24
Finished May 07 02:18:04 PM PDT 24
Peak memory 216352 kb
Host smart-831adf9b-5bcb-4096-b096-3badd7c974e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168995357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2168995357
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3588348961
Short name T446
Test name
Test status
Simulation time 593204802 ps
CPU time 1.81 seconds
Started May 07 02:17:50 PM PDT 24
Finished May 07 02:17:52 PM PDT 24
Peak memory 216276 kb
Host smart-6d972621-133a-4fda-9b0e-d7a0100d1344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588348961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3588348961
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4287288076
Short name T581
Test name
Test status
Simulation time 20689422 ps
CPU time 0.74 seconds
Started May 07 02:17:51 PM PDT 24
Finished May 07 02:17:52 PM PDT 24
Peak memory 205840 kb
Host smart-4a1f41be-f6dc-487a-ae43-4a3be1ab3d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287288076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4287288076
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3955604200
Short name T625
Test name
Test status
Simulation time 262820488 ps
CPU time 2.27 seconds
Started May 07 02:17:52 PM PDT 24
Finished May 07 02:17:55 PM PDT 24
Peak memory 219044 kb
Host smart-20064586-f9ce-46ee-9abe-fc91f39ecc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955604200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3955604200
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2089080706
Short name T67
Test name
Test status
Simulation time 13259658 ps
CPU time 0.68 seconds
Started May 07 02:25:32 PM PDT 24
Finished May 07 02:25:34 PM PDT 24
Peak memory 204824 kb
Host smart-63ff63b5-0e6e-4679-b14b-a51c51c7b24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089080706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2089080706
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.121118079
Short name T92
Test name
Test status
Simulation time 812957681 ps
CPU time 6.46 seconds
Started May 07 02:25:33 PM PDT 24
Finished May 07 02:25:40 PM PDT 24
Peak memory 218864 kb
Host smart-0920c6f6-79dd-4074-b9e9-f93106da291f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121118079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.121118079
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.250815731
Short name T546
Test name
Test status
Simulation time 73238341 ps
CPU time 0.79 seconds
Started May 07 02:25:28 PM PDT 24
Finished May 07 02:25:30 PM PDT 24
Peak memory 207060 kb
Host smart-48acb616-e7c7-4d5e-940a-acb53d44a417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250815731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.250815731
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.601412099
Short name T663
Test name
Test status
Simulation time 1078136748 ps
CPU time 21.56 seconds
Started May 07 02:25:33 PM PDT 24
Finished May 07 02:25:56 PM PDT 24
Peak memory 249140 kb
Host smart-3168b014-9240-4a0c-87c9-fd9fcdb7f5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601412099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.601412099
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4028177333
Short name T178
Test name
Test status
Simulation time 5314674105 ps
CPU time 21.51 seconds
Started May 07 02:25:37 PM PDT 24
Finished May 07 02:25:59 PM PDT 24
Peak memory 223148 kb
Host smart-12c3f63e-1e51-4760-8e7f-c8e34e35c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028177333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4028177333
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4243825998
Short name T246
Test name
Test status
Simulation time 257087083 ps
CPU time 3.16 seconds
Started May 07 02:25:36 PM PDT 24
Finished May 07 02:25:40 PM PDT 24
Peak memory 224076 kb
Host smart-ce92bdca-1269-4cd1-9c50-7f3b15c1104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243825998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4243825998
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4080272155
Short name T503
Test name
Test status
Simulation time 273230068 ps
CPU time 6.28 seconds
Started May 07 02:25:34 PM PDT 24
Finished May 07 02:25:41 PM PDT 24
Peak memory 222556 kb
Host smart-61c227fd-dccc-400d-b3e9-6b4db1bf4fce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4080272155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4080272155
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.399687391
Short name T382
Test name
Test status
Simulation time 20214829184 ps
CPU time 55.65 seconds
Started May 07 02:25:27 PM PDT 24
Finished May 07 02:26:24 PM PDT 24
Peak memory 216504 kb
Host smart-c71d19a4-e3c7-4708-8755-29c6b756ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399687391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.399687391
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.629006321
Short name T396
Test name
Test status
Simulation time 141261735 ps
CPU time 1.31 seconds
Started May 07 02:25:25 PM PDT 24
Finished May 07 02:25:28 PM PDT 24
Peak memory 207916 kb
Host smart-f86d20da-285d-4af5-b660-3d651d1a756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629006321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.629006321
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4200401658
Short name T600
Test name
Test status
Simulation time 211068273 ps
CPU time 2.88 seconds
Started May 07 02:25:33 PM PDT 24
Finished May 07 02:25:37 PM PDT 24
Peak memory 216616 kb
Host smart-b97b3998-5cde-42d9-a59d-3258f25a36a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200401658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4200401658
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3341519672
Short name T579
Test name
Test status
Simulation time 40764900 ps
CPU time 0.95 seconds
Started May 07 02:25:28 PM PDT 24
Finished May 07 02:25:30 PM PDT 24
Peak memory 206824 kb
Host smart-a256b24c-d9a4-4623-b9f0-bc92ba8153c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341519672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3341519672
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.95738919
Short name T606
Test name
Test status
Simulation time 10874288 ps
CPU time 0.71 seconds
Started May 07 02:25:41 PM PDT 24
Finished May 07 02:25:42 PM PDT 24
Peak memory 205936 kb
Host smart-f2baae91-2468-4e09-b561-37f3e298d041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95738919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.95738919
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.689754328
Short name T27
Test name
Test status
Simulation time 5092641146 ps
CPU time 41.73 seconds
Started May 07 02:25:41 PM PDT 24
Finished May 07 02:26:24 PM PDT 24
Peak memory 218884 kb
Host smart-fe4da15f-fa57-499b-aa1b-35ad100b78ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689754328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.689754328
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4024037904
Short name T545
Test name
Test status
Simulation time 53407320 ps
CPU time 0.82 seconds
Started May 07 02:25:35 PM PDT 24
Finished May 07 02:25:37 PM PDT 24
Peak memory 206736 kb
Host smart-b6e44f3c-7836-4788-8f8e-b728b95580c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024037904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4024037904
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1269129865
Short name T292
Test name
Test status
Simulation time 1335221149 ps
CPU time 29.9 seconds
Started May 07 02:25:43 PM PDT 24
Finished May 07 02:26:13 PM PDT 24
Peak memory 252084 kb
Host smart-415c8c0a-3df2-43cd-bb94-3d360271f1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269129865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1269129865
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4059167101
Short name T323
Test name
Test status
Simulation time 20362038618 ps
CPU time 41.08 seconds
Started May 07 02:25:37 PM PDT 24
Finished May 07 02:26:19 PM PDT 24
Peak memory 219008 kb
Host smart-105c6af9-61d0-49de-816f-79845a9cc83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059167101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4059167101
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2629208298
Short name T324
Test name
Test status
Simulation time 134509878 ps
CPU time 3.58 seconds
Started May 07 02:25:41 PM PDT 24
Finished May 07 02:25:45 PM PDT 24
Peak memory 222976 kb
Host smart-3a827fb4-4941-4df6-84ce-3534862073a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629208298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2629208298
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1053990115
Short name T493
Test name
Test status
Simulation time 1020747082 ps
CPU time 5.89 seconds
Started May 07 02:25:41 PM PDT 24
Finished May 07 02:25:47 PM PDT 24
Peak memory 218928 kb
Host smart-3aca8ee7-a447-49ff-904e-cc2590fe0fb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1053990115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1053990115
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2129655796
Short name T389
Test name
Test status
Simulation time 16950783412 ps
CPU time 22.77 seconds
Started May 07 02:25:34 PM PDT 24
Finished May 07 02:25:57 PM PDT 24
Peak memory 216424 kb
Host smart-9431120b-88b2-4be4-ab06-1800039811d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129655796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2129655796
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1276138314
Short name T711
Test name
Test status
Simulation time 5049691213 ps
CPU time 9.42 seconds
Started May 07 02:25:38 PM PDT 24
Finished May 07 02:25:48 PM PDT 24
Peak memory 216392 kb
Host smart-f2e8b52c-e78a-4ebe-9705-7be62bf182ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276138314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1276138314
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1426146041
Short name T583
Test name
Test status
Simulation time 403564223 ps
CPU time 6.68 seconds
Started May 07 02:25:37 PM PDT 24
Finished May 07 02:25:45 PM PDT 24
Peak memory 216360 kb
Host smart-23117cfb-3fb4-4e91-94f6-2380b88fc717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426146041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1426146041
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2465793952
Short name T638
Test name
Test status
Simulation time 2339376499 ps
CPU time 1.08 seconds
Started May 07 02:25:38 PM PDT 24
Finished May 07 02:25:39 PM PDT 24
Peak memory 206920 kb
Host smart-b6ced37a-8d51-4e4f-b2ca-843c644da4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465793952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2465793952
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3225137507
Short name T14
Test name
Test status
Simulation time 20097395 ps
CPU time 0.69 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:25:46 PM PDT 24
Peak memory 204880 kb
Host smart-0a8bb030-0687-426c-b77b-97101060a5f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225137507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3225137507
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3940092913
Short name T699
Test name
Test status
Simulation time 110987339 ps
CPU time 3.01 seconds
Started May 07 02:25:47 PM PDT 24
Finished May 07 02:25:51 PM PDT 24
Peak memory 221188 kb
Host smart-1d64b7d5-1831-4f7f-9b77-16854862f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940092913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3940092913
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.268517930
Short name T505
Test name
Test status
Simulation time 19337041 ps
CPU time 0.73 seconds
Started May 07 02:25:40 PM PDT 24
Finished May 07 02:25:42 PM PDT 24
Peak memory 205692 kb
Host smart-3557a157-ba6e-4f49-b923-4d030b4508e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268517930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.268517930
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2075567432
Short name T614
Test name
Test status
Simulation time 917188579 ps
CPU time 25.78 seconds
Started May 07 02:25:42 PM PDT 24
Finished May 07 02:26:09 PM PDT 24
Peak memory 238172 kb
Host smart-ecc51fac-128e-4807-83b1-7874983a6b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075567432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2075567432
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4035288513
Short name T188
Test name
Test status
Simulation time 1410970943 ps
CPU time 18.9 seconds
Started May 07 02:25:45 PM PDT 24
Finished May 07 02:26:04 PM PDT 24
Peak memory 231380 kb
Host smart-4670042a-75be-448e-b047-ae4c189664f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035288513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4035288513
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1270183950
Short name T624
Test name
Test status
Simulation time 4479073387 ps
CPU time 14.83 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:26:00 PM PDT 24
Peak memory 220552 kb
Host smart-7807ce0f-a50a-4ec6-895a-f976cbf4bf5d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1270183950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1270183950
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4266521106
Short name T530
Test name
Test status
Simulation time 54530594 ps
CPU time 1 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:25:46 PM PDT 24
Peak memory 207216 kb
Host smart-a49ec571-f4e6-40ca-84e5-8d45fab23e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266521106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4266521106
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3131674824
Short name T693
Test name
Test status
Simulation time 3302300243 ps
CPU time 4.5 seconds
Started May 07 02:25:39 PM PDT 24
Finished May 07 02:25:44 PM PDT 24
Peak memory 216388 kb
Host smart-859933f6-1eb4-4a7e-8dd6-98861392f1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131674824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3131674824
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1237504009
Short name T483
Test name
Test status
Simulation time 133887288 ps
CPU time 1.45 seconds
Started May 07 02:25:46 PM PDT 24
Finished May 07 02:25:48 PM PDT 24
Peak memory 216356 kb
Host smart-ede50803-4360-47d7-be28-cf892803f11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237504009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1237504009
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2795389377
Short name T548
Test name
Test status
Simulation time 16613203 ps
CPU time 0.72 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:25:45 PM PDT 24
Peak memory 205832 kb
Host smart-3de2c283-440f-4678-a909-508053fbd3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795389377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2795389377
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3759924183
Short name T653
Test name
Test status
Simulation time 13850200 ps
CPU time 0.75 seconds
Started May 07 02:25:54 PM PDT 24
Finished May 07 02:25:55 PM PDT 24
Peak memory 205416 kb
Host smart-f775db92-c859-4e18-8c45-9073068c7b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759924183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3759924183
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1279467266
Short name T534
Test name
Test status
Simulation time 1275509295 ps
CPU time 4.6 seconds
Started May 07 02:25:52 PM PDT 24
Finished May 07 02:25:58 PM PDT 24
Peak memory 218912 kb
Host smart-0f4a2191-ca71-4b0a-a9f9-ce54dec435ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279467266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1279467266
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2689022291
Short name T498
Test name
Test status
Simulation time 104093942 ps
CPU time 0.77 seconds
Started May 07 02:25:46 PM PDT 24
Finished May 07 02:25:47 PM PDT 24
Peak memory 206696 kb
Host smart-88f9299c-6222-481c-8356-98bfb84f0e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689022291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2689022291
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3541148044
Short name T258
Test name
Test status
Simulation time 1301912162 ps
CPU time 3.33 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:25:47 PM PDT 24
Peak memory 218812 kb
Host smart-75d8e865-d693-4f88-92ae-3daf007e8f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541148044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3541148044
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1345306650
Short name T95
Test name
Test status
Simulation time 6148680065 ps
CPU time 21.69 seconds
Started May 07 02:25:53 PM PDT 24
Finished May 07 02:26:15 PM PDT 24
Peak memory 232804 kb
Host smart-519569bd-0094-4f1e-8834-00a5b5988db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345306650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1345306650
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3619706855
Short name T715
Test name
Test status
Simulation time 1598283352 ps
CPU time 17.64 seconds
Started May 07 02:25:53 PM PDT 24
Finished May 07 02:26:12 PM PDT 24
Peak memory 222968 kb
Host smart-bc0ba179-f1f0-4342-a7d8-3a7c3f141c1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3619706855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3619706855
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2761597852
Short name T516
Test name
Test status
Simulation time 750216719 ps
CPU time 6.14 seconds
Started May 07 02:25:48 PM PDT 24
Finished May 07 02:25:55 PM PDT 24
Peak memory 216280 kb
Host smart-23073a81-e40b-4333-bbd3-45f6c7669cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761597852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2761597852
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.483677054
Short name T687
Test name
Test status
Simulation time 3181693613 ps
CPU time 8.67 seconds
Started May 07 02:25:44 PM PDT 24
Finished May 07 02:25:53 PM PDT 24
Peak memory 216348 kb
Host smart-64e2cc36-b5c3-4566-b650-100f197ed5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483677054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.483677054
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3415878636
Short name T70
Test name
Test status
Simulation time 340274007 ps
CPU time 4.14 seconds
Started May 07 02:25:46 PM PDT 24
Finished May 07 02:25:51 PM PDT 24
Peak memory 216248 kb
Host smart-38820caa-a102-4edc-b25d-817755df2c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415878636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3415878636
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2543680959
Short name T573
Test name
Test status
Simulation time 54578569 ps
CPU time 0.91 seconds
Started May 07 02:25:46 PM PDT 24
Finished May 07 02:25:48 PM PDT 24
Peak memory 205496 kb
Host smart-db83fb1b-3961-44c1-b41e-975b2a02230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543680959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2543680959
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3965702422
Short name T588
Test name
Test status
Simulation time 47141591 ps
CPU time 0.7 seconds
Started May 07 02:26:01 PM PDT 24
Finished May 07 02:26:03 PM PDT 24
Peak memory 205436 kb
Host smart-2adeb9cd-0cff-49a6-ad77-09e4df8a1284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965702422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3965702422
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1941342810
Short name T468
Test name
Test status
Simulation time 61980573 ps
CPU time 0.75 seconds
Started May 07 02:25:51 PM PDT 24
Finished May 07 02:25:52 PM PDT 24
Peak memory 207028 kb
Host smart-e27eca01-c183-4b3a-9fdf-e98819bffd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941342810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1941342810
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3838982584
Short name T584
Test name
Test status
Simulation time 9920658016 ps
CPU time 75.73 seconds
Started May 07 02:26:02 PM PDT 24
Finished May 07 02:27:19 PM PDT 24
Peak memory 257152 kb
Host smart-9ee2a00e-98a0-456c-9255-8e5826f7a672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838982584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3838982584
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4031123505
Short name T177
Test name
Test status
Simulation time 32784493324 ps
CPU time 54.69 seconds
Started May 07 02:25:51 PM PDT 24
Finished May 07 02:26:47 PM PDT 24
Peak memory 232784 kb
Host smart-37fbe55e-59a2-42c8-87d3-31b9663249d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031123505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4031123505
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1420683460
Short name T604
Test name
Test status
Simulation time 4131357361 ps
CPU time 15.48 seconds
Started May 07 02:26:02 PM PDT 24
Finished May 07 02:26:18 PM PDT 24
Peak memory 220236 kb
Host smart-1f17e802-bcf3-4a7a-ab72-8df6a32b7e00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1420683460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1420683460
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.337973527
Short name T694
Test name
Test status
Simulation time 1814679589 ps
CPU time 9.59 seconds
Started May 07 02:25:51 PM PDT 24
Finished May 07 02:26:01 PM PDT 24
Peak memory 216244 kb
Host smart-fcdbb402-f0c7-42ef-9b55-2e8ebf6b0db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337973527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.337973527
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.373354988
Short name T379
Test name
Test status
Simulation time 398695091 ps
CPU time 7.56 seconds
Started May 07 02:25:51 PM PDT 24
Finished May 07 02:25:59 PM PDT 24
Peak memory 216388 kb
Host smart-4d7a5fd4-b7fa-4b8d-8b4c-9f47050b4ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373354988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.373354988
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3528193628
Short name T662
Test name
Test status
Simulation time 29509639 ps
CPU time 0.85 seconds
Started May 07 02:25:54 PM PDT 24
Finished May 07 02:25:56 PM PDT 24
Peak memory 205504 kb
Host smart-ca0155ef-60da-4fc6-a117-087a152c8653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528193628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3528193628
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1806535869
Short name T28
Test name
Test status
Simulation time 5456847152 ps
CPU time 8.11 seconds
Started May 07 02:26:02 PM PDT 24
Finished May 07 02:26:11 PM PDT 24
Peak memory 219388 kb
Host smart-1f9dfe0c-25f5-4b4a-9c42-ee117bbff04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806535869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1806535869
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2006643082
Short name T429
Test name
Test status
Simulation time 25162701 ps
CPU time 0.72 seconds
Started May 07 02:26:05 PM PDT 24
Finished May 07 02:26:07 PM PDT 24
Peak memory 204832 kb
Host smart-4b17033a-7ed3-4c3c-9246-600ca889ef84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006643082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2006643082
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2398453784
Short name T109
Test name
Test status
Simulation time 297696942 ps
CPU time 3.28 seconds
Started May 07 02:26:06 PM PDT 24
Finished May 07 02:26:10 PM PDT 24
Peak memory 222224 kb
Host smart-2bc0c4fe-bec6-4bb7-9a6c-5421d240b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398453784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2398453784
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1624081959
Short name T450
Test name
Test status
Simulation time 19117146 ps
CPU time 0.8 seconds
Started May 07 02:25:59 PM PDT 24
Finished May 07 02:26:01 PM PDT 24
Peak memory 206708 kb
Host smart-2dcd8536-b323-449a-be63-573d74df336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624081959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1624081959
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.252364767
Short name T350
Test name
Test status
Simulation time 34070767787 ps
CPU time 102.74 seconds
Started May 07 02:26:07 PM PDT 24
Finished May 07 02:27:50 PM PDT 24
Peak memory 249168 kb
Host smart-88fd280a-90b1-4591-a581-4e560f6ab72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252364767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.252364767
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3445573536
Short name T553
Test name
Test status
Simulation time 50885426 ps
CPU time 2.42 seconds
Started May 07 02:26:05 PM PDT 24
Finished May 07 02:26:09 PM PDT 24
Peak memory 221972 kb
Host smart-52740656-7995-45a2-a6cd-f4e553feebfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445573536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3445573536
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2604351747
Short name T551
Test name
Test status
Simulation time 1157846973 ps
CPU time 6.88 seconds
Started May 07 02:26:00 PM PDT 24
Finished May 07 02:26:08 PM PDT 24
Peak memory 216928 kb
Host smart-b719210e-f9f8-4732-84d9-a962c031418a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604351747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2604351747
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3656513655
Short name T561
Test name
Test status
Simulation time 669970025 ps
CPU time 9 seconds
Started May 07 02:26:06 PM PDT 24
Finished May 07 02:26:16 PM PDT 24
Peak memory 222092 kb
Host smart-d61bc0ab-6880-48c0-bfc6-9eddb89d4e9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3656513655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3656513655
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1227159879
Short name T385
Test name
Test status
Simulation time 4103730049 ps
CPU time 40.49 seconds
Started May 07 02:26:00 PM PDT 24
Finished May 07 02:26:41 PM PDT 24
Peak memory 216308 kb
Host smart-d16b59f8-5005-40a2-9660-4a37187f1858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227159879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1227159879
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3703349566
Short name T665
Test name
Test status
Simulation time 856039963 ps
CPU time 2.88 seconds
Started May 07 02:26:01 PM PDT 24
Finished May 07 02:26:05 PM PDT 24
Peak memory 216348 kb
Host smart-d0e468a1-f5f2-4306-8a69-1bba06b86b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703349566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3703349566
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.816459986
Short name T685
Test name
Test status
Simulation time 334619095 ps
CPU time 8.38 seconds
Started May 07 02:25:59 PM PDT 24
Finished May 07 02:26:08 PM PDT 24
Peak memory 216364 kb
Host smart-544a6248-85d7-4c73-9677-b87aa5da973d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816459986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.816459986
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2648629538
Short name T674
Test name
Test status
Simulation time 105145650 ps
CPU time 1.03 seconds
Started May 07 02:25:58 PM PDT 24
Finished May 07 02:26:00 PM PDT 24
Peak memory 206264 kb
Host smart-c961ddc5-43f6-4254-8bbc-c3a37395febb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648629538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2648629538
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2661950078
Short name T691
Test name
Test status
Simulation time 1083434664 ps
CPU time 2.89 seconds
Started May 07 02:26:07 PM PDT 24
Finished May 07 02:26:11 PM PDT 24
Peak memory 216308 kb
Host smart-0eaf5805-8df3-4616-ab50-2e80a4c7c1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661950078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2661950078
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.605951759
Short name T416
Test name
Test status
Simulation time 23074563 ps
CPU time 0.68 seconds
Started May 07 02:26:11 PM PDT 24
Finished May 07 02:26:12 PM PDT 24
Peak memory 204852 kb
Host smart-c6f4fc02-fd4d-44b6-b007-c47e63b2c099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605951759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.605951759
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3927843605
Short name T656
Test name
Test status
Simulation time 12558882 ps
CPU time 0.77 seconds
Started May 07 02:26:06 PM PDT 24
Finished May 07 02:26:08 PM PDT 24
Peak memory 206020 kb
Host smart-ec7e8e2d-9047-4e8e-bd04-45104c05f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927843605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3927843605
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2531477778
Short name T363
Test name
Test status
Simulation time 9205038755 ps
CPU time 123.82 seconds
Started May 07 02:26:13 PM PDT 24
Finished May 07 02:28:18 PM PDT 24
Peak memory 235668 kb
Host smart-29d513a6-6bae-44d5-872c-50b665782927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531477778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2531477778
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4209361336
Short name T637
Test name
Test status
Simulation time 753902498 ps
CPU time 3.67 seconds
Started May 07 02:26:14 PM PDT 24
Finished May 07 02:26:18 PM PDT 24
Peak memory 223192 kb
Host smart-02758eb0-da9b-4662-920a-6d3879169fc8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4209361336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4209361336
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.234422764
Short name T32
Test name
Test status
Simulation time 157584904 ps
CPU time 1.18 seconds
Started May 07 02:26:14 PM PDT 24
Finished May 07 02:26:16 PM PDT 24
Peak memory 207424 kb
Host smart-fa96b5e4-f0ee-4d80-86dd-a376d5f3ea08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234422764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.234422764
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4026123038
Short name T374
Test name
Test status
Simulation time 49391718890 ps
CPU time 61.51 seconds
Started May 07 02:26:06 PM PDT 24
Finished May 07 02:27:09 PM PDT 24
Peak memory 216340 kb
Host smart-6eca8a51-8276-4c05-8548-6ec665cf17b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026123038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4026123038
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1867633687
Short name T487
Test name
Test status
Simulation time 9047943855 ps
CPU time 7.49 seconds
Started May 07 02:26:06 PM PDT 24
Finished May 07 02:26:15 PM PDT 24
Peak memory 216484 kb
Host smart-3604e330-b834-4099-910b-578c20a432f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867633687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1867633687
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4106813097
Short name T640
Test name
Test status
Simulation time 223752434 ps
CPU time 6.58 seconds
Started May 07 02:26:05 PM PDT 24
Finished May 07 02:26:12 PM PDT 24
Peak memory 216316 kb
Host smart-ebc39875-1e6b-4893-b973-b8f83141a7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106813097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4106813097
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.87792532
Short name T116
Test name
Test status
Simulation time 17503128 ps
CPU time 0.72 seconds
Started May 07 02:26:06 PM PDT 24
Finished May 07 02:26:08 PM PDT 24
Peak memory 205816 kb
Host smart-fd71d566-1d1c-4639-a42a-be2d5f214d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87792532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.87792532
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4016618005
Short name T696
Test name
Test status
Simulation time 27433020 ps
CPU time 0.73 seconds
Started May 07 02:26:21 PM PDT 24
Finished May 07 02:26:23 PM PDT 24
Peak memory 204876 kb
Host smart-4e719487-c49f-40ed-a29a-54d4c0096a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016618005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4016618005
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3823830556
Short name T712
Test name
Test status
Simulation time 112512472 ps
CPU time 0.78 seconds
Started May 07 02:26:12 PM PDT 24
Finished May 07 02:26:14 PM PDT 24
Peak memory 205668 kb
Host smart-3dd0bfdc-9d72-4fcf-b9ae-eb02bdd2f5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823830556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3823830556
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.544518169
Short name T359
Test name
Test status
Simulation time 693288760 ps
CPU time 13.1 seconds
Started May 07 02:26:19 PM PDT 24
Finished May 07 02:26:32 PM PDT 24
Peak memory 250392 kb
Host smart-1483c936-186b-495d-b158-dd6498bce094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544518169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.544518169
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1505349664
Short name T197
Test name
Test status
Simulation time 238342911 ps
CPU time 4.96 seconds
Started May 07 02:26:17 PM PDT 24
Finished May 07 02:26:23 PM PDT 24
Peak memory 216320 kb
Host smart-77a15fff-0ec1-4bb4-bae7-e874761c50a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505349664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1505349664
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2760396240
Short name T173
Test name
Test status
Simulation time 53553441920 ps
CPU time 40.29 seconds
Started May 07 02:26:14 PM PDT 24
Finished May 07 02:26:55 PM PDT 24
Peak memory 246696 kb
Host smart-7256e398-b43a-4f1a-80d0-149730620ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760396240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2760396240
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.365782848
Short name T623
Test name
Test status
Simulation time 1590474015 ps
CPU time 4.69 seconds
Started May 07 02:26:21 PM PDT 24
Finished May 07 02:26:27 PM PDT 24
Peak memory 220576 kb
Host smart-c42e11ad-f82e-48bc-9546-28224a364a20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=365782848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.365782848
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1793960164
Short name T383
Test name
Test status
Simulation time 12638751812 ps
CPU time 32.34 seconds
Started May 07 02:26:14 PM PDT 24
Finished May 07 02:26:47 PM PDT 24
Peak memory 221044 kb
Host smart-faae28a7-780a-4012-9de1-29586df9b842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793960164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1793960164
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.412864782
Short name T578
Test name
Test status
Simulation time 7656382336 ps
CPU time 11.93 seconds
Started May 07 02:26:17 PM PDT 24
Finished May 07 02:26:30 PM PDT 24
Peak memory 216360 kb
Host smart-3c2091ac-b4ba-4249-9e63-30a8bd4c079e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412864782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.412864782
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3030565583
Short name T444
Test name
Test status
Simulation time 88255300 ps
CPU time 1.23 seconds
Started May 07 02:26:12 PM PDT 24
Finished May 07 02:26:14 PM PDT 24
Peak memory 208056 kb
Host smart-6d886f45-b78f-411f-90ee-60bb4ee54e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030565583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3030565583
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.766685812
Short name T683
Test name
Test status
Simulation time 78594228 ps
CPU time 1.04 seconds
Started May 07 02:26:15 PM PDT 24
Finished May 07 02:26:17 PM PDT 24
Peak memory 206868 kb
Host smart-0e1dde1c-0a37-4bc7-9948-c33232b904fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766685812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.766685812
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1374672813
Short name T488
Test name
Test status
Simulation time 22234471 ps
CPU time 0.7 seconds
Started May 07 02:26:29 PM PDT 24
Finished May 07 02:26:31 PM PDT 24
Peak memory 204880 kb
Host smart-c6b32746-0fc9-4eab-b00d-4ae129b7eea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374672813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1374672813
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2982105612
Short name T401
Test name
Test status
Simulation time 14936238 ps
CPU time 0.78 seconds
Started May 07 02:26:22 PM PDT 24
Finished May 07 02:26:24 PM PDT 24
Peak memory 206704 kb
Host smart-57dd5d87-569a-43ac-8ab4-051542623b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982105612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2982105612
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_intercept.746502203
Short name T531
Test name
Test status
Simulation time 323808855 ps
CPU time 5.01 seconds
Started May 07 02:26:26 PM PDT 24
Finished May 07 02:26:32 PM PDT 24
Peak memory 218780 kb
Host smart-3dfd4851-9954-4330-a5e2-3a788bb648ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746502203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.746502203
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.594798144
Short name T365
Test name
Test status
Simulation time 15606254738 ps
CPU time 16.44 seconds
Started May 07 02:26:23 PM PDT 24
Finished May 07 02:26:40 PM PDT 24
Peak memory 234060 kb
Host smart-fcc83fbc-53bb-40ff-b0a6-a64eaa21a7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594798144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.594798144
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2573395582
Short name T676
Test name
Test status
Simulation time 1513777330 ps
CPU time 16.26 seconds
Started May 07 02:26:24 PM PDT 24
Finished May 07 02:26:41 PM PDT 24
Peak memory 221880 kb
Host smart-58e83f78-9872-4b22-8018-bf81bf47fe4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2573395582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2573395582
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3819682773
Short name T373
Test name
Test status
Simulation time 46987852686 ps
CPU time 56.05 seconds
Started May 07 02:26:20 PM PDT 24
Finished May 07 02:27:16 PM PDT 24
Peak memory 216380 kb
Host smart-354a9f50-6bac-444e-9177-331924cb8485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819682773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3819682773
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.758974478
Short name T19
Test name
Test status
Simulation time 13055649436 ps
CPU time 38.79 seconds
Started May 07 02:26:22 PM PDT 24
Finished May 07 02:27:02 PM PDT 24
Peak memory 216396 kb
Host smart-147c4537-3c3f-4f9f-9b1c-1d73f053d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758974478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.758974478
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2362367849
Short name T562
Test name
Test status
Simulation time 1908324746 ps
CPU time 1.89 seconds
Started May 07 02:26:20 PM PDT 24
Finished May 07 02:26:23 PM PDT 24
Peak memory 216212 kb
Host smart-3aa7663d-5054-4deb-aeb6-f8e798e0a36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362367849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2362367849
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2640660386
Short name T533
Test name
Test status
Simulation time 243532542 ps
CPU time 1.03 seconds
Started May 07 02:26:21 PM PDT 24
Finished May 07 02:26:22 PM PDT 24
Peak memory 206864 kb
Host smart-6bd97acd-53be-4a49-82ed-8cced9079b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640660386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2640660386
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4086400108
Short name T250
Test name
Test status
Simulation time 695894048 ps
CPU time 4.59 seconds
Started May 07 02:26:22 PM PDT 24
Finished May 07 02:26:27 PM PDT 24
Peak memory 223080 kb
Host smart-a21963ed-85b9-4a89-a2da-f45884b59d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086400108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4086400108
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.796737473
Short name T597
Test name
Test status
Simulation time 11440338 ps
CPU time 0.69 seconds
Started May 07 02:26:33 PM PDT 24
Finished May 07 02:26:35 PM PDT 24
Peak memory 205384 kb
Host smart-51759414-8104-4439-8842-e6c635c09724
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796737473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.796737473
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3347098333
Short name T705
Test name
Test status
Simulation time 1151754144 ps
CPU time 4.49 seconds
Started May 07 02:26:32 PM PDT 24
Finished May 07 02:26:37 PM PDT 24
Peak memory 219032 kb
Host smart-b3ae9a9c-777b-4be8-b18c-3fb03dc654e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347098333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3347098333
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2310035894
Short name T571
Test name
Test status
Simulation time 33804417 ps
CPU time 0.79 seconds
Started May 07 02:26:30 PM PDT 24
Finished May 07 02:26:32 PM PDT 24
Peak memory 206756 kb
Host smart-33343f85-a2ea-43b5-b039-bdb2327a638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310035894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2310035894
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1548706664
Short name T577
Test name
Test status
Simulation time 1391834350 ps
CPU time 13.39 seconds
Started May 07 02:26:34 PM PDT 24
Finished May 07 02:26:48 PM PDT 24
Peak memory 249140 kb
Host smart-4024bccd-4297-4399-9f87-a802a86199a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548706664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1548706664
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3142336665
Short name T101
Test name
Test status
Simulation time 520933663 ps
CPU time 7.99 seconds
Started May 07 02:26:29 PM PDT 24
Finished May 07 02:26:38 PM PDT 24
Peak memory 233384 kb
Host smart-7329e0a4-5190-437e-a04c-e0703b3152d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142336665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3142336665
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2472964518
Short name T140
Test name
Test status
Simulation time 2420273315 ps
CPU time 10.03 seconds
Started May 07 02:26:32 PM PDT 24
Finished May 07 02:26:43 PM PDT 24
Peak memory 221756 kb
Host smart-cf60346c-1b52-4978-965e-9bb9d0b6ac17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2472964518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2472964518
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.581291643
Short name T113
Test name
Test status
Simulation time 5155940975 ps
CPU time 15.04 seconds
Started May 07 02:26:25 PM PDT 24
Finished May 07 02:26:41 PM PDT 24
Peak memory 218340 kb
Host smart-70640b0d-27ed-43ba-8f82-cad8f86bdc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581291643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.581291643
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.115646161
Short name T631
Test name
Test status
Simulation time 9708532064 ps
CPU time 23.93 seconds
Started May 07 02:26:27 PM PDT 24
Finished May 07 02:26:52 PM PDT 24
Peak memory 216360 kb
Host smart-a5ef1a03-0fec-4fc2-a0ca-8f7c5c22d1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115646161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.115646161
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2338497287
Short name T537
Test name
Test status
Simulation time 254795715 ps
CPU time 3.12 seconds
Started May 07 02:26:29 PM PDT 24
Finished May 07 02:26:33 PM PDT 24
Peak memory 216288 kb
Host smart-fa0e5f87-6d9b-4637-b154-0de333f99c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338497287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2338497287
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3593458521
Short name T439
Test name
Test status
Simulation time 319194492 ps
CPU time 0.98 seconds
Started May 07 02:26:33 PM PDT 24
Finished May 07 02:26:35 PM PDT 24
Peak memory 205824 kb
Host smart-8176f0a1-8235-4f04-985a-a9bb63ea560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593458521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3593458521
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2241224705
Short name T484
Test name
Test status
Simulation time 12476573 ps
CPU time 0.7 seconds
Started May 07 02:18:14 PM PDT 24
Finished May 07 02:18:15 PM PDT 24
Peak memory 205428 kb
Host smart-4ee8286b-f21e-47bc-a4fb-01a60c05eb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241224705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
241224705
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2886797522
Short name T525
Test name
Test status
Simulation time 66337583 ps
CPU time 0.79 seconds
Started May 07 02:17:55 PM PDT 24
Finished May 07 02:17:57 PM PDT 24
Peak memory 206760 kb
Host smart-7cdd2832-6454-4e26-b569-153c6bae0364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886797522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2886797522
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2445946301
Short name T655
Test name
Test status
Simulation time 48887404298 ps
CPU time 190.64 seconds
Started May 07 02:18:08 PM PDT 24
Finished May 07 02:21:19 PM PDT 24
Peak memory 250904 kb
Host smart-14f5a186-373a-4f3d-8403-935fa92f9d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445946301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2445946301
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2084022478
Short name T264
Test name
Test status
Simulation time 1478070824 ps
CPU time 13.93 seconds
Started May 07 02:18:04 PM PDT 24
Finished May 07 02:18:19 PM PDT 24
Peak memory 223784 kb
Host smart-cc7c02fa-2c4b-43ca-974d-1c29ac9d3b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084022478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2084022478
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2232783624
Short name T180
Test name
Test status
Simulation time 1285347073 ps
CPU time 14.76 seconds
Started May 07 02:18:03 PM PDT 24
Finished May 07 02:18:18 PM PDT 24
Peak memory 232476 kb
Host smart-4e8ccd8c-61fb-4382-9131-f068c2c6d9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232783624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2232783624
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1736467185
Short name T259
Test name
Test status
Simulation time 1713546446 ps
CPU time 5.77 seconds
Started May 07 02:18:03 PM PDT 24
Finished May 07 02:18:10 PM PDT 24
Peak memory 224528 kb
Host smart-fc31b070-4a18-464c-9306-ac5f95ce9c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736467185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1736467185
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.581698105
Short name T75
Test name
Test status
Simulation time 756767962 ps
CPU time 9.15 seconds
Started May 07 02:18:03 PM PDT 24
Finished May 07 02:18:14 PM PDT 24
Peak memory 224384 kb
Host smart-92d03cb2-712f-4cff-b969-9dd507dfbb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581698105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.581698105
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2385999939
Short name T644
Test name
Test status
Simulation time 157514751 ps
CPU time 4.4 seconds
Started May 07 02:18:07 PM PDT 24
Finished May 07 02:18:12 PM PDT 24
Peak memory 220960 kb
Host smart-6ba2f689-710f-4547-8093-10c59bc6c3d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2385999939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2385999939
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2017899872
Short name T646
Test name
Test status
Simulation time 203113139 ps
CPU time 1.05 seconds
Started May 07 02:18:16 PM PDT 24
Finished May 07 02:18:18 PM PDT 24
Peak memory 207440 kb
Host smart-fddb7243-d775-49a9-9737-7f910c4f8957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017899872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2017899872
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1429870701
Short name T664
Test name
Test status
Simulation time 10444510495 ps
CPU time 41.57 seconds
Started May 07 02:18:03 PM PDT 24
Finished May 07 02:18:46 PM PDT 24
Peak memory 216352 kb
Host smart-f3640114-e779-419e-958c-0d08d91c241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429870701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1429870701
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1257500456
Short name T433
Test name
Test status
Simulation time 590883601 ps
CPU time 5.05 seconds
Started May 07 02:18:03 PM PDT 24
Finished May 07 02:18:10 PM PDT 24
Peak memory 215964 kb
Host smart-3e68da16-6cd0-4e5a-9ea2-1d7064ba2de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257500456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1257500456
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.978174446
Short name T641
Test name
Test status
Simulation time 1280175499 ps
CPU time 3.67 seconds
Started May 07 02:18:04 PM PDT 24
Finished May 07 02:18:09 PM PDT 24
Peak memory 216216 kb
Host smart-9037606b-98e0-470a-93b2-2e674d31b0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978174446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.978174446
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3584151422
Short name T23
Test name
Test status
Simulation time 227386131 ps
CPU time 0.96 seconds
Started May 07 02:18:01 PM PDT 24
Finished May 07 02:18:03 PM PDT 24
Peak memory 206832 kb
Host smart-f212e3d7-adb1-4ac4-a75a-039f291536ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584151422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3584151422
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3770936424
Short name T189
Test name
Test status
Simulation time 8794848743 ps
CPU time 9.51 seconds
Started May 07 02:18:03 PM PDT 24
Finished May 07 02:18:14 PM PDT 24
Peak memory 224504 kb
Host smart-ef522366-cd2b-4769-8368-ada37e65660e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770936424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3770936424
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3780353258
Short name T560
Test name
Test status
Simulation time 113413112 ps
CPU time 0.68 seconds
Started May 07 02:18:33 PM PDT 24
Finished May 07 02:18:34 PM PDT 24
Peak memory 205416 kb
Host smart-d73538bb-22f1-4005-ab42-1f4f2b9803b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780353258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
780353258
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1845758943
Short name T434
Test name
Test status
Simulation time 70731095 ps
CPU time 0.8 seconds
Started May 07 02:18:15 PM PDT 24
Finished May 07 02:18:16 PM PDT 24
Peak memory 206696 kb
Host smart-3ea70e49-bb51-4242-8e18-da7f9d2c771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845758943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1845758943
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2187270458
Short name T351
Test name
Test status
Simulation time 1460742643 ps
CPU time 28.16 seconds
Started May 07 02:18:27 PM PDT 24
Finished May 07 02:18:56 PM PDT 24
Peak memory 251112 kb
Host smart-4337703e-1ac8-4eff-b250-92a4c81c31f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187270458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2187270458
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.526000142
Short name T129
Test name
Test status
Simulation time 1599621818 ps
CPU time 9.79 seconds
Started May 07 02:18:21 PM PDT 24
Finished May 07 02:18:31 PM PDT 24
Peak memory 219128 kb
Host smart-3587419a-fed4-432e-bfb4-40f5125e1a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526000142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.526000142
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.636010825
Short name T201
Test name
Test status
Simulation time 3129271743 ps
CPU time 8.24 seconds
Started May 07 02:18:20 PM PDT 24
Finished May 07 02:18:29 PM PDT 24
Peak memory 236704 kb
Host smart-94642668-3f02-4560-a6da-5c7497f169a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636010825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
636010825
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4284584536
Short name T399
Test name
Test status
Simulation time 1492947112 ps
CPU time 14.31 seconds
Started May 07 02:18:32 PM PDT 24
Finished May 07 02:18:48 PM PDT 24
Peak memory 220324 kb
Host smart-d7d12261-9b1e-4efb-9423-edd2fc88393d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4284584536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4284584536
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2633096556
Short name T707
Test name
Test status
Simulation time 42600850 ps
CPU time 0.98 seconds
Started May 07 02:18:31 PM PDT 24
Finished May 07 02:18:33 PM PDT 24
Peak memory 207376 kb
Host smart-205b39c3-3a98-4200-9285-0d095c5bf786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633096556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2633096556
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.467787081
Short name T679
Test name
Test status
Simulation time 2878425165 ps
CPU time 14.86 seconds
Started May 07 02:18:21 PM PDT 24
Finished May 07 02:18:37 PM PDT 24
Peak memory 220244 kb
Host smart-c5ed06a0-dd99-49ea-9c95-4ecebe983455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467787081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.467787081
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3749014788
Short name T112
Test name
Test status
Simulation time 1928236443 ps
CPU time 9.94 seconds
Started May 07 02:18:16 PM PDT 24
Finished May 07 02:18:26 PM PDT 24
Peak memory 216324 kb
Host smart-0b29bc4a-c38e-4a25-9c7b-4fe13500cd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749014788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3749014788
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.103791948
Short name T390
Test name
Test status
Simulation time 28429800 ps
CPU time 0.82 seconds
Started May 07 02:18:20 PM PDT 24
Finished May 07 02:18:22 PM PDT 24
Peak memory 206612 kb
Host smart-5e69c5df-108f-4672-b4ed-6e309baf5a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103791948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.103791948
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3357521013
Short name T510
Test name
Test status
Simulation time 46778486 ps
CPU time 0.73 seconds
Started May 07 02:18:18 PM PDT 24
Finished May 07 02:18:20 PM PDT 24
Peak memory 205844 kb
Host smart-04850955-fdf2-449a-8ac6-3a5dc02e8819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357521013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3357521013
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.942094745
Short name T237
Test name
Test status
Simulation time 1358978984 ps
CPU time 7.64 seconds
Started May 07 02:18:21 PM PDT 24
Finished May 07 02:18:29 PM PDT 24
Peak memory 217352 kb
Host smart-1ced7b35-08e0-4a8c-8271-fc895a8c2037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942094745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.942094745
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3985403787
Short name T481
Test name
Test status
Simulation time 12162242 ps
CPU time 0.71 seconds
Started May 07 02:18:51 PM PDT 24
Finished May 07 02:18:52 PM PDT 24
Peak memory 204860 kb
Host smart-1927e0f7-1a13-4f04-b780-fcacb3c52eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985403787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
985403787
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.254460119
Short name T18
Test name
Test status
Simulation time 17730160 ps
CPU time 0.8 seconds
Started May 07 02:18:32 PM PDT 24
Finished May 07 02:18:34 PM PDT 24
Peak memory 206896 kb
Host smart-ab126242-a8a6-4bf8-8324-9f34017df2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254460119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.254460119
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.954686527
Short name T353
Test name
Test status
Simulation time 2214677273 ps
CPU time 42.26 seconds
Started May 07 02:18:45 PM PDT 24
Finished May 07 02:19:29 PM PDT 24
Peak memory 240792 kb
Host smart-d0cd3bd3-37e4-4a6c-ad9e-c15516873fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954686527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.954686527
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1440746278
Short name T514
Test name
Test status
Simulation time 199492609 ps
CPU time 4.47 seconds
Started May 07 02:18:39 PM PDT 24
Finished May 07 02:18:44 PM PDT 24
Peak memory 219668 kb
Host smart-c85f3a61-5203-4b31-b953-c74ab8e9d5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440746278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1440746278
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2077225726
Short name T141
Test name
Test status
Simulation time 1084636948 ps
CPU time 12.3 seconds
Started May 07 02:18:47 PM PDT 24
Finished May 07 02:19:01 PM PDT 24
Peak memory 222320 kb
Host smart-437df40c-fbaf-4114-a397-442e7423269a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077225726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2077225726
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.802134568
Short name T114
Test name
Test status
Simulation time 1707640052 ps
CPU time 18.93 seconds
Started May 07 02:18:39 PM PDT 24
Finished May 07 02:18:58 PM PDT 24
Peak memory 216272 kb
Host smart-046c379f-b0e3-41b7-979e-06cadc0040a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802134568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.802134568
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3375185379
Short name T447
Test name
Test status
Simulation time 15207423524 ps
CPU time 14.82 seconds
Started May 07 02:18:34 PM PDT 24
Finished May 07 02:18:49 PM PDT 24
Peak memory 216436 kb
Host smart-fcde711f-e9c3-4fca-9c63-517afc9a7c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375185379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3375185379
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.375194550
Short name T16
Test name
Test status
Simulation time 173965149 ps
CPU time 2.7 seconds
Started May 07 02:18:39 PM PDT 24
Finished May 07 02:18:42 PM PDT 24
Peak memory 217456 kb
Host smart-8f9eb388-dfb0-45d0-8cb4-335adf6dfa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375194550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.375194550
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.579635935
Short name T609
Test name
Test status
Simulation time 340274560 ps
CPU time 1.01 seconds
Started May 07 02:18:40 PM PDT 24
Finished May 07 02:18:41 PM PDT 24
Peak memory 207016 kb
Host smart-c4821454-eb1f-4bb0-bf28-33d4571773a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579635935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.579635935
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4208646157
Short name T305
Test name
Test status
Simulation time 235273816 ps
CPU time 5.35 seconds
Started May 07 02:18:40 PM PDT 24
Finished May 07 02:18:46 PM PDT 24
Peak memory 233436 kb
Host smart-36d8a497-fbe5-4b53-b5f9-558d8538af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208646157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4208646157
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1170688771
Short name T500
Test name
Test status
Simulation time 25426937 ps
CPU time 0.73 seconds
Started May 07 02:19:00 PM PDT 24
Finished May 07 02:19:02 PM PDT 24
Peak memory 204880 kb
Host smart-9b917824-192f-4d12-b6fc-185c0ac41415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170688771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
170688771
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1257237084
Short name T589
Test name
Test status
Simulation time 6055592361 ps
CPU time 12.71 seconds
Started May 07 02:18:57 PM PDT 24
Finished May 07 02:19:10 PM PDT 24
Peak memory 218752 kb
Host smart-38e12242-49d9-48f8-9000-c4da577b0f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257237084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1257237084
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2454280122
Short name T402
Test name
Test status
Simulation time 17224293 ps
CPU time 0.74 seconds
Started May 07 02:18:50 PM PDT 24
Finished May 07 02:18:52 PM PDT 24
Peak memory 206648 kb
Host smart-5a367223-a3b1-4177-82d6-921386842967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454280122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2454280122
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3791838694
Short name T274
Test name
Test status
Simulation time 81387105501 ps
CPU time 41.11 seconds
Started May 07 02:18:51 PM PDT 24
Finished May 07 02:19:33 PM PDT 24
Peak memory 232480 kb
Host smart-2ae40888-2f56-4b43-b4d8-c6cc17459d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791838694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3791838694
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1854784446
Short name T515
Test name
Test status
Simulation time 2064718050 ps
CPU time 14.99 seconds
Started May 07 02:18:56 PM PDT 24
Finished May 07 02:19:11 PM PDT 24
Peak memory 222948 kb
Host smart-2f84c233-d703-417f-9cf6-ca7df9ff6323
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1854784446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1854784446
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3921432645
Short name T376
Test name
Test status
Simulation time 5809030031 ps
CPU time 25.45 seconds
Started May 07 02:18:49 PM PDT 24
Finished May 07 02:19:16 PM PDT 24
Peak memory 216336 kb
Host smart-0cab2658-84b6-448e-99eb-754c688f07a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921432645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3921432645
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3847402183
Short name T480
Test name
Test status
Simulation time 10996287797 ps
CPU time 28.29 seconds
Started May 07 02:18:49 PM PDT 24
Finished May 07 02:19:18 PM PDT 24
Peak memory 216388 kb
Host smart-fbab8eb0-5941-4a71-a020-a9e63e23a22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847402183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3847402183
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3663120814
Short name T594
Test name
Test status
Simulation time 634332393 ps
CPU time 1.69 seconds
Started May 07 02:18:51 PM PDT 24
Finished May 07 02:18:54 PM PDT 24
Peak memory 216376 kb
Host smart-2d8cb38f-45f2-4266-8345-56ca5768c466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663120814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3663120814
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2489601897
Short name T566
Test name
Test status
Simulation time 44935126 ps
CPU time 0.8 seconds
Started May 07 02:18:48 PM PDT 24
Finished May 07 02:18:50 PM PDT 24
Peak memory 205824 kb
Host smart-f96fdd3c-eda0-4297-ac69-4733f9122038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489601897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2489601897
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.173845629
Short name T284
Test name
Test status
Simulation time 5534184410 ps
CPU time 6.1 seconds
Started May 07 02:18:54 PM PDT 24
Finished May 07 02:19:00 PM PDT 24
Peak memory 234440 kb
Host smart-3f9bf581-bec5-4f91-8134-d6bfa59f675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173845629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.173845629
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1991076239
Short name T471
Test name
Test status
Simulation time 46178867 ps
CPU time 0.7 seconds
Started May 07 02:19:19 PM PDT 24
Finished May 07 02:19:20 PM PDT 24
Peak memory 205748 kb
Host smart-894a4024-aefa-4fa0-8b29-ce0405f87bb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991076239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
991076239
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2037251157
Short name T567
Test name
Test status
Simulation time 74348952 ps
CPU time 0.74 seconds
Started May 07 02:19:00 PM PDT 24
Finished May 07 02:19:02 PM PDT 24
Peak memory 205712 kb
Host smart-7fa28914-ccfc-4731-9084-a7fafa33f2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037251157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2037251157
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3028206761
Short name T297
Test name
Test status
Simulation time 395616293 ps
CPU time 13.24 seconds
Started May 07 02:19:12 PM PDT 24
Finished May 07 02:19:26 PM PDT 24
Peak memory 249128 kb
Host smart-eedf3c70-6db0-4700-821e-5ec1ec81929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028206761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3028206761
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1013669723
Short name T190
Test name
Test status
Simulation time 4247849484 ps
CPU time 20.86 seconds
Started May 07 02:19:06 PM PDT 24
Finished May 07 02:19:28 PM PDT 24
Peak memory 223068 kb
Host smart-beca18de-55bf-411d-bc14-c954bdb256be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013669723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1013669723
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1257157487
Short name T308
Test name
Test status
Simulation time 51054678865 ps
CPU time 112.36 seconds
Started May 07 02:19:10 PM PDT 24
Finished May 07 02:21:03 PM PDT 24
Peak memory 251060 kb
Host smart-4ca152d7-3a8d-4933-8ea4-83a371a593e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257157487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1257157487
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.284793809
Short name T331
Test name
Test status
Simulation time 17592448769 ps
CPU time 6.64 seconds
Started May 07 02:19:07 PM PDT 24
Finished May 07 02:19:14 PM PDT 24
Peak memory 220860 kb
Host smart-4e791ceb-ad3b-4545-9bc7-7325bec6649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284793809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
284793809
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.561082654
Short name T281
Test name
Test status
Simulation time 37592688 ps
CPU time 2.41 seconds
Started May 07 02:19:07 PM PDT 24
Finished May 07 02:19:10 PM PDT 24
Peak memory 222096 kb
Host smart-b7b8bb05-45a1-4e5a-abf5-86e6dd7b1e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561082654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.561082654
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1443638990
Short name T632
Test name
Test status
Simulation time 10408338612 ps
CPU time 11.81 seconds
Started May 07 02:19:12 PM PDT 24
Finished May 07 02:19:24 PM PDT 24
Peak memory 223296 kb
Host smart-51260038-447e-4377-9d0e-ad400057e146
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1443638990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1443638990
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.910363877
Short name T52
Test name
Test status
Simulation time 11113895146 ps
CPU time 21.53 seconds
Started May 07 02:19:07 PM PDT 24
Finished May 07 02:19:29 PM PDT 24
Peak memory 216700 kb
Host smart-830e9631-7194-43c8-b52f-a7185787f068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910363877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.910363877
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4019167287
Short name T462
Test name
Test status
Simulation time 1515940007 ps
CPU time 9.37 seconds
Started May 07 02:19:08 PM PDT 24
Finished May 07 02:19:18 PM PDT 24
Peak memory 216304 kb
Host smart-757e4807-5662-4b0b-9229-5161cdf7aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019167287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4019167287
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2122035073
Short name T698
Test name
Test status
Simulation time 662476290 ps
CPU time 10.34 seconds
Started May 07 02:19:06 PM PDT 24
Finished May 07 02:19:17 PM PDT 24
Peak memory 216332 kb
Host smart-4ec44494-177a-4407-8006-4c6bbf4dc8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122035073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2122035073
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.14575892
Short name T601
Test name
Test status
Simulation time 38744429 ps
CPU time 0.79 seconds
Started May 07 02:19:07 PM PDT 24
Finished May 07 02:19:09 PM PDT 24
Peak memory 205848 kb
Host smart-71d64e8a-a4d4-4523-821d-9458f9b1e772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14575892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.14575892
Directory /workspace/9.spi_device_tpm_sts_read/latest
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